1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
51 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
146 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
150 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
153 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
154 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
155 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
160 //===----------------------------------------------------------------------===//
161 // Operand Definitions.
165 def brtarget : Operand<OtherVT>;
167 // A list of registers separated by comma. Used by load/store multiple.
168 def reglist : Operand<i32> {
169 let PrintMethod = "printRegisterList";
172 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
173 def cpinst_operand : Operand<i32> {
174 let PrintMethod = "printCPInstOperand";
177 def jtblock_operand : Operand<i32> {
178 let PrintMethod = "printJTBlockOperand";
182 def pclabel : Operand<i32> {
183 let PrintMethod = "printPCLabel";
186 // shifter_operand operands: so_reg and so_imm.
187 def so_reg : Operand<i32>, // reg reg imm
188 ComplexPattern<i32, 3, "SelectShifterOperandReg",
189 [shl,srl,sra,rotr]> {
190 let PrintMethod = "printSORegOperand";
191 let MIOperandInfo = (ops GPR, GPR, i32imm);
194 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
195 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
196 // represented in the imm field in the same 12-bit form that they are encoded
197 // into so_imm instructions: the 8-bit immediate is the least significant bits
198 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
199 def so_imm : Operand<i32>,
201 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
203 let PrintMethod = "printSOImmOperand";
206 // Break so_imm's up into two pieces. This handles immediates with up to 16
207 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
208 // get the first/second pieces.
209 def so_imm2part : Operand<i32>,
211 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
212 let PrintMethod = "printSOImm2PartOperand";
215 def so_imm2part_1 : SDNodeXForm<imm, [{
216 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
217 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
220 def so_imm2part_2 : SDNodeXForm<imm, [{
221 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
222 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
226 // Define ARM specific addressing modes.
228 // addrmode2 := reg +/- reg shop imm
229 // addrmode2 := reg +/- imm12
231 def addrmode2 : Operand<i32>,
232 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
233 let PrintMethod = "printAddrMode2Operand";
234 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
237 def am2offset : Operand<i32>,
238 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
239 let PrintMethod = "printAddrMode2OffsetOperand";
240 let MIOperandInfo = (ops GPR, i32imm);
243 // addrmode3 := reg +/- reg
244 // addrmode3 := reg +/- imm8
246 def addrmode3 : Operand<i32>,
247 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
248 let PrintMethod = "printAddrMode3Operand";
249 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
252 def am3offset : Operand<i32>,
253 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
254 let PrintMethod = "printAddrMode3OffsetOperand";
255 let MIOperandInfo = (ops GPR, i32imm);
258 // addrmode4 := reg, <mode|W>
260 def addrmode4 : Operand<i32>,
261 ComplexPattern<i32, 2, "", []> {
262 let PrintMethod = "printAddrMode4Operand";
263 let MIOperandInfo = (ops GPR, i32imm);
266 // addrmode5 := reg +/- imm8*4
268 def addrmode5 : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
270 let PrintMethod = "printAddrMode5Operand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmodepc := pc + reg
276 def addrmodepc : Operand<i32>,
277 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
278 let PrintMethod = "printAddrModePCOperand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
283 // register whose default is 0 (no register).
284 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
285 (ops (i32 14), (i32 zero_reg))> {
286 let PrintMethod = "printPredicateOperand";
289 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
291 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
292 let PrintMethod = "printSBitModifierOperand";
295 //===----------------------------------------------------------------------===//
296 // ARM Instruction flags. These need to match ARMInstrInfo.h.
300 class AddrMode<bits<4> val> {
303 def AddrModeNone : AddrMode<0>;
304 def AddrMode1 : AddrMode<1>;
305 def AddrMode2 : AddrMode<2>;
306 def AddrMode3 : AddrMode<3>;
307 def AddrMode4 : AddrMode<4>;
308 def AddrMode5 : AddrMode<5>;
309 def AddrModeT1 : AddrMode<6>;
310 def AddrModeT2 : AddrMode<7>;
311 def AddrModeT4 : AddrMode<8>;
312 def AddrModeTs : AddrMode<9>;
315 class SizeFlagVal<bits<3> val> {
318 def SizeInvalid : SizeFlagVal<0>; // Unset.
319 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
320 def Size8Bytes : SizeFlagVal<2>;
321 def Size4Bytes : SizeFlagVal<3>;
322 def Size2Bytes : SizeFlagVal<4>;
324 // Load / store index mode.
325 class IndexMode<bits<2> val> {
328 def IndexModeNone : IndexMode<0>;
329 def IndexModePre : IndexMode<1>;
330 def IndexModePost : IndexMode<2>;
332 //===----------------------------------------------------------------------===//
333 // ARM Instruction templates.
336 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
337 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
338 list<Predicate> Predicates = [IsARM];
340 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
341 list<Predicate> Predicates = [IsARM, HasV5TE];
343 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
344 list<Predicate> Predicates = [IsARM, HasV6];
347 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
350 let Namespace = "ARM";
352 bits<4> Opcode = opcod;
354 bits<4> AddrModeBits = AM.Value;
357 bits<3> SizeFlag = SZ.Value;
360 bits<2> IndexModeBits = IM.Value;
362 let Constraints = cstr;
365 class PseudoInst<dag ops, string asm, list<dag> pattern>
366 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> {
367 let OperandList = ops;
369 let Pattern = pattern;
372 // Almost all ARM instructions are predicable.
373 class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
374 string opc, string asm, string cstr, list<dag> pattern>
375 // FIXME: Set all opcodes to 0 for now.
376 : InstARM<0, am, sz, im, cstr> {
377 let OperandList = !con(oprnds, (ops pred:$p));
378 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
379 let Pattern = pattern;
380 list<Predicate> Predicates = [IsARM];
383 // Same as I except it can optionally modify CPSR.
384 class sI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
385 string opc, string asm, string cstr, list<dag> pattern>
386 // FIXME: Set all opcodes to 0 for now.
387 : InstARM<0, am, sz, im, cstr> {
388 let OperandList = !con(oprnds, (ops pred:$p, cc_out:$s));
389 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
390 let Pattern = pattern;
391 list<Predicate> Predicates = [IsARM];
394 class AI<dag ops, string opc, string asm, list<dag> pattern>
395 : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
396 class AsI<dag ops, string opc, string asm, list<dag> pattern>
397 : sI<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
398 class AI1<dag ops, string opc, string asm, list<dag> pattern>
399 : I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
400 class AsI1<dag ops, string opc, string asm, list<dag> pattern>
401 : sI<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
402 class AI2<dag ops, string opc, string asm, list<dag> pattern>
403 : I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
404 class AI3<dag ops, string opc, string asm, list<dag> pattern>
405 : I<ops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
406 class AI4<dag ops, string opc, string asm, list<dag> pattern>
407 : I<ops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
408 class AI1x2<dag ops, string opc, string asm, list<dag> pattern>
409 : I<ops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
412 class AI2pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
413 : I<ops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
414 class AI3pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
415 : I<ops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
418 class AI2po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
419 : I<ops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
420 class AI3po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
421 : I<ops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
424 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
425 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
428 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
429 /// binop that produces a value.
430 multiclass AsI1_bin_irs<string opc, PatFrag opnode> {
431 def ri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
432 opc, " $dst, $a, $b",
433 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
434 def rr : AsI1<(ops GPR:$dst, GPR:$a, GPR:$b),
435 opc, " $dst, $a, $b",
436 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
437 def rs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
438 opc, " $dst, $a, $b",
439 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
442 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
443 /// instruction modifies the CSPR register.
444 multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> {
445 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
446 opc, "s $dst, $a, $b",
447 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
448 def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
449 opc, "s $dst, $a, $b",
450 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>;
451 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
452 opc, "s $dst, $a, $b",
453 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>;
456 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
457 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
458 /// a explicit result, only implicitly set CPSR.
459 multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
460 def ri : AI1<(ops GPR:$a, so_imm:$b),
462 [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>;
463 def rr : AI1<(ops GPR:$a, GPR:$b),
465 [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>;
466 def rs : AI1<(ops GPR:$a, so_reg:$b),
468 [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
471 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
472 /// register and one whose operand is a register rotated by 8/16/24.
473 multiclass AI_unary_rrot<string opc, PatFrag opnode> {
474 def r : AI<(ops GPR:$dst, GPR:$Src),
476 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
477 def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
478 opc, " $dst, $Src, ror $rot",
479 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
480 Requires<[IsARM, HasV6]>;
483 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
484 /// register and one whose operand is a register rotated by 8/16/24.
485 multiclass AI_bin_rrot<string opc, PatFrag opnode> {
486 def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
487 opc, " $dst, $LHS, $RHS",
488 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
489 Requires<[IsARM, HasV6]>;
490 def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
491 opc, " $dst, $LHS, $RHS, ror $rot",
492 [(set GPR:$dst, (opnode GPR:$LHS,
493 (rotr GPR:$RHS, rot_imm:$rot)))]>,
494 Requires<[IsARM, HasV6]>;
498 class XI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
499 string asm, string cstr, list<dag> pattern>
500 // FIXME: Set all opcodes to 0 for now.
501 : InstARM<0, am, sz, im, cstr> {
502 let OperandList = oprnds;
504 let Pattern = pattern;
505 list<Predicate> Predicates = [IsARM];
508 class AXI<dag ops, string asm, list<dag> pattern>
509 : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
510 class AXI1<dag ops, string asm, list<dag> pattern>
511 : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
512 class AXI2<dag ops, string asm, list<dag> pattern>
513 : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
514 class AXI3<dag ops, string asm, list<dag> pattern>
515 : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
516 class AXI4<dag ops, string asm, list<dag> pattern>
517 : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
519 class AXIx2<dag ops, string asm, list<dag> pattern>
520 : XI<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
522 // BR_JT instructions
523 class JTI<dag ops, string asm, list<dag> pattern>
524 : XI<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
525 class JTI1<dag ops, string asm, list<dag> pattern>
526 : XI<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
527 class JTI2<dag ops, string asm, list<dag> pattern>
528 : XI<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
530 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
531 /// setting carry bit. But it can optionally set CPSR.
532 multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> {
533 def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s),
534 !strconcat(opc, "${s} $dst, $a, $b"),
535 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
536 def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b, cc_out:$s),
537 !strconcat(opc, "${s} $dst, $a, $b"),
538 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
539 def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s),
540 !strconcat(opc, "${s} $dst, $a, $b"),
541 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
544 //===----------------------------------------------------------------------===//
546 //===----------------------------------------------------------------------===//
548 //===----------------------------------------------------------------------===//
549 // Miscellaneous Instructions.
551 def IMPLICIT_DEF_GPR :
552 PseudoInst<(ops GPR:$rD, pred:$p),
553 "@ IMPLICIT_DEF_GPR $rD",
554 [(set GPR:$rD, (undef))]>;
557 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
558 /// the function. The first operand is the ID# for this instruction, the second
559 /// is the index into the MachineConstantPool that this is, the third is the
560 /// size in bytes of this constant pool entry.
561 let isNotDuplicable = 1 in
562 def CONSTPOOL_ENTRY :
563 PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
564 "${instid:label} ${cpidx:cpentry}", []>;
567 PseudoInst<(ops i32imm:$amt, pred:$p),
568 "@ ADJCALLSTACKUP $amt",
569 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
571 def ADJCALLSTACKDOWN :
572 PseudoInst<(ops i32imm:$amt, pred:$p),
573 "@ ADJCALLSTACKDOWN $amt",
574 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
577 PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
578 ".loc $file, $line, $col",
579 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
581 let isNotDuplicable = 1 in {
582 def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p),
583 "$cp:\n\tadd$p $dst, pc, $a",
584 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
586 let isLoad = 1, AddedComplexity = 10 in {
587 def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
588 "${addr:label}:\n\tldr$p $dst, $addr",
589 [(set GPR:$dst, (load addrmodepc:$addr))]>;
591 def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
592 "${addr:label}:\n\tldr${p}h $dst, $addr",
593 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
595 def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
596 "${addr:label}:\n\tldr${p}b $dst, $addr",
597 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
599 def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
600 "${addr:label}:\n\tldr${p}h $dst, $addr",
601 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
603 def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
604 "${addr:label}:\n\tldr${p}b $dst, $addr",
605 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
607 def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
608 "${addr:label}:\n\tldr${p}sh $dst, $addr",
609 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
611 def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
612 "${addr:label}:\n\tldr${p}sb $dst, $addr",
613 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
615 let isStore = 1, AddedComplexity = 10 in {
616 def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
617 "${addr:label}:\n\tstr$p $src, $addr",
618 [(store GPR:$src, addrmodepc:$addr)]>;
620 def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p),
621 "${addr:label}:\n\tstr${p}h $src, $addr",
622 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
624 def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
625 "${addr:label}:\n\tstr${p}b $src, $addr",
626 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
630 //===----------------------------------------------------------------------===//
631 // Control Flow Instructions.
634 let isReturn = 1, isTerminator = 1 in
635 def BX_RET : AI<(ops), "bx", " lr", [(ARMretflag)]>;
637 // FIXME: remove when we have a way to marking a MI with these properties.
638 let isLoad = 1, isReturn = 1, isTerminator = 1 in
639 def LDM_RET : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
640 "ldm${p}${addr:submode} $addr, $dst1",
643 let isCall = 1, noResults = 1,
644 Defs = [R0, R1, R2, R3, R12, LR,
645 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
646 def BL : AXI<(ops i32imm:$func, variable_ops),
648 [(ARMcall tglobaladdr:$func)]>;
650 def BL_pred : AI<(ops i32imm:$func, variable_ops),
651 "bl", " ${func:call}",
652 [(ARMcall_pred tglobaladdr:$func)]>;
655 def BLX : AXI<(ops GPR:$dst, variable_ops),
657 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
660 def BX : AXIx2<(ops GPR:$dst, variable_ops),
661 "mov lr, pc\n\tbx $dst",
662 [(ARMcall_nolink GPR:$dst)]>;
666 let isBranch = 1, isTerminator = 1, noResults = 1 in {
667 // B is "predicable" since it can be xformed into a Bcc.
668 let isBarrier = 1 in {
669 let isPredicable = 1 in
670 def B : AXI<(ops brtarget:$dst), "b $dst",
673 let isNotDuplicable = 1 in {
674 def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
675 "mov pc, $dst \n$jt",
676 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
677 def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
678 "ldr pc, $dst \n$jt",
679 [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
681 def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
682 "add pc, $dst, $idx \n$jt",
683 [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
688 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
689 // a two-value operand where a dag node expects two operands. :(
690 def Bcc : AI<(ops brtarget:$dst), "b", " $dst",
691 [/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
694 //===----------------------------------------------------------------------===//
695 // Load / store Instructions.
700 def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
701 "ldr", " $dst, $addr",
702 [(set GPR:$dst, (load addrmode2:$addr))]>;
704 // Special LDR for loads from non-pc-relative constpools.
705 let isReMaterializable = 1 in
706 def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
707 "ldr", " $dst, $addr", []>;
709 // Loads with zero extension
710 def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
711 "ldr", "h $dst, $addr",
712 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
714 def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
715 "ldr", "b $dst, $addr",
716 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
718 // Loads with sign extension
719 def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
720 "ldr", "sh $dst, $addr",
721 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
723 def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
724 "ldr", "sb $dst, $addr",
725 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
728 def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
729 "ldr", "d $dst, $addr",
730 []>, Requires<[IsARM, HasV5T]>;
733 def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
734 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
736 def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
737 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
739 def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
740 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
742 def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
743 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
745 def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
746 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
748 def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
749 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
751 def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
752 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
754 def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
755 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
757 def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
758 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
760 def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
761 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
766 def STR : AI2<(ops GPR:$src, addrmode2:$addr),
767 "str", " $src, $addr",
768 [(store GPR:$src, addrmode2:$addr)]>;
770 // Stores with truncate
771 def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
772 "str", "h $src, $addr",
773 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
775 def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
776 "str", "b $src, $addr",
777 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
780 def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
781 "str", "d $src, $addr",
782 []>, Requires<[IsARM, HasV5T]>;
785 def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
786 "str", " $src, [$base, $offset]!", "$base = $base_wb",
788 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
790 def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
791 "str", " $src, [$base], $offset", "$base = $base_wb",
793 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
795 def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
796 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
798 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
800 def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
801 "str", "h $src, [$base], $offset", "$base = $base_wb",
802 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
803 GPR:$base, am3offset:$offset))]>;
805 def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
806 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
807 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
808 GPR:$base, am2offset:$offset))]>;
810 def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
811 "str", "b $src, [$base], $offset", "$base = $base_wb",
812 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
813 GPR:$base, am2offset:$offset))]>;
816 //===----------------------------------------------------------------------===//
817 // Load / store multiple Instructions.
821 def LDM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
822 "ldm${p}${addr:submode} $addr, $dst1",
826 def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
827 "stm${p}${addr:submode} $addr, $src1",
830 //===----------------------------------------------------------------------===//
831 // Move Instructions.
834 def MOVr : AsI1<(ops GPR:$dst, GPR:$src),
835 "mov", " $dst, $src", []>;
836 def MOVs : AsI1<(ops GPR:$dst, so_reg:$src),
837 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
839 let isReMaterializable = 1 in
840 def MOVi : AsI1<(ops GPR:$dst, so_imm:$src),
841 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
843 def MOVrx : AsI1<(ops GPR:$dst, GPR:$src),
844 "mov", " $dst, $src, rrx",
845 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
847 // These aren't really mov instructions, but we have to define them this way
848 // due to flag operands.
850 def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
851 "mov", "s $dst, $src, lsr #1",
852 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
853 def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
854 "mov", "s $dst, $src, asr #1",
855 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
857 //===----------------------------------------------------------------------===//
858 // Extend Instructions.
863 defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
864 defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
866 defm SXTAB : AI_bin_rrot<"sxtab",
867 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
868 defm SXTAH : AI_bin_rrot<"sxtah",
869 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
871 // TODO: SXT(A){B|H}16
875 let AddedComplexity = 16 in {
876 defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
877 defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
878 defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
880 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
881 (UXTB16r_rot GPR:$Src, 24)>;
882 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
883 (UXTB16r_rot GPR:$Src, 8)>;
885 defm UXTAB : AI_bin_rrot<"uxtab",
886 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
887 defm UXTAH : AI_bin_rrot<"uxtah",
888 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
891 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
892 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
894 // TODO: UXT(A){B|H}16
896 //===----------------------------------------------------------------------===//
897 // Arithmetic Instructions.
900 defm ADD : AsI1_bin_irs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
901 defm SUB : AsI1_bin_irs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
903 // ADD and SUB with 's' bit set.
904 defm ADDS : ASI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
905 defm SUBS : ASI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
907 // FIXME: Do not allow ADC / SBC to be predicated for now.
908 defm ADC : AsXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
909 defm SBC : AsXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
911 // These don't define reg/reg forms, because they are handled above.
912 def RSBri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
913 "rsb", " $dst, $a, $b",
914 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
916 def RSBrs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
917 "rsb", " $dst, $a, $b",
918 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
920 // RSB with 's' bit set.
921 def RSBSri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
922 "rsb", "s $dst, $a, $b",
923 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
924 def RSBSrs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
925 "rsb", "s $dst, $a, $b",
926 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
928 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
929 def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s),
930 "rsc${s} $dst, $a, $b",
931 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
932 def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s),
933 "rsc${s} $dst, $a, $b",
934 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
936 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
937 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
938 (SUBri GPR:$src, so_imm_neg:$imm)>;
940 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
941 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
942 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
943 // (SBCri GPR:$src, so_imm_neg:$imm)>;
945 // Note: These are implemented in C++ code, because they have to generate
946 // ADD/SUBrs instructions, which use a complex pattern that a xform function
948 // (mul X, 2^n+1) -> (add (X << n), X)
949 // (mul X, 2^n-1) -> (rsb X, (X << n))
952 //===----------------------------------------------------------------------===//
953 // Bitwise Instructions.
956 defm AND : AsI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
957 defm ORR : AsI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
958 defm EOR : AsI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
959 defm BIC : AsI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
961 def MVNr : AsI<(ops GPR:$dst, GPR:$src),
962 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
963 def MVNs : AsI<(ops GPR:$dst, so_reg:$src),
964 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
965 let isReMaterializable = 1 in
966 def MVNi : AsI<(ops GPR:$dst, so_imm:$imm),
967 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
969 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
970 (BICri GPR:$src, so_imm_not:$imm)>;
972 //===----------------------------------------------------------------------===//
973 // Multiply Instructions.
976 def MUL : AsI<(ops GPR:$dst, GPR:$a, GPR:$b),
977 "mul", " $dst, $a, $b",
978 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
980 def MLA : AsI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
981 "mla", " $dst, $a, $b, $c",
982 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
984 // Extra precision multiplies with low / high results
985 def SMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
986 "smull", " $ldst, $hdst, $a, $b", []>;
988 def UMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
989 "umull", " $ldst, $hdst, $a, $b", []>;
991 // Multiply + accumulate
992 def SMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
993 "smlal", " $ldst, $hdst, $a, $b", []>;
995 def UMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
996 "umlal", " $ldst, $hdst, $a, $b", []>;
998 def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
999 "umaal", " $ldst, $hdst, $a, $b", []>,
1000 Requires<[IsARM, HasV6]>;
1002 // Most significant word multiply
1003 def SMMUL : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1004 "smmul", " $dst, $a, $b",
1005 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1006 Requires<[IsARM, HasV6]>;
1008 def SMMLA : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
1009 "smmla", " $dst, $a, $b, $c",
1010 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1011 Requires<[IsARM, HasV6]>;
1014 def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
1015 "smmls", " $dst, $a, $b, $c",
1016 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1017 Requires<[IsARM, HasV6]>;
1019 multiclass AI_smul<string opc, PatFrag opnode> {
1020 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1021 !strconcat(opc, "bb"), " $dst, $a, $b",
1022 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1023 (sext_inreg GPR:$b, i16)))]>,
1024 Requires<[IsARM, HasV5TE]>;
1025 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1026 !strconcat(opc, "bt"), " $dst, $a, $b",
1027 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1028 (sra GPR:$b, 16)))]>,
1029 Requires<[IsARM, HasV5TE]>;
1030 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1031 !strconcat(opc, "tb"), " $dst, $a, $b",
1032 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1033 (sext_inreg GPR:$b, i16)))]>,
1034 Requires<[IsARM, HasV5TE]>;
1035 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1036 !strconcat(opc, "tt"), " $dst, $a, $b",
1037 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1038 (sra GPR:$b, 16)))]>,
1039 Requires<[IsARM, HasV5TE]>;
1040 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1041 !strconcat(opc, "wb"), " $dst, $a, $b",
1042 [(set GPR:$dst, (sra (opnode GPR:$a,
1043 (sext_inreg GPR:$b, i16)), 16))]>,
1044 Requires<[IsARM, HasV5TE]>;
1045 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1046 !strconcat(opc, "wt"), " $dst, $a, $b",
1047 [(set GPR:$dst, (sra (opnode GPR:$a,
1048 (sra GPR:$b, 16)), 16))]>,
1049 Requires<[IsARM, HasV5TE]>;
1052 multiclass AI_smla<string opc, PatFrag opnode> {
1053 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1054 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1055 [(set GPR:$dst, (add GPR:$acc,
1056 (opnode (sext_inreg GPR:$a, i16),
1057 (sext_inreg GPR:$b, i16))))]>,
1058 Requires<[IsARM, HasV5TE]>;
1059 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1060 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1061 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1062 (sra GPR:$b, 16))))]>,
1063 Requires<[IsARM, HasV5TE]>;
1064 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1065 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1066 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1067 (sext_inreg GPR:$b, i16))))]>,
1068 Requires<[IsARM, HasV5TE]>;
1069 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1070 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1071 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1072 (sra GPR:$b, 16))))]>,
1073 Requires<[IsARM, HasV5TE]>;
1075 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1076 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1077 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1078 (sext_inreg GPR:$b, i16)), 16)))]>,
1079 Requires<[IsARM, HasV5TE]>;
1080 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1081 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1082 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1083 (sra GPR:$b, 16)), 16)))]>,
1084 Requires<[IsARM, HasV5TE]>;
1087 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1088 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1090 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1091 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1093 //===----------------------------------------------------------------------===//
1094 // Misc. Arithmetic Instructions.
1097 def CLZ : AI<(ops GPR:$dst, GPR:$src),
1098 "clz", " $dst, $src",
1099 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1101 def REV : AI<(ops GPR:$dst, GPR:$src),
1102 "rev", " $dst, $src",
1103 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1105 def REV16 : AI<(ops GPR:$dst, GPR:$src),
1106 "rev16", " $dst, $src",
1108 (or (and (srl GPR:$src, 8), 0xFF),
1109 (or (and (shl GPR:$src, 8), 0xFF00),
1110 (or (and (srl GPR:$src, 8), 0xFF0000),
1111 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1112 Requires<[IsARM, HasV6]>;
1114 def REVSH : AI<(ops GPR:$dst, GPR:$src),
1115 "revsh", " $dst, $src",
1118 (or (srl (and GPR:$src, 0xFF00), 8),
1119 (shl GPR:$src, 8)), i16))]>,
1120 Requires<[IsARM, HasV6]>;
1122 def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
1123 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1124 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1125 (and (shl GPR:$src2, (i32 imm:$shamt)),
1127 Requires<[IsARM, HasV6]>;
1129 // Alternate cases for PKHBT where identities eliminate some nodes.
1130 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1131 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1132 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1133 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1136 def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
1137 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1138 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1139 (and (sra GPR:$src2, imm16_31:$shamt),
1140 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1142 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1143 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1144 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1145 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1146 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1147 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1148 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1151 //===----------------------------------------------------------------------===//
1152 // Comparison Instructions...
1155 defm CMP : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1156 defm CMN : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1158 // Note that TST/TEQ don't set all the same flags that CMP does!
1159 defm TST : AI1_cmp_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1160 defm TEQ : AI1_cmp_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1162 defm CMPnz : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1163 defm CMNnz : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1165 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1166 (CMNri GPR:$src, so_imm_neg:$imm)>;
1168 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1169 (CMNri GPR:$src, so_imm_neg:$imm)>;
1172 // Conditional moves
1173 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1174 // a two-value operand where a dag node expects two operands. :(
1175 def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true),
1176 "mov", " $dst, $true",
1177 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1178 RegConstraint<"$false = $dst">;
1180 def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true),
1181 "mov", " $dst, $true",
1182 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1183 RegConstraint<"$false = $dst">;
1185 def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true),
1186 "mov", " $dst, $true",
1187 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1188 RegConstraint<"$false = $dst">;
1191 // LEApcrel - Load a pc-relative address into a register without offending the
1193 def LEApcrel : AXI1<(ops GPR:$dst, i32imm:$label, pred:$p),
1194 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1195 "${:private}PCRELL${:uid}+8))\n"),
1196 !strconcat("${:private}PCRELL${:uid}:\n\t",
1197 "add$p $dst, pc, #PCRELV${:uid}")),
1200 def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
1201 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1202 "${:private}PCRELL${:uid}+8))\n"),
1203 !strconcat("${:private}PCRELL${:uid}:\n\t",
1204 "add$p $dst, pc, #PCRELV${:uid}")),
1207 //===----------------------------------------------------------------------===//
1211 // __aeabi_read_tp preserves the registers r1-r3.
1213 Defs = [R0, R12, LR, CPSR] in {
1214 def TPsoft : AXI<(ops),
1215 "bl __aeabi_read_tp",
1216 [(set R0, ARMthread_pointer)]>;
1219 //===----------------------------------------------------------------------===//
1220 // Non-Instruction Patterns
1223 // ConstantPool, GlobalAddress, and JumpTable
1224 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1225 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1226 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1227 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1229 // Large immediate handling.
1231 // Two piece so_imms.
1232 let isReMaterializable = 1 in
1233 def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
1234 "mov", " $dst, $src",
1235 [(set GPR:$dst, so_imm2part:$src)]>;
1237 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1238 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1239 (so_imm2part_2 imm:$RHS))>;
1240 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1241 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1242 (so_imm2part_2 imm:$RHS))>;
1244 // TODO: add,sub,and, 3-instr forms?
1248 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1250 // zextload i1 -> zextload i8
1251 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1253 // extload -> zextload
1254 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1255 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1256 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1258 // truncstore i1 -> truncstore i8
1259 def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
1260 (STRB GPR:$src, addrmode2:$dst)>;
1261 def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1262 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1263 def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1264 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1267 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1268 (SMULBB GPR:$a, GPR:$b)>;
1269 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1270 (SMULBB GPR:$a, GPR:$b)>;
1271 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1272 (SMULBT GPR:$a, GPR:$b)>;
1273 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1274 (SMULBT GPR:$a, GPR:$b)>;
1275 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1276 (SMULTB GPR:$a, GPR:$b)>;
1277 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1278 (SMULTB GPR:$a, GPR:$b)>;
1279 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1280 (SMULWB GPR:$a, GPR:$b)>;
1281 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1282 (SMULWB GPR:$a, GPR:$b)>;
1284 def : ARMV5TEPat<(add GPR:$acc,
1285 (mul (sra (shl GPR:$a, 16), 16),
1286 (sra (shl GPR:$b, 16), 16))),
1287 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1288 def : ARMV5TEPat<(add GPR:$acc,
1289 (mul sext_16_node:$a, sext_16_node:$b)),
1290 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1291 def : ARMV5TEPat<(add GPR:$acc,
1292 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1293 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1294 def : ARMV5TEPat<(add GPR:$acc,
1295 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1296 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1297 def : ARMV5TEPat<(add GPR:$acc,
1298 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1299 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1300 def : ARMV5TEPat<(add GPR:$acc,
1301 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1302 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1303 def : ARMV5TEPat<(add GPR:$acc,
1304 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1305 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1306 def : ARMV5TEPat<(add GPR:$acc,
1307 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1308 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1310 //===----------------------------------------------------------------------===//
1314 include "ARMInstrThumb.td"
1316 //===----------------------------------------------------------------------===//
1317 // Floating Point Support
1320 include "ARMInstrVFP.td"