1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3">;
182 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
183 AssemblerPredicate<"FeatureVFP4">;
184 def NoVFP4 : Predicate<"!Subtarget->hasVFP4()">;
185 def HasNEON : Predicate<"Subtarget->hasNEON()">,
186 AssemblerPredicate<"FeatureNEON">;
187 def HasNEON2 : Predicate<"Subtarget->hasNEON2()">,
188 AssemblerPredicate<"FeatureNEON2">;
189 def NoNEON2 : Predicate<"!Subtarget->hasNEON2()">;
190 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
191 AssemblerPredicate<"FeatureFP16">;
192 def HasDivide : Predicate<"Subtarget->hasDivide()">,
193 AssemblerPredicate<"FeatureHWDiv">;
194 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
195 AssemblerPredicate<"FeatureT2XtPk">;
196 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
197 AssemblerPredicate<"FeatureDSPThumb2">;
198 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
199 AssemblerPredicate<"FeatureDB">;
200 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
201 AssemblerPredicate<"FeatureMP">;
202 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
203 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
204 def IsThumb : Predicate<"Subtarget->isThumb()">,
205 AssemblerPredicate<"ModeThumb">;
206 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
207 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
208 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
209 def IsMClass : Predicate<"Subtarget->isMClass()">,
210 AssemblerPredicate<"FeatureMClass">;
211 def IsARClass : Predicate<"!Subtarget->isMClass()">,
212 AssemblerPredicate<"!FeatureMClass">;
213 def IsARM : Predicate<"!Subtarget->isThumb()">,
214 AssemblerPredicate<"!ModeThumb">;
215 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
216 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
217 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
219 // FIXME: Eventually this will be just "hasV6T2Ops".
220 def UseMovt : Predicate<"Subtarget->useMovt()">;
221 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
222 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
224 //===----------------------------------------------------------------------===//
225 // ARM Flag Definitions.
227 class RegConstraint<string C> {
228 string Constraints = C;
231 //===----------------------------------------------------------------------===//
232 // ARM specific transformation functions and pattern fragments.
235 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
236 // so_imm_neg def below.
237 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
241 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
242 // so_imm_not def below.
243 def so_imm_not_XFORM : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
247 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
248 def imm16_31 : ImmLeaf<i32, [{
249 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
252 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
253 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
254 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
255 }], so_imm_neg_XFORM> {
256 let ParserMatchClass = so_imm_neg_asmoperand;
259 // Note: this pattern doesn't require an encoder method and such, as it's
260 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
261 // is handled by the destination instructions, which use so_imm.
262 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
263 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
264 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
265 }], so_imm_not_XFORM> {
266 let ParserMatchClass = so_imm_not_asmoperand;
269 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
270 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
271 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
274 /// Split a 32-bit immediate into two 16 bit parts.
275 def hi16 : SDNodeXForm<imm, [{
276 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
279 def lo16AllZero : PatLeaf<(i32 imm), [{
280 // Returns true if all low 16-bits are 0.
281 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
284 class BinOpWithFlagFrag<dag res> :
285 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
286 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
287 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
289 // An 'and' node with a single use.
290 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'xor' node with a single use.
295 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
296 return N->hasOneUse();
299 // An 'fmul' node with a single use.
300 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
301 return N->hasOneUse();
304 // An 'fadd' node which checks for single non-hazardous use.
305 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 // An 'fsub' node which checks for single non-hazardous use.
310 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
311 return hasNoVMLxHazardUse(N);
314 //===----------------------------------------------------------------------===//
315 // Operand Definitions.
318 // Immediate operands with a shared generic asm render method.
319 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
322 // FIXME: rename brtarget to t2_brtarget
323 def brtarget : Operand<OtherVT> {
324 let EncoderMethod = "getBranchTargetOpValue";
325 let OperandType = "OPERAND_PCREL";
326 let DecoderMethod = "DecodeT2BROperand";
329 // FIXME: get rid of this one?
330 def uncondbrtarget : Operand<OtherVT> {
331 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
332 let OperandType = "OPERAND_PCREL";
335 // Branch target for ARM. Handles conditional/unconditional
336 def br_target : Operand<OtherVT> {
337 let EncoderMethod = "getARMBranchTargetOpValue";
338 let OperandType = "OPERAND_PCREL";
342 // FIXME: rename bltarget to t2_bl_target?
343 def bltarget : Operand<i32> {
344 // Encoded the same as branch targets.
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
349 // Call target for ARM. Handles conditional/unconditional
350 // FIXME: rename bl_target to t2_bltarget?
351 def bl_target : Operand<i32> {
352 let EncoderMethod = "getARMBLTargetOpValue";
353 let OperandType = "OPERAND_PCREL";
356 def blx_target : Operand<i32> {
357 let EncoderMethod = "getARMBLXTargetOpValue";
358 let OperandType = "OPERAND_PCREL";
361 // A list of registers separated by comma. Used by load/store multiple.
362 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
363 def reglist : Operand<i32> {
364 let EncoderMethod = "getRegisterListOpValue";
365 let ParserMatchClass = RegListAsmOperand;
366 let PrintMethod = "printRegisterList";
367 let DecoderMethod = "DecodeRegListOperand";
370 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
371 def dpr_reglist : Operand<i32> {
372 let EncoderMethod = "getRegisterListOpValue";
373 let ParserMatchClass = DPRRegListAsmOperand;
374 let PrintMethod = "printRegisterList";
375 let DecoderMethod = "DecodeDPRRegListOperand";
378 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
379 def spr_reglist : Operand<i32> {
380 let EncoderMethod = "getRegisterListOpValue";
381 let ParserMatchClass = SPRRegListAsmOperand;
382 let PrintMethod = "printRegisterList";
383 let DecoderMethod = "DecodeSPRRegListOperand";
386 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
387 def cpinst_operand : Operand<i32> {
388 let PrintMethod = "printCPInstOperand";
392 def pclabel : Operand<i32> {
393 let PrintMethod = "printPCLabel";
396 // ADR instruction labels.
397 def adrlabel : Operand<i32> {
398 let EncoderMethod = "getAdrLabelOpValue";
401 def neon_vcvt_imm32 : Operand<i32> {
402 let EncoderMethod = "getNEONVcvtImm32OpValue";
403 let DecoderMethod = "DecodeVCVTImmOperand";
406 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
407 def rot_imm_XFORM: SDNodeXForm<imm, [{
408 switch (N->getZExtValue()){
410 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
411 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
412 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
413 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
416 def RotImmAsmOperand : AsmOperandClass {
418 let ParserMethod = "parseRotImm";
420 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
421 int32_t v = N->getZExtValue();
422 return v == 8 || v == 16 || v == 24; }],
424 let PrintMethod = "printRotImmOperand";
425 let ParserMatchClass = RotImmAsmOperand;
428 // shift_imm: An integer that encodes a shift amount and the type of shift
429 // (asr or lsl). The 6-bit immediate encodes as:
432 // {4-0} imm5 shift amount.
433 // asr #32 encoded as imm5 == 0.
434 def ShifterImmAsmOperand : AsmOperandClass {
435 let Name = "ShifterImm";
436 let ParserMethod = "parseShifterImm";
438 def shift_imm : Operand<i32> {
439 let PrintMethod = "printShiftImmOperand";
440 let ParserMatchClass = ShifterImmAsmOperand;
443 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
444 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
445 def so_reg_reg : Operand<i32>, // reg reg imm
446 ComplexPattern<i32, 3, "SelectRegShifterOperand",
447 [shl, srl, sra, rotr]> {
448 let EncoderMethod = "getSORegRegOpValue";
449 let PrintMethod = "printSORegRegOperand";
450 let DecoderMethod = "DecodeSORegRegOperand";
451 let ParserMatchClass = ShiftedRegAsmOperand;
452 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
455 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
456 def so_reg_imm : Operand<i32>, // reg imm
457 ComplexPattern<i32, 2, "SelectImmShifterOperand",
458 [shl, srl, sra, rotr]> {
459 let EncoderMethod = "getSORegImmOpValue";
460 let PrintMethod = "printSORegImmOperand";
461 let DecoderMethod = "DecodeSORegImmOperand";
462 let ParserMatchClass = ShiftedImmAsmOperand;
463 let MIOperandInfo = (ops GPR, i32imm);
466 // FIXME: Does this need to be distinct from so_reg?
467 def shift_so_reg_reg : Operand<i32>, // reg reg imm
468 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
469 [shl,srl,sra,rotr]> {
470 let EncoderMethod = "getSORegRegOpValue";
471 let PrintMethod = "printSORegRegOperand";
472 let DecoderMethod = "DecodeSORegRegOperand";
473 let ParserMatchClass = ShiftedRegAsmOperand;
474 let MIOperandInfo = (ops GPR, GPR, i32imm);
477 // FIXME: Does this need to be distinct from so_reg?
478 def shift_so_reg_imm : Operand<i32>, // reg reg imm
479 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
480 [shl,srl,sra,rotr]> {
481 let EncoderMethod = "getSORegImmOpValue";
482 let PrintMethod = "printSORegImmOperand";
483 let DecoderMethod = "DecodeSORegImmOperand";
484 let ParserMatchClass = ShiftedImmAsmOperand;
485 let MIOperandInfo = (ops GPR, i32imm);
489 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
490 // 8-bit immediate rotated by an arbitrary number of bits.
491 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
492 def so_imm : Operand<i32>, ImmLeaf<i32, [{
493 return ARM_AM::getSOImmVal(Imm) != -1;
495 let EncoderMethod = "getSOImmOpValue";
496 let ParserMatchClass = SOImmAsmOperand;
497 let DecoderMethod = "DecodeSOImmOperand";
500 // Break so_imm's up into two pieces. This handles immediates with up to 16
501 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
502 // get the first/second pieces.
503 def so_imm2part : PatLeaf<(imm), [{
504 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
507 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
509 def arm_i32imm : PatLeaf<(imm), [{
510 if (Subtarget->hasV6T2Ops())
512 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
515 /// imm0_1 predicate - Immediate in the range [0,1].
516 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
517 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
519 /// imm0_3 predicate - Immediate in the range [0,3].
520 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
521 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
523 /// imm0_7 predicate - Immediate in the range [0,7].
524 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
525 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
526 return Imm >= 0 && Imm < 8;
528 let ParserMatchClass = Imm0_7AsmOperand;
531 /// imm8 predicate - Immediate is exactly 8.
532 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
533 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
534 let ParserMatchClass = Imm8AsmOperand;
537 /// imm16 predicate - Immediate is exactly 16.
538 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
539 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
540 let ParserMatchClass = Imm16AsmOperand;
543 /// imm32 predicate - Immediate is exactly 32.
544 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
545 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
546 let ParserMatchClass = Imm32AsmOperand;
549 /// imm1_7 predicate - Immediate in the range [1,7].
550 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
551 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
552 let ParserMatchClass = Imm1_7AsmOperand;
555 /// imm1_15 predicate - Immediate in the range [1,15].
556 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
557 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
558 let ParserMatchClass = Imm1_15AsmOperand;
561 /// imm1_31 predicate - Immediate in the range [1,31].
562 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
563 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
564 let ParserMatchClass = Imm1_31AsmOperand;
567 /// imm0_15 predicate - Immediate in the range [0,15].
568 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
569 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
570 return Imm >= 0 && Imm < 16;
572 let ParserMatchClass = Imm0_15AsmOperand;
575 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
576 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
577 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
578 return Imm >= 0 && Imm < 32;
580 let ParserMatchClass = Imm0_31AsmOperand;
583 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
584 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
585 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
586 return Imm >= 0 && Imm < 32;
588 let ParserMatchClass = Imm0_32AsmOperand;
591 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
592 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
593 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
594 return Imm >= 0 && Imm < 64;
596 let ParserMatchClass = Imm0_63AsmOperand;
599 /// imm0_255 predicate - Immediate in the range [0,255].
600 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
601 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
602 let ParserMatchClass = Imm0_255AsmOperand;
605 /// imm0_65535 - An immediate is in the range [0.65535].
606 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
607 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
608 return Imm >= 0 && Imm < 65536;
610 let ParserMatchClass = Imm0_65535AsmOperand;
613 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
614 // a relocatable expression.
616 // FIXME: This really needs a Thumb version separate from the ARM version.
617 // While the range is the same, and can thus use the same match class,
618 // the encoding is different so it should have a different encoder method.
619 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
620 def imm0_65535_expr : Operand<i32> {
621 let EncoderMethod = "getHiLo16ImmOpValue";
622 let ParserMatchClass = Imm0_65535ExprAsmOperand;
625 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
626 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
627 def imm24b : Operand<i32>, ImmLeaf<i32, [{
628 return Imm >= 0 && Imm <= 0xffffff;
630 let ParserMatchClass = Imm24bitAsmOperand;
634 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
636 def BitfieldAsmOperand : AsmOperandClass {
637 let Name = "Bitfield";
638 let ParserMethod = "parseBitfield";
641 def bf_inv_mask_imm : Operand<i32>,
643 return ARM::isBitFieldInvertedMask(N->getZExtValue());
645 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
646 let PrintMethod = "printBitfieldInvMaskImmOperand";
647 let DecoderMethod = "DecodeBitfieldMaskOperand";
648 let ParserMatchClass = BitfieldAsmOperand;
651 def imm1_32_XFORM: SDNodeXForm<imm, [{
652 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
654 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
655 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
656 uint64_t Imm = N->getZExtValue();
657 return Imm > 0 && Imm <= 32;
660 let PrintMethod = "printImmPlusOneOperand";
661 let ParserMatchClass = Imm1_32AsmOperand;
664 def imm1_16_XFORM: SDNodeXForm<imm, [{
665 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
667 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
668 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
670 let PrintMethod = "printImmPlusOneOperand";
671 let ParserMatchClass = Imm1_16AsmOperand;
674 // Define ARM specific addressing modes.
675 // addrmode_imm12 := reg +/- imm12
677 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
678 def addrmode_imm12 : Operand<i32>,
679 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
680 // 12-bit immediate operand. Note that instructions using this encode
681 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
682 // immediate values are as normal.
684 let EncoderMethod = "getAddrModeImm12OpValue";
685 let PrintMethod = "printAddrModeImm12Operand";
686 let DecoderMethod = "DecodeAddrModeImm12Operand";
687 let ParserMatchClass = MemImm12OffsetAsmOperand;
688 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
690 // ldst_so_reg := reg +/- reg shop imm
692 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
693 def ldst_so_reg : Operand<i32>,
694 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
695 let EncoderMethod = "getLdStSORegOpValue";
696 // FIXME: Simplify the printer
697 let PrintMethod = "printAddrMode2Operand";
698 let DecoderMethod = "DecodeSORegMemOperand";
699 let ParserMatchClass = MemRegOffsetAsmOperand;
700 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
703 // postidx_imm8 := +/- [0,255]
706 // {8} 1 is imm8 is non-negative. 0 otherwise.
707 // {7-0} [0,255] imm8 value.
708 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
709 def postidx_imm8 : Operand<i32> {
710 let PrintMethod = "printPostIdxImm8Operand";
711 let ParserMatchClass = PostIdxImm8AsmOperand;
712 let MIOperandInfo = (ops i32imm);
715 // postidx_imm8s4 := +/- [0,1020]
718 // {8} 1 is imm8 is non-negative. 0 otherwise.
719 // {7-0} [0,255] imm8 value, scaled by 4.
720 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
721 def postidx_imm8s4 : Operand<i32> {
722 let PrintMethod = "printPostIdxImm8s4Operand";
723 let ParserMatchClass = PostIdxImm8s4AsmOperand;
724 let MIOperandInfo = (ops i32imm);
728 // postidx_reg := +/- reg
730 def PostIdxRegAsmOperand : AsmOperandClass {
731 let Name = "PostIdxReg";
732 let ParserMethod = "parsePostIdxReg";
734 def postidx_reg : Operand<i32> {
735 let EncoderMethod = "getPostIdxRegOpValue";
736 let DecoderMethod = "DecodePostIdxReg";
737 let PrintMethod = "printPostIdxRegOperand";
738 let ParserMatchClass = PostIdxRegAsmOperand;
739 let MIOperandInfo = (ops GPR, i32imm);
743 // addrmode2 := reg +/- imm12
744 // := reg +/- reg shop imm
746 // FIXME: addrmode2 should be refactored the rest of the way to always
747 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
748 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
749 def addrmode2 : Operand<i32>,
750 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
751 let EncoderMethod = "getAddrMode2OpValue";
752 let PrintMethod = "printAddrMode2Operand";
753 let ParserMatchClass = AddrMode2AsmOperand;
754 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
757 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
758 let Name = "PostIdxRegShifted";
759 let ParserMethod = "parsePostIdxReg";
761 def am2offset_reg : Operand<i32>,
762 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
763 [], [SDNPWantRoot]> {
764 let EncoderMethod = "getAddrMode2OffsetOpValue";
765 let PrintMethod = "printAddrMode2OffsetOperand";
766 // When using this for assembly, it's always as a post-index offset.
767 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
768 let MIOperandInfo = (ops GPRnopc, i32imm);
771 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
772 // the GPR is purely vestigal at this point.
773 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
774 def am2offset_imm : Operand<i32>,
775 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
776 [], [SDNPWantRoot]> {
777 let EncoderMethod = "getAddrMode2OffsetOpValue";
778 let PrintMethod = "printAddrMode2OffsetOperand";
779 let ParserMatchClass = AM2OffsetImmAsmOperand;
780 let MIOperandInfo = (ops GPRnopc, i32imm);
784 // addrmode3 := reg +/- reg
785 // addrmode3 := reg +/- imm8
787 // FIXME: split into imm vs. reg versions.
788 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
789 def addrmode3 : Operand<i32>,
790 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
791 let EncoderMethod = "getAddrMode3OpValue";
792 let PrintMethod = "printAddrMode3Operand";
793 let ParserMatchClass = AddrMode3AsmOperand;
794 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
797 // FIXME: split into imm vs. reg versions.
798 // FIXME: parser method to handle +/- register.
799 def AM3OffsetAsmOperand : AsmOperandClass {
800 let Name = "AM3Offset";
801 let ParserMethod = "parseAM3Offset";
803 def am3offset : Operand<i32>,
804 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
805 [], [SDNPWantRoot]> {
806 let EncoderMethod = "getAddrMode3OffsetOpValue";
807 let PrintMethod = "printAddrMode3OffsetOperand";
808 let ParserMatchClass = AM3OffsetAsmOperand;
809 let MIOperandInfo = (ops GPR, i32imm);
812 // ldstm_mode := {ia, ib, da, db}
814 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
815 let EncoderMethod = "getLdStmModeOpValue";
816 let PrintMethod = "printLdStmModeOperand";
819 // addrmode5 := reg +/- imm8*4
821 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
822 def addrmode5 : Operand<i32>,
823 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
824 let PrintMethod = "printAddrMode5Operand";
825 let EncoderMethod = "getAddrMode5OpValue";
826 let DecoderMethod = "DecodeAddrMode5Operand";
827 let ParserMatchClass = AddrMode5AsmOperand;
828 let MIOperandInfo = (ops GPR:$base, i32imm);
831 // addrmode6 := reg with optional alignment
833 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
834 def addrmode6 : Operand<i32>,
835 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
836 let PrintMethod = "printAddrMode6Operand";
837 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
838 let EncoderMethod = "getAddrMode6AddressOpValue";
839 let DecoderMethod = "DecodeAddrMode6Operand";
840 let ParserMatchClass = AddrMode6AsmOperand;
843 def am6offset : Operand<i32>,
844 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
845 [], [SDNPWantRoot]> {
846 let PrintMethod = "printAddrMode6OffsetOperand";
847 let MIOperandInfo = (ops GPR);
848 let EncoderMethod = "getAddrMode6OffsetOpValue";
849 let DecoderMethod = "DecodeGPRRegisterClass";
852 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
853 // (single element from one lane) for size 32.
854 def addrmode6oneL32 : Operand<i32>,
855 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
856 let PrintMethod = "printAddrMode6Operand";
857 let MIOperandInfo = (ops GPR:$addr, i32imm);
858 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
861 // Special version of addrmode6 to handle alignment encoding for VLD-dup
862 // instructions, specifically VLD4-dup.
863 def addrmode6dup : Operand<i32>,
864 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
865 let PrintMethod = "printAddrMode6Operand";
866 let MIOperandInfo = (ops GPR:$addr, i32imm);
867 let EncoderMethod = "getAddrMode6DupAddressOpValue";
868 // FIXME: This is close, but not quite right. The alignment specifier is
870 let ParserMatchClass = AddrMode6AsmOperand;
873 // addrmodepc := pc + reg
875 def addrmodepc : Operand<i32>,
876 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
877 let PrintMethod = "printAddrModePCOperand";
878 let MIOperandInfo = (ops GPR, i32imm);
881 // addr_offset_none := reg
883 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
884 def addr_offset_none : Operand<i32>,
885 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
886 let PrintMethod = "printAddrMode7Operand";
887 let DecoderMethod = "DecodeAddrMode7Operand";
888 let ParserMatchClass = MemNoOffsetAsmOperand;
889 let MIOperandInfo = (ops GPR:$base);
892 def nohash_imm : Operand<i32> {
893 let PrintMethod = "printNoHashImmediate";
896 def CoprocNumAsmOperand : AsmOperandClass {
897 let Name = "CoprocNum";
898 let ParserMethod = "parseCoprocNumOperand";
900 def p_imm : Operand<i32> {
901 let PrintMethod = "printPImmediate";
902 let ParserMatchClass = CoprocNumAsmOperand;
903 let DecoderMethod = "DecodeCoprocessor";
906 def CoprocRegAsmOperand : AsmOperandClass {
907 let Name = "CoprocReg";
908 let ParserMethod = "parseCoprocRegOperand";
910 def c_imm : Operand<i32> {
911 let PrintMethod = "printCImmediate";
912 let ParserMatchClass = CoprocRegAsmOperand;
914 def CoprocOptionAsmOperand : AsmOperandClass {
915 let Name = "CoprocOption";
916 let ParserMethod = "parseCoprocOptionOperand";
918 def coproc_option_imm : Operand<i32> {
919 let PrintMethod = "printCoprocOptionImm";
920 let ParserMatchClass = CoprocOptionAsmOperand;
923 //===----------------------------------------------------------------------===//
925 include "ARMInstrFormats.td"
927 //===----------------------------------------------------------------------===//
928 // Multiclass helpers...
931 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
932 /// binop that produces a value.
933 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
934 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
935 PatFrag opnode, string baseOpc, bit Commutable = 0> {
936 // The register-immediate version is re-materializable. This is useful
937 // in particular for taking the address of a local.
938 let isReMaterializable = 1 in {
939 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
940 iii, opc, "\t$Rd, $Rn, $imm",
941 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
946 let Inst{19-16} = Rn;
947 let Inst{15-12} = Rd;
948 let Inst{11-0} = imm;
951 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
952 iir, opc, "\t$Rd, $Rn, $Rm",
953 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
958 let isCommutable = Commutable;
959 let Inst{19-16} = Rn;
960 let Inst{15-12} = Rd;
961 let Inst{11-4} = 0b00000000;
965 def rsi : AsI1<opcod, (outs GPR:$Rd),
966 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
967 iis, opc, "\t$Rd, $Rn, $shift",
968 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
973 let Inst{19-16} = Rn;
974 let Inst{15-12} = Rd;
975 let Inst{11-5} = shift{11-5};
977 let Inst{3-0} = shift{3-0};
980 def rsr : AsI1<opcod, (outs GPR:$Rd),
981 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
982 iis, opc, "\t$Rd, $Rn, $shift",
983 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
988 let Inst{19-16} = Rn;
989 let Inst{15-12} = Rd;
990 let Inst{11-8} = shift{11-8};
992 let Inst{6-5} = shift{6-5};
994 let Inst{3-0} = shift{3-0};
997 // Assembly aliases for optional destination operand when it's the same
998 // as the source operand.
999 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1000 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1001 so_imm:$imm, pred:$p,
1004 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1005 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1009 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1010 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1011 so_reg_imm:$shift, pred:$p,
1014 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1015 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1016 so_reg_reg:$shift, pred:$p,
1022 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1023 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1024 /// it is equivalent to the AsI1_bin_irs counterpart.
1025 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1026 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1027 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1028 // The register-immediate version is re-materializable. This is useful
1029 // in particular for taking the address of a local.
1030 let isReMaterializable = 1 in {
1031 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1032 iii, opc, "\t$Rd, $Rn, $imm",
1033 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1038 let Inst{19-16} = Rn;
1039 let Inst{15-12} = Rd;
1040 let Inst{11-0} = imm;
1043 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1044 iir, opc, "\t$Rd, $Rn, $Rm",
1045 [/* pattern left blank */]> {
1049 let Inst{11-4} = 0b00000000;
1052 let Inst{15-12} = Rd;
1053 let Inst{19-16} = Rn;
1056 def rsi : AsI1<opcod, (outs GPR:$Rd),
1057 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1058 iis, opc, "\t$Rd, $Rn, $shift",
1059 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1064 let Inst{19-16} = Rn;
1065 let Inst{15-12} = Rd;
1066 let Inst{11-5} = shift{11-5};
1068 let Inst{3-0} = shift{3-0};
1071 def rsr : AsI1<opcod, (outs GPR:$Rd),
1072 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1073 iis, opc, "\t$Rd, $Rn, $shift",
1074 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1079 let Inst{19-16} = Rn;
1080 let Inst{15-12} = Rd;
1081 let Inst{11-8} = shift{11-8};
1083 let Inst{6-5} = shift{6-5};
1085 let Inst{3-0} = shift{3-0};
1088 // Assembly aliases for optional destination operand when it's the same
1089 // as the source operand.
1090 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1091 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1092 so_imm:$imm, pred:$p,
1095 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1096 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1100 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1101 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1102 so_reg_imm:$shift, pred:$p,
1105 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1106 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1107 so_reg_reg:$shift, pred:$p,
1113 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1115 /// These opcodes will be converted to the real non-S opcodes by
1116 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1117 let hasPostISelHook = 1, Defs = [CPSR] in {
1118 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1119 InstrItinClass iis, PatFrag opnode,
1120 bit Commutable = 0> {
1121 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1123 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1125 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1127 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1128 let isCommutable = Commutable;
1130 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1131 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1133 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1134 so_reg_imm:$shift))]>;
1136 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1137 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1139 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1140 so_reg_reg:$shift))]>;
1144 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1145 /// operands are reversed.
1146 let hasPostISelHook = 1, Defs = [CPSR] in {
1147 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1148 InstrItinClass iis, PatFrag opnode,
1149 bit Commutable = 0> {
1150 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1152 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1154 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1155 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1157 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1160 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1161 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1163 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1168 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1169 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1170 /// a explicit result, only implicitly set CPSR.
1171 let isCompare = 1, Defs = [CPSR] in {
1172 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1173 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1174 PatFrag opnode, bit Commutable = 0> {
1175 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1177 [(opnode GPR:$Rn, so_imm:$imm)]> {
1182 let Inst{19-16} = Rn;
1183 let Inst{15-12} = 0b0000;
1184 let Inst{11-0} = imm;
1186 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1188 [(opnode GPR:$Rn, GPR:$Rm)]> {
1191 let isCommutable = Commutable;
1194 let Inst{19-16} = Rn;
1195 let Inst{15-12} = 0b0000;
1196 let Inst{11-4} = 0b00000000;
1199 def rsi : AI1<opcod, (outs),
1200 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1201 opc, "\t$Rn, $shift",
1202 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1207 let Inst{19-16} = Rn;
1208 let Inst{15-12} = 0b0000;
1209 let Inst{11-5} = shift{11-5};
1211 let Inst{3-0} = shift{3-0};
1213 def rsr : AI1<opcod, (outs),
1214 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1215 opc, "\t$Rn, $shift",
1216 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1221 let Inst{19-16} = Rn;
1222 let Inst{15-12} = 0b0000;
1223 let Inst{11-8} = shift{11-8};
1225 let Inst{6-5} = shift{6-5};
1227 let Inst{3-0} = shift{3-0};
1233 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1234 /// register and one whose operand is a register rotated by 8/16/24.
1235 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1236 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1237 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1238 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1239 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1240 Requires<[IsARM, HasV6]> {
1244 let Inst{19-16} = 0b1111;
1245 let Inst{15-12} = Rd;
1246 let Inst{11-10} = rot;
1250 class AI_ext_rrot_np<bits<8> opcod, string opc>
1251 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1252 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1253 Requires<[IsARM, HasV6]> {
1255 let Inst{19-16} = 0b1111;
1256 let Inst{11-10} = rot;
1259 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1260 /// register and one whose operand is a register rotated by 8/16/24.
1261 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1262 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1263 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1264 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1265 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1266 Requires<[IsARM, HasV6]> {
1271 let Inst{19-16} = Rn;
1272 let Inst{15-12} = Rd;
1273 let Inst{11-10} = rot;
1274 let Inst{9-4} = 0b000111;
1278 class AI_exta_rrot_np<bits<8> opcod, string opc>
1279 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1280 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1281 Requires<[IsARM, HasV6]> {
1284 let Inst{19-16} = Rn;
1285 let Inst{11-10} = rot;
1288 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1289 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1290 string baseOpc, bit Commutable = 0> {
1291 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1292 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1293 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1294 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1300 let Inst{15-12} = Rd;
1301 let Inst{19-16} = Rn;
1302 let Inst{11-0} = imm;
1304 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1305 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1306 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1311 let Inst{11-4} = 0b00000000;
1313 let isCommutable = Commutable;
1315 let Inst{15-12} = Rd;
1316 let Inst{19-16} = Rn;
1318 def rsi : AsI1<opcod, (outs GPR:$Rd),
1319 (ins GPR:$Rn, so_reg_imm:$shift),
1320 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1321 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1327 let Inst{19-16} = Rn;
1328 let Inst{15-12} = Rd;
1329 let Inst{11-5} = shift{11-5};
1331 let Inst{3-0} = shift{3-0};
1333 def rsr : AsI1<opcod, (outs GPR:$Rd),
1334 (ins GPR:$Rn, so_reg_reg:$shift),
1335 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1336 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1342 let Inst{19-16} = Rn;
1343 let Inst{15-12} = Rd;
1344 let Inst{11-8} = shift{11-8};
1346 let Inst{6-5} = shift{6-5};
1348 let Inst{3-0} = shift{3-0};
1352 // Assembly aliases for optional destination operand when it's the same
1353 // as the source operand.
1354 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1355 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1356 so_imm:$imm, pred:$p,
1359 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1360 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1364 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1365 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1366 so_reg_imm:$shift, pred:$p,
1369 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1370 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1371 so_reg_reg:$shift, pred:$p,
1376 /// AI1_rsc_irs - Define instructions and patterns for rsc
1377 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1379 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1380 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1381 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1382 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1388 let Inst{15-12} = Rd;
1389 let Inst{19-16} = Rn;
1390 let Inst{11-0} = imm;
1392 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1393 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1394 [/* pattern left blank */]> {
1398 let Inst{11-4} = 0b00000000;
1401 let Inst{15-12} = Rd;
1402 let Inst{19-16} = Rn;
1404 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1405 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1406 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1412 let Inst{19-16} = Rn;
1413 let Inst{15-12} = Rd;
1414 let Inst{11-5} = shift{11-5};
1416 let Inst{3-0} = shift{3-0};
1418 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1419 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1420 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1426 let Inst{19-16} = Rn;
1427 let Inst{15-12} = Rd;
1428 let Inst{11-8} = shift{11-8};
1430 let Inst{6-5} = shift{6-5};
1432 let Inst{3-0} = shift{3-0};
1436 // Assembly aliases for optional destination operand when it's the same
1437 // as the source operand.
1438 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1439 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1440 so_imm:$imm, pred:$p,
1443 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1444 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1448 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1449 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1450 so_reg_imm:$shift, pred:$p,
1453 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1454 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1455 so_reg_reg:$shift, pred:$p,
1460 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1461 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1462 InstrItinClass iir, PatFrag opnode> {
1463 // Note: We use the complex addrmode_imm12 rather than just an input
1464 // GPR and a constrained immediate so that we can use this to match
1465 // frame index references and avoid matching constant pool references.
1466 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1467 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1468 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1471 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1472 let Inst{19-16} = addr{16-13}; // Rn
1473 let Inst{15-12} = Rt;
1474 let Inst{11-0} = addr{11-0}; // imm12
1476 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1477 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1478 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1481 let shift{4} = 0; // Inst{4} = 0
1482 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1483 let Inst{19-16} = shift{16-13}; // Rn
1484 let Inst{15-12} = Rt;
1485 let Inst{11-0} = shift{11-0};
1490 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1491 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1492 InstrItinClass iir, PatFrag opnode> {
1493 // Note: We use the complex addrmode_imm12 rather than just an input
1494 // GPR and a constrained immediate so that we can use this to match
1495 // frame index references and avoid matching constant pool references.
1496 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1497 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1498 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1501 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1502 let Inst{19-16} = addr{16-13}; // Rn
1503 let Inst{15-12} = Rt;
1504 let Inst{11-0} = addr{11-0}; // imm12
1506 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1507 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1508 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1511 let shift{4} = 0; // Inst{4} = 0
1512 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1513 let Inst{19-16} = shift{16-13}; // Rn
1514 let Inst{15-12} = Rt;
1515 let Inst{11-0} = shift{11-0};
1521 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1522 InstrItinClass iir, PatFrag opnode> {
1523 // Note: We use the complex addrmode_imm12 rather than just an input
1524 // GPR and a constrained immediate so that we can use this to match
1525 // frame index references and avoid matching constant pool references.
1526 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1527 (ins GPR:$Rt, addrmode_imm12:$addr),
1528 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1529 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1532 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1533 let Inst{19-16} = addr{16-13}; // Rn
1534 let Inst{15-12} = Rt;
1535 let Inst{11-0} = addr{11-0}; // imm12
1537 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1538 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1539 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1542 let shift{4} = 0; // Inst{4} = 0
1543 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1544 let Inst{19-16} = shift{16-13}; // Rn
1545 let Inst{15-12} = Rt;
1546 let Inst{11-0} = shift{11-0};
1550 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1551 InstrItinClass iir, PatFrag opnode> {
1552 // Note: We use the complex addrmode_imm12 rather than just an input
1553 // GPR and a constrained immediate so that we can use this to match
1554 // frame index references and avoid matching constant pool references.
1555 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1556 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1557 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1558 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1561 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1562 let Inst{19-16} = addr{16-13}; // Rn
1563 let Inst{15-12} = Rt;
1564 let Inst{11-0} = addr{11-0}; // imm12
1566 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1567 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1568 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1571 let shift{4} = 0; // Inst{4} = 0
1572 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1573 let Inst{19-16} = shift{16-13}; // Rn
1574 let Inst{15-12} = Rt;
1575 let Inst{11-0} = shift{11-0};
1580 //===----------------------------------------------------------------------===//
1582 //===----------------------------------------------------------------------===//
1584 //===----------------------------------------------------------------------===//
1585 // Miscellaneous Instructions.
1588 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1589 /// the function. The first operand is the ID# for this instruction, the second
1590 /// is the index into the MachineConstantPool that this is, the third is the
1591 /// size in bytes of this constant pool entry.
1592 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1593 def CONSTPOOL_ENTRY :
1594 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1595 i32imm:$size), NoItinerary, []>;
1597 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1598 // from removing one half of the matched pairs. That breaks PEI, which assumes
1599 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1600 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1601 def ADJCALLSTACKUP :
1602 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1603 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1605 def ADJCALLSTACKDOWN :
1606 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1607 [(ARMcallseq_start timm:$amt)]>;
1610 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1611 // (These pseudos use a hand-written selection code).
1612 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1613 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1614 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1616 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1617 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1619 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1620 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1622 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1623 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1625 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1626 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1628 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1629 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1631 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1632 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1634 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1635 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1636 GPR:$set1, GPR:$set2),
1640 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1641 Requires<[IsARM, HasV6T2]> {
1642 let Inst{27-16} = 0b001100100000;
1643 let Inst{15-8} = 0b11110000;
1644 let Inst{7-0} = 0b00000000;
1647 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1648 Requires<[IsARM, HasV6T2]> {
1649 let Inst{27-16} = 0b001100100000;
1650 let Inst{15-8} = 0b11110000;
1651 let Inst{7-0} = 0b00000001;
1654 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1655 Requires<[IsARM, HasV6T2]> {
1656 let Inst{27-16} = 0b001100100000;
1657 let Inst{15-8} = 0b11110000;
1658 let Inst{7-0} = 0b00000010;
1661 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1662 Requires<[IsARM, HasV6T2]> {
1663 let Inst{27-16} = 0b001100100000;
1664 let Inst{15-8} = 0b11110000;
1665 let Inst{7-0} = 0b00000011;
1668 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1669 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1674 let Inst{15-12} = Rd;
1675 let Inst{19-16} = Rn;
1676 let Inst{27-20} = 0b01101000;
1677 let Inst{7-4} = 0b1011;
1678 let Inst{11-8} = 0b1111;
1681 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1682 []>, Requires<[IsARM, HasV6T2]> {
1683 let Inst{27-16} = 0b001100100000;
1684 let Inst{15-8} = 0b11110000;
1685 let Inst{7-0} = 0b00000100;
1688 // The i32imm operand $val can be used by a debugger to store more information
1689 // about the breakpoint.
1690 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1691 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1693 let Inst{3-0} = val{3-0};
1694 let Inst{19-8} = val{15-4};
1695 let Inst{27-20} = 0b00010010;
1696 let Inst{7-4} = 0b0111;
1699 // Change Processor State
1700 // FIXME: We should use InstAlias to handle the optional operands.
1701 class CPS<dag iops, string asm_ops>
1702 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1703 []>, Requires<[IsARM]> {
1709 let Inst{31-28} = 0b1111;
1710 let Inst{27-20} = 0b00010000;
1711 let Inst{19-18} = imod;
1712 let Inst{17} = M; // Enabled if mode is set;
1713 let Inst{16-9} = 0b00000000;
1714 let Inst{8-6} = iflags;
1716 let Inst{4-0} = mode;
1719 let DecoderMethod = "DecodeCPSInstruction" in {
1721 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1722 "$imod\t$iflags, $mode">;
1723 let mode = 0, M = 0 in
1724 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1726 let imod = 0, iflags = 0, M = 1 in
1727 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1730 // Preload signals the memory system of possible future data/instruction access.
1731 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1733 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1734 !strconcat(opc, "\t$addr"),
1735 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1738 let Inst{31-26} = 0b111101;
1739 let Inst{25} = 0; // 0 for immediate form
1740 let Inst{24} = data;
1741 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1742 let Inst{22} = read;
1743 let Inst{21-20} = 0b01;
1744 let Inst{19-16} = addr{16-13}; // Rn
1745 let Inst{15-12} = 0b1111;
1746 let Inst{11-0} = addr{11-0}; // imm12
1749 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1750 !strconcat(opc, "\t$shift"),
1751 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1753 let Inst{31-26} = 0b111101;
1754 let Inst{25} = 1; // 1 for register form
1755 let Inst{24} = data;
1756 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1757 let Inst{22} = read;
1758 let Inst{21-20} = 0b01;
1759 let Inst{19-16} = shift{16-13}; // Rn
1760 let Inst{15-12} = 0b1111;
1761 let Inst{11-0} = shift{11-0};
1766 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1767 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1768 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1770 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1771 "setend\t$end", []>, Requires<[IsARM]> {
1773 let Inst{31-10} = 0b1111000100000001000000;
1778 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1779 []>, Requires<[IsARM, HasV7]> {
1781 let Inst{27-4} = 0b001100100000111100001111;
1782 let Inst{3-0} = opt;
1785 // A5.4 Permanently UNDEFINED instructions.
1786 let isBarrier = 1, isTerminator = 1 in
1787 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1790 let Inst = 0xe7ffdefe;
1793 // Address computation and loads and stores in PIC mode.
1794 let isNotDuplicable = 1 in {
1795 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1797 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1799 let AddedComplexity = 10 in {
1800 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1802 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1804 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1806 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1808 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1810 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1812 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1814 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1816 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1818 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1820 let AddedComplexity = 10 in {
1821 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1822 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1824 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1825 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1826 addrmodepc:$addr)]>;
1828 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1829 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1831 } // isNotDuplicable = 1
1834 // LEApcrel - Load a pc-relative address into a register without offending the
1836 let neverHasSideEffects = 1, isReMaterializable = 1 in
1837 // The 'adr' mnemonic encodes differently if the label is before or after
1838 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1839 // know until then which form of the instruction will be used.
1840 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1841 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1844 let Inst{27-25} = 0b001;
1846 let Inst{23-22} = label{13-12};
1849 let Inst{19-16} = 0b1111;
1850 let Inst{15-12} = Rd;
1851 let Inst{11-0} = label{11-0};
1853 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1856 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1857 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1860 //===----------------------------------------------------------------------===//
1861 // Control Flow Instructions.
1864 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1866 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1867 "bx", "\tlr", [(ARMretflag)]>,
1868 Requires<[IsARM, HasV4T]> {
1869 let Inst{27-0} = 0b0001001011111111111100011110;
1873 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1874 "mov", "\tpc, lr", [(ARMretflag)]>,
1875 Requires<[IsARM, NoV4T]> {
1876 let Inst{27-0} = 0b0001101000001111000000001110;
1880 // Indirect branches
1881 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1883 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1884 [(brind GPR:$dst)]>,
1885 Requires<[IsARM, HasV4T]> {
1887 let Inst{31-4} = 0b1110000100101111111111110001;
1888 let Inst{3-0} = dst;
1891 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1892 "bx", "\t$dst", [/* pattern left blank */]>,
1893 Requires<[IsARM, HasV4T]> {
1895 let Inst{27-4} = 0b000100101111111111110001;
1896 let Inst{3-0} = dst;
1900 // SP is marked as a use to prevent stack-pointer assignments that appear
1901 // immediately before calls from potentially appearing dead.
1903 // FIXME: Do we really need a non-predicated version? If so, it should
1904 // at least be a pseudo instruction expanding to the predicated version
1905 // at MC lowering time.
1906 Defs = [LR], Uses = [SP] in {
1907 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1908 IIC_Br, "bl\t$func",
1909 [(ARMcall tglobaladdr:$func)]>,
1910 Requires<[IsARM, IsNotIOS]> {
1911 let Inst{31-28} = 0b1110;
1913 let Inst{23-0} = func;
1914 let DecoderMethod = "DecodeBranchImmInstruction";
1917 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1918 IIC_Br, "bl", "\t$func",
1919 [(ARMcall_pred tglobaladdr:$func)]>,
1920 Requires<[IsARM, IsNotIOS]> {
1922 let Inst{23-0} = func;
1923 let DecoderMethod = "DecodeBranchImmInstruction";
1927 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1928 IIC_Br, "blx\t$func",
1929 [(ARMcall GPR:$func)]>,
1930 Requires<[IsARM, HasV5T, IsNotIOS]> {
1932 let Inst{31-4} = 0b1110000100101111111111110011;
1933 let Inst{3-0} = func;
1936 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1937 IIC_Br, "blx", "\t$func",
1938 [(ARMcall_pred GPR:$func)]>,
1939 Requires<[IsARM, HasV5T, IsNotIOS]> {
1941 let Inst{27-4} = 0b000100101111111111110011;
1942 let Inst{3-0} = func;
1946 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1947 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1948 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1949 Requires<[IsARM, HasV4T, IsNotIOS]>;
1952 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1953 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1954 Requires<[IsARM, NoV4T, IsNotIOS]>;
1956 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1957 // return stack predictor.
1958 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1959 (ins bl_target:$func, variable_ops),
1960 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1961 Requires<[IsARM, IsNotIOS]>;
1965 // On IOS R9 is call-clobbered.
1966 // R7 is marked as a use to prevent frame-pointer assignments from being
1967 // moved above / below calls.
1968 Defs = [LR], Uses = [R7, SP] in {
1969 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1971 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1972 Requires<[IsARM, IsIOS]>;
1974 def BLr9_pred : ARMPseudoExpand<(outs),
1975 (ins bl_target:$func, pred:$p, variable_ops),
1977 [(ARMcall_pred tglobaladdr:$func)],
1978 (BL_pred bl_target:$func, pred:$p)>,
1979 Requires<[IsARM, IsIOS]>;
1982 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1984 [(ARMcall GPR:$func)],
1986 Requires<[IsARM, HasV5T, IsIOS]>;
1988 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1990 [(ARMcall_pred GPR:$func)],
1991 (BLX_pred GPR:$func, pred:$p)>,
1992 Requires<[IsARM, HasV5T, IsIOS]>;
1995 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1996 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1997 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1998 Requires<[IsARM, HasV4T, IsIOS]>;
2001 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
2002 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2003 Requires<[IsARM, NoV4T, IsIOS]>;
2005 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2006 // return stack predictor.
2007 def BMOVPCBr9_CALL : ARMPseudoInst<(outs),(ins bl_target:$func, variable_ops),
2008 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2009 Requires<[IsARM, IsIOS]>;
2012 let isBranch = 1, isTerminator = 1 in {
2013 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2014 // a two-value operand where a dag node expects two operands. :(
2015 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2016 IIC_Br, "b", "\t$target",
2017 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2019 let Inst{23-0} = target;
2020 let DecoderMethod = "DecodeBranchImmInstruction";
2023 let isBarrier = 1 in {
2024 // B is "predicable" since it's just a Bcc with an 'always' condition.
2025 let isPredicable = 1 in
2026 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2027 // should be sufficient.
2028 // FIXME: Is B really a Barrier? That doesn't seem right.
2029 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2030 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2032 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2033 def BR_JTr : ARMPseudoInst<(outs),
2034 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2036 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2037 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2038 // into i12 and rs suffixed versions.
2039 def BR_JTm : ARMPseudoInst<(outs),
2040 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2042 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2044 def BR_JTadd : ARMPseudoInst<(outs),
2045 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2047 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2049 } // isNotDuplicable = 1, isIndirectBranch = 1
2055 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2056 "blx\t$target", []>,
2057 Requires<[IsARM, HasV5T]> {
2058 let Inst{31-25} = 0b1111101;
2060 let Inst{23-0} = target{24-1};
2061 let Inst{24} = target{0};
2064 // Branch and Exchange Jazelle
2065 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2066 [/* pattern left blank */]> {
2068 let Inst{23-20} = 0b0010;
2069 let Inst{19-8} = 0xfff;
2070 let Inst{7-4} = 0b0010;
2071 let Inst{3-0} = func;
2076 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2078 let Uses = [SP] in {
2079 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2080 IIC_Br, []>, Requires<[IsIOS]>;
2082 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2083 IIC_Br, []>, Requires<[IsIOS]>;
2085 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2087 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2088 Requires<[IsARM, IsIOS]>;
2090 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2093 Requires<[IsARM, IsIOS]>;
2097 // Non-IOS versions (the difference is R9).
2098 let Uses = [SP] in {
2099 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2100 IIC_Br, []>, Requires<[IsNotIOS]>;
2102 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2103 IIC_Br, []>, Requires<[IsNotIOS]>;
2105 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2107 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2108 Requires<[IsARM, IsNotIOS]>;
2110 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2113 Requires<[IsARM, IsNotIOS]>;
2117 // Secure Monitor Call is a system instruction.
2118 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2121 let Inst{23-4} = 0b01100000000000000111;
2122 let Inst{3-0} = opt;
2125 // Supervisor Call (Software Interrupt)
2126 let isCall = 1, Uses = [SP] in {
2127 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2129 let Inst{23-0} = svc;
2133 // Store Return State
2134 class SRSI<bit wb, string asm>
2135 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2136 NoItinerary, asm, "", []> {
2138 let Inst{31-28} = 0b1111;
2139 let Inst{27-25} = 0b100;
2143 let Inst{19-16} = 0b1101; // SP
2144 let Inst{15-5} = 0b00000101000;
2145 let Inst{4-0} = mode;
2148 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2149 let Inst{24-23} = 0;
2151 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2152 let Inst{24-23} = 0;
2154 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2155 let Inst{24-23} = 0b10;
2157 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2158 let Inst{24-23} = 0b10;
2160 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2161 let Inst{24-23} = 0b01;
2163 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2164 let Inst{24-23} = 0b01;
2166 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2167 let Inst{24-23} = 0b11;
2169 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2170 let Inst{24-23} = 0b11;
2173 // Return From Exception
2174 class RFEI<bit wb, string asm>
2175 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2176 NoItinerary, asm, "", []> {
2178 let Inst{31-28} = 0b1111;
2179 let Inst{27-25} = 0b100;
2183 let Inst{19-16} = Rn;
2184 let Inst{15-0} = 0xa00;
2187 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2188 let Inst{24-23} = 0;
2190 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2191 let Inst{24-23} = 0;
2193 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2194 let Inst{24-23} = 0b10;
2196 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2197 let Inst{24-23} = 0b10;
2199 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2200 let Inst{24-23} = 0b01;
2202 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2203 let Inst{24-23} = 0b01;
2205 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2206 let Inst{24-23} = 0b11;
2208 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2209 let Inst{24-23} = 0b11;
2212 //===----------------------------------------------------------------------===//
2213 // Load / Store Instructions.
2219 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2220 UnOpFrag<(load node:$Src)>>;
2221 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2222 UnOpFrag<(zextloadi8 node:$Src)>>;
2223 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2224 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2225 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2226 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2228 // Special LDR for loads from non-pc-relative constpools.
2229 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2230 isReMaterializable = 1, isCodeGenOnly = 1 in
2231 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2232 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2236 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2237 let Inst{19-16} = 0b1111;
2238 let Inst{15-12} = Rt;
2239 let Inst{11-0} = addr{11-0}; // imm12
2242 // Loads with zero extension
2243 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2244 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2245 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2247 // Loads with sign extension
2248 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2249 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2250 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2252 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2253 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2254 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2256 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2258 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2259 (ins addrmode3:$addr), LdMiscFrm,
2260 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2261 []>, Requires<[IsARM, HasV5TE]>;
2265 multiclass AI2_ldridx<bit isByte, string opc,
2266 InstrItinClass iii, InstrItinClass iir> {
2267 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2268 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2269 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2272 let Inst{23} = addr{12};
2273 let Inst{19-16} = addr{16-13};
2274 let Inst{11-0} = addr{11-0};
2275 let DecoderMethod = "DecodeLDRPreImm";
2276 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2279 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2280 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2281 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2284 let Inst{23} = addr{12};
2285 let Inst{19-16} = addr{16-13};
2286 let Inst{11-0} = addr{11-0};
2288 let DecoderMethod = "DecodeLDRPreReg";
2289 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2292 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2293 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2294 IndexModePost, LdFrm, iir,
2295 opc, "\t$Rt, $addr, $offset",
2296 "$addr.base = $Rn_wb", []> {
2302 let Inst{23} = offset{12};
2303 let Inst{19-16} = addr;
2304 let Inst{11-0} = offset{11-0};
2306 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2309 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2310 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2311 IndexModePost, LdFrm, iii,
2312 opc, "\t$Rt, $addr, $offset",
2313 "$addr.base = $Rn_wb", []> {
2319 let Inst{23} = offset{12};
2320 let Inst{19-16} = addr;
2321 let Inst{11-0} = offset{11-0};
2323 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2328 let mayLoad = 1, neverHasSideEffects = 1 in {
2329 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2330 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2331 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2332 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2335 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2336 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2337 (ins addrmode3:$addr), IndexModePre,
2339 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2341 let Inst{23} = addr{8}; // U bit
2342 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2343 let Inst{19-16} = addr{12-9}; // Rn
2344 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2345 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2346 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2347 let DecoderMethod = "DecodeAddrMode3Instruction";
2349 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2350 (ins addr_offset_none:$addr, am3offset:$offset),
2351 IndexModePost, LdMiscFrm, itin,
2352 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2356 let Inst{23} = offset{8}; // U bit
2357 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2358 let Inst{19-16} = addr;
2359 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2360 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2361 let DecoderMethod = "DecodeAddrMode3Instruction";
2365 let mayLoad = 1, neverHasSideEffects = 1 in {
2366 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2367 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2368 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2369 let hasExtraDefRegAllocReq = 1 in {
2370 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2371 (ins addrmode3:$addr), IndexModePre,
2372 LdMiscFrm, IIC_iLoad_d_ru,
2373 "ldrd", "\t$Rt, $Rt2, $addr!",
2374 "$addr.base = $Rn_wb", []> {
2376 let Inst{23} = addr{8}; // U bit
2377 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2378 let Inst{19-16} = addr{12-9}; // Rn
2379 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2380 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2381 let DecoderMethod = "DecodeAddrMode3Instruction";
2382 let AsmMatchConverter = "cvtLdrdPre";
2384 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2385 (ins addr_offset_none:$addr, am3offset:$offset),
2386 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2387 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2388 "$addr.base = $Rn_wb", []> {
2391 let Inst{23} = offset{8}; // U bit
2392 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2393 let Inst{19-16} = addr;
2394 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2395 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2396 let DecoderMethod = "DecodeAddrMode3Instruction";
2398 } // hasExtraDefRegAllocReq = 1
2399 } // mayLoad = 1, neverHasSideEffects = 1
2401 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2402 let mayLoad = 1, neverHasSideEffects = 1 in {
2403 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2404 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2405 IndexModePost, LdFrm, IIC_iLoad_ru,
2406 "ldrt", "\t$Rt, $addr, $offset",
2407 "$addr.base = $Rn_wb", []> {
2413 let Inst{23} = offset{12};
2414 let Inst{21} = 1; // overwrite
2415 let Inst{19-16} = addr;
2416 let Inst{11-5} = offset{11-5};
2418 let Inst{3-0} = offset{3-0};
2419 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2422 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2423 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2424 IndexModePost, LdFrm, IIC_iLoad_ru,
2425 "ldrt", "\t$Rt, $addr, $offset",
2426 "$addr.base = $Rn_wb", []> {
2432 let Inst{23} = offset{12};
2433 let Inst{21} = 1; // overwrite
2434 let Inst{19-16} = addr;
2435 let Inst{11-0} = offset{11-0};
2436 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2439 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2440 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2441 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2442 "ldrbt", "\t$Rt, $addr, $offset",
2443 "$addr.base = $Rn_wb", []> {
2449 let Inst{23} = offset{12};
2450 let Inst{21} = 1; // overwrite
2451 let Inst{19-16} = addr;
2452 let Inst{11-5} = offset{11-5};
2454 let Inst{3-0} = offset{3-0};
2455 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2458 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2459 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2460 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2461 "ldrbt", "\t$Rt, $addr, $offset",
2462 "$addr.base = $Rn_wb", []> {
2468 let Inst{23} = offset{12};
2469 let Inst{21} = 1; // overwrite
2470 let Inst{19-16} = addr;
2471 let Inst{11-0} = offset{11-0};
2472 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2475 multiclass AI3ldrT<bits<4> op, string opc> {
2476 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2477 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2478 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2479 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2481 let Inst{23} = offset{8};
2483 let Inst{11-8} = offset{7-4};
2484 let Inst{3-0} = offset{3-0};
2485 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2487 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2488 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2489 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2490 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2492 let Inst{23} = Rm{4};
2495 let Inst{3-0} = Rm{3-0};
2496 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2500 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2501 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2502 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2507 // Stores with truncate
2508 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2509 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2510 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2513 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2514 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2515 StMiscFrm, IIC_iStore_d_r,
2516 "strd", "\t$Rt, $src2, $addr", []>,
2517 Requires<[IsARM, HasV5TE]> {
2522 multiclass AI2_stridx<bit isByte, string opc,
2523 InstrItinClass iii, InstrItinClass iir> {
2524 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2525 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2527 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2530 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2531 let Inst{19-16} = addr{16-13}; // Rn
2532 let Inst{11-0} = addr{11-0}; // imm12
2533 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2534 let DecoderMethod = "DecodeSTRPreImm";
2537 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2538 (ins GPR:$Rt, ldst_so_reg:$addr),
2539 IndexModePre, StFrm, iir,
2540 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2543 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2544 let Inst{19-16} = addr{16-13}; // Rn
2545 let Inst{11-0} = addr{11-0};
2546 let Inst{4} = 0; // Inst{4} = 0
2547 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2548 let DecoderMethod = "DecodeSTRPreReg";
2550 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2551 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2552 IndexModePost, StFrm, iir,
2553 opc, "\t$Rt, $addr, $offset",
2554 "$addr.base = $Rn_wb", []> {
2560 let Inst{23} = offset{12};
2561 let Inst{19-16} = addr;
2562 let Inst{11-0} = offset{11-0};
2564 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2567 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2568 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2569 IndexModePost, StFrm, iii,
2570 opc, "\t$Rt, $addr, $offset",
2571 "$addr.base = $Rn_wb", []> {
2577 let Inst{23} = offset{12};
2578 let Inst{19-16} = addr;
2579 let Inst{11-0} = offset{11-0};
2581 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2585 let mayStore = 1, neverHasSideEffects = 1 in {
2586 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2587 // IIC_iStore_siu depending on whether it the offset register is shifted.
2588 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2589 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2592 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2593 am2offset_reg:$offset),
2594 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2595 am2offset_reg:$offset)>;
2596 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2597 am2offset_imm:$offset),
2598 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2599 am2offset_imm:$offset)>;
2600 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2601 am2offset_reg:$offset),
2602 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2603 am2offset_reg:$offset)>;
2604 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2605 am2offset_imm:$offset),
2606 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2607 am2offset_imm:$offset)>;
2609 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2610 // put the patterns on the instruction definitions directly as ISel wants
2611 // the address base and offset to be separate operands, not a single
2612 // complex operand like we represent the instructions themselves. The
2613 // pseudos map between the two.
2614 let usesCustomInserter = 1,
2615 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2616 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2617 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2620 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2621 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2622 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2625 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2626 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2627 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2630 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2631 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2632 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2635 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2636 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2637 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2640 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2645 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2646 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2647 StMiscFrm, IIC_iStore_bh_ru,
2648 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2650 let Inst{23} = addr{8}; // U bit
2651 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2652 let Inst{19-16} = addr{12-9}; // Rn
2653 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2654 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2655 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2656 let DecoderMethod = "DecodeAddrMode3Instruction";
2659 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2660 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2661 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2662 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2663 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2664 addr_offset_none:$addr,
2665 am3offset:$offset))]> {
2668 let Inst{23} = offset{8}; // U bit
2669 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2670 let Inst{19-16} = addr;
2671 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2672 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2673 let DecoderMethod = "DecodeAddrMode3Instruction";
2676 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2677 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2678 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2679 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2680 "strd", "\t$Rt, $Rt2, $addr!",
2681 "$addr.base = $Rn_wb", []> {
2683 let Inst{23} = addr{8}; // U bit
2684 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2685 let Inst{19-16} = addr{12-9}; // Rn
2686 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2687 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2688 let DecoderMethod = "DecodeAddrMode3Instruction";
2689 let AsmMatchConverter = "cvtStrdPre";
2692 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2693 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2695 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2696 "strd", "\t$Rt, $Rt2, $addr, $offset",
2697 "$addr.base = $Rn_wb", []> {
2700 let Inst{23} = offset{8}; // U bit
2701 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2702 let Inst{19-16} = addr;
2703 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2704 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2705 let DecoderMethod = "DecodeAddrMode3Instruction";
2707 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2709 // STRT, STRBT, and STRHT
2711 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2712 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2713 IndexModePost, StFrm, IIC_iStore_bh_ru,
2714 "strbt", "\t$Rt, $addr, $offset",
2715 "$addr.base = $Rn_wb", []> {
2721 let Inst{23} = offset{12};
2722 let Inst{21} = 1; // overwrite
2723 let Inst{19-16} = addr;
2724 let Inst{11-5} = offset{11-5};
2726 let Inst{3-0} = offset{3-0};
2727 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2730 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2731 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2732 IndexModePost, StFrm, IIC_iStore_bh_ru,
2733 "strbt", "\t$Rt, $addr, $offset",
2734 "$addr.base = $Rn_wb", []> {
2740 let Inst{23} = offset{12};
2741 let Inst{21} = 1; // overwrite
2742 let Inst{19-16} = addr;
2743 let Inst{11-0} = offset{11-0};
2744 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2747 let mayStore = 1, neverHasSideEffects = 1 in {
2748 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2749 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2750 IndexModePost, StFrm, IIC_iStore_ru,
2751 "strt", "\t$Rt, $addr, $offset",
2752 "$addr.base = $Rn_wb", []> {
2758 let Inst{23} = offset{12};
2759 let Inst{21} = 1; // overwrite
2760 let Inst{19-16} = addr;
2761 let Inst{11-5} = offset{11-5};
2763 let Inst{3-0} = offset{3-0};
2764 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2767 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2768 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2769 IndexModePost, StFrm, IIC_iStore_ru,
2770 "strt", "\t$Rt, $addr, $offset",
2771 "$addr.base = $Rn_wb", []> {
2777 let Inst{23} = offset{12};
2778 let Inst{21} = 1; // overwrite
2779 let Inst{19-16} = addr;
2780 let Inst{11-0} = offset{11-0};
2781 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2786 multiclass AI3strT<bits<4> op, string opc> {
2787 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2788 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2789 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2790 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2792 let Inst{23} = offset{8};
2794 let Inst{11-8} = offset{7-4};
2795 let Inst{3-0} = offset{3-0};
2796 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2798 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2799 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2800 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2801 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2803 let Inst{23} = Rm{4};
2806 let Inst{3-0} = Rm{3-0};
2807 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2812 defm STRHT : AI3strT<0b1011, "strht">;
2815 //===----------------------------------------------------------------------===//
2816 // Load / store multiple Instructions.
2819 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2820 InstrItinClass itin, InstrItinClass itin_upd> {
2821 // IA is the default, so no need for an explicit suffix on the
2822 // mnemonic here. Without it is the cannonical spelling.
2824 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2825 IndexModeNone, f, itin,
2826 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2827 let Inst{24-23} = 0b01; // Increment After
2828 let Inst{22} = P_bit;
2829 let Inst{21} = 0; // No writeback
2830 let Inst{20} = L_bit;
2833 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2834 IndexModeUpd, f, itin_upd,
2835 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2836 let Inst{24-23} = 0b01; // Increment After
2837 let Inst{22} = P_bit;
2838 let Inst{21} = 1; // Writeback
2839 let Inst{20} = L_bit;
2841 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2844 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2845 IndexModeNone, f, itin,
2846 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2847 let Inst{24-23} = 0b00; // Decrement After
2848 let Inst{22} = P_bit;
2849 let Inst{21} = 0; // No writeback
2850 let Inst{20} = L_bit;
2853 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2854 IndexModeUpd, f, itin_upd,
2855 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2856 let Inst{24-23} = 0b00; // Decrement After
2857 let Inst{22} = P_bit;
2858 let Inst{21} = 1; // Writeback
2859 let Inst{20} = L_bit;
2861 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2864 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2865 IndexModeNone, f, itin,
2866 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2867 let Inst{24-23} = 0b10; // Decrement Before
2868 let Inst{22} = P_bit;
2869 let Inst{21} = 0; // No writeback
2870 let Inst{20} = L_bit;
2873 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2874 IndexModeUpd, f, itin_upd,
2875 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2876 let Inst{24-23} = 0b10; // Decrement Before
2877 let Inst{22} = P_bit;
2878 let Inst{21} = 1; // Writeback
2879 let Inst{20} = L_bit;
2881 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2884 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2885 IndexModeNone, f, itin,
2886 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2887 let Inst{24-23} = 0b11; // Increment Before
2888 let Inst{22} = P_bit;
2889 let Inst{21} = 0; // No writeback
2890 let Inst{20} = L_bit;
2893 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2894 IndexModeUpd, f, itin_upd,
2895 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2896 let Inst{24-23} = 0b11; // Increment Before
2897 let Inst{22} = P_bit;
2898 let Inst{21} = 1; // Writeback
2899 let Inst{20} = L_bit;
2901 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2905 let neverHasSideEffects = 1 in {
2907 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2908 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2911 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2912 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2915 } // neverHasSideEffects
2917 // FIXME: remove when we have a way to marking a MI with these properties.
2918 // FIXME: Should pc be an implicit operand like PICADD, etc?
2919 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2920 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2921 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2922 reglist:$regs, variable_ops),
2923 4, IIC_iLoad_mBr, [],
2924 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2925 RegConstraint<"$Rn = $wb">;
2927 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2928 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2931 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2932 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2937 //===----------------------------------------------------------------------===//
2938 // Move Instructions.
2941 let neverHasSideEffects = 1 in
2942 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2943 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2947 let Inst{19-16} = 0b0000;
2948 let Inst{11-4} = 0b00000000;
2951 let Inst{15-12} = Rd;
2954 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2955 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2957 // A version for the smaller set of tail call registers.
2958 let neverHasSideEffects = 1 in
2959 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2960 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2964 let Inst{11-4} = 0b00000000;
2967 let Inst{15-12} = Rd;
2970 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2971 DPSoRegRegFrm, IIC_iMOVsr,
2972 "mov", "\t$Rd, $src",
2973 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2976 let Inst{15-12} = Rd;
2977 let Inst{19-16} = 0b0000;
2978 let Inst{11-8} = src{11-8};
2980 let Inst{6-5} = src{6-5};
2982 let Inst{3-0} = src{3-0};
2986 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2987 DPSoRegImmFrm, IIC_iMOVsr,
2988 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2992 let Inst{15-12} = Rd;
2993 let Inst{19-16} = 0b0000;
2994 let Inst{11-5} = src{11-5};
2996 let Inst{3-0} = src{3-0};
3000 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3001 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3002 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
3006 let Inst{15-12} = Rd;
3007 let Inst{19-16} = 0b0000;
3008 let Inst{11-0} = imm;
3011 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3012 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3014 "movw", "\t$Rd, $imm",
3015 [(set GPR:$Rd, imm0_65535:$imm)]>,
3016 Requires<[IsARM, HasV6T2]>, UnaryDP {
3019 let Inst{15-12} = Rd;
3020 let Inst{11-0} = imm{11-0};
3021 let Inst{19-16} = imm{15-12};
3024 let DecoderMethod = "DecodeArmMOVTWInstruction";
3027 def : InstAlias<"mov${p} $Rd, $imm",
3028 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3031 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3032 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3034 let Constraints = "$src = $Rd" in {
3035 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3036 (ins GPR:$src, imm0_65535_expr:$imm),
3038 "movt", "\t$Rd, $imm",
3040 (or (and GPR:$src, 0xffff),
3041 lo16AllZero:$imm))]>, UnaryDP,
3042 Requires<[IsARM, HasV6T2]> {
3045 let Inst{15-12} = Rd;
3046 let Inst{11-0} = imm{11-0};
3047 let Inst{19-16} = imm{15-12};
3050 let DecoderMethod = "DecodeArmMOVTWInstruction";
3053 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3054 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3058 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3059 Requires<[IsARM, HasV6T2]>;
3061 let Uses = [CPSR] in
3062 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3063 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3066 // These aren't really mov instructions, but we have to define them this way
3067 // due to flag operands.
3069 let Defs = [CPSR] in {
3070 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3071 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3073 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3074 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3078 //===----------------------------------------------------------------------===//
3079 // Extend Instructions.
3084 def SXTB : AI_ext_rrot<0b01101010,
3085 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3086 def SXTH : AI_ext_rrot<0b01101011,
3087 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3089 def SXTAB : AI_exta_rrot<0b01101010,
3090 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3091 def SXTAH : AI_exta_rrot<0b01101011,
3092 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3094 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3096 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3100 let AddedComplexity = 16 in {
3101 def UXTB : AI_ext_rrot<0b01101110,
3102 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3103 def UXTH : AI_ext_rrot<0b01101111,
3104 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3105 def UXTB16 : AI_ext_rrot<0b01101100,
3106 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3108 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3109 // The transformation should probably be done as a combiner action
3110 // instead so we can include a check for masking back in the upper
3111 // eight bits of the source into the lower eight bits of the result.
3112 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3113 // (UXTB16r_rot GPR:$Src, 3)>;
3114 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3115 (UXTB16 GPR:$Src, 1)>;
3117 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3118 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3119 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3120 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3123 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3124 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3127 def SBFX : I<(outs GPRnopc:$Rd),
3128 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3129 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3130 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3131 Requires<[IsARM, HasV6T2]> {
3136 let Inst{27-21} = 0b0111101;
3137 let Inst{6-4} = 0b101;
3138 let Inst{20-16} = width;
3139 let Inst{15-12} = Rd;
3140 let Inst{11-7} = lsb;
3144 def UBFX : I<(outs GPR:$Rd),
3145 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3146 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3147 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3148 Requires<[IsARM, HasV6T2]> {
3153 let Inst{27-21} = 0b0111111;
3154 let Inst{6-4} = 0b101;
3155 let Inst{20-16} = width;
3156 let Inst{15-12} = Rd;
3157 let Inst{11-7} = lsb;
3161 //===----------------------------------------------------------------------===//
3162 // Arithmetic Instructions.
3165 defm ADD : AsI1_bin_irs<0b0100, "add",
3166 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3167 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3168 defm SUB : AsI1_bin_irs<0b0010, "sub",
3169 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3170 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3172 // ADD and SUB with 's' bit set.
3174 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3175 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3176 // AdjustInstrPostInstrSelection where we determine whether or not to
3177 // set the "s" bit based on CPSR liveness.
3179 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3180 // support for an optional CPSR definition that corresponds to the DAG
3181 // node's second value. We can then eliminate the implicit def of CPSR.
3182 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3183 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3184 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3185 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3187 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3188 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3190 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3191 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3194 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3195 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3196 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3198 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3199 // CPSR and the implicit def of CPSR is not needed.
3200 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3201 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3203 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3204 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3207 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3208 // The assume-no-carry-in form uses the negation of the input since add/sub
3209 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3210 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3212 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3213 (SUBri GPR:$src, so_imm_neg:$imm)>;
3214 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3215 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3217 // The with-carry-in form matches bitwise not instead of the negation.
3218 // Effectively, the inverse interpretation of the carry flag already accounts
3219 // for part of the negation.
3220 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3221 (SBCri GPR:$src, so_imm_not:$imm)>;
3223 // Note: These are implemented in C++ code, because they have to generate
3224 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3226 // (mul X, 2^n+1) -> (add (X << n), X)
3227 // (mul X, 2^n-1) -> (rsb X, (X << n))
3229 // ARM Arithmetic Instruction
3230 // GPR:$dst = GPR:$a op GPR:$b
3231 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3232 list<dag> pattern = [],
3233 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3234 string asm = "\t$Rd, $Rn, $Rm">
3235 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3239 let Inst{27-20} = op27_20;
3240 let Inst{11-4} = op11_4;
3241 let Inst{19-16} = Rn;
3242 let Inst{15-12} = Rd;
3246 // Saturating add/subtract
3248 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3249 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3250 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3251 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3252 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3253 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3254 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3255 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3257 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3258 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3261 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3262 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3263 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3264 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3265 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3266 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3267 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3268 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3269 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3270 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3271 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3272 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3274 // Signed/Unsigned add/subtract
3276 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3277 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3278 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3279 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3280 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3281 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3282 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3283 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3284 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3285 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3286 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3287 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3289 // Signed/Unsigned halving add/subtract
3291 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3292 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3293 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3294 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3295 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3296 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3297 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3298 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3299 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3300 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3301 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3302 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3304 // Unsigned Sum of Absolute Differences [and Accumulate].
3306 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3307 MulFrm /* for convenience */, NoItinerary, "usad8",
3308 "\t$Rd, $Rn, $Rm", []>,
3309 Requires<[IsARM, HasV6]> {
3313 let Inst{27-20} = 0b01111000;
3314 let Inst{15-12} = 0b1111;
3315 let Inst{7-4} = 0b0001;
3316 let Inst{19-16} = Rd;
3317 let Inst{11-8} = Rm;
3320 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3321 MulFrm /* for convenience */, NoItinerary, "usada8",
3322 "\t$Rd, $Rn, $Rm, $Ra", []>,
3323 Requires<[IsARM, HasV6]> {
3328 let Inst{27-20} = 0b01111000;
3329 let Inst{7-4} = 0b0001;
3330 let Inst{19-16} = Rd;
3331 let Inst{15-12} = Ra;
3332 let Inst{11-8} = Rm;
3336 // Signed/Unsigned saturate
3338 def SSAT : AI<(outs GPRnopc:$Rd),
3339 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3340 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3345 let Inst{27-21} = 0b0110101;
3346 let Inst{5-4} = 0b01;
3347 let Inst{20-16} = sat_imm;
3348 let Inst{15-12} = Rd;
3349 let Inst{11-7} = sh{4-0};
3350 let Inst{6} = sh{5};
3354 def SSAT16 : AI<(outs GPRnopc:$Rd),
3355 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3356 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3360 let Inst{27-20} = 0b01101010;
3361 let Inst{11-4} = 0b11110011;
3362 let Inst{15-12} = Rd;
3363 let Inst{19-16} = sat_imm;
3367 def USAT : AI<(outs GPRnopc:$Rd),
3368 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3369 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3374 let Inst{27-21} = 0b0110111;
3375 let Inst{5-4} = 0b01;
3376 let Inst{15-12} = Rd;
3377 let Inst{11-7} = sh{4-0};
3378 let Inst{6} = sh{5};
3379 let Inst{20-16} = sat_imm;
3383 def USAT16 : AI<(outs GPRnopc:$Rd),
3384 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3385 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3389 let Inst{27-20} = 0b01101110;
3390 let Inst{11-4} = 0b11110011;
3391 let Inst{15-12} = Rd;
3392 let Inst{19-16} = sat_imm;
3396 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3397 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3398 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3399 (USAT imm:$pos, GPRnopc:$a, 0)>;
3401 //===----------------------------------------------------------------------===//
3402 // Bitwise Instructions.
3405 defm AND : AsI1_bin_irs<0b0000, "and",
3406 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3407 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3408 defm ORR : AsI1_bin_irs<0b1100, "orr",
3409 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3410 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3411 defm EOR : AsI1_bin_irs<0b0001, "eor",
3412 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3413 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3414 defm BIC : AsI1_bin_irs<0b1110, "bic",
3415 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3416 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3418 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3419 // like in the actual instruction encoding. The complexity of mapping the mask
3420 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3421 // instruction description.
3422 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3423 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3424 "bfc", "\t$Rd, $imm", "$src = $Rd",
3425 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3426 Requires<[IsARM, HasV6T2]> {
3429 let Inst{27-21} = 0b0111110;
3430 let Inst{6-0} = 0b0011111;
3431 let Inst{15-12} = Rd;
3432 let Inst{11-7} = imm{4-0}; // lsb
3433 let Inst{20-16} = imm{9-5}; // msb
3436 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3437 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3438 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3439 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3440 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3441 bf_inv_mask_imm:$imm))]>,
3442 Requires<[IsARM, HasV6T2]> {
3446 let Inst{27-21} = 0b0111110;
3447 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3448 let Inst{15-12} = Rd;
3449 let Inst{11-7} = imm{4-0}; // lsb
3450 let Inst{20-16} = imm{9-5}; // width
3454 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3455 "mvn", "\t$Rd, $Rm",
3456 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3460 let Inst{19-16} = 0b0000;
3461 let Inst{11-4} = 0b00000000;
3462 let Inst{15-12} = Rd;
3465 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3466 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3467 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3471 let Inst{19-16} = 0b0000;
3472 let Inst{15-12} = Rd;
3473 let Inst{11-5} = shift{11-5};
3475 let Inst{3-0} = shift{3-0};
3477 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3478 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3479 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3483 let Inst{19-16} = 0b0000;
3484 let Inst{15-12} = Rd;
3485 let Inst{11-8} = shift{11-8};
3487 let Inst{6-5} = shift{6-5};
3489 let Inst{3-0} = shift{3-0};
3491 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3492 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3493 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3494 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3498 let Inst{19-16} = 0b0000;
3499 let Inst{15-12} = Rd;
3500 let Inst{11-0} = imm;
3503 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3504 (BICri GPR:$src, so_imm_not:$imm)>;
3506 //===----------------------------------------------------------------------===//
3507 // Multiply Instructions.
3509 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3510 string opc, string asm, list<dag> pattern>
3511 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3515 let Inst{19-16} = Rd;
3516 let Inst{11-8} = Rm;
3519 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3520 string opc, string asm, list<dag> pattern>
3521 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3526 let Inst{19-16} = RdHi;
3527 let Inst{15-12} = RdLo;
3528 let Inst{11-8} = Rm;
3532 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3533 // property. Remove them when it's possible to add those properties
3534 // on an individual MachineInstr, not just an instuction description.
3535 let isCommutable = 1 in {
3536 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3537 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3538 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3539 Requires<[IsARM, HasV6]> {
3540 let Inst{15-12} = 0b0000;
3543 let Constraints = "@earlyclobber $Rd" in
3544 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3545 pred:$p, cc_out:$s),
3547 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3548 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3549 Requires<[IsARM, NoV6]>;
3552 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3553 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3554 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3555 Requires<[IsARM, HasV6]> {
3557 let Inst{15-12} = Ra;
3560 let Constraints = "@earlyclobber $Rd" in
3561 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3562 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3564 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3565 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3566 Requires<[IsARM, NoV6]>;
3568 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3569 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3570 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3571 Requires<[IsARM, HasV6T2]> {
3576 let Inst{19-16} = Rd;
3577 let Inst{15-12} = Ra;
3578 let Inst{11-8} = Rm;
3582 // Extra precision multiplies with low / high results
3583 let neverHasSideEffects = 1 in {
3584 let isCommutable = 1 in {
3585 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3586 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3587 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3588 Requires<[IsARM, HasV6]>;
3590 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3591 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3592 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3593 Requires<[IsARM, HasV6]>;
3595 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3596 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3597 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3599 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3600 Requires<[IsARM, NoV6]>;
3602 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3603 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3605 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3606 Requires<[IsARM, NoV6]>;
3610 // Multiply + accumulate
3611 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3612 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3613 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3614 Requires<[IsARM, HasV6]>;
3615 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3616 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3617 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3618 Requires<[IsARM, HasV6]>;
3620 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3621 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3622 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3623 Requires<[IsARM, HasV6]> {
3628 let Inst{19-16} = RdHi;
3629 let Inst{15-12} = RdLo;
3630 let Inst{11-8} = Rm;
3634 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3635 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3636 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3638 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3639 Requires<[IsARM, NoV6]>;
3640 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3641 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3643 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3644 Requires<[IsARM, NoV6]>;
3645 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3646 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3648 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3649 Requires<[IsARM, NoV6]>;
3652 } // neverHasSideEffects
3654 // Most significant word multiply
3655 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3656 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3657 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3658 Requires<[IsARM, HasV6]> {
3659 let Inst{15-12} = 0b1111;
3662 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3663 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3664 Requires<[IsARM, HasV6]> {
3665 let Inst{15-12} = 0b1111;
3668 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3669 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3670 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3671 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3672 Requires<[IsARM, HasV6]>;
3674 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3675 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3676 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3677 Requires<[IsARM, HasV6]>;
3679 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3680 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3681 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3682 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3683 Requires<[IsARM, HasV6]>;
3685 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3686 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3687 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3688 Requires<[IsARM, HasV6]>;
3690 multiclass AI_smul<string opc, PatFrag opnode> {
3691 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3692 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3693 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3694 (sext_inreg GPR:$Rm, i16)))]>,
3695 Requires<[IsARM, HasV5TE]>;
3697 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3698 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3699 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3700 (sra GPR:$Rm, (i32 16))))]>,
3701 Requires<[IsARM, HasV5TE]>;
3703 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3704 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3705 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3706 (sext_inreg GPR:$Rm, i16)))]>,
3707 Requires<[IsARM, HasV5TE]>;
3709 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3710 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3711 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3712 (sra GPR:$Rm, (i32 16))))]>,
3713 Requires<[IsARM, HasV5TE]>;
3715 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3716 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3717 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3718 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3719 Requires<[IsARM, HasV5TE]>;
3721 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3722 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3723 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3724 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3725 Requires<[IsARM, HasV5TE]>;
3729 multiclass AI_smla<string opc, PatFrag opnode> {
3730 let DecoderMethod = "DecodeSMLAInstruction" in {
3731 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3732 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3733 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3734 [(set GPRnopc:$Rd, (add GPR:$Ra,
3735 (opnode (sext_inreg GPRnopc:$Rn, i16),
3736 (sext_inreg GPRnopc:$Rm, i16))))]>,
3737 Requires<[IsARM, HasV5TE]>;
3739 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3740 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3741 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3743 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3744 (sra GPRnopc:$Rm, (i32 16)))))]>,
3745 Requires<[IsARM, HasV5TE]>;
3747 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3748 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3749 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3751 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3752 (sext_inreg GPRnopc:$Rm, i16))))]>,
3753 Requires<[IsARM, HasV5TE]>;
3755 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3756 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3757 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3759 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3760 (sra GPRnopc:$Rm, (i32 16)))))]>,
3761 Requires<[IsARM, HasV5TE]>;
3763 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3764 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3765 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3767 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3768 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3769 Requires<[IsARM, HasV5TE]>;
3771 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3772 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3773 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3775 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3776 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3777 Requires<[IsARM, HasV5TE]>;
3781 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3782 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3784 // Halfword multiply accumulate long: SMLAL<x><y>.
3785 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3786 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3787 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3788 Requires<[IsARM, HasV5TE]>;
3790 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3791 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3792 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3793 Requires<[IsARM, HasV5TE]>;
3795 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3796 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3797 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3798 Requires<[IsARM, HasV5TE]>;
3800 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3801 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3802 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3803 Requires<[IsARM, HasV5TE]>;
3805 // Helper class for AI_smld.
3806 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3807 InstrItinClass itin, string opc, string asm>
3808 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3811 let Inst{27-23} = 0b01110;
3812 let Inst{22} = long;
3813 let Inst{21-20} = 0b00;
3814 let Inst{11-8} = Rm;
3821 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3822 InstrItinClass itin, string opc, string asm>
3823 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3825 let Inst{15-12} = 0b1111;
3826 let Inst{19-16} = Rd;
3828 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3829 InstrItinClass itin, string opc, string asm>
3830 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3833 let Inst{19-16} = Rd;
3834 let Inst{15-12} = Ra;
3836 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3837 InstrItinClass itin, string opc, string asm>
3838 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3841 let Inst{19-16} = RdHi;
3842 let Inst{15-12} = RdLo;
3845 multiclass AI_smld<bit sub, string opc> {
3847 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3848 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3849 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3851 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3852 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3853 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3855 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3856 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3857 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3859 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3860 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3861 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3865 defm SMLA : AI_smld<0, "smla">;
3866 defm SMLS : AI_smld<1, "smls">;
3868 multiclass AI_sdml<bit sub, string opc> {
3870 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3871 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3872 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3873 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3876 defm SMUA : AI_sdml<0, "smua">;
3877 defm SMUS : AI_sdml<1, "smus">;
3879 //===----------------------------------------------------------------------===//
3880 // Misc. Arithmetic Instructions.
3883 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3884 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3885 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3887 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3888 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3889 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3890 Requires<[IsARM, HasV6T2]>;
3892 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3893 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3894 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3896 let AddedComplexity = 5 in
3897 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3898 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3899 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3900 Requires<[IsARM, HasV6]>;
3902 let AddedComplexity = 5 in
3903 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3904 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3905 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3906 Requires<[IsARM, HasV6]>;
3908 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3909 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3912 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3913 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3914 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3915 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3916 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3918 Requires<[IsARM, HasV6]>;
3920 // Alternate cases for PKHBT where identities eliminate some nodes.
3921 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3922 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3923 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3924 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3926 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3927 // will match the pattern below.
3928 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3929 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3930 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3931 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3932 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3934 Requires<[IsARM, HasV6]>;
3936 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3937 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3938 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3939 (srl GPRnopc:$src2, imm16_31:$sh)),
3940 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3941 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3942 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3943 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3945 //===----------------------------------------------------------------------===//
3946 // Comparison Instructions...
3949 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3950 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3951 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3953 // ARMcmpZ can re-use the above instruction definitions.
3954 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3955 (CMPri GPR:$src, so_imm:$imm)>;
3956 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3957 (CMPrr GPR:$src, GPR:$rhs)>;
3958 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3959 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3960 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3961 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3963 // FIXME: We have to be careful when using the CMN instruction and comparison
3964 // with 0. One would expect these two pieces of code should give identical
3980 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3981 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3982 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3983 // value of r0 and the carry bit (because the "carry bit" parameter to
3984 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3985 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3986 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3987 // parameter to AddWithCarry is defined as 0).
3989 // When x is 0 and unsigned:
3993 // ~x + 1 = 0x1 0000 0000
3994 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3996 // Therefore, we should disable CMN when comparing against zero, until we can
3997 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3998 // when it's a comparison which doesn't look at the 'carry' flag).
4000 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
4002 // This is related to <rdar://problem/7569620>.
4004 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
4005 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
4007 // Note that TST/TEQ don't set all the same flags that CMP does!
4008 defm TST : AI1_cmp_irs<0b1000, "tst",
4009 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4010 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4011 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4012 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4013 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4015 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
4016 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4017 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
4019 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4020 // (CMNri GPR:$src, so_imm_neg:$imm)>;
4022 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4023 (CMNzri GPR:$src, so_imm_neg:$imm)>;
4025 // Pseudo i64 compares for some floating point compares.
4026 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4028 def BCCi64 : PseudoInst<(outs),
4029 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4031 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4033 def BCCZi64 : PseudoInst<(outs),
4034 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4035 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4036 } // usesCustomInserter
4039 // Conditional moves
4040 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4041 // a two-value operand where a dag node expects two operands. :(
4042 let neverHasSideEffects = 1 in {
4043 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4045 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4046 RegConstraint<"$false = $Rd">;
4047 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4048 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4050 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4051 imm:$cc, CCR:$ccr))*/]>,
4052 RegConstraint<"$false = $Rd">;
4053 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4054 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4056 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4057 imm:$cc, CCR:$ccr))*/]>,
4058 RegConstraint<"$false = $Rd">;
4061 let isMoveImm = 1 in
4062 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4063 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4066 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4068 let isMoveImm = 1 in
4069 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4070 (ins GPR:$false, so_imm:$imm, pred:$p),
4072 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4073 RegConstraint<"$false = $Rd">;
4075 // Two instruction predicate mov immediate.
4076 let isMoveImm = 1 in
4077 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4078 (ins GPR:$false, i32imm:$src, pred:$p),
4079 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4081 let isMoveImm = 1 in
4082 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4083 (ins GPR:$false, so_imm:$imm, pred:$p),
4085 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4086 RegConstraint<"$false = $Rd">;
4088 let isCodeGenOnly = 1 in {
4089 // Conditional instructions
4090 multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
4091 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
4092 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
4093 iii, opc, "\t$Rd, $Rn, $imm", []>,
4094 RegConstraint<"$Rn = $Rd"> {
4099 let Inst{19-16} = Rn;
4100 let Inst{15-12} = Rd;
4101 let Inst{11-0} = imm;
4103 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
4104 iir, opc, "\t$Rd, $Rn, $Rm", []>,
4105 RegConstraint<"$Rn = $Rd"> {
4110 let Inst{19-16} = Rn;
4111 let Inst{15-12} = Rd;
4112 let Inst{11-4} = 0b00000000;
4116 def rsi : AsI1<opcod, (outs GPR:$Rd),
4117 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
4118 iis, opc, "\t$Rd, $Rn, $shift", []>,
4119 RegConstraint<"$Rn = $Rd"> {
4124 let Inst{19-16} = Rn;
4125 let Inst{15-12} = Rd;
4126 let Inst{11-5} = shift{11-5};
4128 let Inst{3-0} = shift{3-0};
4131 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
4132 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
4133 iis, opc, "\t$Rd, $Rn, $shift", []>,
4134 RegConstraint<"$Rn = $Rd"> {
4139 let Inst{19-16} = Rn;
4140 let Inst{15-12} = Rd;
4141 let Inst{11-8} = shift{11-8};
4143 let Inst{6-5} = shift{6-5};
4145 let Inst{3-0} = shift{3-0};
4149 defm ANDCC : AsI1_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4150 defm ORRCC : AsI1_bincc_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4151 defm EORCC : AsI1_bincc_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4154 } // neverHasSideEffects
4156 //===----------------------------------------------------------------------===//
4157 // Atomic operations intrinsics
4160 def MemBarrierOptOperand : AsmOperandClass {
4161 let Name = "MemBarrierOpt";
4162 let ParserMethod = "parseMemBarrierOptOperand";
4164 def memb_opt : Operand<i32> {
4165 let PrintMethod = "printMemBOption";
4166 let ParserMatchClass = MemBarrierOptOperand;
4167 let DecoderMethod = "DecodeMemBarrierOption";
4170 // memory barriers protect the atomic sequences
4171 let hasSideEffects = 1 in {
4172 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4173 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4174 Requires<[IsARM, HasDB]> {
4176 let Inst{31-4} = 0xf57ff05;
4177 let Inst{3-0} = opt;
4181 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4182 "dsb", "\t$opt", []>,
4183 Requires<[IsARM, HasDB]> {
4185 let Inst{31-4} = 0xf57ff04;
4186 let Inst{3-0} = opt;
4189 // ISB has only full system option
4190 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4191 "isb", "\t$opt", []>,
4192 Requires<[IsARM, HasDB]> {
4194 let Inst{31-4} = 0xf57ff06;
4195 let Inst{3-0} = opt;
4198 // Pseudo isntruction that combines movs + predicated rsbmi
4199 // to implement integer ABS
4200 let usesCustomInserter = 1, Defs = [CPSR] in {
4201 def ABS : ARMPseudoInst<
4202 (outs GPR:$dst), (ins GPR:$src),
4203 8, NoItinerary, []>;
4206 let usesCustomInserter = 1 in {
4207 let Defs = [CPSR] in {
4208 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4209 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4210 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4211 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4212 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4213 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4214 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4215 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4216 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4217 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4218 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4219 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4220 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4221 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4222 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4223 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4224 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4225 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4226 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4227 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4228 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4229 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4230 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4231 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4232 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4233 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4234 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4235 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4236 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4237 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4238 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4239 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4240 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4241 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4242 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4243 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4244 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4245 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4246 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4247 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4248 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4249 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4250 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4251 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4252 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4253 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4254 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4255 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4256 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4257 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4258 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4259 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4261 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4262 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4264 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4265 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4267 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4268 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4270 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4271 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4273 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4274 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4276 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4277 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4279 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4280 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4282 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4283 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4285 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4286 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4288 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4289 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4291 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4292 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4294 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4295 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4297 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4299 def ATOMIC_SWAP_I8 : PseudoInst<
4300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4301 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4302 def ATOMIC_SWAP_I16 : PseudoInst<
4303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4304 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4305 def ATOMIC_SWAP_I32 : PseudoInst<
4306 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4307 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4309 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4311 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4312 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4314 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4315 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4316 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4317 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4321 let mayLoad = 1 in {
4322 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4324 "ldrexb", "\t$Rt, $addr", []>;
4325 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4326 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4327 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4328 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4329 let hasExtraDefRegAllocReq = 1 in
4330 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4331 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4332 let DecoderMethod = "DecodeDoubleRegLoad";
4336 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4337 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4338 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4339 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4340 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4341 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4342 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4343 let hasExtraSrcRegAllocReq = 1 in
4344 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4345 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4346 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4347 let DecoderMethod = "DecodeDoubleRegStore";
4352 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4353 Requires<[IsARM, HasV7]> {
4354 let Inst{31-0} = 0b11110101011111111111000000011111;
4357 // SWP/SWPB are deprecated in V6/V7.
4358 let mayLoad = 1, mayStore = 1 in {
4359 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4361 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4365 //===----------------------------------------------------------------------===//
4366 // Coprocessor Instructions.
4369 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4370 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4371 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4372 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4373 imm:$CRm, imm:$opc2)]> {
4381 let Inst{3-0} = CRm;
4383 let Inst{7-5} = opc2;
4384 let Inst{11-8} = cop;
4385 let Inst{15-12} = CRd;
4386 let Inst{19-16} = CRn;
4387 let Inst{23-20} = opc1;
4390 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4391 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4392 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4393 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4394 imm:$CRm, imm:$opc2)]> {
4395 let Inst{31-28} = 0b1111;
4403 let Inst{3-0} = CRm;
4405 let Inst{7-5} = opc2;
4406 let Inst{11-8} = cop;
4407 let Inst{15-12} = CRd;
4408 let Inst{19-16} = CRn;
4409 let Inst{23-20} = opc1;
4412 class ACI<dag oops, dag iops, string opc, string asm,
4413 IndexMode im = IndexModeNone>
4414 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4416 let Inst{27-25} = 0b110;
4418 class ACInoP<dag oops, dag iops, string opc, string asm,
4419 IndexMode im = IndexModeNone>
4420 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4422 let Inst{31-28} = 0b1111;
4423 let Inst{27-25} = 0b110;
4425 multiclass LdStCop<bit load, bit Dbit, string asm> {
4426 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4427 asm, "\t$cop, $CRd, $addr"> {
4431 let Inst{24} = 1; // P = 1
4432 let Inst{23} = addr{8};
4433 let Inst{22} = Dbit;
4434 let Inst{21} = 0; // W = 0
4435 let Inst{20} = load;
4436 let Inst{19-16} = addr{12-9};
4437 let Inst{15-12} = CRd;
4438 let Inst{11-8} = cop;
4439 let Inst{7-0} = addr{7-0};
4440 let DecoderMethod = "DecodeCopMemInstruction";
4442 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4443 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4447 let Inst{24} = 1; // P = 1
4448 let Inst{23} = addr{8};
4449 let Inst{22} = Dbit;
4450 let Inst{21} = 1; // W = 1
4451 let Inst{20} = load;
4452 let Inst{19-16} = addr{12-9};
4453 let Inst{15-12} = CRd;
4454 let Inst{11-8} = cop;
4455 let Inst{7-0} = addr{7-0};
4456 let DecoderMethod = "DecodeCopMemInstruction";
4458 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4459 postidx_imm8s4:$offset),
4460 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4465 let Inst{24} = 0; // P = 0
4466 let Inst{23} = offset{8};
4467 let Inst{22} = Dbit;
4468 let Inst{21} = 1; // W = 1
4469 let Inst{20} = load;
4470 let Inst{19-16} = addr;
4471 let Inst{15-12} = CRd;
4472 let Inst{11-8} = cop;
4473 let Inst{7-0} = offset{7-0};
4474 let DecoderMethod = "DecodeCopMemInstruction";
4476 def _OPTION : ACI<(outs),
4477 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4478 coproc_option_imm:$option),
4479 asm, "\t$cop, $CRd, $addr, $option"> {
4484 let Inst{24} = 0; // P = 0
4485 let Inst{23} = 1; // U = 1
4486 let Inst{22} = Dbit;
4487 let Inst{21} = 0; // W = 0
4488 let Inst{20} = load;
4489 let Inst{19-16} = addr;
4490 let Inst{15-12} = CRd;
4491 let Inst{11-8} = cop;
4492 let Inst{7-0} = option;
4493 let DecoderMethod = "DecodeCopMemInstruction";
4496 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4497 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4498 asm, "\t$cop, $CRd, $addr"> {
4502 let Inst{24} = 1; // P = 1
4503 let Inst{23} = addr{8};
4504 let Inst{22} = Dbit;
4505 let Inst{21} = 0; // W = 0
4506 let Inst{20} = load;
4507 let Inst{19-16} = addr{12-9};
4508 let Inst{15-12} = CRd;
4509 let Inst{11-8} = cop;
4510 let Inst{7-0} = addr{7-0};
4511 let DecoderMethod = "DecodeCopMemInstruction";
4513 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4514 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4518 let Inst{24} = 1; // P = 1
4519 let Inst{23} = addr{8};
4520 let Inst{22} = Dbit;
4521 let Inst{21} = 1; // W = 1
4522 let Inst{20} = load;
4523 let Inst{19-16} = addr{12-9};
4524 let Inst{15-12} = CRd;
4525 let Inst{11-8} = cop;
4526 let Inst{7-0} = addr{7-0};
4527 let DecoderMethod = "DecodeCopMemInstruction";
4529 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4530 postidx_imm8s4:$offset),
4531 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4536 let Inst{24} = 0; // P = 0
4537 let Inst{23} = offset{8};
4538 let Inst{22} = Dbit;
4539 let Inst{21} = 1; // W = 1
4540 let Inst{20} = load;
4541 let Inst{19-16} = addr;
4542 let Inst{15-12} = CRd;
4543 let Inst{11-8} = cop;
4544 let Inst{7-0} = offset{7-0};
4545 let DecoderMethod = "DecodeCopMemInstruction";
4547 def _OPTION : ACInoP<(outs),
4548 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4549 coproc_option_imm:$option),
4550 asm, "\t$cop, $CRd, $addr, $option"> {
4555 let Inst{24} = 0; // P = 0
4556 let Inst{23} = 1; // U = 1
4557 let Inst{22} = Dbit;
4558 let Inst{21} = 0; // W = 0
4559 let Inst{20} = load;
4560 let Inst{19-16} = addr;
4561 let Inst{15-12} = CRd;
4562 let Inst{11-8} = cop;
4563 let Inst{7-0} = option;
4564 let DecoderMethod = "DecodeCopMemInstruction";
4568 defm LDC : LdStCop <1, 0, "ldc">;
4569 defm LDCL : LdStCop <1, 1, "ldcl">;
4570 defm STC : LdStCop <0, 0, "stc">;
4571 defm STCL : LdStCop <0, 1, "stcl">;
4572 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4573 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4574 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4575 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4577 //===----------------------------------------------------------------------===//
4578 // Move between coprocessor and ARM core register.
4581 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4583 : ABI<0b1110, oops, iops, NoItinerary, opc,
4584 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4585 let Inst{20} = direction;
4595 let Inst{15-12} = Rt;
4596 let Inst{11-8} = cop;
4597 let Inst{23-21} = opc1;
4598 let Inst{7-5} = opc2;
4599 let Inst{3-0} = CRm;
4600 let Inst{19-16} = CRn;
4603 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4605 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4606 c_imm:$CRm, imm0_7:$opc2),
4607 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4608 imm:$CRm, imm:$opc2)]>;
4609 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4610 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4611 c_imm:$CRm, 0, pred:$p)>;
4612 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4614 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4616 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4617 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4618 c_imm:$CRm, 0, pred:$p)>;
4620 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4621 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4623 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4625 : ABXI<0b1110, oops, iops, NoItinerary,
4626 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4627 let Inst{31-28} = 0b1111;
4628 let Inst{20} = direction;
4638 let Inst{15-12} = Rt;
4639 let Inst{11-8} = cop;
4640 let Inst{23-21} = opc1;
4641 let Inst{7-5} = opc2;
4642 let Inst{3-0} = CRm;
4643 let Inst{19-16} = CRn;
4646 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4648 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4649 c_imm:$CRm, imm0_7:$opc2),
4650 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4651 imm:$CRm, imm:$opc2)]>;
4652 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4653 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4655 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4657 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4659 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4660 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4663 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4664 imm:$CRm, imm:$opc2),
4665 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4667 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4668 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4669 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4670 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4671 let Inst{23-21} = 0b010;
4672 let Inst{20} = direction;
4680 let Inst{15-12} = Rt;
4681 let Inst{19-16} = Rt2;
4682 let Inst{11-8} = cop;
4683 let Inst{7-4} = opc1;
4684 let Inst{3-0} = CRm;
4687 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4688 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4690 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4692 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4693 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4694 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4695 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4696 let Inst{31-28} = 0b1111;
4697 let Inst{23-21} = 0b010;
4698 let Inst{20} = direction;
4706 let Inst{15-12} = Rt;
4707 let Inst{19-16} = Rt2;
4708 let Inst{11-8} = cop;
4709 let Inst{7-4} = opc1;
4710 let Inst{3-0} = CRm;
4713 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4714 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4716 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4718 //===----------------------------------------------------------------------===//
4719 // Move between special register and ARM core register
4722 // Move to ARM core register from Special Register
4723 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4724 "mrs", "\t$Rd, apsr", []> {
4726 let Inst{23-16} = 0b00001111;
4727 let Inst{15-12} = Rd;
4728 let Inst{7-4} = 0b0000;
4731 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4733 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4734 "mrs", "\t$Rd, spsr", []> {
4736 let Inst{23-16} = 0b01001111;
4737 let Inst{15-12} = Rd;
4738 let Inst{7-4} = 0b0000;
4741 // Move from ARM core register to Special Register
4743 // No need to have both system and application versions, the encodings are the
4744 // same and the assembly parser has no way to distinguish between them. The mask
4745 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4746 // the mask with the fields to be accessed in the special register.
4747 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4748 "msr", "\t$mask, $Rn", []> {
4753 let Inst{22} = mask{4}; // R bit
4754 let Inst{21-20} = 0b10;
4755 let Inst{19-16} = mask{3-0};
4756 let Inst{15-12} = 0b1111;
4757 let Inst{11-4} = 0b00000000;
4761 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4762 "msr", "\t$mask, $a", []> {
4767 let Inst{22} = mask{4}; // R bit
4768 let Inst{21-20} = 0b10;
4769 let Inst{19-16} = mask{3-0};
4770 let Inst{15-12} = 0b1111;
4774 //===----------------------------------------------------------------------===//
4778 // __aeabi_read_tp preserves the registers r1-r3.
4779 // This is a pseudo inst so that we can get the encoding right,
4780 // complete with fixup for the aeabi_read_tp function.
4782 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4783 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4784 [(set R0, ARMthread_pointer)]>;
4787 //===----------------------------------------------------------------------===//
4788 // SJLJ Exception handling intrinsics
4789 // eh_sjlj_setjmp() is an instruction sequence to store the return
4790 // address and save #0 in R0 for the non-longjmp case.
4791 // Since by its nature we may be coming from some other function to get
4792 // here, and we're using the stack frame for the containing function to
4793 // save/restore registers, we can't keep anything live in regs across
4794 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4795 // when we get here from a longjmp(). We force everything out of registers
4796 // except for our own input by listing the relevant registers in Defs. By
4797 // doing so, we also cause the prologue/epilogue code to actively preserve
4798 // all of the callee-saved resgisters, which is exactly what we want.
4799 // A constant value is passed in $val, and we use the location as a scratch.
4801 // These are pseudo-instructions and are lowered to individual MC-insts, so
4802 // no encoding information is necessary.
4804 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4805 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4806 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4807 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4809 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4810 Requires<[IsARM, HasVFP2]>;
4814 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4815 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4816 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4818 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4819 Requires<[IsARM, NoVFP]>;
4822 // FIXME: Non-IOS version(s)
4823 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4824 Defs = [ R7, LR, SP ] in {
4825 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4827 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4828 Requires<[IsARM, IsIOS]>;
4831 // eh.sjlj.dispatchsetup pseudo-instructions.
4832 // These pseudos are used for both ARM and Thumb2. Any differences are
4833 // handled when the pseudo is expanded (which happens before any passes
4834 // that need the instruction size).
4836 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4837 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4839 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4842 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4844 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4847 //===----------------------------------------------------------------------===//
4848 // Non-Instruction Patterns
4851 // ARMv4 indirect branch using (MOVr PC, dst)
4852 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4853 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4854 4, IIC_Br, [(brind GPR:$dst)],
4855 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4856 Requires<[IsARM, NoV4T]>;
4858 // Large immediate handling.
4860 // 32-bit immediate using two piece so_imms or movw + movt.
4861 // This is a single pseudo instruction, the benefit is that it can be remat'd
4862 // as a single unit instead of having to handle reg inputs.
4863 // FIXME: Remove this when we can do generalized remat.
4864 let isReMaterializable = 1, isMoveImm = 1 in
4865 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4866 [(set GPR:$dst, (arm_i32imm:$src))]>,
4869 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4870 // It also makes it possible to rematerialize the instructions.
4871 // FIXME: Remove this when we can do generalized remat and when machine licm
4872 // can properly the instructions.
4873 let isReMaterializable = 1 in {
4874 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4876 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4877 Requires<[IsARM, UseMovt]>;
4879 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4881 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4882 Requires<[IsARM, UseMovt]>;
4884 let AddedComplexity = 10 in
4885 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4887 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4888 Requires<[IsARM, UseMovt]>;
4889 } // isReMaterializable
4891 // ConstantPool, GlobalAddress, and JumpTable
4892 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4893 Requires<[IsARM, DontUseMovt]>;
4894 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4895 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4896 Requires<[IsARM, UseMovt]>;
4897 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4898 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4900 // TODO: add,sub,and, 3-instr forms?
4903 def : ARMPat<(ARMtcret tcGPR:$dst),
4904 (TCRETURNri tcGPR:$dst)>, Requires<[IsIOS]>;
4906 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4907 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4909 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4910 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4912 def : ARMPat<(ARMtcret tcGPR:$dst),
4913 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotIOS]>;
4915 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4916 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4918 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4919 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4922 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4923 Requires<[IsARM, IsNotIOS]>;
4924 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4925 Requires<[IsARM, IsIOS]>;
4926 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4927 (BMOVPCB_CALL texternalsym:$func)>,
4928 Requires<[IsARM, IsNotIOS]>;
4929 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4930 (BMOVPCBr9_CALL texternalsym:$func)>,
4931 Requires<[IsARM, IsIOS]>;
4933 // zextload i1 -> zextload i8
4934 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4935 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4937 // extload -> zextload
4938 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4939 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4940 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4941 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4943 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4945 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4946 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4949 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4950 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4951 (SMULBB GPR:$a, GPR:$b)>;
4952 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4953 (SMULBB GPR:$a, GPR:$b)>;
4954 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4955 (sra GPR:$b, (i32 16))),
4956 (SMULBT GPR:$a, GPR:$b)>;
4957 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4958 (SMULBT GPR:$a, GPR:$b)>;
4959 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4960 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4961 (SMULTB GPR:$a, GPR:$b)>;
4962 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4963 (SMULTB GPR:$a, GPR:$b)>;
4964 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4966 (SMULWB GPR:$a, GPR:$b)>;
4967 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4968 (SMULWB GPR:$a, GPR:$b)>;
4970 def : ARMV5TEPat<(add GPR:$acc,
4971 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4972 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4973 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4974 def : ARMV5TEPat<(add GPR:$acc,
4975 (mul sext_16_node:$a, sext_16_node:$b)),
4976 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4977 def : ARMV5TEPat<(add GPR:$acc,
4978 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4979 (sra GPR:$b, (i32 16)))),
4980 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4981 def : ARMV5TEPat<(add GPR:$acc,
4982 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4983 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4984 def : ARMV5TEPat<(add GPR:$acc,
4985 (mul (sra GPR:$a, (i32 16)),
4986 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4987 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4988 def : ARMV5TEPat<(add GPR:$acc,
4989 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4990 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4991 def : ARMV5TEPat<(add GPR:$acc,
4992 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4994 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4995 def : ARMV5TEPat<(add GPR:$acc,
4996 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4997 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5000 // Pre-v7 uses MCR for synchronization barriers.
5001 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5002 Requires<[IsARM, HasV6]>;
5004 // SXT/UXT with no rotate
5005 let AddedComplexity = 16 in {
5006 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5007 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5008 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5009 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5010 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5011 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5012 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5015 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5016 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5018 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5019 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5020 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5021 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5023 // Atomic load/store patterns
5024 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5025 (LDRBrs ldst_so_reg:$src)>;
5026 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5027 (LDRBi12 addrmode_imm12:$src)>;
5028 def : ARMPat<(atomic_load_16 addrmode3:$src),
5029 (LDRH addrmode3:$src)>;
5030 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5031 (LDRrs ldst_so_reg:$src)>;
5032 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5033 (LDRi12 addrmode_imm12:$src)>;
5034 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5035 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5036 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5037 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5038 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5039 (STRH GPR:$val, addrmode3:$ptr)>;
5040 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5041 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5042 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5043 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5046 //===----------------------------------------------------------------------===//
5050 include "ARMInstrThumb.td"
5052 //===----------------------------------------------------------------------===//
5056 include "ARMInstrThumb2.td"
5058 //===----------------------------------------------------------------------===//
5059 // Floating Point Support
5062 include "ARMInstrVFP.td"
5064 //===----------------------------------------------------------------------===//
5065 // Advanced SIMD (NEON) Support
5068 include "ARMInstrNEON.td"
5070 //===----------------------------------------------------------------------===//
5071 // Assembler aliases
5075 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5076 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5077 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5079 // System instructions
5080 def : MnemonicAlias<"swi", "svc">;
5082 // Load / Store Multiple
5083 def : MnemonicAlias<"ldmfd", "ldm">;
5084 def : MnemonicAlias<"ldmia", "ldm">;
5085 def : MnemonicAlias<"ldmea", "ldmdb">;
5086 def : MnemonicAlias<"stmfd", "stmdb">;
5087 def : MnemonicAlias<"stmia", "stm">;
5088 def : MnemonicAlias<"stmea", "stm">;
5090 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5091 // shift amount is zero (i.e., unspecified).
5092 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5093 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5094 Requires<[IsARM, HasV6]>;
5095 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5096 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5097 Requires<[IsARM, HasV6]>;
5099 // PUSH/POP aliases for STM/LDM
5100 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5101 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5103 // SSAT/USAT optional shift operand.
5104 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5105 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5106 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5107 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5110 // Extend instruction optional rotate operand.
5111 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5112 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5113 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5114 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5115 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5116 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5117 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5118 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5119 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5120 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5121 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5122 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5124 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5125 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5126 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5127 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5128 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5129 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5130 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5131 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5132 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5133 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5134 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5135 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5139 def : MnemonicAlias<"rfefa", "rfeda">;
5140 def : MnemonicAlias<"rfeea", "rfedb">;
5141 def : MnemonicAlias<"rfefd", "rfeia">;
5142 def : MnemonicAlias<"rfeed", "rfeib">;
5143 def : MnemonicAlias<"rfe", "rfeia">;
5146 def : MnemonicAlias<"srsfa", "srsda">;
5147 def : MnemonicAlias<"srsea", "srsdb">;
5148 def : MnemonicAlias<"srsfd", "srsia">;
5149 def : MnemonicAlias<"srsed", "srsib">;
5150 def : MnemonicAlias<"srs", "srsia">;
5153 def : MnemonicAlias<"qsubaddx", "qsax">;
5155 def : MnemonicAlias<"saddsubx", "sasx">;
5156 // SHASX == SHADDSUBX
5157 def : MnemonicAlias<"shaddsubx", "shasx">;
5158 // SHSAX == SHSUBADDX
5159 def : MnemonicAlias<"shsubaddx", "shsax">;
5161 def : MnemonicAlias<"ssubaddx", "ssax">;
5163 def : MnemonicAlias<"uaddsubx", "uasx">;
5164 // UHASX == UHADDSUBX
5165 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5166 // UHSAX == UHSUBADDX
5167 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5168 // UQASX == UQADDSUBX
5169 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5170 // UQSAX == UQSUBADDX
5171 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5173 def : MnemonicAlias<"usubaddx", "usax">;
5175 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5177 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5178 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5179 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5180 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5181 // Same for AND <--> BIC
5182 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5183 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5184 pred:$p, cc_out:$s)>;
5185 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5186 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5187 pred:$p, cc_out:$s)>;
5188 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5189 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5190 pred:$p, cc_out:$s)>;
5191 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5192 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5193 pred:$p, cc_out:$s)>;
5195 // Likewise, "add Rd, so_imm_neg" -> sub
5196 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5197 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5198 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5199 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5200 // Same for CMP <--> CMN via so_imm_neg
5201 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5202 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5203 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5204 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5206 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5207 // LSR, ROR, and RRX instructions.
5208 // FIXME: We need C++ parser hooks to map the alias to the MOV
5209 // encoding. It seems we should be able to do that sort of thing
5210 // in tblgen, but it could get ugly.
5211 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5212 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5214 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5215 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5217 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5218 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5220 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5221 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5223 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5224 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5225 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5226 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5228 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5229 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5231 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5232 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5234 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5235 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5237 // shifter instructions also support a two-operand form.
5238 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
5239 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5240 def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
5241 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5242 def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
5243 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5244 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
5245 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5246 def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
5247 (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5249 def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
5250 (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5252 def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
5253 (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5255 def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
5256 (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5260 // 'mul' instruction can be specified with only two operands.
5261 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
5262 (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
5264 // "neg" is and alias for "rsb rd, rn, #0"
5265 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5266 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5268 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5269 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5270 Requires<[IsARM, NoV6]>;
5272 // UMULL/SMULL are available on all arches, but the instruction definitions
5273 // need difference constraints pre-v6. Use these aliases for the assembly
5274 // parsing on pre-v6.
5275 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5276 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5277 Requires<[IsARM, NoV6]>;
5278 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5279 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5280 Requires<[IsARM, NoV6]>;
5282 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5284 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;