1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
62 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
76 def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
77 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
80 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
83 SDTCisInt<0>, SDTCisVT<1, i32>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
86 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
93 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
94 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
96 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
97 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
100 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
101 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
102 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
104 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
106 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
107 [SDNPHasChain, SDNPSideEffect,
108 SDNPOptInGlue, SDNPOutGlue]>;
109 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
112 SDNPMayStore, SDNPMayLoad]>;
114 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
124 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
131 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
134 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
136 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
139 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
142 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
145 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
149 [SDNPOutGlue, SDNPCommutative]>;
151 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
153 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
154 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
155 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
157 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
159 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
160 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
163 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
164 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
165 SDT_ARMEH_SJLJ_Setjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
168 SDT_ARMEH_SJLJ_Longjmp,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
171 SDT_ARMEH_SJLJ_SetupDispatch,
172 [SDNPHasChain, SDNPSideEffect]>;
174 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
175 [SDNPHasChain, SDNPSideEffect]>;
176 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
177 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
179 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
181 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
182 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
184 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
186 def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
187 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
188 SDNPMayStore, SDNPMayLoad]>;
190 //===----------------------------------------------------------------------===//
191 // ARM Instruction Predicate Definitions.
193 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
194 AssemblerPredicate<"HasV4TOps", "armv4t">;
195 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
196 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
197 AssemblerPredicate<"HasV5TOps", "armv5t">;
198 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
199 AssemblerPredicate<"HasV5TEOps", "armv5te">;
200 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
201 AssemblerPredicate<"HasV6Ops", "armv6">;
202 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
203 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
204 AssemblerPredicate<"HasV6MOps",
205 "armv6m or armv6t2">;
206 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
207 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
208 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
209 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
210 AssemblerPredicate<"HasV6KOps", "armv6k">;
211 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
212 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
213 AssemblerPredicate<"HasV7Ops", "armv7">;
214 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
215 AssemblerPredicate<"HasV8Ops", "armv8">;
216 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
217 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
218 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
219 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
220 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
221 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
222 AssemblerPredicate<"FeatureVFP2", "VFP2">;
223 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
224 AssemblerPredicate<"FeatureVFP3", "VFP3">;
225 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
226 AssemblerPredicate<"FeatureVFP4", "VFP4">;
227 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
228 AssemblerPredicate<"!FeatureVFPOnlySP",
229 "double precision VFP">;
230 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
231 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
232 def HasNEON : Predicate<"Subtarget->hasNEON()">,
233 AssemblerPredicate<"FeatureNEON", "NEON">;
234 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
235 AssemblerPredicate<"FeatureCrypto", "crypto">;
236 def HasCRC : Predicate<"Subtarget->hasCRC()">,
237 AssemblerPredicate<"FeatureCRC", "crc">;
238 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
239 AssemblerPredicate<"FeatureFP16","half-float">;
240 def HasDivide : Predicate<"Subtarget->hasDivide()">,
241 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
242 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
243 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
244 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
245 AssemblerPredicate<"FeatureT2XtPk",
247 def HasDSP : Predicate<"Subtarget->hasDSP()">,
248 AssemblerPredicate<"FeatureDSP", "dsp">;
249 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
250 AssemblerPredicate<"FeatureDB",
252 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
253 AssemblerPredicate<"FeatureMP",
255 def HasVirtualization: Predicate<"false">,
256 AssemblerPredicate<"FeatureVirtualization",
257 "virtualization-extensions">;
258 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
259 AssemblerPredicate<"FeatureTrustZone",
261 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
262 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
263 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
264 def IsThumb : Predicate<"Subtarget->isThumb()">,
265 AssemblerPredicate<"ModeThumb", "thumb">;
266 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
267 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
268 AssemblerPredicate<"ModeThumb,FeatureThumb2",
270 def IsMClass : Predicate<"Subtarget->isMClass()">,
271 AssemblerPredicate<"FeatureMClass", "armv*m">;
272 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
273 AssemblerPredicate<"!FeatureMClass",
275 def IsARM : Predicate<"!Subtarget->isThumb()">,
276 AssemblerPredicate<"!ModeThumb", "arm-mode">;
277 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
278 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
279 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
280 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
281 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
282 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
284 // FIXME: Eventually this will be just "hasV6T2Ops".
285 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
286 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
287 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
288 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
290 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
291 // But only select them if more precision in FP computation is allowed.
292 // Do not use them for Darwin platforms.
293 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
294 " FPOpFusion::Fast && "
295 " Subtarget->hasVFP4()) && "
296 "!Subtarget->isTargetDarwin()">;
297 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
298 " FPOpFusion::Fast &&"
299 " Subtarget->hasVFP4()) || "
300 "Subtarget->isTargetDarwin()">;
302 // VGETLNi32 is microcoded on Swift - prefer VMOV.
303 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
304 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
306 // VDUP.32 is microcoded on Swift - prefer VMOV.
307 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
308 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
310 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
311 // this allows more effective execution domain optimization. See
312 // setExecutionDomain().
313 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
314 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
316 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
317 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
319 //===----------------------------------------------------------------------===//
320 // ARM Flag Definitions.
322 class RegConstraint<string C> {
323 string Constraints = C;
326 //===----------------------------------------------------------------------===//
327 // ARM specific transformation functions and pattern fragments.
330 // imm_neg_XFORM - Return the negation of an i32 immediate value.
331 def imm_neg_XFORM : SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
335 // imm_not_XFORM - Return the complement of a i32 immediate value.
336 def imm_not_XFORM : SDNodeXForm<imm, [{
337 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
340 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
341 def imm16_31 : ImmLeaf<i32, [{
342 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
345 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
346 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
347 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
350 /// Split a 32-bit immediate into two 16 bit parts.
351 def hi16 : SDNodeXForm<imm, [{
352 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
356 def lo16AllZero : PatLeaf<(i32 imm), [{
357 // Returns true if all low 16-bits are 0.
358 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
361 class BinOpWithFlagFrag<dag res> :
362 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
363 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
364 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
366 // An 'and' node with a single use.
367 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
368 return N->hasOneUse();
371 // An 'xor' node with a single use.
372 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
373 return N->hasOneUse();
376 // An 'fmul' node with a single use.
377 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
378 return N->hasOneUse();
381 // An 'fadd' node which checks for single non-hazardous use.
382 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
383 return hasNoVMLxHazardUse(N);
386 // An 'fsub' node which checks for single non-hazardous use.
387 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
388 return hasNoVMLxHazardUse(N);
391 //===----------------------------------------------------------------------===//
392 // Operand Definitions.
395 // Immediate operands with a shared generic asm render method.
396 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
398 // Operands that are part of a memory addressing mode.
399 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
402 // FIXME: rename brtarget to t2_brtarget
403 def brtarget : Operand<OtherVT> {
404 let EncoderMethod = "getBranchTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
406 let DecoderMethod = "DecodeT2BROperand";
409 // FIXME: get rid of this one?
410 def uncondbrtarget : Operand<OtherVT> {
411 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
412 let OperandType = "OPERAND_PCREL";
415 // Branch target for ARM. Handles conditional/unconditional
416 def br_target : Operand<OtherVT> {
417 let EncoderMethod = "getARMBranchTargetOpValue";
418 let OperandType = "OPERAND_PCREL";
422 // FIXME: rename bltarget to t2_bl_target?
423 def bltarget : Operand<i32> {
424 // Encoded the same as branch targets.
425 let EncoderMethod = "getBranchTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 // Call target for ARM. Handles conditional/unconditional
430 // FIXME: rename bl_target to t2_bltarget?
431 def bl_target : Operand<i32> {
432 let EncoderMethod = "getARMBLTargetOpValue";
433 let OperandType = "OPERAND_PCREL";
436 def blx_target : Operand<i32> {
437 let EncoderMethod = "getARMBLXTargetOpValue";
438 let OperandType = "OPERAND_PCREL";
441 // A list of registers separated by comma. Used by load/store multiple.
442 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
443 def reglist : Operand<i32> {
444 let EncoderMethod = "getRegisterListOpValue";
445 let ParserMatchClass = RegListAsmOperand;
446 let PrintMethod = "printRegisterList";
447 let DecoderMethod = "DecodeRegListOperand";
450 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
452 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
453 def dpr_reglist : Operand<i32> {
454 let EncoderMethod = "getRegisterListOpValue";
455 let ParserMatchClass = DPRRegListAsmOperand;
456 let PrintMethod = "printRegisterList";
457 let DecoderMethod = "DecodeDPRRegListOperand";
460 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
461 def spr_reglist : Operand<i32> {
462 let EncoderMethod = "getRegisterListOpValue";
463 let ParserMatchClass = SPRRegListAsmOperand;
464 let PrintMethod = "printRegisterList";
465 let DecoderMethod = "DecodeSPRRegListOperand";
468 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
469 def cpinst_operand : Operand<i32> {
470 let PrintMethod = "printCPInstOperand";
474 def pclabel : Operand<i32> {
475 let PrintMethod = "printPCLabel";
478 // ADR instruction labels.
479 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
480 def adrlabel : Operand<i32> {
481 let EncoderMethod = "getAdrLabelOpValue";
482 let ParserMatchClass = AdrLabelAsmOperand;
483 let PrintMethod = "printAdrLabelOperand<0>";
486 def neon_vcvt_imm32 : Operand<i32> {
487 let EncoderMethod = "getNEONVcvtImm32OpValue";
488 let DecoderMethod = "DecodeVCVTImmOperand";
491 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
492 def rot_imm_XFORM: SDNodeXForm<imm, [{
493 switch (N->getZExtValue()){
494 default: llvm_unreachable(nullptr);
495 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
496 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
497 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
498 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
501 def RotImmAsmOperand : AsmOperandClass {
503 let ParserMethod = "parseRotImm";
505 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
506 int32_t v = N->getZExtValue();
507 return v == 8 || v == 16 || v == 24; }],
509 let PrintMethod = "printRotImmOperand";
510 let ParserMatchClass = RotImmAsmOperand;
513 // shift_imm: An integer that encodes a shift amount and the type of shift
514 // (asr or lsl). The 6-bit immediate encodes as:
517 // {4-0} imm5 shift amount.
518 // asr #32 encoded as imm5 == 0.
519 def ShifterImmAsmOperand : AsmOperandClass {
520 let Name = "ShifterImm";
521 let ParserMethod = "parseShifterImm";
523 def shift_imm : Operand<i32> {
524 let PrintMethod = "printShiftImmOperand";
525 let ParserMatchClass = ShifterImmAsmOperand;
528 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
529 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
530 def so_reg_reg : Operand<i32>, // reg reg imm
531 ComplexPattern<i32, 3, "SelectRegShifterOperand",
532 [shl, srl, sra, rotr]> {
533 let EncoderMethod = "getSORegRegOpValue";
534 let PrintMethod = "printSORegRegOperand";
535 let DecoderMethod = "DecodeSORegRegOperand";
536 let ParserMatchClass = ShiftedRegAsmOperand;
537 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
540 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
541 def so_reg_imm : Operand<i32>, // reg imm
542 ComplexPattern<i32, 2, "SelectImmShifterOperand",
543 [shl, srl, sra, rotr]> {
544 let EncoderMethod = "getSORegImmOpValue";
545 let PrintMethod = "printSORegImmOperand";
546 let DecoderMethod = "DecodeSORegImmOperand";
547 let ParserMatchClass = ShiftedImmAsmOperand;
548 let MIOperandInfo = (ops GPR, i32imm);
551 // FIXME: Does this need to be distinct from so_reg?
552 def shift_so_reg_reg : Operand<i32>, // reg reg imm
553 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
554 [shl,srl,sra,rotr]> {
555 let EncoderMethod = "getSORegRegOpValue";
556 let PrintMethod = "printSORegRegOperand";
557 let DecoderMethod = "DecodeSORegRegOperand";
558 let ParserMatchClass = ShiftedRegAsmOperand;
559 let MIOperandInfo = (ops GPR, GPR, i32imm);
562 // FIXME: Does this need to be distinct from so_reg?
563 def shift_so_reg_imm : Operand<i32>, // reg reg imm
564 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
565 [shl,srl,sra,rotr]> {
566 let EncoderMethod = "getSORegImmOpValue";
567 let PrintMethod = "printSORegImmOperand";
568 let DecoderMethod = "DecodeSORegImmOperand";
569 let ParserMatchClass = ShiftedImmAsmOperand;
570 let MIOperandInfo = (ops GPR, i32imm);
573 // mod_imm: match a 32-bit immediate operand, which can be encoded into
574 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
575 // - "Modified Immediate Constants"). Within the MC layer we keep this
576 // immediate in its encoded form.
577 def ModImmAsmOperand: AsmOperandClass {
579 let ParserMethod = "parseModImm";
581 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
582 return ARM_AM::getSOImmVal(Imm) != -1;
584 let EncoderMethod = "getModImmOpValue";
585 let PrintMethod = "printModImmOperand";
586 let ParserMatchClass = ModImmAsmOperand;
589 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
590 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
591 // The actual parsing, encoding, decoding are handled by the destination
592 // instructions, which use mod_imm.
594 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
595 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
596 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
598 let ParserMatchClass = ModImmNotAsmOperand;
601 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
602 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
603 unsigned Value = -(unsigned)N->getZExtValue();
604 return Value && ARM_AM::getSOImmVal(Value) != -1;
606 let ParserMatchClass = ModImmNegAsmOperand;
609 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
610 def arm_i32imm : PatLeaf<(imm), [{
611 if (Subtarget->useMovt(*MF))
613 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
616 /// imm0_1 predicate - Immediate in the range [0,1].
617 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
618 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
620 /// imm0_3 predicate - Immediate in the range [0,3].
621 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
622 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
624 /// imm0_7 predicate - Immediate in the range [0,7].
625 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
626 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
627 return Imm >= 0 && Imm < 8;
629 let ParserMatchClass = Imm0_7AsmOperand;
632 /// imm8 predicate - Immediate is exactly 8.
633 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
634 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
635 let ParserMatchClass = Imm8AsmOperand;
638 /// imm16 predicate - Immediate is exactly 16.
639 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
640 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
641 let ParserMatchClass = Imm16AsmOperand;
644 /// imm32 predicate - Immediate is exactly 32.
645 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
646 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
647 let ParserMatchClass = Imm32AsmOperand;
650 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
652 /// imm1_7 predicate - Immediate in the range [1,7].
653 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
654 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
655 let ParserMatchClass = Imm1_7AsmOperand;
658 /// imm1_15 predicate - Immediate in the range [1,15].
659 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
660 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
661 let ParserMatchClass = Imm1_15AsmOperand;
664 /// imm1_31 predicate - Immediate in the range [1,31].
665 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
666 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
667 let ParserMatchClass = Imm1_31AsmOperand;
670 /// imm0_15 predicate - Immediate in the range [0,15].
671 def Imm0_15AsmOperand: ImmAsmOperand {
672 let Name = "Imm0_15";
673 let DiagnosticType = "ImmRange0_15";
675 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
676 return Imm >= 0 && Imm < 16;
678 let ParserMatchClass = Imm0_15AsmOperand;
681 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
682 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
683 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
684 return Imm >= 0 && Imm < 32;
686 let ParserMatchClass = Imm0_31AsmOperand;
689 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
690 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
691 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
692 return Imm >= 0 && Imm < 32;
694 let ParserMatchClass = Imm0_32AsmOperand;
697 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
698 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
699 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
700 return Imm >= 0 && Imm < 64;
702 let ParserMatchClass = Imm0_63AsmOperand;
705 /// imm0_239 predicate - Immediate in the range [0,239].
706 def Imm0_239AsmOperand : ImmAsmOperand {
707 let Name = "Imm0_239";
708 let DiagnosticType = "ImmRange0_239";
710 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
711 let ParserMatchClass = Imm0_239AsmOperand;
714 /// imm0_255 predicate - Immediate in the range [0,255].
715 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
716 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
717 let ParserMatchClass = Imm0_255AsmOperand;
720 /// imm0_65535 - An immediate is in the range [0.65535].
721 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
722 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
723 return Imm >= 0 && Imm < 65536;
725 let ParserMatchClass = Imm0_65535AsmOperand;
728 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
729 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
730 return -Imm >= 0 && -Imm < 65536;
733 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
734 // a relocatable expression.
736 // FIXME: This really needs a Thumb version separate from the ARM version.
737 // While the range is the same, and can thus use the same match class,
738 // the encoding is different so it should have a different encoder method.
739 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
740 def imm0_65535_expr : Operand<i32> {
741 let EncoderMethod = "getHiLo16ImmOpValue";
742 let ParserMatchClass = Imm0_65535ExprAsmOperand;
745 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
746 def imm256_65535_expr : Operand<i32> {
747 let ParserMatchClass = Imm256_65535ExprAsmOperand;
750 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
751 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
752 def imm24b : Operand<i32>, ImmLeaf<i32, [{
753 return Imm >= 0 && Imm <= 0xffffff;
755 let ParserMatchClass = Imm24bitAsmOperand;
759 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
761 def BitfieldAsmOperand : AsmOperandClass {
762 let Name = "Bitfield";
763 let ParserMethod = "parseBitfield";
766 def bf_inv_mask_imm : Operand<i32>,
768 return ARM::isBitFieldInvertedMask(N->getZExtValue());
770 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
771 let PrintMethod = "printBitfieldInvMaskImmOperand";
772 let DecoderMethod = "DecodeBitfieldMaskOperand";
773 let ParserMatchClass = BitfieldAsmOperand;
776 def imm1_32_XFORM: SDNodeXForm<imm, [{
777 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
780 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
781 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
782 uint64_t Imm = N->getZExtValue();
783 return Imm > 0 && Imm <= 32;
786 let PrintMethod = "printImmPlusOneOperand";
787 let ParserMatchClass = Imm1_32AsmOperand;
790 def imm1_16_XFORM: SDNodeXForm<imm, [{
791 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
794 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
795 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
797 let PrintMethod = "printImmPlusOneOperand";
798 let ParserMatchClass = Imm1_16AsmOperand;
801 // Define ARM specific addressing modes.
802 // addrmode_imm12 := reg +/- imm12
804 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
805 class AddrMode_Imm12 : MemOperand,
806 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
807 // 12-bit immediate operand. Note that instructions using this encode
808 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
809 // immediate values are as normal.
811 let EncoderMethod = "getAddrModeImm12OpValue";
812 let DecoderMethod = "DecodeAddrModeImm12Operand";
813 let ParserMatchClass = MemImm12OffsetAsmOperand;
814 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
817 def addrmode_imm12 : AddrMode_Imm12 {
818 let PrintMethod = "printAddrModeImm12Operand<false>";
821 def addrmode_imm12_pre : AddrMode_Imm12 {
822 let PrintMethod = "printAddrModeImm12Operand<true>";
825 // ldst_so_reg := reg +/- reg shop imm
827 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
828 def ldst_so_reg : MemOperand,
829 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
830 let EncoderMethod = "getLdStSORegOpValue";
831 // FIXME: Simplify the printer
832 let PrintMethod = "printAddrMode2Operand";
833 let DecoderMethod = "DecodeSORegMemOperand";
834 let ParserMatchClass = MemRegOffsetAsmOperand;
835 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
838 // postidx_imm8 := +/- [0,255]
841 // {8} 1 is imm8 is non-negative. 0 otherwise.
842 // {7-0} [0,255] imm8 value.
843 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
844 def postidx_imm8 : MemOperand {
845 let PrintMethod = "printPostIdxImm8Operand";
846 let ParserMatchClass = PostIdxImm8AsmOperand;
847 let MIOperandInfo = (ops i32imm);
850 // postidx_imm8s4 := +/- [0,1020]
853 // {8} 1 is imm8 is non-negative. 0 otherwise.
854 // {7-0} [0,255] imm8 value, scaled by 4.
855 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
856 def postidx_imm8s4 : MemOperand {
857 let PrintMethod = "printPostIdxImm8s4Operand";
858 let ParserMatchClass = PostIdxImm8s4AsmOperand;
859 let MIOperandInfo = (ops i32imm);
863 // postidx_reg := +/- reg
865 def PostIdxRegAsmOperand : AsmOperandClass {
866 let Name = "PostIdxReg";
867 let ParserMethod = "parsePostIdxReg";
869 def postidx_reg : MemOperand {
870 let EncoderMethod = "getPostIdxRegOpValue";
871 let DecoderMethod = "DecodePostIdxReg";
872 let PrintMethod = "printPostIdxRegOperand";
873 let ParserMatchClass = PostIdxRegAsmOperand;
874 let MIOperandInfo = (ops GPRnopc, i32imm);
878 // addrmode2 := reg +/- imm12
879 // := reg +/- reg shop imm
881 // FIXME: addrmode2 should be refactored the rest of the way to always
882 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
883 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
884 def addrmode2 : MemOperand,
885 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
886 let EncoderMethod = "getAddrMode2OpValue";
887 let PrintMethod = "printAddrMode2Operand";
888 let ParserMatchClass = AddrMode2AsmOperand;
889 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
892 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
893 let Name = "PostIdxRegShifted";
894 let ParserMethod = "parsePostIdxReg";
896 def am2offset_reg : MemOperand,
897 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
898 [], [SDNPWantRoot]> {
899 let EncoderMethod = "getAddrMode2OffsetOpValue";
900 let PrintMethod = "printAddrMode2OffsetOperand";
901 // When using this for assembly, it's always as a post-index offset.
902 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
903 let MIOperandInfo = (ops GPRnopc, i32imm);
906 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
907 // the GPR is purely vestigal at this point.
908 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
909 def am2offset_imm : MemOperand,
910 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
911 [], [SDNPWantRoot]> {
912 let EncoderMethod = "getAddrMode2OffsetOpValue";
913 let PrintMethod = "printAddrMode2OffsetOperand";
914 let ParserMatchClass = AM2OffsetImmAsmOperand;
915 let MIOperandInfo = (ops GPRnopc, i32imm);
919 // addrmode3 := reg +/- reg
920 // addrmode3 := reg +/- imm8
922 // FIXME: split into imm vs. reg versions.
923 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
924 class AddrMode3 : MemOperand,
925 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
926 let EncoderMethod = "getAddrMode3OpValue";
927 let ParserMatchClass = AddrMode3AsmOperand;
928 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
931 def addrmode3 : AddrMode3
933 let PrintMethod = "printAddrMode3Operand<false>";
936 def addrmode3_pre : AddrMode3
938 let PrintMethod = "printAddrMode3Operand<true>";
941 // FIXME: split into imm vs. reg versions.
942 // FIXME: parser method to handle +/- register.
943 def AM3OffsetAsmOperand : AsmOperandClass {
944 let Name = "AM3Offset";
945 let ParserMethod = "parseAM3Offset";
947 def am3offset : MemOperand,
948 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
949 [], [SDNPWantRoot]> {
950 let EncoderMethod = "getAddrMode3OffsetOpValue";
951 let PrintMethod = "printAddrMode3OffsetOperand";
952 let ParserMatchClass = AM3OffsetAsmOperand;
953 let MIOperandInfo = (ops GPR, i32imm);
956 // ldstm_mode := {ia, ib, da, db}
958 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
959 let EncoderMethod = "getLdStmModeOpValue";
960 let PrintMethod = "printLdStmModeOperand";
963 // addrmode5 := reg +/- imm8*4
965 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
966 class AddrMode5 : MemOperand,
967 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
968 let EncoderMethod = "getAddrMode5OpValue";
969 let DecoderMethod = "DecodeAddrMode5Operand";
970 let ParserMatchClass = AddrMode5AsmOperand;
971 let MIOperandInfo = (ops GPR:$base, i32imm);
974 def addrmode5 : AddrMode5 {
975 let PrintMethod = "printAddrMode5Operand<false>";
978 def addrmode5_pre : AddrMode5 {
979 let PrintMethod = "printAddrMode5Operand<true>";
982 // addrmode6 := reg with optional alignment
984 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
985 def addrmode6 : MemOperand,
986 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
987 let PrintMethod = "printAddrMode6Operand";
988 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
989 let EncoderMethod = "getAddrMode6AddressOpValue";
990 let DecoderMethod = "DecodeAddrMode6Operand";
991 let ParserMatchClass = AddrMode6AsmOperand;
994 def am6offset : MemOperand,
995 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
996 [], [SDNPWantRoot]> {
997 let PrintMethod = "printAddrMode6OffsetOperand";
998 let MIOperandInfo = (ops GPR);
999 let EncoderMethod = "getAddrMode6OffsetOpValue";
1000 let DecoderMethod = "DecodeGPRRegisterClass";
1003 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1004 // (single element from one lane) for size 32.
1005 def addrmode6oneL32 : MemOperand,
1006 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1007 let PrintMethod = "printAddrMode6Operand";
1008 let MIOperandInfo = (ops GPR:$addr, i32imm);
1009 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1012 // Base class for addrmode6 with specific alignment restrictions.
1013 class AddrMode6Align : MemOperand,
1014 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1015 let PrintMethod = "printAddrMode6Operand";
1016 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1017 let EncoderMethod = "getAddrMode6AddressOpValue";
1018 let DecoderMethod = "DecodeAddrMode6Operand";
1021 // Special version of addrmode6 to handle no allowed alignment encoding for
1022 // VLD/VST instructions and checking the alignment is not specified.
1023 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1024 let Name = "AlignedMemoryNone";
1025 let DiagnosticType = "AlignedMemoryRequiresNone";
1027 def addrmode6alignNone : AddrMode6Align {
1028 // The alignment specifier can only be omitted.
1029 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1032 // Special version of addrmode6 to handle 16-bit alignment encoding for
1033 // VLD/VST instructions and checking the alignment value.
1034 def AddrMode6Align16AsmOperand : AsmOperandClass {
1035 let Name = "AlignedMemory16";
1036 let DiagnosticType = "AlignedMemoryRequires16";
1038 def addrmode6align16 : AddrMode6Align {
1039 // The alignment specifier can only be 16 or omitted.
1040 let ParserMatchClass = AddrMode6Align16AsmOperand;
1043 // Special version of addrmode6 to handle 32-bit alignment encoding for
1044 // VLD/VST instructions and checking the alignment value.
1045 def AddrMode6Align32AsmOperand : AsmOperandClass {
1046 let Name = "AlignedMemory32";
1047 let DiagnosticType = "AlignedMemoryRequires32";
1049 def addrmode6align32 : AddrMode6Align {
1050 // The alignment specifier can only be 32 or omitted.
1051 let ParserMatchClass = AddrMode6Align32AsmOperand;
1054 // Special version of addrmode6 to handle 64-bit alignment encoding for
1055 // VLD/VST instructions and checking the alignment value.
1056 def AddrMode6Align64AsmOperand : AsmOperandClass {
1057 let Name = "AlignedMemory64";
1058 let DiagnosticType = "AlignedMemoryRequires64";
1060 def addrmode6align64 : AddrMode6Align {
1061 // The alignment specifier can only be 64 or omitted.
1062 let ParserMatchClass = AddrMode6Align64AsmOperand;
1065 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1066 // for VLD/VST instructions and checking the alignment value.
1067 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1068 let Name = "AlignedMemory64or128";
1069 let DiagnosticType = "AlignedMemoryRequires64or128";
1071 def addrmode6align64or128 : AddrMode6Align {
1072 // The alignment specifier can only be 64, 128 or omitted.
1073 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1076 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1077 // encoding for VLD/VST instructions and checking the alignment value.
1078 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1079 let Name = "AlignedMemory64or128or256";
1080 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1082 def addrmode6align64or128or256 : AddrMode6Align {
1083 // The alignment specifier can only be 64, 128, 256 or omitted.
1084 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1087 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1088 // instructions, specifically VLD4-dup.
1089 def addrmode6dup : MemOperand,
1090 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1091 let PrintMethod = "printAddrMode6Operand";
1092 let MIOperandInfo = (ops GPR:$addr, i32imm);
1093 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1094 // FIXME: This is close, but not quite right. The alignment specifier is
1096 let ParserMatchClass = AddrMode6AsmOperand;
1099 // Base class for addrmode6dup with specific alignment restrictions.
1100 class AddrMode6DupAlign : MemOperand,
1101 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1102 let PrintMethod = "printAddrMode6Operand";
1103 let MIOperandInfo = (ops GPR:$addr, i32imm);
1104 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1107 // Special version of addrmode6 to handle no allowed alignment encoding for
1108 // VLD-dup instruction and checking the alignment is not specified.
1109 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1110 let Name = "DupAlignedMemoryNone";
1111 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1113 def addrmode6dupalignNone : AddrMode6DupAlign {
1114 // The alignment specifier can only be omitted.
1115 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1118 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1119 // instruction and checking the alignment value.
1120 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1121 let Name = "DupAlignedMemory16";
1122 let DiagnosticType = "DupAlignedMemoryRequires16";
1124 def addrmode6dupalign16 : AddrMode6DupAlign {
1125 // The alignment specifier can only be 16 or omitted.
1126 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1129 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1130 // instruction and checking the alignment value.
1131 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1132 let Name = "DupAlignedMemory32";
1133 let DiagnosticType = "DupAlignedMemoryRequires32";
1135 def addrmode6dupalign32 : AddrMode6DupAlign {
1136 // The alignment specifier can only be 32 or omitted.
1137 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1140 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1141 // instructions and checking the alignment value.
1142 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1143 let Name = "DupAlignedMemory64";
1144 let DiagnosticType = "DupAlignedMemoryRequires64";
1146 def addrmode6dupalign64 : AddrMode6DupAlign {
1147 // The alignment specifier can only be 64 or omitted.
1148 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1151 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1152 // for VLD instructions and checking the alignment value.
1153 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1154 let Name = "DupAlignedMemory64or128";
1155 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1157 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1158 // The alignment specifier can only be 64, 128 or omitted.
1159 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1162 // addrmodepc := pc + reg
1164 def addrmodepc : MemOperand,
1165 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1166 let PrintMethod = "printAddrModePCOperand";
1167 let MIOperandInfo = (ops GPR, i32imm);
1170 // addr_offset_none := reg
1172 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1173 def addr_offset_none : MemOperand,
1174 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1175 let PrintMethod = "printAddrMode7Operand";
1176 let DecoderMethod = "DecodeAddrMode7Operand";
1177 let ParserMatchClass = MemNoOffsetAsmOperand;
1178 let MIOperandInfo = (ops GPR:$base);
1181 def nohash_imm : Operand<i32> {
1182 let PrintMethod = "printNoHashImmediate";
1185 def CoprocNumAsmOperand : AsmOperandClass {
1186 let Name = "CoprocNum";
1187 let ParserMethod = "parseCoprocNumOperand";
1189 def p_imm : Operand<i32> {
1190 let PrintMethod = "printPImmediate";
1191 let ParserMatchClass = CoprocNumAsmOperand;
1192 let DecoderMethod = "DecodeCoprocessor";
1195 def CoprocRegAsmOperand : AsmOperandClass {
1196 let Name = "CoprocReg";
1197 let ParserMethod = "parseCoprocRegOperand";
1199 def c_imm : Operand<i32> {
1200 let PrintMethod = "printCImmediate";
1201 let ParserMatchClass = CoprocRegAsmOperand;
1203 def CoprocOptionAsmOperand : AsmOperandClass {
1204 let Name = "CoprocOption";
1205 let ParserMethod = "parseCoprocOptionOperand";
1207 def coproc_option_imm : Operand<i32> {
1208 let PrintMethod = "printCoprocOptionImm";
1209 let ParserMatchClass = CoprocOptionAsmOperand;
1212 //===----------------------------------------------------------------------===//
1214 include "ARMInstrFormats.td"
1216 //===----------------------------------------------------------------------===//
1217 // Multiclass helpers...
1220 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1221 /// binop that produces a value.
1222 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1223 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1224 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1225 PatFrag opnode, bit Commutable = 0> {
1226 // The register-immediate version is re-materializable. This is useful
1227 // in particular for taking the address of a local.
1228 let isReMaterializable = 1 in {
1229 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1230 iii, opc, "\t$Rd, $Rn, $imm",
1231 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1232 Sched<[WriteALU, ReadALU]> {
1237 let Inst{19-16} = Rn;
1238 let Inst{15-12} = Rd;
1239 let Inst{11-0} = imm;
1242 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1243 iir, opc, "\t$Rd, $Rn, $Rm",
1244 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1245 Sched<[WriteALU, ReadALU, ReadALU]> {
1250 let isCommutable = Commutable;
1251 let Inst{19-16} = Rn;
1252 let Inst{15-12} = Rd;
1253 let Inst{11-4} = 0b00000000;
1257 def rsi : AsI1<opcod, (outs GPR:$Rd),
1258 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1259 iis, opc, "\t$Rd, $Rn, $shift",
1260 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1261 Sched<[WriteALUsi, ReadALU]> {
1266 let Inst{19-16} = Rn;
1267 let Inst{15-12} = Rd;
1268 let Inst{11-5} = shift{11-5};
1270 let Inst{3-0} = shift{3-0};
1273 def rsr : AsI1<opcod, (outs GPR:$Rd),
1274 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1275 iis, opc, "\t$Rd, $Rn, $shift",
1276 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1277 Sched<[WriteALUsr, ReadALUsr]> {
1282 let Inst{19-16} = Rn;
1283 let Inst{15-12} = Rd;
1284 let Inst{11-8} = shift{11-8};
1286 let Inst{6-5} = shift{6-5};
1288 let Inst{3-0} = shift{3-0};
1292 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1293 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1294 /// it is equivalent to the AsI1_bin_irs counterpart.
1295 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1296 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1297 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1298 PatFrag opnode, bit Commutable = 0> {
1299 // The register-immediate version is re-materializable. This is useful
1300 // in particular for taking the address of a local.
1301 let isReMaterializable = 1 in {
1302 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1303 iii, opc, "\t$Rd, $Rn, $imm",
1304 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1305 Sched<[WriteALU, ReadALU]> {
1310 let Inst{19-16} = Rn;
1311 let Inst{15-12} = Rd;
1312 let Inst{11-0} = imm;
1315 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1316 iir, opc, "\t$Rd, $Rn, $Rm",
1317 [/* pattern left blank */]>,
1318 Sched<[WriteALU, ReadALU, ReadALU]> {
1322 let Inst{11-4} = 0b00000000;
1325 let Inst{15-12} = Rd;
1326 let Inst{19-16} = Rn;
1329 def rsi : AsI1<opcod, (outs GPR:$Rd),
1330 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1331 iis, opc, "\t$Rd, $Rn, $shift",
1332 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1333 Sched<[WriteALUsi, ReadALU]> {
1338 let Inst{19-16} = Rn;
1339 let Inst{15-12} = Rd;
1340 let Inst{11-5} = shift{11-5};
1342 let Inst{3-0} = shift{3-0};
1345 def rsr : AsI1<opcod, (outs GPR:$Rd),
1346 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1347 iis, opc, "\t$Rd, $Rn, $shift",
1348 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1349 Sched<[WriteALUsr, ReadALUsr]> {
1354 let Inst{19-16} = Rn;
1355 let Inst{15-12} = Rd;
1356 let Inst{11-8} = shift{11-8};
1358 let Inst{6-5} = shift{6-5};
1360 let Inst{3-0} = shift{3-0};
1364 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1366 /// These opcodes will be converted to the real non-S opcodes by
1367 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1368 let hasPostISelHook = 1, Defs = [CPSR] in {
1369 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1370 InstrItinClass iis, PatFrag opnode,
1371 bit Commutable = 0> {
1372 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1374 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1375 Sched<[WriteALU, ReadALU]>;
1377 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1379 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1380 Sched<[WriteALU, ReadALU, ReadALU]> {
1381 let isCommutable = Commutable;
1383 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1384 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1386 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1387 so_reg_imm:$shift))]>,
1388 Sched<[WriteALUsi, ReadALU]>;
1390 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1391 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1393 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1394 so_reg_reg:$shift))]>,
1395 Sched<[WriteALUSsr, ReadALUsr]>;
1399 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1400 /// operands are reversed.
1401 let hasPostISelHook = 1, Defs = [CPSR] in {
1402 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1403 InstrItinClass iis, PatFrag opnode,
1404 bit Commutable = 0> {
1405 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1407 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1408 Sched<[WriteALU, ReadALU]>;
1410 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1411 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1413 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1415 Sched<[WriteALUsi, ReadALU]>;
1417 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1418 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1420 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1422 Sched<[WriteALUSsr, ReadALUsr]>;
1426 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1427 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1428 /// a explicit result, only implicitly set CPSR.
1429 let isCompare = 1, Defs = [CPSR] in {
1430 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1431 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1432 PatFrag opnode, bit Commutable = 0,
1433 string rrDecoderMethod = ""> {
1434 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1436 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1437 Sched<[WriteCMP, ReadALU]> {
1442 let Inst{19-16} = Rn;
1443 let Inst{15-12} = 0b0000;
1444 let Inst{11-0} = imm;
1446 let Unpredictable{15-12} = 0b1111;
1448 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1450 [(opnode GPR:$Rn, GPR:$Rm)]>,
1451 Sched<[WriteCMP, ReadALU, ReadALU]> {
1454 let isCommutable = Commutable;
1457 let Inst{19-16} = Rn;
1458 let Inst{15-12} = 0b0000;
1459 let Inst{11-4} = 0b00000000;
1461 let DecoderMethod = rrDecoderMethod;
1463 let Unpredictable{15-12} = 0b1111;
1465 def rsi : AI1<opcod, (outs),
1466 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1467 opc, "\t$Rn, $shift",
1468 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1469 Sched<[WriteCMPsi, ReadALU]> {
1474 let Inst{19-16} = Rn;
1475 let Inst{15-12} = 0b0000;
1476 let Inst{11-5} = shift{11-5};
1478 let Inst{3-0} = shift{3-0};
1480 let Unpredictable{15-12} = 0b1111;
1482 def rsr : AI1<opcod, (outs),
1483 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1484 opc, "\t$Rn, $shift",
1485 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1486 Sched<[WriteCMPsr, ReadALU]> {
1491 let Inst{19-16} = Rn;
1492 let Inst{15-12} = 0b0000;
1493 let Inst{11-8} = shift{11-8};
1495 let Inst{6-5} = shift{6-5};
1497 let Inst{3-0} = shift{3-0};
1499 let Unpredictable{15-12} = 0b1111;
1505 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1506 /// register and one whose operand is a register rotated by 8/16/24.
1507 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1508 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1509 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1510 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1511 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1512 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1516 let Inst{19-16} = 0b1111;
1517 let Inst{15-12} = Rd;
1518 let Inst{11-10} = rot;
1522 class AI_ext_rrot_np<bits<8> opcod, string opc>
1523 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1524 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1525 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1527 let Inst{19-16} = 0b1111;
1528 let Inst{11-10} = rot;
1531 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1532 /// register and one whose operand is a register rotated by 8/16/24.
1533 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1534 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1535 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1536 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1537 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1538 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1543 let Inst{19-16} = Rn;
1544 let Inst{15-12} = Rd;
1545 let Inst{11-10} = rot;
1546 let Inst{9-4} = 0b000111;
1550 class AI_exta_rrot_np<bits<8> opcod, string opc>
1551 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1552 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1553 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1556 let Inst{19-16} = Rn;
1557 let Inst{11-10} = rot;
1560 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1561 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1562 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1563 bit Commutable = 0> {
1564 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1565 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1566 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1567 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1569 Sched<[WriteALU, ReadALU]> {
1574 let Inst{15-12} = Rd;
1575 let Inst{19-16} = Rn;
1576 let Inst{11-0} = imm;
1578 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1579 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1580 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1582 Sched<[WriteALU, ReadALU, ReadALU]> {
1586 let Inst{11-4} = 0b00000000;
1588 let isCommutable = Commutable;
1590 let Inst{15-12} = Rd;
1591 let Inst{19-16} = Rn;
1593 def rsi : AsI1<opcod, (outs GPR:$Rd),
1594 (ins GPR:$Rn, so_reg_imm:$shift),
1595 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1596 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1598 Sched<[WriteALUsi, ReadALU]> {
1603 let Inst{19-16} = Rn;
1604 let Inst{15-12} = Rd;
1605 let Inst{11-5} = shift{11-5};
1607 let Inst{3-0} = shift{3-0};
1609 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1610 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1611 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1612 [(set GPRnopc:$Rd, CPSR,
1613 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1615 Sched<[WriteALUsr, ReadALUsr]> {
1620 let Inst{19-16} = Rn;
1621 let Inst{15-12} = Rd;
1622 let Inst{11-8} = shift{11-8};
1624 let Inst{6-5} = shift{6-5};
1626 let Inst{3-0} = shift{3-0};
1631 /// AI1_rsc_irs - Define instructions and patterns for rsc
1632 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1633 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1634 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1635 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1636 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1637 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1639 Sched<[WriteALU, ReadALU]> {
1644 let Inst{15-12} = Rd;
1645 let Inst{19-16} = Rn;
1646 let Inst{11-0} = imm;
1648 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1649 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1650 [/* pattern left blank */]>,
1651 Sched<[WriteALU, ReadALU, ReadALU]> {
1655 let Inst{11-4} = 0b00000000;
1658 let Inst{15-12} = Rd;
1659 let Inst{19-16} = Rn;
1661 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1662 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1663 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1665 Sched<[WriteALUsi, ReadALU]> {
1670 let Inst{19-16} = Rn;
1671 let Inst{15-12} = Rd;
1672 let Inst{11-5} = shift{11-5};
1674 let Inst{3-0} = shift{3-0};
1676 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1677 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1678 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1680 Sched<[WriteALUsr, ReadALUsr]> {
1685 let Inst{19-16} = Rn;
1686 let Inst{15-12} = Rd;
1687 let Inst{11-8} = shift{11-8};
1689 let Inst{6-5} = shift{6-5};
1691 let Inst{3-0} = shift{3-0};
1696 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1697 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1698 InstrItinClass iir, PatFrag opnode> {
1699 // Note: We use the complex addrmode_imm12 rather than just an input
1700 // GPR and a constrained immediate so that we can use this to match
1701 // frame index references and avoid matching constant pool references.
1702 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1703 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1704 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1707 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1708 let Inst{19-16} = addr{16-13}; // Rn
1709 let Inst{15-12} = Rt;
1710 let Inst{11-0} = addr{11-0}; // imm12
1712 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1713 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1714 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1717 let shift{4} = 0; // Inst{4} = 0
1718 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1719 let Inst{19-16} = shift{16-13}; // Rn
1720 let Inst{15-12} = Rt;
1721 let Inst{11-0} = shift{11-0};
1726 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1727 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1728 InstrItinClass iir, PatFrag opnode> {
1729 // Note: We use the complex addrmode_imm12 rather than just an input
1730 // GPR and a constrained immediate so that we can use this to match
1731 // frame index references and avoid matching constant pool references.
1732 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1733 (ins addrmode_imm12:$addr),
1734 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1735 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1738 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1739 let Inst{19-16} = addr{16-13}; // Rn
1740 let Inst{15-12} = Rt;
1741 let Inst{11-0} = addr{11-0}; // imm12
1743 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1744 (ins ldst_so_reg:$shift),
1745 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1746 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1749 let shift{4} = 0; // Inst{4} = 0
1750 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1751 let Inst{19-16} = shift{16-13}; // Rn
1752 let Inst{15-12} = Rt;
1753 let Inst{11-0} = shift{11-0};
1759 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1760 InstrItinClass iir, PatFrag opnode> {
1761 // Note: We use the complex addrmode_imm12 rather than just an input
1762 // GPR and a constrained immediate so that we can use this to match
1763 // frame index references and avoid matching constant pool references.
1764 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1765 (ins GPR:$Rt, addrmode_imm12:$addr),
1766 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1767 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1770 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1771 let Inst{19-16} = addr{16-13}; // Rn
1772 let Inst{15-12} = Rt;
1773 let Inst{11-0} = addr{11-0}; // imm12
1775 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1776 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1777 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1780 let shift{4} = 0; // Inst{4} = 0
1781 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1782 let Inst{19-16} = shift{16-13}; // Rn
1783 let Inst{15-12} = Rt;
1784 let Inst{11-0} = shift{11-0};
1788 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1789 InstrItinClass iir, PatFrag opnode> {
1790 // Note: We use the complex addrmode_imm12 rather than just an input
1791 // GPR and a constrained immediate so that we can use this to match
1792 // frame index references and avoid matching constant pool references.
1793 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1794 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1795 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1796 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1799 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1800 let Inst{19-16} = addr{16-13}; // Rn
1801 let Inst{15-12} = Rt;
1802 let Inst{11-0} = addr{11-0}; // imm12
1804 def rs : AI2ldst<0b011, 0, isByte, (outs),
1805 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1806 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1807 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1810 let shift{4} = 0; // Inst{4} = 0
1811 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1812 let Inst{19-16} = shift{16-13}; // Rn
1813 let Inst{15-12} = Rt;
1814 let Inst{11-0} = shift{11-0};
1819 //===----------------------------------------------------------------------===//
1821 //===----------------------------------------------------------------------===//
1823 //===----------------------------------------------------------------------===//
1824 // Miscellaneous Instructions.
1827 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1828 /// the function. The first operand is the ID# for this instruction, the second
1829 /// is the index into the MachineConstantPool that this is, the third is the
1830 /// size in bytes of this constant pool entry.
1831 let hasSideEffects = 0, isNotDuplicable = 1 in
1832 def CONSTPOOL_ENTRY :
1833 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1834 i32imm:$size), NoItinerary, []>;
1836 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1837 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1838 /// mode). Used mostly in ARM and Thumb-1 modes.
1839 def JUMPTABLE_ADDRS :
1840 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1841 i32imm:$size), NoItinerary, []>;
1843 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1844 /// that cannot be optimised to use TBB or TBH.
1845 def JUMPTABLE_INSTS :
1846 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1847 i32imm:$size), NoItinerary, []>;
1849 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1850 /// a TBB instruction.
1852 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1853 i32imm:$size), NoItinerary, []>;
1855 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1856 /// a TBH instruction.
1858 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1859 i32imm:$size), NoItinerary, []>;
1862 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1863 // from removing one half of the matched pairs. That breaks PEI, which assumes
1864 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1865 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1866 def ADJCALLSTACKUP :
1867 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1868 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1870 def ADJCALLSTACKDOWN :
1871 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1872 [(ARMcallseq_start timm:$amt)]>;
1875 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1876 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1877 Requires<[IsARM, HasV6]> {
1879 let Inst{27-8} = 0b00110010000011110000;
1880 let Inst{7-0} = imm;
1883 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1884 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1885 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1886 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1887 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1888 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1890 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1891 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1896 let Inst{15-12} = Rd;
1897 let Inst{19-16} = Rn;
1898 let Inst{27-20} = 0b01101000;
1899 let Inst{7-4} = 0b1011;
1900 let Inst{11-8} = 0b1111;
1901 let Unpredictable{11-8} = 0b1111;
1904 // The 16-bit operand $val can be used by a debugger to store more information
1905 // about the breakpoint.
1906 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1907 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1909 let Inst{3-0} = val{3-0};
1910 let Inst{19-8} = val{15-4};
1911 let Inst{27-20} = 0b00010010;
1912 let Inst{31-28} = 0xe; // AL
1913 let Inst{7-4} = 0b0111;
1915 // default immediate for breakpoint mnemonic
1916 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1918 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1919 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1921 let Inst{3-0} = val{3-0};
1922 let Inst{19-8} = val{15-4};
1923 let Inst{27-20} = 0b00010000;
1924 let Inst{31-28} = 0xe; // AL
1925 let Inst{7-4} = 0b0111;
1928 // Change Processor State
1929 // FIXME: We should use InstAlias to handle the optional operands.
1930 class CPS<dag iops, string asm_ops>
1931 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1932 []>, Requires<[IsARM]> {
1938 let Inst{31-28} = 0b1111;
1939 let Inst{27-20} = 0b00010000;
1940 let Inst{19-18} = imod;
1941 let Inst{17} = M; // Enabled if mode is set;
1942 let Inst{16-9} = 0b00000000;
1943 let Inst{8-6} = iflags;
1945 let Inst{4-0} = mode;
1948 let DecoderMethod = "DecodeCPSInstruction" in {
1950 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1951 "$imod\t$iflags, $mode">;
1952 let mode = 0, M = 0 in
1953 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1955 let imod = 0, iflags = 0, M = 1 in
1956 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1959 // Preload signals the memory system of possible future data/instruction access.
1960 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1962 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1963 IIC_Preload, !strconcat(opc, "\t$addr"),
1964 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1965 Sched<[WritePreLd]> {
1968 let Inst{31-26} = 0b111101;
1969 let Inst{25} = 0; // 0 for immediate form
1970 let Inst{24} = data;
1971 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1972 let Inst{22} = read;
1973 let Inst{21-20} = 0b01;
1974 let Inst{19-16} = addr{16-13}; // Rn
1975 let Inst{15-12} = 0b1111;
1976 let Inst{11-0} = addr{11-0}; // imm12
1979 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1980 !strconcat(opc, "\t$shift"),
1981 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1982 Sched<[WritePreLd]> {
1984 let Inst{31-26} = 0b111101;
1985 let Inst{25} = 1; // 1 for register form
1986 let Inst{24} = data;
1987 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1988 let Inst{22} = read;
1989 let Inst{21-20} = 0b01;
1990 let Inst{19-16} = shift{16-13}; // Rn
1991 let Inst{15-12} = 0b1111;
1992 let Inst{11-0} = shift{11-0};
1997 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1998 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1999 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2001 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
2002 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2004 let Inst{31-10} = 0b1111000100000001000000;
2009 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2010 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2012 let Inst{27-4} = 0b001100100000111100001111;
2013 let Inst{3-0} = opt;
2016 // A8.8.247 UDF - Undefined (Encoding A1)
2017 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2018 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2020 let Inst{31-28} = 0b1110; // AL
2021 let Inst{27-25} = 0b011;
2022 let Inst{24-20} = 0b11111;
2023 let Inst{19-8} = imm16{15-4};
2024 let Inst{7-4} = 0b1111;
2025 let Inst{3-0} = imm16{3-0};
2029 * A5.4 Permanently UNDEFINED instructions.
2031 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2032 * Other UDF encodings generate SIGILL.
2034 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2036 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2038 * 1101 1110 iiii iiii
2039 * It uses the following encoding:
2040 * 1110 0111 1111 1110 1101 1110 1111 0000
2041 * - In ARM: UDF #60896;
2042 * - In Thumb: UDF #254 followed by a branch-to-self.
2044 let isBarrier = 1, isTerminator = 1 in
2045 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2047 Requires<[IsARM,UseNaClTrap]> {
2048 let Inst = 0xe7fedef0;
2050 let isBarrier = 1, isTerminator = 1 in
2051 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2053 Requires<[IsARM,DontUseNaClTrap]> {
2054 let Inst = 0xe7ffdefe;
2057 // Address computation and loads and stores in PIC mode.
2058 let isNotDuplicable = 1 in {
2059 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2061 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2062 Sched<[WriteALU, ReadALU]>;
2064 let AddedComplexity = 10 in {
2065 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2067 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2069 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2071 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2073 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2075 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2077 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2079 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2081 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2083 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2085 let AddedComplexity = 10 in {
2086 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2087 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2089 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2090 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2091 addrmodepc:$addr)]>;
2093 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2094 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2096 } // isNotDuplicable = 1
2099 // LEApcrel - Load a pc-relative address into a register without offending the
2101 let hasSideEffects = 0, isReMaterializable = 1 in
2102 // The 'adr' mnemonic encodes differently if the label is before or after
2103 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2104 // know until then which form of the instruction will be used.
2105 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2106 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2107 Sched<[WriteALU, ReadALU]> {
2110 let Inst{27-25} = 0b001;
2112 let Inst{23-22} = label{13-12};
2115 let Inst{19-16} = 0b1111;
2116 let Inst{15-12} = Rd;
2117 let Inst{11-0} = label{11-0};
2120 let hasSideEffects = 1 in {
2121 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2122 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2124 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2125 (ins i32imm:$label, pred:$p),
2126 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2129 //===----------------------------------------------------------------------===//
2130 // Control Flow Instructions.
2133 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2135 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2136 "bx", "\tlr", [(ARMretflag)]>,
2137 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2138 let Inst{27-0} = 0b0001001011111111111100011110;
2142 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2143 "mov", "\tpc, lr", [(ARMretflag)]>,
2144 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2145 let Inst{27-0} = 0b0001101000001111000000001110;
2148 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2149 // the user-space one).
2150 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2152 [(ARMintretflag imm:$offset)]>;
2155 // Indirect branches
2156 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2158 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2159 [(brind GPR:$dst)]>,
2160 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2162 let Inst{31-4} = 0b1110000100101111111111110001;
2163 let Inst{3-0} = dst;
2166 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2167 "bx", "\t$dst", [/* pattern left blank */]>,
2168 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2170 let Inst{27-4} = 0b000100101111111111110001;
2171 let Inst{3-0} = dst;
2175 // SP is marked as a use to prevent stack-pointer assignments that appear
2176 // immediately before calls from potentially appearing dead.
2178 // FIXME: Do we really need a non-predicated version? If so, it should
2179 // at least be a pseudo instruction expanding to the predicated version
2180 // at MC lowering time.
2181 Defs = [LR], Uses = [SP] in {
2182 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2183 IIC_Br, "bl\t$func",
2184 [(ARMcall tglobaladdr:$func)]>,
2185 Requires<[IsARM]>, Sched<[WriteBrL]> {
2186 let Inst{31-28} = 0b1110;
2188 let Inst{23-0} = func;
2189 let DecoderMethod = "DecodeBranchImmInstruction";
2192 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2193 IIC_Br, "bl", "\t$func",
2194 [(ARMcall_pred tglobaladdr:$func)]>,
2195 Requires<[IsARM]>, Sched<[WriteBrL]> {
2197 let Inst{23-0} = func;
2198 let DecoderMethod = "DecodeBranchImmInstruction";
2202 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2203 IIC_Br, "blx\t$func",
2204 [(ARMcall GPR:$func)]>,
2205 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2207 let Inst{31-4} = 0b1110000100101111111111110011;
2208 let Inst{3-0} = func;
2211 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2212 IIC_Br, "blx", "\t$func",
2213 [(ARMcall_pred GPR:$func)]>,
2214 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2216 let Inst{27-4} = 0b000100101111111111110011;
2217 let Inst{3-0} = func;
2221 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2222 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2223 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2224 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2227 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2228 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2229 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2231 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2232 // return stack predictor.
2233 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2234 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2235 Requires<[IsARM]>, Sched<[WriteBr]>;
2238 let isBranch = 1, isTerminator = 1 in {
2239 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2240 // a two-value operand where a dag node expects two operands. :(
2241 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2242 IIC_Br, "b", "\t$target",
2243 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2246 let Inst{23-0} = target;
2247 let DecoderMethod = "DecodeBranchImmInstruction";
2250 let isBarrier = 1 in {
2251 // B is "predicable" since it's just a Bcc with an 'always' condition.
2252 let isPredicable = 1 in
2253 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2254 // should be sufficient.
2255 // FIXME: Is B really a Barrier? That doesn't seem right.
2256 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2257 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2260 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2261 def BR_JTr : ARMPseudoInst<(outs),
2262 (ins GPR:$target, i32imm:$jt),
2264 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2266 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2267 // into i12 and rs suffixed versions.
2268 def BR_JTm : ARMPseudoInst<(outs),
2269 (ins addrmode2:$target, i32imm:$jt),
2271 [(ARMbrjt (i32 (load addrmode2:$target)),
2272 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2273 def BR_JTadd : ARMPseudoInst<(outs),
2274 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2276 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2277 Sched<[WriteBrTbl]>;
2278 } // isNotDuplicable = 1, isIndirectBranch = 1
2284 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2285 "blx\t$target", []>,
2286 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2287 let Inst{31-25} = 0b1111101;
2289 let Inst{23-0} = target{24-1};
2290 let Inst{24} = target{0};
2294 // Branch and Exchange Jazelle
2295 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2296 [/* pattern left blank */]>, Sched<[WriteBr]> {
2298 let Inst{23-20} = 0b0010;
2299 let Inst{19-8} = 0xfff;
2300 let Inst{7-4} = 0b0010;
2301 let Inst{3-0} = func;
2307 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2308 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2311 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2314 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2316 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2317 Requires<[IsARM]>, Sched<[WriteBr]>;
2319 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2321 (BX GPR:$dst)>, Sched<[WriteBr]>,
2325 // Secure Monitor Call is a system instruction.
2326 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2327 []>, Requires<[IsARM, HasTrustZone]> {
2329 let Inst{23-4} = 0b01100000000000000111;
2330 let Inst{3-0} = opt;
2332 def : MnemonicAlias<"smi", "smc">;
2334 // Supervisor Call (Software Interrupt)
2335 let isCall = 1, Uses = [SP] in {
2336 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2339 let Inst{23-0} = svc;
2343 // Store Return State
2344 class SRSI<bit wb, string asm>
2345 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2346 NoItinerary, asm, "", []> {
2348 let Inst{31-28} = 0b1111;
2349 let Inst{27-25} = 0b100;
2353 let Inst{19-16} = 0b1101; // SP
2354 let Inst{15-5} = 0b00000101000;
2355 let Inst{4-0} = mode;
2358 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2359 let Inst{24-23} = 0;
2361 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2362 let Inst{24-23} = 0;
2364 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2365 let Inst{24-23} = 0b10;
2367 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2368 let Inst{24-23} = 0b10;
2370 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2371 let Inst{24-23} = 0b01;
2373 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2374 let Inst{24-23} = 0b01;
2376 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2377 let Inst{24-23} = 0b11;
2379 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2380 let Inst{24-23} = 0b11;
2383 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2384 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2386 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2387 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2389 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2390 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2392 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2393 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2395 // Return From Exception
2396 class RFEI<bit wb, string asm>
2397 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2398 NoItinerary, asm, "", []> {
2400 let Inst{31-28} = 0b1111;
2401 let Inst{27-25} = 0b100;
2405 let Inst{19-16} = Rn;
2406 let Inst{15-0} = 0xa00;
2409 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2410 let Inst{24-23} = 0;
2412 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2413 let Inst{24-23} = 0;
2415 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2416 let Inst{24-23} = 0b10;
2418 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2419 let Inst{24-23} = 0b10;
2421 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2422 let Inst{24-23} = 0b01;
2424 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2425 let Inst{24-23} = 0b01;
2427 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2428 let Inst{24-23} = 0b11;
2430 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2431 let Inst{24-23} = 0b11;
2434 // Hypervisor Call is a system instruction
2436 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2437 "hvc", "\t$imm", []>,
2438 Requires<[IsARM, HasVirtualization]> {
2441 // Even though HVC isn't predicable, it's encoding includes a condition field.
2442 // The instruction is undefined if the condition field is 0xf otherwise it is
2443 // unpredictable if it isn't condition AL (0xe).
2444 let Inst{31-28} = 0b1110;
2445 let Unpredictable{31-28} = 0b1111;
2446 let Inst{27-24} = 0b0001;
2447 let Inst{23-20} = 0b0100;
2448 let Inst{19-8} = imm{15-4};
2449 let Inst{7-4} = 0b0111;
2450 let Inst{3-0} = imm{3-0};
2454 // Return from exception in Hypervisor mode.
2455 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2456 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2457 Requires<[IsARM, HasVirtualization]> {
2458 let Inst{23-0} = 0b011000000000000001101110;
2461 //===----------------------------------------------------------------------===//
2462 // Load / Store Instructions.
2468 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2469 UnOpFrag<(load node:$Src)>>;
2470 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2471 UnOpFrag<(zextloadi8 node:$Src)>>;
2472 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2473 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2474 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2475 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2477 // Special LDR for loads from non-pc-relative constpools.
2478 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2479 isReMaterializable = 1, isCodeGenOnly = 1 in
2480 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2481 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2485 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2486 let Inst{19-16} = 0b1111;
2487 let Inst{15-12} = Rt;
2488 let Inst{11-0} = addr{11-0}; // imm12
2491 // Loads with zero extension
2492 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2493 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2494 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2496 // Loads with sign extension
2497 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2498 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2499 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2501 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2502 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2503 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2505 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2507 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2508 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2509 Requires<[IsARM, HasV5TE]>;
2512 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2513 NoItinerary, "lda", "\t$Rt, $addr", []>;
2514 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2515 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2516 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2517 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2520 multiclass AI2_ldridx<bit isByte, string opc,
2521 InstrItinClass iii, InstrItinClass iir> {
2522 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2523 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2524 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2527 let Inst{23} = addr{12};
2528 let Inst{19-16} = addr{16-13};
2529 let Inst{11-0} = addr{11-0};
2530 let DecoderMethod = "DecodeLDRPreImm";
2533 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2534 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2535 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2538 let Inst{23} = addr{12};
2539 let Inst{19-16} = addr{16-13};
2540 let Inst{11-0} = addr{11-0};
2542 let DecoderMethod = "DecodeLDRPreReg";
2545 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2546 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2547 IndexModePost, LdFrm, iir,
2548 opc, "\t$Rt, $addr, $offset",
2549 "$addr.base = $Rn_wb", []> {
2555 let Inst{23} = offset{12};
2556 let Inst{19-16} = addr;
2557 let Inst{11-0} = offset{11-0};
2560 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2563 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2564 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2565 IndexModePost, LdFrm, iii,
2566 opc, "\t$Rt, $addr, $offset",
2567 "$addr.base = $Rn_wb", []> {
2573 let Inst{23} = offset{12};
2574 let Inst{19-16} = addr;
2575 let Inst{11-0} = offset{11-0};
2577 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2582 let mayLoad = 1, hasSideEffects = 0 in {
2583 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2584 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2585 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2586 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2589 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2590 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2591 (ins addrmode3_pre:$addr), IndexModePre,
2593 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2595 let Inst{23} = addr{8}; // U bit
2596 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2597 let Inst{19-16} = addr{12-9}; // Rn
2598 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2599 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2600 let DecoderMethod = "DecodeAddrMode3Instruction";
2602 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2603 (ins addr_offset_none:$addr, am3offset:$offset),
2604 IndexModePost, LdMiscFrm, itin,
2605 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2609 let Inst{23} = offset{8}; // U bit
2610 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2611 let Inst{19-16} = addr;
2612 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2613 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2614 let DecoderMethod = "DecodeAddrMode3Instruction";
2618 let mayLoad = 1, hasSideEffects = 0 in {
2619 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2620 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2621 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2622 let hasExtraDefRegAllocReq = 1 in {
2623 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2624 (ins addrmode3_pre:$addr), IndexModePre,
2625 LdMiscFrm, IIC_iLoad_d_ru,
2626 "ldrd", "\t$Rt, $Rt2, $addr!",
2627 "$addr.base = $Rn_wb", []> {
2629 let Inst{23} = addr{8}; // U bit
2630 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2631 let Inst{19-16} = addr{12-9}; // Rn
2632 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2633 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2634 let DecoderMethod = "DecodeAddrMode3Instruction";
2636 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2637 (ins addr_offset_none:$addr, am3offset:$offset),
2638 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2639 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2640 "$addr.base = $Rn_wb", []> {
2643 let Inst{23} = offset{8}; // U bit
2644 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2645 let Inst{19-16} = addr;
2646 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2647 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2648 let DecoderMethod = "DecodeAddrMode3Instruction";
2650 } // hasExtraDefRegAllocReq = 1
2651 } // mayLoad = 1, hasSideEffects = 0
2653 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2654 let mayLoad = 1, hasSideEffects = 0 in {
2655 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2656 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2657 IndexModePost, LdFrm, IIC_iLoad_ru,
2658 "ldrt", "\t$Rt, $addr, $offset",
2659 "$addr.base = $Rn_wb", []> {
2665 let Inst{23} = offset{12};
2666 let Inst{21} = 1; // overwrite
2667 let Inst{19-16} = addr;
2668 let Inst{11-5} = offset{11-5};
2670 let Inst{3-0} = offset{3-0};
2671 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2675 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2676 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2677 IndexModePost, LdFrm, IIC_iLoad_ru,
2678 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2684 let Inst{23} = offset{12};
2685 let Inst{21} = 1; // overwrite
2686 let Inst{19-16} = addr;
2687 let Inst{11-0} = offset{11-0};
2688 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2691 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2692 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2693 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2694 "ldrbt", "\t$Rt, $addr, $offset",
2695 "$addr.base = $Rn_wb", []> {
2701 let Inst{23} = offset{12};
2702 let Inst{21} = 1; // overwrite
2703 let Inst{19-16} = addr;
2704 let Inst{11-5} = offset{11-5};
2706 let Inst{3-0} = offset{3-0};
2707 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2711 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2712 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2713 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2714 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2720 let Inst{23} = offset{12};
2721 let Inst{21} = 1; // overwrite
2722 let Inst{19-16} = addr;
2723 let Inst{11-0} = offset{11-0};
2724 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2727 multiclass AI3ldrT<bits<4> op, string opc> {
2728 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2729 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2730 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2731 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2733 let Inst{23} = offset{8};
2735 let Inst{11-8} = offset{7-4};
2736 let Inst{3-0} = offset{3-0};
2738 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2739 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2740 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2741 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2743 let Inst{23} = Rm{4};
2746 let Unpredictable{11-8} = 0b1111;
2747 let Inst{3-0} = Rm{3-0};
2748 let DecoderMethod = "DecodeLDR";
2752 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2753 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2754 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2758 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2762 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2767 // Stores with truncate
2768 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2769 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2770 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2773 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2774 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2775 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2776 Requires<[IsARM, HasV5TE]> {
2782 multiclass AI2_stridx<bit isByte, string opc,
2783 InstrItinClass iii, InstrItinClass iir> {
2784 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2785 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2787 opc, "\t$Rt, $addr!",
2788 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2791 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2792 let Inst{19-16} = addr{16-13}; // Rn
2793 let Inst{11-0} = addr{11-0}; // imm12
2794 let DecoderMethod = "DecodeSTRPreImm";
2797 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2798 (ins GPR:$Rt, ldst_so_reg:$addr),
2799 IndexModePre, StFrm, iir,
2800 opc, "\t$Rt, $addr!",
2801 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2804 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2805 let Inst{19-16} = addr{16-13}; // Rn
2806 let Inst{11-0} = addr{11-0};
2807 let Inst{4} = 0; // Inst{4} = 0
2808 let DecoderMethod = "DecodeSTRPreReg";
2810 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2811 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2812 IndexModePost, StFrm, iir,
2813 opc, "\t$Rt, $addr, $offset",
2814 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2820 let Inst{23} = offset{12};
2821 let Inst{19-16} = addr;
2822 let Inst{11-0} = offset{11-0};
2825 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2828 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2829 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2830 IndexModePost, StFrm, iii,
2831 opc, "\t$Rt, $addr, $offset",
2832 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2838 let Inst{23} = offset{12};
2839 let Inst{19-16} = addr;
2840 let Inst{11-0} = offset{11-0};
2842 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2846 let mayStore = 1, hasSideEffects = 0 in {
2847 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2848 // IIC_iStore_siu depending on whether it the offset register is shifted.
2849 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2850 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2853 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2854 am2offset_reg:$offset),
2855 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2856 am2offset_reg:$offset)>;
2857 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2858 am2offset_imm:$offset),
2859 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2860 am2offset_imm:$offset)>;
2861 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2862 am2offset_reg:$offset),
2863 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2864 am2offset_reg:$offset)>;
2865 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2866 am2offset_imm:$offset),
2867 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2868 am2offset_imm:$offset)>;
2870 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2871 // put the patterns on the instruction definitions directly as ISel wants
2872 // the address base and offset to be separate operands, not a single
2873 // complex operand like we represent the instructions themselves. The
2874 // pseudos map between the two.
2875 let usesCustomInserter = 1,
2876 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2877 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2878 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2881 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2882 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2883 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2886 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2887 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2888 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2891 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2892 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2893 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2896 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2897 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2898 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2901 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2906 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2907 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2908 StMiscFrm, IIC_iStore_bh_ru,
2909 "strh", "\t$Rt, $addr!",
2910 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2912 let Inst{23} = addr{8}; // U bit
2913 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2914 let Inst{19-16} = addr{12-9}; // Rn
2915 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2916 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2917 let DecoderMethod = "DecodeAddrMode3Instruction";
2920 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2921 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2922 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2923 "strh", "\t$Rt, $addr, $offset",
2924 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2925 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2926 addr_offset_none:$addr,
2927 am3offset:$offset))]> {
2930 let Inst{23} = offset{8}; // U bit
2931 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2932 let Inst{19-16} = addr;
2933 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2934 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2935 let DecoderMethod = "DecodeAddrMode3Instruction";
2938 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2939 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2940 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2941 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2942 "strd", "\t$Rt, $Rt2, $addr!",
2943 "$addr.base = $Rn_wb", []> {
2945 let Inst{23} = addr{8}; // U bit
2946 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2947 let Inst{19-16} = addr{12-9}; // Rn
2948 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2949 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2950 let DecoderMethod = "DecodeAddrMode3Instruction";
2953 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2954 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2956 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2957 "strd", "\t$Rt, $Rt2, $addr, $offset",
2958 "$addr.base = $Rn_wb", []> {
2961 let Inst{23} = offset{8}; // U bit
2962 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2963 let Inst{19-16} = addr;
2964 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2965 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2966 let DecoderMethod = "DecodeAddrMode3Instruction";
2968 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2970 // STRT, STRBT, and STRHT
2972 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2973 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2974 IndexModePost, StFrm, IIC_iStore_bh_ru,
2975 "strbt", "\t$Rt, $addr, $offset",
2976 "$addr.base = $Rn_wb", []> {
2982 let Inst{23} = offset{12};
2983 let Inst{21} = 1; // overwrite
2984 let Inst{19-16} = addr;
2985 let Inst{11-5} = offset{11-5};
2987 let Inst{3-0} = offset{3-0};
2988 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2992 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2993 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2994 IndexModePost, StFrm, IIC_iStore_bh_ru,
2995 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3001 let Inst{23} = offset{12};
3002 let Inst{21} = 1; // overwrite
3003 let Inst{19-16} = addr;
3004 let Inst{11-0} = offset{11-0};
3005 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3009 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3010 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3012 let mayStore = 1, hasSideEffects = 0 in {
3013 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3014 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3015 IndexModePost, StFrm, IIC_iStore_ru,
3016 "strt", "\t$Rt, $addr, $offset",
3017 "$addr.base = $Rn_wb", []> {
3023 let Inst{23} = offset{12};
3024 let Inst{21} = 1; // overwrite
3025 let Inst{19-16} = addr;
3026 let Inst{11-5} = offset{11-5};
3028 let Inst{3-0} = offset{3-0};
3029 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3033 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3034 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3035 IndexModePost, StFrm, IIC_iStore_ru,
3036 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3042 let Inst{23} = offset{12};
3043 let Inst{21} = 1; // overwrite
3044 let Inst{19-16} = addr;
3045 let Inst{11-0} = offset{11-0};
3046 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3051 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3052 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3054 multiclass AI3strT<bits<4> op, string opc> {
3055 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3056 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3057 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3058 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3060 let Inst{23} = offset{8};
3062 let Inst{11-8} = offset{7-4};
3063 let Inst{3-0} = offset{3-0};
3065 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3066 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3067 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3068 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3070 let Inst{23} = Rm{4};
3073 let Inst{3-0} = Rm{3-0};
3078 defm STRHT : AI3strT<0b1011, "strht">;
3080 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3081 NoItinerary, "stl", "\t$Rt, $addr", []>;
3082 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3083 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3084 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3085 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3087 //===----------------------------------------------------------------------===//
3088 // Load / store multiple Instructions.
3091 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3092 InstrItinClass itin, InstrItinClass itin_upd> {
3093 // IA is the default, so no need for an explicit suffix on the
3094 // mnemonic here. Without it is the canonical spelling.
3096 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3097 IndexModeNone, f, itin,
3098 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3099 let Inst{24-23} = 0b01; // Increment After
3100 let Inst{22} = P_bit;
3101 let Inst{21} = 0; // No writeback
3102 let Inst{20} = L_bit;
3105 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3106 IndexModeUpd, f, itin_upd,
3107 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3108 let Inst{24-23} = 0b01; // Increment After
3109 let Inst{22} = P_bit;
3110 let Inst{21} = 1; // Writeback
3111 let Inst{20} = L_bit;
3113 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3116 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3117 IndexModeNone, f, itin,
3118 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3119 let Inst{24-23} = 0b00; // Decrement After
3120 let Inst{22} = P_bit;
3121 let Inst{21} = 0; // No writeback
3122 let Inst{20} = L_bit;
3125 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3126 IndexModeUpd, f, itin_upd,
3127 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3128 let Inst{24-23} = 0b00; // Decrement After
3129 let Inst{22} = P_bit;
3130 let Inst{21} = 1; // Writeback
3131 let Inst{20} = L_bit;
3133 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3136 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3137 IndexModeNone, f, itin,
3138 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3139 let Inst{24-23} = 0b10; // Decrement Before
3140 let Inst{22} = P_bit;
3141 let Inst{21} = 0; // No writeback
3142 let Inst{20} = L_bit;
3145 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3146 IndexModeUpd, f, itin_upd,
3147 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3148 let Inst{24-23} = 0b10; // Decrement Before
3149 let Inst{22} = P_bit;
3150 let Inst{21} = 1; // Writeback
3151 let Inst{20} = L_bit;
3153 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3156 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3157 IndexModeNone, f, itin,
3158 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3159 let Inst{24-23} = 0b11; // Increment Before
3160 let Inst{22} = P_bit;
3161 let Inst{21} = 0; // No writeback
3162 let Inst{20} = L_bit;
3165 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3166 IndexModeUpd, f, itin_upd,
3167 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3168 let Inst{24-23} = 0b11; // Increment Before
3169 let Inst{22} = P_bit;
3170 let Inst{21} = 1; // Writeback
3171 let Inst{20} = L_bit;
3173 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3177 let hasSideEffects = 0 in {
3179 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3180 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3181 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3183 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3184 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3186 ComplexDeprecationPredicate<"ARMStore">;
3190 // FIXME: remove when we have a way to marking a MI with these properties.
3191 // FIXME: Should pc be an implicit operand like PICADD, etc?
3192 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3193 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3194 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3195 reglist:$regs, variable_ops),
3196 4, IIC_iLoad_mBr, [],
3197 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3198 RegConstraint<"$Rn = $wb">;
3200 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3201 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3204 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3205 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3210 //===----------------------------------------------------------------------===//
3211 // Move Instructions.
3214 let hasSideEffects = 0 in
3215 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3216 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3220 let Inst{19-16} = 0b0000;
3221 let Inst{11-4} = 0b00000000;
3224 let Inst{15-12} = Rd;
3227 // A version for the smaller set of tail call registers.
3228 let hasSideEffects = 0 in
3229 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3230 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3234 let Inst{11-4} = 0b00000000;
3237 let Inst{15-12} = Rd;
3240 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3241 DPSoRegRegFrm, IIC_iMOVsr,
3242 "mov", "\t$Rd, $src",
3243 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3247 let Inst{15-12} = Rd;
3248 let Inst{19-16} = 0b0000;
3249 let Inst{11-8} = src{11-8};
3251 let Inst{6-5} = src{6-5};
3253 let Inst{3-0} = src{3-0};
3257 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3258 DPSoRegImmFrm, IIC_iMOVsr,
3259 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3260 UnaryDP, Sched<[WriteALU]> {
3263 let Inst{15-12} = Rd;
3264 let Inst{19-16} = 0b0000;
3265 let Inst{11-5} = src{11-5};
3267 let Inst{3-0} = src{3-0};
3271 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3272 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3273 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3278 let Inst{15-12} = Rd;
3279 let Inst{19-16} = 0b0000;
3280 let Inst{11-0} = imm;
3283 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3284 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3286 "movw", "\t$Rd, $imm",
3287 [(set GPR:$Rd, imm0_65535:$imm)]>,
3288 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3291 let Inst{15-12} = Rd;
3292 let Inst{11-0} = imm{11-0};
3293 let Inst{19-16} = imm{15-12};
3296 let DecoderMethod = "DecodeArmMOVTWInstruction";
3299 def : InstAlias<"mov${p} $Rd, $imm",
3300 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3303 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3304 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3307 let Constraints = "$src = $Rd" in {
3308 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3309 (ins GPR:$src, imm0_65535_expr:$imm),
3311 "movt", "\t$Rd, $imm",
3313 (or (and GPR:$src, 0xffff),
3314 lo16AllZero:$imm))]>, UnaryDP,
3315 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3318 let Inst{15-12} = Rd;
3319 let Inst{11-0} = imm{11-0};
3320 let Inst{19-16} = imm{15-12};
3323 let DecoderMethod = "DecodeArmMOVTWInstruction";
3326 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3327 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3332 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3333 Requires<[IsARM, HasV6T2]>;
3335 let Uses = [CPSR] in
3336 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3337 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3338 Requires<[IsARM]>, Sched<[WriteALU]>;
3340 // These aren't really mov instructions, but we have to define them this way
3341 // due to flag operands.
3343 let Defs = [CPSR] in {
3344 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3345 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3346 Sched<[WriteALU]>, Requires<[IsARM]>;
3347 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3348 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3349 Sched<[WriteALU]>, Requires<[IsARM]>;
3352 //===----------------------------------------------------------------------===//
3353 // Extend Instructions.
3358 def SXTB : AI_ext_rrot<0b01101010,
3359 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3360 def SXTH : AI_ext_rrot<0b01101011,
3361 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3363 def SXTAB : AI_exta_rrot<0b01101010,
3364 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3365 def SXTAH : AI_exta_rrot<0b01101011,
3366 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3368 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3370 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3374 let AddedComplexity = 16 in {
3375 def UXTB : AI_ext_rrot<0b01101110,
3376 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3377 def UXTH : AI_ext_rrot<0b01101111,
3378 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3379 def UXTB16 : AI_ext_rrot<0b01101100,
3380 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3382 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3383 // The transformation should probably be done as a combiner action
3384 // instead so we can include a check for masking back in the upper
3385 // eight bits of the source into the lower eight bits of the result.
3386 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3387 // (UXTB16r_rot GPR:$Src, 3)>;
3388 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3389 (UXTB16 GPR:$Src, 1)>;
3391 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3392 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3393 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3394 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3397 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3398 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3401 def SBFX : I<(outs GPRnopc:$Rd),
3402 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3403 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3404 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3405 Requires<[IsARM, HasV6T2]> {
3410 let Inst{27-21} = 0b0111101;
3411 let Inst{6-4} = 0b101;
3412 let Inst{20-16} = width;
3413 let Inst{15-12} = Rd;
3414 let Inst{11-7} = lsb;
3418 def UBFX : I<(outs GPRnopc:$Rd),
3419 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3420 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3421 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3422 Requires<[IsARM, HasV6T2]> {
3427 let Inst{27-21} = 0b0111111;
3428 let Inst{6-4} = 0b101;
3429 let Inst{20-16} = width;
3430 let Inst{15-12} = Rd;
3431 let Inst{11-7} = lsb;
3435 //===----------------------------------------------------------------------===//
3436 // Arithmetic Instructions.
3439 defm ADD : AsI1_bin_irs<0b0100, "add",
3440 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3441 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3442 defm SUB : AsI1_bin_irs<0b0010, "sub",
3443 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3444 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3446 // ADD and SUB with 's' bit set.
3448 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3449 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3450 // AdjustInstrPostInstrSelection where we determine whether or not to
3451 // set the "s" bit based on CPSR liveness.
3453 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3454 // support for an optional CPSR definition that corresponds to the DAG
3455 // node's second value. We can then eliminate the implicit def of CPSR.
3456 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3457 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3458 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3459 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3461 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3462 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3463 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3464 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3466 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3467 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3468 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3470 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3471 // CPSR and the implicit def of CPSR is not needed.
3472 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3473 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3475 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3476 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3478 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3479 // The assume-no-carry-in form uses the negation of the input since add/sub
3480 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3481 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3483 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3484 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3485 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3486 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3488 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3489 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3490 Requires<[IsARM, HasV6T2]>;
3491 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3492 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3493 Requires<[IsARM, HasV6T2]>;
3495 // The with-carry-in form matches bitwise not instead of the negation.
3496 // Effectively, the inverse interpretation of the carry flag already accounts
3497 // for part of the negation.
3498 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3499 (SBCri GPR:$src, mod_imm_not:$imm)>;
3500 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3501 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3502 Requires<[IsARM, HasV6T2]>;
3504 // Note: These are implemented in C++ code, because they have to generate
3505 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3507 // (mul X, 2^n+1) -> (add (X << n), X)
3508 // (mul X, 2^n-1) -> (rsb X, (X << n))
3510 // ARM Arithmetic Instruction
3511 // GPR:$dst = GPR:$a op GPR:$b
3512 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3513 list<dag> pattern = [],
3514 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3515 string asm = "\t$Rd, $Rn, $Rm">
3516 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3517 Sched<[WriteALU, ReadALU, ReadALU]> {
3521 let Inst{27-20} = op27_20;
3522 let Inst{11-4} = op11_4;
3523 let Inst{19-16} = Rn;
3524 let Inst{15-12} = Rd;
3527 let Unpredictable{11-8} = 0b1111;
3530 // Saturating add/subtract
3532 let DecoderMethod = "DecodeQADDInstruction" in
3533 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3534 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3535 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3537 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3538 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3539 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3540 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3541 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3543 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3544 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3547 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3548 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3549 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3550 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3551 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3552 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3553 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3554 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3555 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3556 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3557 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3558 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3560 // Signed/Unsigned add/subtract
3562 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3563 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3564 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3565 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3566 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3567 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3568 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3569 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3570 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3571 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3572 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3573 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3575 // Signed/Unsigned halving add/subtract
3577 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3578 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3579 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3580 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3581 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3582 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3583 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3584 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3585 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3586 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3587 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3588 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3590 // Unsigned Sum of Absolute Differences [and Accumulate].
3592 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3593 MulFrm /* for convenience */, NoItinerary, "usad8",
3594 "\t$Rd, $Rn, $Rm", []>,
3595 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3599 let Inst{27-20} = 0b01111000;
3600 let Inst{15-12} = 0b1111;
3601 let Inst{7-4} = 0b0001;
3602 let Inst{19-16} = Rd;
3603 let Inst{11-8} = Rm;
3606 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3607 MulFrm /* for convenience */, NoItinerary, "usada8",
3608 "\t$Rd, $Rn, $Rm, $Ra", []>,
3609 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3614 let Inst{27-20} = 0b01111000;
3615 let Inst{7-4} = 0b0001;
3616 let Inst{19-16} = Rd;
3617 let Inst{15-12} = Ra;
3618 let Inst{11-8} = Rm;
3622 // Signed/Unsigned saturate
3624 def SSAT : AI<(outs GPRnopc:$Rd),
3625 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3626 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3631 let Inst{27-21} = 0b0110101;
3632 let Inst{5-4} = 0b01;
3633 let Inst{20-16} = sat_imm;
3634 let Inst{15-12} = Rd;
3635 let Inst{11-7} = sh{4-0};
3636 let Inst{6} = sh{5};
3640 def SSAT16 : AI<(outs GPRnopc:$Rd),
3641 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3642 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3646 let Inst{27-20} = 0b01101010;
3647 let Inst{11-4} = 0b11110011;
3648 let Inst{15-12} = Rd;
3649 let Inst{19-16} = sat_imm;
3653 def USAT : AI<(outs GPRnopc:$Rd),
3654 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3655 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3660 let Inst{27-21} = 0b0110111;
3661 let Inst{5-4} = 0b01;
3662 let Inst{15-12} = Rd;
3663 let Inst{11-7} = sh{4-0};
3664 let Inst{6} = sh{5};
3665 let Inst{20-16} = sat_imm;
3669 def USAT16 : AI<(outs GPRnopc:$Rd),
3670 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3671 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3675 let Inst{27-20} = 0b01101110;
3676 let Inst{11-4} = 0b11110011;
3677 let Inst{15-12} = Rd;
3678 let Inst{19-16} = sat_imm;
3682 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
3683 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
3684 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
3685 (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
3687 //===----------------------------------------------------------------------===//
3688 // Bitwise Instructions.
3691 defm AND : AsI1_bin_irs<0b0000, "and",
3692 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3693 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3694 defm ORR : AsI1_bin_irs<0b1100, "orr",
3695 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3696 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3697 defm EOR : AsI1_bin_irs<0b0001, "eor",
3698 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3699 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3700 defm BIC : AsI1_bin_irs<0b1110, "bic",
3701 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3702 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3704 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3705 // like in the actual instruction encoding. The complexity of mapping the mask
3706 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3707 // instruction description.
3708 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3709 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3710 "bfc", "\t$Rd, $imm", "$src = $Rd",
3711 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3712 Requires<[IsARM, HasV6T2]> {
3715 let Inst{27-21} = 0b0111110;
3716 let Inst{6-0} = 0b0011111;
3717 let Inst{15-12} = Rd;
3718 let Inst{11-7} = imm{4-0}; // lsb
3719 let Inst{20-16} = imm{9-5}; // msb
3722 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3723 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3724 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3725 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3726 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3727 bf_inv_mask_imm:$imm))]>,
3728 Requires<[IsARM, HasV6T2]> {
3732 let Inst{27-21} = 0b0111110;
3733 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3734 let Inst{15-12} = Rd;
3735 let Inst{11-7} = imm{4-0}; // lsb
3736 let Inst{20-16} = imm{9-5}; // width
3740 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3741 "mvn", "\t$Rd, $Rm",
3742 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3746 let Inst{19-16} = 0b0000;
3747 let Inst{11-4} = 0b00000000;
3748 let Inst{15-12} = Rd;
3751 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3752 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3753 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3758 let Inst{19-16} = 0b0000;
3759 let Inst{15-12} = Rd;
3760 let Inst{11-5} = shift{11-5};
3762 let Inst{3-0} = shift{3-0};
3764 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3765 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3766 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3771 let Inst{19-16} = 0b0000;
3772 let Inst{15-12} = Rd;
3773 let Inst{11-8} = shift{11-8};
3775 let Inst{6-5} = shift{6-5};
3777 let Inst{3-0} = shift{3-0};
3779 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3780 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3781 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3782 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3786 let Inst{19-16} = 0b0000;
3787 let Inst{15-12} = Rd;
3788 let Inst{11-0} = imm;
3791 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3792 (BICri GPR:$src, mod_imm_not:$imm)>;
3794 //===----------------------------------------------------------------------===//
3795 // Multiply Instructions.
3797 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3798 string opc, string asm, list<dag> pattern>
3799 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3803 let Inst{19-16} = Rd;
3804 let Inst{11-8} = Rm;
3807 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3808 string opc, string asm, list<dag> pattern>
3809 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3814 let Inst{19-16} = RdHi;
3815 let Inst{15-12} = RdLo;
3816 let Inst{11-8} = Rm;
3819 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3820 string opc, string asm, list<dag> pattern>
3821 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3826 let Inst{19-16} = RdHi;
3827 let Inst{15-12} = RdLo;
3828 let Inst{11-8} = Rm;
3832 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3833 // property. Remove them when it's possible to add those properties
3834 // on an individual MachineInstr, not just an instruction description.
3835 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3836 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3837 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3838 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3839 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3840 Requires<[IsARM, HasV6]> {
3841 let Inst{15-12} = 0b0000;
3842 let Unpredictable{15-12} = 0b1111;
3845 let Constraints = "@earlyclobber $Rd" in
3846 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3847 pred:$p, cc_out:$s),
3849 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3850 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3851 Requires<[IsARM, NoV6, UseMulOps]>;
3854 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3856 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3857 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3858 Requires<[IsARM, HasV6, UseMulOps]> {
3860 let Inst{15-12} = Ra;
3863 let Constraints = "@earlyclobber $Rd" in
3864 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3865 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3866 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3867 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3868 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3869 Requires<[IsARM, NoV6]>;
3871 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3872 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3873 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3874 Requires<[IsARM, HasV6T2, UseMulOps]> {
3879 let Inst{19-16} = Rd;
3880 let Inst{15-12} = Ra;
3881 let Inst{11-8} = Rm;
3885 // Extra precision multiplies with low / high results
3886 let hasSideEffects = 0 in {
3887 let isCommutable = 1 in {
3888 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3889 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3890 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3891 Requires<[IsARM, HasV6]>;
3893 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3894 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3895 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3896 Requires<[IsARM, HasV6]>;
3898 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3899 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3900 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3902 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3903 Requires<[IsARM, NoV6]>;
3905 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3906 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3908 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3909 Requires<[IsARM, NoV6]>;
3913 // Multiply + accumulate
3914 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3915 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3916 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3917 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3918 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3919 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3920 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3921 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3923 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3924 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3925 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3926 Requires<[IsARM, HasV6]> {
3931 let Inst{19-16} = RdHi;
3932 let Inst{15-12} = RdLo;
3933 let Inst{11-8} = Rm;
3938 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3939 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3940 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3942 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3943 pred:$p, cc_out:$s)>,
3944 Requires<[IsARM, NoV6]>;
3945 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3946 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3948 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3949 pred:$p, cc_out:$s)>,
3950 Requires<[IsARM, NoV6]>;
3955 // Most significant word multiply
3956 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3957 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3958 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3959 Requires<[IsARM, HasV6]> {
3960 let Inst{15-12} = 0b1111;
3963 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3964 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3965 Requires<[IsARM, HasV6]> {
3966 let Inst{15-12} = 0b1111;
3969 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3970 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3971 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3972 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3973 Requires<[IsARM, HasV6, UseMulOps]>;
3975 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3976 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3977 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3978 Requires<[IsARM, HasV6]>;
3980 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3981 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3982 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3983 Requires<[IsARM, HasV6, UseMulOps]>;
3985 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3986 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3987 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3988 Requires<[IsARM, HasV6]>;
3990 multiclass AI_smul<string opc, PatFrag opnode> {
3991 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3992 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3993 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3994 (sext_inreg GPR:$Rm, i16)))]>,
3995 Requires<[IsARM, HasV5TE]>;
3997 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3998 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3999 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4000 (sra GPR:$Rm, (i32 16))))]>,
4001 Requires<[IsARM, HasV5TE]>;
4003 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4004 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4005 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4006 (sext_inreg GPR:$Rm, i16)))]>,
4007 Requires<[IsARM, HasV5TE]>;
4009 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4010 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4011 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4012 (sra GPR:$Rm, (i32 16))))]>,
4013 Requires<[IsARM, HasV5TE]>;
4015 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4016 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4018 Requires<[IsARM, HasV5TE]>;
4020 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4021 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4023 Requires<[IsARM, HasV5TE]>;
4027 multiclass AI_smla<string opc, PatFrag opnode> {
4028 let DecoderMethod = "DecodeSMLAInstruction" in {
4029 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4030 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4031 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4032 [(set GPRnopc:$Rd, (add GPR:$Ra,
4033 (opnode (sext_inreg GPRnopc:$Rn, i16),
4034 (sext_inreg GPRnopc:$Rm, i16))))]>,
4035 Requires<[IsARM, HasV5TE, UseMulOps]>;
4037 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4038 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4039 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4041 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4042 (sra GPRnopc:$Rm, (i32 16)))))]>,
4043 Requires<[IsARM, HasV5TE, UseMulOps]>;
4045 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4046 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4047 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4049 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4050 (sext_inreg GPRnopc:$Rm, i16))))]>,
4051 Requires<[IsARM, HasV5TE, UseMulOps]>;
4053 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4054 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4055 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4057 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4058 (sra GPRnopc:$Rm, (i32 16)))))]>,
4059 Requires<[IsARM, HasV5TE, UseMulOps]>;
4061 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4062 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4063 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4065 Requires<[IsARM, HasV5TE, UseMulOps]>;
4067 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4068 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4069 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4071 Requires<[IsARM, HasV5TE, UseMulOps]>;
4075 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4076 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4078 // Halfword multiply accumulate long: SMLAL<x><y>.
4079 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4080 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4081 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4082 Requires<[IsARM, HasV5TE]>;
4084 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4085 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4086 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4087 Requires<[IsARM, HasV5TE]>;
4089 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4090 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4091 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4092 Requires<[IsARM, HasV5TE]>;
4094 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4095 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4096 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4097 Requires<[IsARM, HasV5TE]>;
4099 // Helper class for AI_smld.
4100 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4101 InstrItinClass itin, string opc, string asm>
4102 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4105 let Inst{27-23} = 0b01110;
4106 let Inst{22} = long;
4107 let Inst{21-20} = 0b00;
4108 let Inst{11-8} = Rm;
4115 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4116 InstrItinClass itin, string opc, string asm>
4117 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4119 let Inst{15-12} = 0b1111;
4120 let Inst{19-16} = Rd;
4122 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4123 InstrItinClass itin, string opc, string asm>
4124 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4127 let Inst{19-16} = Rd;
4128 let Inst{15-12} = Ra;
4130 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4131 InstrItinClass itin, string opc, string asm>
4132 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4135 let Inst{19-16} = RdHi;
4136 let Inst{15-12} = RdLo;
4139 multiclass AI_smld<bit sub, string opc> {
4141 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4142 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4143 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4145 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4146 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4147 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4149 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4150 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4151 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4153 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4154 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4155 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4159 defm SMLA : AI_smld<0, "smla">;
4160 defm SMLS : AI_smld<1, "smls">;
4162 multiclass AI_sdml<bit sub, string opc> {
4164 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4165 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4166 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4167 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4170 defm SMUA : AI_sdml<0, "smua">;
4171 defm SMUS : AI_sdml<1, "smus">;
4173 //===----------------------------------------------------------------------===//
4174 // Division Instructions (ARMv7-A with virtualization extension)
4176 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4177 "sdiv", "\t$Rd, $Rn, $Rm",
4178 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4179 Requires<[IsARM, HasDivideInARM]>;
4181 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4182 "udiv", "\t$Rd, $Rn, $Rm",
4183 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4184 Requires<[IsARM, HasDivideInARM]>;
4186 //===----------------------------------------------------------------------===//
4187 // Misc. Arithmetic Instructions.
4190 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4191 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4192 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4195 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4196 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4197 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4198 Requires<[IsARM, HasV6T2]>,
4201 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4202 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4203 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4206 let AddedComplexity = 5 in
4207 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4208 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4209 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4210 Requires<[IsARM, HasV6]>,
4213 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4214 (REV16 (LDRH addrmode3:$addr))>;
4215 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4216 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4218 let AddedComplexity = 5 in
4219 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4220 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4221 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4222 Requires<[IsARM, HasV6]>,
4225 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4226 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4229 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4230 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4231 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4232 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4233 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4235 Requires<[IsARM, HasV6]>,
4236 Sched<[WriteALUsi, ReadALU]>;
4238 // Alternate cases for PKHBT where identities eliminate some nodes.
4239 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4240 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4241 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4242 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4244 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4245 // will match the pattern below.
4246 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4247 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4248 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4249 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4250 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4252 Requires<[IsARM, HasV6]>,
4253 Sched<[WriteALUsi, ReadALU]>;
4255 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4256 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4257 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4258 // pkhtb src1, src2, asr (17..31).
4259 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4260 (srl GPRnopc:$src2, imm16:$sh)),
4261 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4262 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4263 (sra GPRnopc:$src2, imm16_31:$sh)),
4264 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4265 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4266 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4267 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4269 //===----------------------------------------------------------------------===//
4273 // + CRC32{B,H,W} 0x04C11DB7
4274 // + CRC32C{B,H,W} 0x1EDC6F41
4277 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4278 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4279 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4280 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4281 Requires<[IsARM, HasV8, HasCRC]> {
4286 let Inst{31-28} = 0b1110;
4287 let Inst{27-23} = 0b00010;
4288 let Inst{22-21} = sz;
4290 let Inst{19-16} = Rn;
4291 let Inst{15-12} = Rd;
4292 let Inst{11-10} = 0b00;
4295 let Inst{7-4} = 0b0100;
4298 let Unpredictable{11-8} = 0b1101;
4301 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4302 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4303 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4304 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4305 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4306 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4308 //===----------------------------------------------------------------------===//
4309 // ARMv8.1a Privilege Access Never extension
4313 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4314 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4317 let Inst{31-28} = 0b1111;
4318 let Inst{27-20} = 0b00010001;
4319 let Inst{19-16} = 0b0000;
4320 let Inst{15-10} = 0b000000;
4323 let Inst{7-4} = 0b0000;
4324 let Inst{3-0} = 0b0000;
4326 let Unpredictable{19-16} = 0b1111;
4327 let Unpredictable{15-10} = 0b111111;
4328 let Unpredictable{8} = 0b1;
4329 let Unpredictable{3-0} = 0b1111;
4332 //===----------------------------------------------------------------------===//
4333 // Comparison Instructions...
4336 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4337 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4338 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4340 // ARMcmpZ can re-use the above instruction definitions.
4341 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4342 (CMPri GPR:$src, mod_imm:$imm)>;
4343 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4344 (CMPrr GPR:$src, GPR:$rhs)>;
4345 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4346 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4347 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4348 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4350 // CMN register-integer
4351 let isCompare = 1, Defs = [CPSR] in {
4352 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4353 "cmn", "\t$Rn, $imm",
4354 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4355 Sched<[WriteCMP, ReadALU]> {
4360 let Inst{19-16} = Rn;
4361 let Inst{15-12} = 0b0000;
4362 let Inst{11-0} = imm;
4364 let Unpredictable{15-12} = 0b1111;
4367 // CMN register-register/shift
4368 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4369 "cmn", "\t$Rn, $Rm",
4370 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4371 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4374 let isCommutable = 1;
4377 let Inst{19-16} = Rn;
4378 let Inst{15-12} = 0b0000;
4379 let Inst{11-4} = 0b00000000;
4382 let Unpredictable{15-12} = 0b1111;
4385 def CMNzrsi : AI1<0b1011, (outs),
4386 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4387 "cmn", "\t$Rn, $shift",
4388 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4389 GPR:$Rn, so_reg_imm:$shift)]>,
4390 Sched<[WriteCMPsi, ReadALU]> {
4395 let Inst{19-16} = Rn;
4396 let Inst{15-12} = 0b0000;
4397 let Inst{11-5} = shift{11-5};
4399 let Inst{3-0} = shift{3-0};
4401 let Unpredictable{15-12} = 0b1111;
4404 def CMNzrsr : AI1<0b1011, (outs),
4405 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4406 "cmn", "\t$Rn, $shift",
4407 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4408 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4409 Sched<[WriteCMPsr, ReadALU]> {
4414 let Inst{19-16} = Rn;
4415 let Inst{15-12} = 0b0000;
4416 let Inst{11-8} = shift{11-8};
4418 let Inst{6-5} = shift{6-5};
4420 let Inst{3-0} = shift{3-0};
4422 let Unpredictable{15-12} = 0b1111;
4427 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4428 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4430 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4431 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4433 // Note that TST/TEQ don't set all the same flags that CMP does!
4434 defm TST : AI1_cmp_irs<0b1000, "tst",
4435 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4436 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4437 "DecodeTSTInstruction">;
4438 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4439 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4440 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4442 // Pseudo i64 compares for some floating point compares.
4443 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4445 def BCCi64 : PseudoInst<(outs),
4446 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4448 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4451 def BCCZi64 : PseudoInst<(outs),
4452 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4453 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4455 } // usesCustomInserter
4458 // Conditional moves
4459 let hasSideEffects = 0 in {
4461 let isCommutable = 1, isSelect = 1 in
4462 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4463 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4465 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4467 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4469 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4470 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4473 (ARMcmov GPR:$false, so_reg_imm:$shift,
4475 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4476 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4477 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4479 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4481 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4484 let isMoveImm = 1 in
4486 : ARMPseudoInst<(outs GPR:$Rd),
4487 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4489 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4491 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4494 let isMoveImm = 1 in
4495 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4496 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4498 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4500 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4502 // Two instruction predicate mov immediate.
4503 let isMoveImm = 1 in
4505 : ARMPseudoInst<(outs GPR:$Rd),
4506 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4508 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4510 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4512 let isMoveImm = 1 in
4513 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4514 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4516 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4518 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4523 //===----------------------------------------------------------------------===//
4524 // Atomic operations intrinsics
4527 def MemBarrierOptOperand : AsmOperandClass {
4528 let Name = "MemBarrierOpt";
4529 let ParserMethod = "parseMemBarrierOptOperand";
4531 def memb_opt : Operand<i32> {
4532 let PrintMethod = "printMemBOption";
4533 let ParserMatchClass = MemBarrierOptOperand;
4534 let DecoderMethod = "DecodeMemBarrierOption";
4537 def InstSyncBarrierOptOperand : AsmOperandClass {
4538 let Name = "InstSyncBarrierOpt";
4539 let ParserMethod = "parseInstSyncBarrierOptOperand";
4541 def instsyncb_opt : Operand<i32> {
4542 let PrintMethod = "printInstSyncBOption";
4543 let ParserMatchClass = InstSyncBarrierOptOperand;
4544 let DecoderMethod = "DecodeInstSyncBarrierOption";
4547 // Memory barriers protect the atomic sequences
4548 let hasSideEffects = 1 in {
4549 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4550 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4551 Requires<[IsARM, HasDB]> {
4553 let Inst{31-4} = 0xf57ff05;
4554 let Inst{3-0} = opt;
4557 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4558 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4559 Requires<[IsARM, HasDB]> {
4561 let Inst{31-4} = 0xf57ff04;
4562 let Inst{3-0} = opt;
4565 // ISB has only full system option
4566 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4567 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4568 Requires<[IsARM, HasDB]> {
4570 let Inst{31-4} = 0xf57ff06;
4571 let Inst{3-0} = opt;
4575 let usesCustomInserter = 1, Defs = [CPSR] in {
4577 // Pseudo instruction that combines movs + predicated rsbmi
4578 // to implement integer ABS
4579 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4582 let usesCustomInserter = 1 in {
4583 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4584 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4586 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4589 let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in {
4590 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs...
4591 // Copies N registers worth of memory from address %src to address %dst
4592 // and returns the incremented addresses. N scratch register will
4593 // be attached for the copy to use.
4594 def MEMCPY : PseudoInst<
4595 (outs GPR:$newdst, GPR:$newsrc),
4596 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
4598 [(set GPR:$newdst, GPR:$newsrc,
4599 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4602 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4603 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4606 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4607 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4610 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4611 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4614 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4615 (int_arm_strex node:$val, node:$ptr), [{
4616 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4619 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4620 (int_arm_strex node:$val, node:$ptr), [{
4621 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4624 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4625 (int_arm_strex node:$val, node:$ptr), [{
4626 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4629 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4630 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4633 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4634 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4637 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4638 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4641 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4642 (int_arm_stlex node:$val, node:$ptr), [{
4643 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4646 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4647 (int_arm_stlex node:$val, node:$ptr), [{
4648 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4651 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4652 (int_arm_stlex node:$val, node:$ptr), [{
4653 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4656 let mayLoad = 1 in {
4657 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4658 NoItinerary, "ldrexb", "\t$Rt, $addr",
4659 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4660 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4661 NoItinerary, "ldrexh", "\t$Rt, $addr",
4662 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4663 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4664 NoItinerary, "ldrex", "\t$Rt, $addr",
4665 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4666 let hasExtraDefRegAllocReq = 1 in
4667 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4668 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4669 let DecoderMethod = "DecodeDoubleRegLoad";
4672 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4673 NoItinerary, "ldaexb", "\t$Rt, $addr",
4674 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4675 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4676 NoItinerary, "ldaexh", "\t$Rt, $addr",
4677 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4678 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4679 NoItinerary, "ldaex", "\t$Rt, $addr",
4680 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4681 let hasExtraDefRegAllocReq = 1 in
4682 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4683 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4684 let DecoderMethod = "DecodeDoubleRegLoad";
4688 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4689 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4690 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4691 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4692 addr_offset_none:$addr))]>;
4693 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4694 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4695 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4696 addr_offset_none:$addr))]>;
4697 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4698 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4699 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4700 addr_offset_none:$addr))]>;
4701 let hasExtraSrcRegAllocReq = 1 in
4702 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4703 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4704 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4705 let DecoderMethod = "DecodeDoubleRegStore";
4707 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4708 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4710 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4711 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4712 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4714 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4715 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4716 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4718 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4719 let hasExtraSrcRegAllocReq = 1 in
4720 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4721 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4722 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4723 let DecoderMethod = "DecodeDoubleRegStore";
4727 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4729 Requires<[IsARM, HasV7]> {
4730 let Inst{31-0} = 0b11110101011111111111000000011111;
4733 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4734 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4735 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4736 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4738 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4739 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4740 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4741 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4743 class acquiring_load<PatFrag base>
4744 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4745 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4746 return isAtLeastAcquire(Ordering);
4749 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4750 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4751 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4753 class releasing_store<PatFrag base>
4754 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4755 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4756 return isAtLeastRelease(Ordering);
4759 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4760 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4761 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4763 let AddedComplexity = 8 in {
4764 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4765 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4766 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4767 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4768 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4769 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4772 // SWP/SWPB are deprecated in V6/V7.
4773 let mayLoad = 1, mayStore = 1 in {
4774 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4775 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4777 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4778 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4782 //===----------------------------------------------------------------------===//
4783 // Coprocessor Instructions.
4786 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4787 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4788 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4789 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4790 imm:$CRm, imm:$opc2)]>,
4799 let Inst{3-0} = CRm;
4801 let Inst{7-5} = opc2;
4802 let Inst{11-8} = cop;
4803 let Inst{15-12} = CRd;
4804 let Inst{19-16} = CRn;
4805 let Inst{23-20} = opc1;
4808 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4809 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4810 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4811 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4812 imm:$CRm, imm:$opc2)]>,
4814 let Inst{31-28} = 0b1111;
4822 let Inst{3-0} = CRm;
4824 let Inst{7-5} = opc2;
4825 let Inst{11-8} = cop;
4826 let Inst{15-12} = CRd;
4827 let Inst{19-16} = CRn;
4828 let Inst{23-20} = opc1;
4831 class ACI<dag oops, dag iops, string opc, string asm,
4832 IndexMode im = IndexModeNone>
4833 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4835 let Inst{27-25} = 0b110;
4837 class ACInoP<dag oops, dag iops, string opc, string asm,
4838 IndexMode im = IndexModeNone>
4839 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4841 let Inst{31-28} = 0b1111;
4842 let Inst{27-25} = 0b110;
4844 multiclass LdStCop<bit load, bit Dbit, string asm> {
4845 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4846 asm, "\t$cop, $CRd, $addr"> {
4850 let Inst{24} = 1; // P = 1
4851 let Inst{23} = addr{8};
4852 let Inst{22} = Dbit;
4853 let Inst{21} = 0; // W = 0
4854 let Inst{20} = load;
4855 let Inst{19-16} = addr{12-9};
4856 let Inst{15-12} = CRd;
4857 let Inst{11-8} = cop;
4858 let Inst{7-0} = addr{7-0};
4859 let DecoderMethod = "DecodeCopMemInstruction";
4861 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4862 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4866 let Inst{24} = 1; // P = 1
4867 let Inst{23} = addr{8};
4868 let Inst{22} = Dbit;
4869 let Inst{21} = 1; // W = 1
4870 let Inst{20} = load;
4871 let Inst{19-16} = addr{12-9};
4872 let Inst{15-12} = CRd;
4873 let Inst{11-8} = cop;
4874 let Inst{7-0} = addr{7-0};
4875 let DecoderMethod = "DecodeCopMemInstruction";
4877 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4878 postidx_imm8s4:$offset),
4879 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4884 let Inst{24} = 0; // P = 0
4885 let Inst{23} = offset{8};
4886 let Inst{22} = Dbit;
4887 let Inst{21} = 1; // W = 1
4888 let Inst{20} = load;
4889 let Inst{19-16} = addr;
4890 let Inst{15-12} = CRd;
4891 let Inst{11-8} = cop;
4892 let Inst{7-0} = offset{7-0};
4893 let DecoderMethod = "DecodeCopMemInstruction";
4895 def _OPTION : ACI<(outs),
4896 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4897 coproc_option_imm:$option),
4898 asm, "\t$cop, $CRd, $addr, $option"> {
4903 let Inst{24} = 0; // P = 0
4904 let Inst{23} = 1; // U = 1
4905 let Inst{22} = Dbit;
4906 let Inst{21} = 0; // W = 0
4907 let Inst{20} = load;
4908 let Inst{19-16} = addr;
4909 let Inst{15-12} = CRd;
4910 let Inst{11-8} = cop;
4911 let Inst{7-0} = option;
4912 let DecoderMethod = "DecodeCopMemInstruction";
4915 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4916 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4917 asm, "\t$cop, $CRd, $addr"> {
4921 let Inst{24} = 1; // P = 1
4922 let Inst{23} = addr{8};
4923 let Inst{22} = Dbit;
4924 let Inst{21} = 0; // W = 0
4925 let Inst{20} = load;
4926 let Inst{19-16} = addr{12-9};
4927 let Inst{15-12} = CRd;
4928 let Inst{11-8} = cop;
4929 let Inst{7-0} = addr{7-0};
4930 let DecoderMethod = "DecodeCopMemInstruction";
4932 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4933 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4937 let Inst{24} = 1; // P = 1
4938 let Inst{23} = addr{8};
4939 let Inst{22} = Dbit;
4940 let Inst{21} = 1; // W = 1
4941 let Inst{20} = load;
4942 let Inst{19-16} = addr{12-9};
4943 let Inst{15-12} = CRd;
4944 let Inst{11-8} = cop;
4945 let Inst{7-0} = addr{7-0};
4946 let DecoderMethod = "DecodeCopMemInstruction";
4948 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4949 postidx_imm8s4:$offset),
4950 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4955 let Inst{24} = 0; // P = 0
4956 let Inst{23} = offset{8};
4957 let Inst{22} = Dbit;
4958 let Inst{21} = 1; // W = 1
4959 let Inst{20} = load;
4960 let Inst{19-16} = addr;
4961 let Inst{15-12} = CRd;
4962 let Inst{11-8} = cop;
4963 let Inst{7-0} = offset{7-0};
4964 let DecoderMethod = "DecodeCopMemInstruction";
4966 def _OPTION : ACInoP<(outs),
4967 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4968 coproc_option_imm:$option),
4969 asm, "\t$cop, $CRd, $addr, $option"> {
4974 let Inst{24} = 0; // P = 0
4975 let Inst{23} = 1; // U = 1
4976 let Inst{22} = Dbit;
4977 let Inst{21} = 0; // W = 0
4978 let Inst{20} = load;
4979 let Inst{19-16} = addr;
4980 let Inst{15-12} = CRd;
4981 let Inst{11-8} = cop;
4982 let Inst{7-0} = option;
4983 let DecoderMethod = "DecodeCopMemInstruction";
4987 defm LDC : LdStCop <1, 0, "ldc">;
4988 defm LDCL : LdStCop <1, 1, "ldcl">;
4989 defm STC : LdStCop <0, 0, "stc">;
4990 defm STCL : LdStCop <0, 1, "stcl">;
4991 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4992 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4993 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4994 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4996 //===----------------------------------------------------------------------===//
4997 // Move between coprocessor and ARM core register.
5000 class MovRCopro<string opc, bit direction, dag oops, dag iops,
5002 : ABI<0b1110, oops, iops, NoItinerary, opc,
5003 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5004 let Inst{20} = direction;
5014 let Inst{15-12} = Rt;
5015 let Inst{11-8} = cop;
5016 let Inst{23-21} = opc1;
5017 let Inst{7-5} = opc2;
5018 let Inst{3-0} = CRm;
5019 let Inst{19-16} = CRn;
5022 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5024 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5025 c_imm:$CRm, imm0_7:$opc2),
5026 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5027 imm:$CRm, imm:$opc2)]>,
5028 ComplexDeprecationPredicate<"MCR">;
5029 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5030 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5031 c_imm:$CRm, 0, pred:$p)>;
5032 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5033 (outs GPRwithAPSR:$Rt),
5034 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5036 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5037 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5038 c_imm:$CRm, 0, pred:$p)>;
5040 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5041 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5043 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5045 : ABXI<0b1110, oops, iops, NoItinerary,
5046 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5047 let Inst{31-24} = 0b11111110;
5048 let Inst{20} = direction;
5058 let Inst{15-12} = Rt;
5059 let Inst{11-8} = cop;
5060 let Inst{23-21} = opc1;
5061 let Inst{7-5} = opc2;
5062 let Inst{3-0} = CRm;
5063 let Inst{19-16} = CRn;
5066 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5068 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5069 c_imm:$CRm, imm0_7:$opc2),
5070 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5071 imm:$CRm, imm:$opc2)]>,
5073 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5074 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5076 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5077 (outs GPRwithAPSR:$Rt),
5078 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5081 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5082 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5085 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5086 imm:$CRm, imm:$opc2),
5087 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5089 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5091 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5094 let Inst{23-21} = 0b010;
5095 let Inst{20} = direction;
5103 let Inst{15-12} = Rt;
5104 let Inst{19-16} = Rt2;
5105 let Inst{11-8} = cop;
5106 let Inst{7-4} = opc1;
5107 let Inst{3-0} = CRm;
5110 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5111 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5112 GPRnopc:$Rt2, c_imm:$CRm),
5113 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5114 GPRnopc:$Rt2, imm:$CRm)]>;
5115 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5116 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5117 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5119 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5120 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5121 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5122 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5124 let Inst{31-28} = 0b1111;
5125 let Inst{23-21} = 0b010;
5126 let Inst{20} = direction;
5134 let Inst{15-12} = Rt;
5135 let Inst{19-16} = Rt2;
5136 let Inst{11-8} = cop;
5137 let Inst{7-4} = opc1;
5138 let Inst{3-0} = CRm;
5140 let DecoderMethod = "DecodeMRRC2";
5143 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5144 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5145 GPRnopc:$Rt2, imm:$CRm)]>;
5146 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5148 //===----------------------------------------------------------------------===//
5149 // Move between special register and ARM core register
5152 // Move to ARM core register from Special Register
5153 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5154 "mrs", "\t$Rd, apsr", []> {
5156 let Inst{23-16} = 0b00001111;
5157 let Unpredictable{19-17} = 0b111;
5159 let Inst{15-12} = Rd;
5161 let Inst{11-0} = 0b000000000000;
5162 let Unpredictable{11-0} = 0b110100001111;
5165 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5168 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5169 // section B9.3.9, with the R bit set to 1.
5170 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5171 "mrs", "\t$Rd, spsr", []> {
5173 let Inst{23-16} = 0b01001111;
5174 let Unpredictable{19-16} = 0b1111;
5176 let Inst{15-12} = Rd;
5178 let Inst{11-0} = 0b000000000000;
5179 let Unpredictable{11-0} = 0b110100001111;
5182 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5183 // separate encoding (distinguished by bit 5.
5184 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5185 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5186 Requires<[IsARM, HasVirtualization]> {
5191 let Inst{22} = banked{5}; // R bit
5192 let Inst{21-20} = 0b00;
5193 let Inst{19-16} = banked{3-0};
5194 let Inst{15-12} = Rd;
5195 let Inst{11-9} = 0b001;
5196 let Inst{8} = banked{4};
5197 let Inst{7-0} = 0b00000000;
5200 // Move from ARM core register to Special Register
5202 // No need to have both system and application versions of MSR (immediate) or
5203 // MSR (register), the encodings are the same and the assembly parser has no way
5204 // to distinguish between them. The mask operand contains the special register
5205 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5206 // accessed in the special register.
5207 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5208 "msr", "\t$mask, $Rn", []> {
5213 let Inst{22} = mask{4}; // R bit
5214 let Inst{21-20} = 0b10;
5215 let Inst{19-16} = mask{3-0};
5216 let Inst{15-12} = 0b1111;
5217 let Inst{11-4} = 0b00000000;
5221 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5222 "msr", "\t$mask, $imm", []> {
5227 let Inst{22} = mask{4}; // R bit
5228 let Inst{21-20} = 0b10;
5229 let Inst{19-16} = mask{3-0};
5230 let Inst{15-12} = 0b1111;
5231 let Inst{11-0} = imm;
5234 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5235 // separate encoding (distinguished by bit 5.
5236 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5237 NoItinerary, "msr", "\t$banked, $Rn", []>,
5238 Requires<[IsARM, HasVirtualization]> {
5243 let Inst{22} = banked{5}; // R bit
5244 let Inst{21-20} = 0b10;
5245 let Inst{19-16} = banked{3-0};
5246 let Inst{15-12} = 0b1111;
5247 let Inst{11-9} = 0b001;
5248 let Inst{8} = banked{4};
5249 let Inst{7-4} = 0b0000;
5253 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5254 // are needed to probe the stack when allocating more than
5255 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5256 // ensure that the guard pages used by the OS virtual memory manager are
5257 // allocated in correct sequence.
5258 // The main point of having separate instruction are extra unmodelled effects
5259 // (compared to ordinary calls) like stack pointer change.
5261 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5262 [SDNPHasChain, SDNPSideEffect]>;
5263 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5264 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5266 def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
5267 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
5268 let usesCustomInserter = 1, Defs = [CPSR] in
5269 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary,
5270 [(win__dbzchk GPR:$divisor)]>;
5272 //===----------------------------------------------------------------------===//
5276 // __aeabi_read_tp preserves the registers r1-r3.
5277 // This is a pseudo inst so that we can get the encoding right,
5278 // complete with fixup for the aeabi_read_tp function.
5279 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5280 // is defined in "ARMInstrThumb.td".
5282 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5283 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5284 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5287 //===----------------------------------------------------------------------===//
5288 // SJLJ Exception handling intrinsics
5289 // eh_sjlj_setjmp() is an instruction sequence to store the return
5290 // address and save #0 in R0 for the non-longjmp case.
5291 // Since by its nature we may be coming from some other function to get
5292 // here, and we're using the stack frame for the containing function to
5293 // save/restore registers, we can't keep anything live in regs across
5294 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5295 // when we get here from a longjmp(). We force everything out of registers
5296 // except for our own input by listing the relevant registers in Defs. By
5297 // doing so, we also cause the prologue/epilogue code to actively preserve
5298 // all of the callee-saved resgisters, which is exactly what we want.
5299 // A constant value is passed in $val, and we use the location as a scratch.
5301 // These are pseudo-instructions and are lowered to individual MC-insts, so
5302 // no encoding information is necessary.
5304 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5305 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5306 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5307 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5309 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5310 Requires<[IsARM, HasVFP2]>;
5314 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5315 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5316 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5318 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5319 Requires<[IsARM, NoVFP]>;
5322 // FIXME: Non-IOS version(s)
5323 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5324 Defs = [ R7, LR, SP ] in {
5325 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5327 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5331 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5332 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5333 [(ARMeh_sjlj_setup_dispatch)]>;
5335 // eh.sjlj.dispatchsetup pseudo-instruction.
5336 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5337 // the pseudo is expanded (which happens before any passes that need the
5338 // instruction size).
5339 let isBarrier = 1 in
5340 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5343 //===----------------------------------------------------------------------===//
5344 // Non-Instruction Patterns
5347 // ARMv4 indirect branch using (MOVr PC, dst)
5348 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5349 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5350 4, IIC_Br, [(brind GPR:$dst)],
5351 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5352 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5354 // Large immediate handling.
5356 // 32-bit immediate using two piece mod_imms or movw + movt.
5357 // This is a single pseudo instruction, the benefit is that it can be remat'd
5358 // as a single unit instead of having to handle reg inputs.
5359 // FIXME: Remove this when we can do generalized remat.
5360 let isReMaterializable = 1, isMoveImm = 1 in
5361 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5362 [(set GPR:$dst, (arm_i32imm:$src))]>,
5365 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5366 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5367 Requires<[IsARM, DontUseMovt]>;
5369 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5370 // It also makes it possible to rematerialize the instructions.
5371 // FIXME: Remove this when we can do generalized remat and when machine licm
5372 // can properly the instructions.
5373 let isReMaterializable = 1 in {
5374 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5376 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5377 Requires<[IsARM, UseMovt]>;
5379 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5382 (ARMWrapperPIC tglobaladdr:$addr))]>,
5383 Requires<[IsARM, DontUseMovt]>;
5385 let AddedComplexity = 10 in
5386 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5389 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5390 Requires<[IsARM, DontUseMovt]>;
5392 let AddedComplexity = 10 in
5393 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5395 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5396 Requires<[IsARM, UseMovt]>;
5397 } // isReMaterializable
5399 // ConstantPool, GlobalAddress, and JumpTable
5400 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5401 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5402 Requires<[IsARM, UseMovt]>;
5403 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5404 (LEApcrelJT tjumptable:$dst)>;
5406 // TODO: add,sub,and, 3-instr forms?
5408 // Tail calls. These patterns also apply to Thumb mode.
5409 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5410 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5411 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5414 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5415 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5416 (BMOVPCB_CALL texternalsym:$func)>;
5418 // zextload i1 -> zextload i8
5419 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5420 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5422 // extload -> zextload
5423 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5424 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5425 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5426 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5428 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5430 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5431 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5434 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5435 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5436 (SMULBB GPR:$a, GPR:$b)>;
5437 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5438 (SMULBB GPR:$a, GPR:$b)>;
5439 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5440 (sra GPR:$b, (i32 16))),
5441 (SMULBT GPR:$a, GPR:$b)>;
5442 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5443 (SMULBT GPR:$a, GPR:$b)>;
5444 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5445 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5446 (SMULTB GPR:$a, GPR:$b)>;
5447 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5448 (SMULTB GPR:$a, GPR:$b)>;
5450 def : ARMV5MOPat<(add GPR:$acc,
5451 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5452 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5453 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5454 def : ARMV5MOPat<(add GPR:$acc,
5455 (mul sext_16_node:$a, sext_16_node:$b)),
5456 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5457 def : ARMV5MOPat<(add GPR:$acc,
5458 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5459 (sra GPR:$b, (i32 16)))),
5460 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5461 def : ARMV5MOPat<(add GPR:$acc,
5462 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5463 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5464 def : ARMV5MOPat<(add GPR:$acc,
5465 (mul (sra GPR:$a, (i32 16)),
5466 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5467 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5468 def : ARMV5MOPat<(add GPR:$acc,
5469 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5470 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5473 // Pre-v7 uses MCR for synchronization barriers.
5474 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5475 Requires<[IsARM, HasV6]>;
5477 // SXT/UXT with no rotate
5478 let AddedComplexity = 16 in {
5479 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5480 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5481 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5482 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5483 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5484 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5485 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5488 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5489 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5491 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5492 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5493 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5494 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5496 // Atomic load/store patterns
5497 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5498 (LDRBrs ldst_so_reg:$src)>;
5499 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5500 (LDRBi12 addrmode_imm12:$src)>;
5501 def : ARMPat<(atomic_load_16 addrmode3:$src),
5502 (LDRH addrmode3:$src)>;
5503 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5504 (LDRrs ldst_so_reg:$src)>;
5505 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5506 (LDRi12 addrmode_imm12:$src)>;
5507 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5508 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5509 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5510 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5511 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5512 (STRH GPR:$val, addrmode3:$ptr)>;
5513 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5514 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5515 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5516 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5519 //===----------------------------------------------------------------------===//
5523 include "ARMInstrThumb.td"
5525 //===----------------------------------------------------------------------===//
5529 include "ARMInstrThumb2.td"
5531 //===----------------------------------------------------------------------===//
5532 // Floating Point Support
5535 include "ARMInstrVFP.td"
5537 //===----------------------------------------------------------------------===//
5538 // Advanced SIMD (NEON) Support
5541 include "ARMInstrNEON.td"
5543 //===----------------------------------------------------------------------===//
5544 // Assembler aliases
5548 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5549 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5550 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5552 // System instructions
5553 def : MnemonicAlias<"swi", "svc">;
5555 // Load / Store Multiple
5556 def : MnemonicAlias<"ldmfd", "ldm">;
5557 def : MnemonicAlias<"ldmia", "ldm">;
5558 def : MnemonicAlias<"ldmea", "ldmdb">;
5559 def : MnemonicAlias<"stmfd", "stmdb">;
5560 def : MnemonicAlias<"stmia", "stm">;
5561 def : MnemonicAlias<"stmea", "stm">;
5563 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5564 // shift amount is zero (i.e., unspecified).
5565 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5566 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5567 Requires<[IsARM, HasV6]>;
5568 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5569 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5570 Requires<[IsARM, HasV6]>;
5572 // PUSH/POP aliases for STM/LDM
5573 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5574 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5576 // SSAT/USAT optional shift operand.
5577 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5578 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5579 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5580 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5583 // Extend instruction optional rotate operand.
5584 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5585 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5586 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5587 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5588 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5589 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5590 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5591 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5592 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5593 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5594 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5595 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5597 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5598 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5599 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5600 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5601 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5602 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5603 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5604 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5605 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5606 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5607 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5608 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5612 def : MnemonicAlias<"rfefa", "rfeda">;
5613 def : MnemonicAlias<"rfeea", "rfedb">;
5614 def : MnemonicAlias<"rfefd", "rfeia">;
5615 def : MnemonicAlias<"rfeed", "rfeib">;
5616 def : MnemonicAlias<"rfe", "rfeia">;
5619 def : MnemonicAlias<"srsfa", "srsib">;
5620 def : MnemonicAlias<"srsea", "srsia">;
5621 def : MnemonicAlias<"srsfd", "srsdb">;
5622 def : MnemonicAlias<"srsed", "srsda">;
5623 def : MnemonicAlias<"srs", "srsia">;
5626 def : MnemonicAlias<"qsubaddx", "qsax">;
5628 def : MnemonicAlias<"saddsubx", "sasx">;
5629 // SHASX == SHADDSUBX
5630 def : MnemonicAlias<"shaddsubx", "shasx">;
5631 // SHSAX == SHSUBADDX
5632 def : MnemonicAlias<"shsubaddx", "shsax">;
5634 def : MnemonicAlias<"ssubaddx", "ssax">;
5636 def : MnemonicAlias<"uaddsubx", "uasx">;
5637 // UHASX == UHADDSUBX
5638 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5639 // UHSAX == UHSUBADDX
5640 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5641 // UQASX == UQADDSUBX
5642 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5643 // UQSAX == UQSUBADDX
5644 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5646 def : MnemonicAlias<"usubaddx", "usax">;
5648 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5650 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5651 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5652 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5653 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5654 // Same for AND <--> BIC
5655 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5656 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5657 pred:$p, cc_out:$s)>;
5658 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5659 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5660 pred:$p, cc_out:$s)>;
5661 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5662 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5663 pred:$p, cc_out:$s)>;
5664 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5665 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5666 pred:$p, cc_out:$s)>;
5668 // Likewise, "add Rd, mod_imm_neg" -> sub
5669 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5670 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5671 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5672 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5673 // Same for CMP <--> CMN via mod_imm_neg
5674 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5675 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5676 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5677 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5679 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5680 // LSR, ROR, and RRX instructions.
5681 // FIXME: We need C++ parser hooks to map the alias to the MOV
5682 // encoding. It seems we should be able to do that sort of thing
5683 // in tblgen, but it could get ugly.
5684 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5685 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5686 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5688 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5689 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5691 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5692 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5694 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5695 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5698 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5699 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5700 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5701 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5702 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5704 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5705 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5707 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5708 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5710 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5711 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5715 // "neg" is and alias for "rsb rd, rn, #0"
5716 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5717 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5719 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5720 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5721 Requires<[IsARM, NoV6]>;
5723 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5724 // the instruction definitions need difference constraints pre-v6.
5725 // Use these aliases for the assembly parsing on pre-v6.
5726 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5727 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5728 Requires<[IsARM, NoV6]>;
5729 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5730 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5731 pred:$p, cc_out:$s)>,
5732 Requires<[IsARM, NoV6]>;
5733 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5734 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5735 Requires<[IsARM, NoV6]>;
5736 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5737 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5738 Requires<[IsARM, NoV6]>;
5739 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5740 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5741 Requires<[IsARM, NoV6]>;
5742 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5743 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5744 Requires<[IsARM, NoV6]>;
5746 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5748 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5749 ComplexDeprecationPredicate<"IT">;
5751 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5752 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5754 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;