1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
62 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
96 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
98 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
99 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
100 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
101 [SDNPHasChain, SDNPSideEffect,
102 SDNPOptInGlue, SDNPOutGlue]>;
103 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
105 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
106 SDNPMayStore, SDNPMayLoad]>;
108 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
109 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
111 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
118 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
119 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
120 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
165 SDT_ARMEH_SJLJ_SetupDispatch,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
187 AssemblerPredicate<"HasV5TOps", "armv5t">;
188 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
189 AssemblerPredicate<"HasV5TEOps", "armv5te">;
190 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
191 AssemblerPredicate<"HasV6Ops", "armv6">;
192 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
193 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
194 AssemblerPredicate<"HasV6MOps",
195 "armv6m or armv6t2">;
196 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
197 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
198 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
199 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
200 AssemblerPredicate<"HasV6KOps", "armv6k">;
201 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
202 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
204 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
208 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
209 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
210 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
211 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
212 AssemblerPredicate<"FeatureVFP2", "VFP2">;
213 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
214 AssemblerPredicate<"FeatureVFP3", "VFP3">;
215 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
216 AssemblerPredicate<"FeatureVFP4", "VFP4">;
217 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
218 AssemblerPredicate<"!FeatureVFPOnlySP",
219 "double precision VFP">;
220 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
221 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
222 def HasNEON : Predicate<"Subtarget->hasNEON()">,
223 AssemblerPredicate<"FeatureNEON", "NEON">;
224 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
225 AssemblerPredicate<"FeatureCrypto", "crypto">;
226 def HasCRC : Predicate<"Subtarget->hasCRC()">,
227 AssemblerPredicate<"FeatureCRC", "crc">;
228 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
229 AssemblerPredicate<"FeatureFP16","half-float">;
230 def HasDivide : Predicate<"Subtarget->hasDivide()">,
231 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
232 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
233 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
234 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
235 AssemblerPredicate<"FeatureT2XtPk",
237 def HasDSP : Predicate<"Subtarget->hasDSP()">,
238 AssemblerPredicate<"FeatureDSP", "dsp">;
239 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
240 AssemblerPredicate<"FeatureDB",
242 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
243 AssemblerPredicate<"FeatureMP",
245 def HasVirtualization: Predicate<"false">,
246 AssemblerPredicate<"FeatureVirtualization",
247 "virtualization-extensions">;
248 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
249 AssemblerPredicate<"FeatureTrustZone",
251 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
252 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
253 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
254 def IsThumb : Predicate<"Subtarget->isThumb()">,
255 AssemblerPredicate<"ModeThumb", "thumb">;
256 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
257 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
258 AssemblerPredicate<"ModeThumb,FeatureThumb2",
260 def IsMClass : Predicate<"Subtarget->isMClass()">,
261 AssemblerPredicate<"FeatureMClass", "armv*m">;
262 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
263 AssemblerPredicate<"!FeatureMClass",
265 def IsARM : Predicate<"!Subtarget->isThumb()">,
266 AssemblerPredicate<"!ModeThumb", "arm-mode">;
267 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
268 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
269 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
270 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
271 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
272 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
274 // FIXME: Eventually this will be just "hasV6T2Ops".
275 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
276 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
277 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
278 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
280 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
281 // But only select them if more precision in FP computation is allowed.
282 // Do not use them for Darwin platforms.
283 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
284 " FPOpFusion::Fast && "
285 " Subtarget->hasVFP4()) && "
286 "!Subtarget->isTargetDarwin()">;
287 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
288 " FPOpFusion::Fast &&"
289 " Subtarget->hasVFP4()) || "
290 "Subtarget->isTargetDarwin()">;
292 // VGETLNi32 is microcoded on Swift - prefer VMOV.
293 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
294 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
296 // VDUP.32 is microcoded on Swift - prefer VMOV.
297 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
298 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
300 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
301 // this allows more effective execution domain optimization. See
302 // setExecutionDomain().
303 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
304 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
306 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
307 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
309 //===----------------------------------------------------------------------===//
310 // ARM Flag Definitions.
312 class RegConstraint<string C> {
313 string Constraints = C;
316 //===----------------------------------------------------------------------===//
317 // ARM specific transformation functions and pattern fragments.
320 // imm_neg_XFORM - Return the negation of an i32 immediate value.
321 def imm_neg_XFORM : SDNodeXForm<imm, [{
322 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
325 // imm_not_XFORM - Return the complement of a i32 immediate value.
326 def imm_not_XFORM : SDNodeXForm<imm, [{
327 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
330 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
331 def imm16_31 : ImmLeaf<i32, [{
332 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
335 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
336 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
337 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
340 /// Split a 32-bit immediate into two 16 bit parts.
341 def hi16 : SDNodeXForm<imm, [{
342 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
346 def lo16AllZero : PatLeaf<(i32 imm), [{
347 // Returns true if all low 16-bits are 0.
348 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
351 class BinOpWithFlagFrag<dag res> :
352 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
353 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
354 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
356 // An 'and' node with a single use.
357 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
358 return N->hasOneUse();
361 // An 'xor' node with a single use.
362 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
363 return N->hasOneUse();
366 // An 'fmul' node with a single use.
367 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
368 return N->hasOneUse();
371 // An 'fadd' node which checks for single non-hazardous use.
372 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
373 return hasNoVMLxHazardUse(N);
376 // An 'fsub' node which checks for single non-hazardous use.
377 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
378 return hasNoVMLxHazardUse(N);
381 //===----------------------------------------------------------------------===//
382 // Operand Definitions.
385 // Immediate operands with a shared generic asm render method.
386 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
388 // Operands that are part of a memory addressing mode.
389 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
392 // FIXME: rename brtarget to t2_brtarget
393 def brtarget : Operand<OtherVT> {
394 let EncoderMethod = "getBranchTargetOpValue";
395 let OperandType = "OPERAND_PCREL";
396 let DecoderMethod = "DecodeT2BROperand";
399 // FIXME: get rid of this one?
400 def uncondbrtarget : Operand<OtherVT> {
401 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
402 let OperandType = "OPERAND_PCREL";
405 // Branch target for ARM. Handles conditional/unconditional
406 def br_target : Operand<OtherVT> {
407 let EncoderMethod = "getARMBranchTargetOpValue";
408 let OperandType = "OPERAND_PCREL";
412 // FIXME: rename bltarget to t2_bl_target?
413 def bltarget : Operand<i32> {
414 // Encoded the same as branch targets.
415 let EncoderMethod = "getBranchTargetOpValue";
416 let OperandType = "OPERAND_PCREL";
419 // Call target for ARM. Handles conditional/unconditional
420 // FIXME: rename bl_target to t2_bltarget?
421 def bl_target : Operand<i32> {
422 let EncoderMethod = "getARMBLTargetOpValue";
423 let OperandType = "OPERAND_PCREL";
426 def blx_target : Operand<i32> {
427 let EncoderMethod = "getARMBLXTargetOpValue";
428 let OperandType = "OPERAND_PCREL";
431 // A list of registers separated by comma. Used by load/store multiple.
432 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
433 def reglist : Operand<i32> {
434 let EncoderMethod = "getRegisterListOpValue";
435 let ParserMatchClass = RegListAsmOperand;
436 let PrintMethod = "printRegisterList";
437 let DecoderMethod = "DecodeRegListOperand";
440 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
442 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
443 def dpr_reglist : Operand<i32> {
444 let EncoderMethod = "getRegisterListOpValue";
445 let ParserMatchClass = DPRRegListAsmOperand;
446 let PrintMethod = "printRegisterList";
447 let DecoderMethod = "DecodeDPRRegListOperand";
450 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
451 def spr_reglist : Operand<i32> {
452 let EncoderMethod = "getRegisterListOpValue";
453 let ParserMatchClass = SPRRegListAsmOperand;
454 let PrintMethod = "printRegisterList";
455 let DecoderMethod = "DecodeSPRRegListOperand";
458 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
459 def cpinst_operand : Operand<i32> {
460 let PrintMethod = "printCPInstOperand";
464 def pclabel : Operand<i32> {
465 let PrintMethod = "printPCLabel";
468 // ADR instruction labels.
469 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
470 def adrlabel : Operand<i32> {
471 let EncoderMethod = "getAdrLabelOpValue";
472 let ParserMatchClass = AdrLabelAsmOperand;
473 let PrintMethod = "printAdrLabelOperand<0>";
476 def neon_vcvt_imm32 : Operand<i32> {
477 let EncoderMethod = "getNEONVcvtImm32OpValue";
478 let DecoderMethod = "DecodeVCVTImmOperand";
481 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
482 def rot_imm_XFORM: SDNodeXForm<imm, [{
483 switch (N->getZExtValue()){
484 default: llvm_unreachable(nullptr);
485 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
486 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
487 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
488 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
491 def RotImmAsmOperand : AsmOperandClass {
493 let ParserMethod = "parseRotImm";
495 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
496 int32_t v = N->getZExtValue();
497 return v == 8 || v == 16 || v == 24; }],
499 let PrintMethod = "printRotImmOperand";
500 let ParserMatchClass = RotImmAsmOperand;
503 // shift_imm: An integer that encodes a shift amount and the type of shift
504 // (asr or lsl). The 6-bit immediate encodes as:
507 // {4-0} imm5 shift amount.
508 // asr #32 encoded as imm5 == 0.
509 def ShifterImmAsmOperand : AsmOperandClass {
510 let Name = "ShifterImm";
511 let ParserMethod = "parseShifterImm";
513 def shift_imm : Operand<i32> {
514 let PrintMethod = "printShiftImmOperand";
515 let ParserMatchClass = ShifterImmAsmOperand;
518 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
519 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
520 def so_reg_reg : Operand<i32>, // reg reg imm
521 ComplexPattern<i32, 3, "SelectRegShifterOperand",
522 [shl, srl, sra, rotr]> {
523 let EncoderMethod = "getSORegRegOpValue";
524 let PrintMethod = "printSORegRegOperand";
525 let DecoderMethod = "DecodeSORegRegOperand";
526 let ParserMatchClass = ShiftedRegAsmOperand;
527 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
530 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
531 def so_reg_imm : Operand<i32>, // reg imm
532 ComplexPattern<i32, 2, "SelectImmShifterOperand",
533 [shl, srl, sra, rotr]> {
534 let EncoderMethod = "getSORegImmOpValue";
535 let PrintMethod = "printSORegImmOperand";
536 let DecoderMethod = "DecodeSORegImmOperand";
537 let ParserMatchClass = ShiftedImmAsmOperand;
538 let MIOperandInfo = (ops GPR, i32imm);
541 // FIXME: Does this need to be distinct from so_reg?
542 def shift_so_reg_reg : Operand<i32>, // reg reg imm
543 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
544 [shl,srl,sra,rotr]> {
545 let EncoderMethod = "getSORegRegOpValue";
546 let PrintMethod = "printSORegRegOperand";
547 let DecoderMethod = "DecodeSORegRegOperand";
548 let ParserMatchClass = ShiftedRegAsmOperand;
549 let MIOperandInfo = (ops GPR, GPR, i32imm);
552 // FIXME: Does this need to be distinct from so_reg?
553 def shift_so_reg_imm : Operand<i32>, // reg reg imm
554 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
555 [shl,srl,sra,rotr]> {
556 let EncoderMethod = "getSORegImmOpValue";
557 let PrintMethod = "printSORegImmOperand";
558 let DecoderMethod = "DecodeSORegImmOperand";
559 let ParserMatchClass = ShiftedImmAsmOperand;
560 let MIOperandInfo = (ops GPR, i32imm);
563 // mod_imm: match a 32-bit immediate operand, which can be encoded into
564 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
565 // - "Modified Immediate Constants"). Within the MC layer we keep this
566 // immediate in its encoded form.
567 def ModImmAsmOperand: AsmOperandClass {
569 let ParserMethod = "parseModImm";
571 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
572 return ARM_AM::getSOImmVal(Imm) != -1;
574 let EncoderMethod = "getModImmOpValue";
575 let PrintMethod = "printModImmOperand";
576 let ParserMatchClass = ModImmAsmOperand;
579 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
580 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
581 // The actual parsing, encoding, decoding are handled by the destination
582 // instructions, which use mod_imm.
584 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
585 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
586 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
588 let ParserMatchClass = ModImmNotAsmOperand;
591 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
592 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
593 unsigned Value = -(unsigned)N->getZExtValue();
594 return Value && ARM_AM::getSOImmVal(Value) != -1;
596 let ParserMatchClass = ModImmNegAsmOperand;
599 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
600 def arm_i32imm : PatLeaf<(imm), [{
601 if (Subtarget->useMovt(*MF))
603 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
606 /// imm0_1 predicate - Immediate in the range [0,1].
607 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
608 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
610 /// imm0_3 predicate - Immediate in the range [0,3].
611 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
612 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
614 /// imm0_7 predicate - Immediate in the range [0,7].
615 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
616 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
617 return Imm >= 0 && Imm < 8;
619 let ParserMatchClass = Imm0_7AsmOperand;
622 /// imm8 predicate - Immediate is exactly 8.
623 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
624 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
625 let ParserMatchClass = Imm8AsmOperand;
628 /// imm16 predicate - Immediate is exactly 16.
629 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
630 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
631 let ParserMatchClass = Imm16AsmOperand;
634 /// imm32 predicate - Immediate is exactly 32.
635 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
636 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
637 let ParserMatchClass = Imm32AsmOperand;
640 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
642 /// imm1_7 predicate - Immediate in the range [1,7].
643 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
644 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
645 let ParserMatchClass = Imm1_7AsmOperand;
648 /// imm1_15 predicate - Immediate in the range [1,15].
649 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
650 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
651 let ParserMatchClass = Imm1_15AsmOperand;
654 /// imm1_31 predicate - Immediate in the range [1,31].
655 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
656 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
657 let ParserMatchClass = Imm1_31AsmOperand;
660 /// imm0_15 predicate - Immediate in the range [0,15].
661 def Imm0_15AsmOperand: ImmAsmOperand {
662 let Name = "Imm0_15";
663 let DiagnosticType = "ImmRange0_15";
665 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
666 return Imm >= 0 && Imm < 16;
668 let ParserMatchClass = Imm0_15AsmOperand;
671 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
672 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
673 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
674 return Imm >= 0 && Imm < 32;
676 let ParserMatchClass = Imm0_31AsmOperand;
679 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
680 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
681 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
682 return Imm >= 0 && Imm < 32;
684 let ParserMatchClass = Imm0_32AsmOperand;
687 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
688 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
689 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
690 return Imm >= 0 && Imm < 64;
692 let ParserMatchClass = Imm0_63AsmOperand;
695 /// imm0_239 predicate - Immediate in the range [0,239].
696 def Imm0_239AsmOperand : ImmAsmOperand {
697 let Name = "Imm0_239";
698 let DiagnosticType = "ImmRange0_239";
700 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
701 let ParserMatchClass = Imm0_239AsmOperand;
704 /// imm0_255 predicate - Immediate in the range [0,255].
705 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
706 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
707 let ParserMatchClass = Imm0_255AsmOperand;
710 /// imm0_65535 - An immediate is in the range [0.65535].
711 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
712 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
713 return Imm >= 0 && Imm < 65536;
715 let ParserMatchClass = Imm0_65535AsmOperand;
718 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
719 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
720 return -Imm >= 0 && -Imm < 65536;
723 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
724 // a relocatable expression.
726 // FIXME: This really needs a Thumb version separate from the ARM version.
727 // While the range is the same, and can thus use the same match class,
728 // the encoding is different so it should have a different encoder method.
729 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
730 def imm0_65535_expr : Operand<i32> {
731 let EncoderMethod = "getHiLo16ImmOpValue";
732 let ParserMatchClass = Imm0_65535ExprAsmOperand;
735 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
736 def imm256_65535_expr : Operand<i32> {
737 let ParserMatchClass = Imm256_65535ExprAsmOperand;
740 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
741 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
742 def imm24b : Operand<i32>, ImmLeaf<i32, [{
743 return Imm >= 0 && Imm <= 0xffffff;
745 let ParserMatchClass = Imm24bitAsmOperand;
749 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
751 def BitfieldAsmOperand : AsmOperandClass {
752 let Name = "Bitfield";
753 let ParserMethod = "parseBitfield";
756 def bf_inv_mask_imm : Operand<i32>,
758 return ARM::isBitFieldInvertedMask(N->getZExtValue());
760 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
761 let PrintMethod = "printBitfieldInvMaskImmOperand";
762 let DecoderMethod = "DecodeBitfieldMaskOperand";
763 let ParserMatchClass = BitfieldAsmOperand;
766 def imm1_32_XFORM: SDNodeXForm<imm, [{
767 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
770 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
771 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
772 uint64_t Imm = N->getZExtValue();
773 return Imm > 0 && Imm <= 32;
776 let PrintMethod = "printImmPlusOneOperand";
777 let ParserMatchClass = Imm1_32AsmOperand;
780 def imm1_16_XFORM: SDNodeXForm<imm, [{
781 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
784 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
785 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
787 let PrintMethod = "printImmPlusOneOperand";
788 let ParserMatchClass = Imm1_16AsmOperand;
791 // Define ARM specific addressing modes.
792 // addrmode_imm12 := reg +/- imm12
794 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
795 class AddrMode_Imm12 : MemOperand,
796 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
797 // 12-bit immediate operand. Note that instructions using this encode
798 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
799 // immediate values are as normal.
801 let EncoderMethod = "getAddrModeImm12OpValue";
802 let DecoderMethod = "DecodeAddrModeImm12Operand";
803 let ParserMatchClass = MemImm12OffsetAsmOperand;
804 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
807 def addrmode_imm12 : AddrMode_Imm12 {
808 let PrintMethod = "printAddrModeImm12Operand<false>";
811 def addrmode_imm12_pre : AddrMode_Imm12 {
812 let PrintMethod = "printAddrModeImm12Operand<true>";
815 // ldst_so_reg := reg +/- reg shop imm
817 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
818 def ldst_so_reg : MemOperand,
819 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
820 let EncoderMethod = "getLdStSORegOpValue";
821 // FIXME: Simplify the printer
822 let PrintMethod = "printAddrMode2Operand";
823 let DecoderMethod = "DecodeSORegMemOperand";
824 let ParserMatchClass = MemRegOffsetAsmOperand;
825 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
828 // postidx_imm8 := +/- [0,255]
831 // {8} 1 is imm8 is non-negative. 0 otherwise.
832 // {7-0} [0,255] imm8 value.
833 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
834 def postidx_imm8 : MemOperand {
835 let PrintMethod = "printPostIdxImm8Operand";
836 let ParserMatchClass = PostIdxImm8AsmOperand;
837 let MIOperandInfo = (ops i32imm);
840 // postidx_imm8s4 := +/- [0,1020]
843 // {8} 1 is imm8 is non-negative. 0 otherwise.
844 // {7-0} [0,255] imm8 value, scaled by 4.
845 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
846 def postidx_imm8s4 : MemOperand {
847 let PrintMethod = "printPostIdxImm8s4Operand";
848 let ParserMatchClass = PostIdxImm8s4AsmOperand;
849 let MIOperandInfo = (ops i32imm);
853 // postidx_reg := +/- reg
855 def PostIdxRegAsmOperand : AsmOperandClass {
856 let Name = "PostIdxReg";
857 let ParserMethod = "parsePostIdxReg";
859 def postidx_reg : MemOperand {
860 let EncoderMethod = "getPostIdxRegOpValue";
861 let DecoderMethod = "DecodePostIdxReg";
862 let PrintMethod = "printPostIdxRegOperand";
863 let ParserMatchClass = PostIdxRegAsmOperand;
864 let MIOperandInfo = (ops GPRnopc, i32imm);
868 // addrmode2 := reg +/- imm12
869 // := reg +/- reg shop imm
871 // FIXME: addrmode2 should be refactored the rest of the way to always
872 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
873 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
874 def addrmode2 : MemOperand,
875 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
876 let EncoderMethod = "getAddrMode2OpValue";
877 let PrintMethod = "printAddrMode2Operand";
878 let ParserMatchClass = AddrMode2AsmOperand;
879 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
882 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
883 let Name = "PostIdxRegShifted";
884 let ParserMethod = "parsePostIdxReg";
886 def am2offset_reg : MemOperand,
887 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
888 [], [SDNPWantRoot]> {
889 let EncoderMethod = "getAddrMode2OffsetOpValue";
890 let PrintMethod = "printAddrMode2OffsetOperand";
891 // When using this for assembly, it's always as a post-index offset.
892 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
893 let MIOperandInfo = (ops GPRnopc, i32imm);
896 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
897 // the GPR is purely vestigal at this point.
898 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
899 def am2offset_imm : MemOperand,
900 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
901 [], [SDNPWantRoot]> {
902 let EncoderMethod = "getAddrMode2OffsetOpValue";
903 let PrintMethod = "printAddrMode2OffsetOperand";
904 let ParserMatchClass = AM2OffsetImmAsmOperand;
905 let MIOperandInfo = (ops GPRnopc, i32imm);
909 // addrmode3 := reg +/- reg
910 // addrmode3 := reg +/- imm8
912 // FIXME: split into imm vs. reg versions.
913 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
914 class AddrMode3 : MemOperand,
915 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
916 let EncoderMethod = "getAddrMode3OpValue";
917 let ParserMatchClass = AddrMode3AsmOperand;
918 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
921 def addrmode3 : AddrMode3
923 let PrintMethod = "printAddrMode3Operand<false>";
926 def addrmode3_pre : AddrMode3
928 let PrintMethod = "printAddrMode3Operand<true>";
931 // FIXME: split into imm vs. reg versions.
932 // FIXME: parser method to handle +/- register.
933 def AM3OffsetAsmOperand : AsmOperandClass {
934 let Name = "AM3Offset";
935 let ParserMethod = "parseAM3Offset";
937 def am3offset : MemOperand,
938 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
939 [], [SDNPWantRoot]> {
940 let EncoderMethod = "getAddrMode3OffsetOpValue";
941 let PrintMethod = "printAddrMode3OffsetOperand";
942 let ParserMatchClass = AM3OffsetAsmOperand;
943 let MIOperandInfo = (ops GPR, i32imm);
946 // ldstm_mode := {ia, ib, da, db}
948 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
949 let EncoderMethod = "getLdStmModeOpValue";
950 let PrintMethod = "printLdStmModeOperand";
953 // addrmode5 := reg +/- imm8*4
955 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
956 class AddrMode5 : MemOperand,
957 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
958 let EncoderMethod = "getAddrMode5OpValue";
959 let DecoderMethod = "DecodeAddrMode5Operand";
960 let ParserMatchClass = AddrMode5AsmOperand;
961 let MIOperandInfo = (ops GPR:$base, i32imm);
964 def addrmode5 : AddrMode5 {
965 let PrintMethod = "printAddrMode5Operand<false>";
968 def addrmode5_pre : AddrMode5 {
969 let PrintMethod = "printAddrMode5Operand<true>";
972 // addrmode6 := reg with optional alignment
974 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
975 def addrmode6 : MemOperand,
976 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
977 let PrintMethod = "printAddrMode6Operand";
978 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
979 let EncoderMethod = "getAddrMode6AddressOpValue";
980 let DecoderMethod = "DecodeAddrMode6Operand";
981 let ParserMatchClass = AddrMode6AsmOperand;
984 def am6offset : MemOperand,
985 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
986 [], [SDNPWantRoot]> {
987 let PrintMethod = "printAddrMode6OffsetOperand";
988 let MIOperandInfo = (ops GPR);
989 let EncoderMethod = "getAddrMode6OffsetOpValue";
990 let DecoderMethod = "DecodeGPRRegisterClass";
993 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
994 // (single element from one lane) for size 32.
995 def addrmode6oneL32 : MemOperand,
996 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
997 let PrintMethod = "printAddrMode6Operand";
998 let MIOperandInfo = (ops GPR:$addr, i32imm);
999 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1002 // Base class for addrmode6 with specific alignment restrictions.
1003 class AddrMode6Align : MemOperand,
1004 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1005 let PrintMethod = "printAddrMode6Operand";
1006 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1007 let EncoderMethod = "getAddrMode6AddressOpValue";
1008 let DecoderMethod = "DecodeAddrMode6Operand";
1011 // Special version of addrmode6 to handle no allowed alignment encoding for
1012 // VLD/VST instructions and checking the alignment is not specified.
1013 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1014 let Name = "AlignedMemoryNone";
1015 let DiagnosticType = "AlignedMemoryRequiresNone";
1017 def addrmode6alignNone : AddrMode6Align {
1018 // The alignment specifier can only be omitted.
1019 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1022 // Special version of addrmode6 to handle 16-bit alignment encoding for
1023 // VLD/VST instructions and checking the alignment value.
1024 def AddrMode6Align16AsmOperand : AsmOperandClass {
1025 let Name = "AlignedMemory16";
1026 let DiagnosticType = "AlignedMemoryRequires16";
1028 def addrmode6align16 : AddrMode6Align {
1029 // The alignment specifier can only be 16 or omitted.
1030 let ParserMatchClass = AddrMode6Align16AsmOperand;
1033 // Special version of addrmode6 to handle 32-bit alignment encoding for
1034 // VLD/VST instructions and checking the alignment value.
1035 def AddrMode6Align32AsmOperand : AsmOperandClass {
1036 let Name = "AlignedMemory32";
1037 let DiagnosticType = "AlignedMemoryRequires32";
1039 def addrmode6align32 : AddrMode6Align {
1040 // The alignment specifier can only be 32 or omitted.
1041 let ParserMatchClass = AddrMode6Align32AsmOperand;
1044 // Special version of addrmode6 to handle 64-bit alignment encoding for
1045 // VLD/VST instructions and checking the alignment value.
1046 def AddrMode6Align64AsmOperand : AsmOperandClass {
1047 let Name = "AlignedMemory64";
1048 let DiagnosticType = "AlignedMemoryRequires64";
1050 def addrmode6align64 : AddrMode6Align {
1051 // The alignment specifier can only be 64 or omitted.
1052 let ParserMatchClass = AddrMode6Align64AsmOperand;
1055 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1056 // for VLD/VST instructions and checking the alignment value.
1057 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1058 let Name = "AlignedMemory64or128";
1059 let DiagnosticType = "AlignedMemoryRequires64or128";
1061 def addrmode6align64or128 : AddrMode6Align {
1062 // The alignment specifier can only be 64, 128 or omitted.
1063 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1066 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1067 // encoding for VLD/VST instructions and checking the alignment value.
1068 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1069 let Name = "AlignedMemory64or128or256";
1070 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1072 def addrmode6align64or128or256 : AddrMode6Align {
1073 // The alignment specifier can only be 64, 128, 256 or omitted.
1074 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1077 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1078 // instructions, specifically VLD4-dup.
1079 def addrmode6dup : MemOperand,
1080 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1081 let PrintMethod = "printAddrMode6Operand";
1082 let MIOperandInfo = (ops GPR:$addr, i32imm);
1083 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1084 // FIXME: This is close, but not quite right. The alignment specifier is
1086 let ParserMatchClass = AddrMode6AsmOperand;
1089 // Base class for addrmode6dup with specific alignment restrictions.
1090 class AddrMode6DupAlign : MemOperand,
1091 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1092 let PrintMethod = "printAddrMode6Operand";
1093 let MIOperandInfo = (ops GPR:$addr, i32imm);
1094 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1097 // Special version of addrmode6 to handle no allowed alignment encoding for
1098 // VLD-dup instruction and checking the alignment is not specified.
1099 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1100 let Name = "DupAlignedMemoryNone";
1101 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1103 def addrmode6dupalignNone : AddrMode6DupAlign {
1104 // The alignment specifier can only be omitted.
1105 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1108 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1109 // instruction and checking the alignment value.
1110 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1111 let Name = "DupAlignedMemory16";
1112 let DiagnosticType = "DupAlignedMemoryRequires16";
1114 def addrmode6dupalign16 : AddrMode6DupAlign {
1115 // The alignment specifier can only be 16 or omitted.
1116 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1119 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1120 // instruction and checking the alignment value.
1121 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1122 let Name = "DupAlignedMemory32";
1123 let DiagnosticType = "DupAlignedMemoryRequires32";
1125 def addrmode6dupalign32 : AddrMode6DupAlign {
1126 // The alignment specifier can only be 32 or omitted.
1127 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1130 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1131 // instructions and checking the alignment value.
1132 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1133 let Name = "DupAlignedMemory64";
1134 let DiagnosticType = "DupAlignedMemoryRequires64";
1136 def addrmode6dupalign64 : AddrMode6DupAlign {
1137 // The alignment specifier can only be 64 or omitted.
1138 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1141 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1142 // for VLD instructions and checking the alignment value.
1143 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1144 let Name = "DupAlignedMemory64or128";
1145 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1147 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1148 // The alignment specifier can only be 64, 128 or omitted.
1149 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1152 // addrmodepc := pc + reg
1154 def addrmodepc : MemOperand,
1155 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1156 let PrintMethod = "printAddrModePCOperand";
1157 let MIOperandInfo = (ops GPR, i32imm);
1160 // addr_offset_none := reg
1162 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1163 def addr_offset_none : MemOperand,
1164 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1165 let PrintMethod = "printAddrMode7Operand";
1166 let DecoderMethod = "DecodeAddrMode7Operand";
1167 let ParserMatchClass = MemNoOffsetAsmOperand;
1168 let MIOperandInfo = (ops GPR:$base);
1171 def nohash_imm : Operand<i32> {
1172 let PrintMethod = "printNoHashImmediate";
1175 def CoprocNumAsmOperand : AsmOperandClass {
1176 let Name = "CoprocNum";
1177 let ParserMethod = "parseCoprocNumOperand";
1179 def p_imm : Operand<i32> {
1180 let PrintMethod = "printPImmediate";
1181 let ParserMatchClass = CoprocNumAsmOperand;
1182 let DecoderMethod = "DecodeCoprocessor";
1185 def CoprocRegAsmOperand : AsmOperandClass {
1186 let Name = "CoprocReg";
1187 let ParserMethod = "parseCoprocRegOperand";
1189 def c_imm : Operand<i32> {
1190 let PrintMethod = "printCImmediate";
1191 let ParserMatchClass = CoprocRegAsmOperand;
1193 def CoprocOptionAsmOperand : AsmOperandClass {
1194 let Name = "CoprocOption";
1195 let ParserMethod = "parseCoprocOptionOperand";
1197 def coproc_option_imm : Operand<i32> {
1198 let PrintMethod = "printCoprocOptionImm";
1199 let ParserMatchClass = CoprocOptionAsmOperand;
1202 //===----------------------------------------------------------------------===//
1204 include "ARMInstrFormats.td"
1206 //===----------------------------------------------------------------------===//
1207 // Multiclass helpers...
1210 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1211 /// binop that produces a value.
1212 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1213 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1214 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1215 PatFrag opnode, bit Commutable = 0> {
1216 // The register-immediate version is re-materializable. This is useful
1217 // in particular for taking the address of a local.
1218 let isReMaterializable = 1 in {
1219 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1220 iii, opc, "\t$Rd, $Rn, $imm",
1221 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1222 Sched<[WriteALU, ReadALU]> {
1227 let Inst{19-16} = Rn;
1228 let Inst{15-12} = Rd;
1229 let Inst{11-0} = imm;
1232 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1233 iir, opc, "\t$Rd, $Rn, $Rm",
1234 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1235 Sched<[WriteALU, ReadALU, ReadALU]> {
1240 let isCommutable = Commutable;
1241 let Inst{19-16} = Rn;
1242 let Inst{15-12} = Rd;
1243 let Inst{11-4} = 0b00000000;
1247 def rsi : AsI1<opcod, (outs GPR:$Rd),
1248 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1249 iis, opc, "\t$Rd, $Rn, $shift",
1250 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1251 Sched<[WriteALUsi, ReadALU]> {
1256 let Inst{19-16} = Rn;
1257 let Inst{15-12} = Rd;
1258 let Inst{11-5} = shift{11-5};
1260 let Inst{3-0} = shift{3-0};
1263 def rsr : AsI1<opcod, (outs GPR:$Rd),
1264 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1265 iis, opc, "\t$Rd, $Rn, $shift",
1266 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1267 Sched<[WriteALUsr, ReadALUsr]> {
1272 let Inst{19-16} = Rn;
1273 let Inst{15-12} = Rd;
1274 let Inst{11-8} = shift{11-8};
1276 let Inst{6-5} = shift{6-5};
1278 let Inst{3-0} = shift{3-0};
1282 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1283 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1284 /// it is equivalent to the AsI1_bin_irs counterpart.
1285 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1286 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1287 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1288 PatFrag opnode, bit Commutable = 0> {
1289 // The register-immediate version is re-materializable. This is useful
1290 // in particular for taking the address of a local.
1291 let isReMaterializable = 1 in {
1292 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1293 iii, opc, "\t$Rd, $Rn, $imm",
1294 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1295 Sched<[WriteALU, ReadALU]> {
1300 let Inst{19-16} = Rn;
1301 let Inst{15-12} = Rd;
1302 let Inst{11-0} = imm;
1305 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1306 iir, opc, "\t$Rd, $Rn, $Rm",
1307 [/* pattern left blank */]>,
1308 Sched<[WriteALU, ReadALU, ReadALU]> {
1312 let Inst{11-4} = 0b00000000;
1315 let Inst{15-12} = Rd;
1316 let Inst{19-16} = Rn;
1319 def rsi : AsI1<opcod, (outs GPR:$Rd),
1320 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1321 iis, opc, "\t$Rd, $Rn, $shift",
1322 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1323 Sched<[WriteALUsi, ReadALU]> {
1328 let Inst{19-16} = Rn;
1329 let Inst{15-12} = Rd;
1330 let Inst{11-5} = shift{11-5};
1332 let Inst{3-0} = shift{3-0};
1335 def rsr : AsI1<opcod, (outs GPR:$Rd),
1336 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1337 iis, opc, "\t$Rd, $Rn, $shift",
1338 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1339 Sched<[WriteALUsr, ReadALUsr]> {
1344 let Inst{19-16} = Rn;
1345 let Inst{15-12} = Rd;
1346 let Inst{11-8} = shift{11-8};
1348 let Inst{6-5} = shift{6-5};
1350 let Inst{3-0} = shift{3-0};
1354 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1356 /// These opcodes will be converted to the real non-S opcodes by
1357 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1358 let hasPostISelHook = 1, Defs = [CPSR] in {
1359 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1360 InstrItinClass iis, PatFrag opnode,
1361 bit Commutable = 0> {
1362 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1364 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1365 Sched<[WriteALU, ReadALU]>;
1367 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1369 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1370 Sched<[WriteALU, ReadALU, ReadALU]> {
1371 let isCommutable = Commutable;
1373 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1374 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1376 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1377 so_reg_imm:$shift))]>,
1378 Sched<[WriteALUsi, ReadALU]>;
1380 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1381 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1383 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1384 so_reg_reg:$shift))]>,
1385 Sched<[WriteALUSsr, ReadALUsr]>;
1389 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1390 /// operands are reversed.
1391 let hasPostISelHook = 1, Defs = [CPSR] in {
1392 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1393 InstrItinClass iis, PatFrag opnode,
1394 bit Commutable = 0> {
1395 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1397 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1398 Sched<[WriteALU, ReadALU]>;
1400 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1401 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1403 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1405 Sched<[WriteALUsi, ReadALU]>;
1407 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1408 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1410 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1412 Sched<[WriteALUSsr, ReadALUsr]>;
1416 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1417 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1418 /// a explicit result, only implicitly set CPSR.
1419 let isCompare = 1, Defs = [CPSR] in {
1420 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1421 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1422 PatFrag opnode, bit Commutable = 0,
1423 string rrDecoderMethod = ""> {
1424 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1426 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1427 Sched<[WriteCMP, ReadALU]> {
1432 let Inst{19-16} = Rn;
1433 let Inst{15-12} = 0b0000;
1434 let Inst{11-0} = imm;
1436 let Unpredictable{15-12} = 0b1111;
1438 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1440 [(opnode GPR:$Rn, GPR:$Rm)]>,
1441 Sched<[WriteCMP, ReadALU, ReadALU]> {
1444 let isCommutable = Commutable;
1447 let Inst{19-16} = Rn;
1448 let Inst{15-12} = 0b0000;
1449 let Inst{11-4} = 0b00000000;
1451 let DecoderMethod = rrDecoderMethod;
1453 let Unpredictable{15-12} = 0b1111;
1455 def rsi : AI1<opcod, (outs),
1456 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1457 opc, "\t$Rn, $shift",
1458 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1459 Sched<[WriteCMPsi, ReadALU]> {
1464 let Inst{19-16} = Rn;
1465 let Inst{15-12} = 0b0000;
1466 let Inst{11-5} = shift{11-5};
1468 let Inst{3-0} = shift{3-0};
1470 let Unpredictable{15-12} = 0b1111;
1472 def rsr : AI1<opcod, (outs),
1473 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1474 opc, "\t$Rn, $shift",
1475 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1476 Sched<[WriteCMPsr, ReadALU]> {
1481 let Inst{19-16} = Rn;
1482 let Inst{15-12} = 0b0000;
1483 let Inst{11-8} = shift{11-8};
1485 let Inst{6-5} = shift{6-5};
1487 let Inst{3-0} = shift{3-0};
1489 let Unpredictable{15-12} = 0b1111;
1495 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1496 /// register and one whose operand is a register rotated by 8/16/24.
1497 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1498 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1499 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1500 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1501 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1502 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1506 let Inst{19-16} = 0b1111;
1507 let Inst{15-12} = Rd;
1508 let Inst{11-10} = rot;
1512 class AI_ext_rrot_np<bits<8> opcod, string opc>
1513 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1514 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1515 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1517 let Inst{19-16} = 0b1111;
1518 let Inst{11-10} = rot;
1521 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1522 /// register and one whose operand is a register rotated by 8/16/24.
1523 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1524 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1525 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1526 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1527 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1528 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1533 let Inst{19-16} = Rn;
1534 let Inst{15-12} = Rd;
1535 let Inst{11-10} = rot;
1536 let Inst{9-4} = 0b000111;
1540 class AI_exta_rrot_np<bits<8> opcod, string opc>
1541 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1542 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1543 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1546 let Inst{19-16} = Rn;
1547 let Inst{11-10} = rot;
1550 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1551 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1552 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1553 bit Commutable = 0> {
1554 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1555 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1556 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1557 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1559 Sched<[WriteALU, ReadALU]> {
1564 let Inst{15-12} = Rd;
1565 let Inst{19-16} = Rn;
1566 let Inst{11-0} = imm;
1568 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1569 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1570 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1572 Sched<[WriteALU, ReadALU, ReadALU]> {
1576 let Inst{11-4} = 0b00000000;
1578 let isCommutable = Commutable;
1580 let Inst{15-12} = Rd;
1581 let Inst{19-16} = Rn;
1583 def rsi : AsI1<opcod, (outs GPR:$Rd),
1584 (ins GPR:$Rn, so_reg_imm:$shift),
1585 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1586 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1588 Sched<[WriteALUsi, ReadALU]> {
1593 let Inst{19-16} = Rn;
1594 let Inst{15-12} = Rd;
1595 let Inst{11-5} = shift{11-5};
1597 let Inst{3-0} = shift{3-0};
1599 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1600 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1601 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1602 [(set GPRnopc:$Rd, CPSR,
1603 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1605 Sched<[WriteALUsr, ReadALUsr]> {
1610 let Inst{19-16} = Rn;
1611 let Inst{15-12} = Rd;
1612 let Inst{11-8} = shift{11-8};
1614 let Inst{6-5} = shift{6-5};
1616 let Inst{3-0} = shift{3-0};
1621 /// AI1_rsc_irs - Define instructions and patterns for rsc
1622 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1623 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1624 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1625 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1626 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1627 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1629 Sched<[WriteALU, ReadALU]> {
1634 let Inst{15-12} = Rd;
1635 let Inst{19-16} = Rn;
1636 let Inst{11-0} = imm;
1638 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1639 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1640 [/* pattern left blank */]>,
1641 Sched<[WriteALU, ReadALU, ReadALU]> {
1645 let Inst{11-4} = 0b00000000;
1648 let Inst{15-12} = Rd;
1649 let Inst{19-16} = Rn;
1651 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1652 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1653 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1655 Sched<[WriteALUsi, ReadALU]> {
1660 let Inst{19-16} = Rn;
1661 let Inst{15-12} = Rd;
1662 let Inst{11-5} = shift{11-5};
1664 let Inst{3-0} = shift{3-0};
1666 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1667 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1668 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1670 Sched<[WriteALUsr, ReadALUsr]> {
1675 let Inst{19-16} = Rn;
1676 let Inst{15-12} = Rd;
1677 let Inst{11-8} = shift{11-8};
1679 let Inst{6-5} = shift{6-5};
1681 let Inst{3-0} = shift{3-0};
1686 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1687 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1688 InstrItinClass iir, PatFrag opnode> {
1689 // Note: We use the complex addrmode_imm12 rather than just an input
1690 // GPR and a constrained immediate so that we can use this to match
1691 // frame index references and avoid matching constant pool references.
1692 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1693 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1694 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1697 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1698 let Inst{19-16} = addr{16-13}; // Rn
1699 let Inst{15-12} = Rt;
1700 let Inst{11-0} = addr{11-0}; // imm12
1702 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1703 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1704 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1707 let shift{4} = 0; // Inst{4} = 0
1708 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1709 let Inst{19-16} = shift{16-13}; // Rn
1710 let Inst{15-12} = Rt;
1711 let Inst{11-0} = shift{11-0};
1716 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1717 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1718 InstrItinClass iir, PatFrag opnode> {
1719 // Note: We use the complex addrmode_imm12 rather than just an input
1720 // GPR and a constrained immediate so that we can use this to match
1721 // frame index references and avoid matching constant pool references.
1722 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1723 (ins addrmode_imm12:$addr),
1724 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1725 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1728 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1729 let Inst{19-16} = addr{16-13}; // Rn
1730 let Inst{15-12} = Rt;
1731 let Inst{11-0} = addr{11-0}; // imm12
1733 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1734 (ins ldst_so_reg:$shift),
1735 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1736 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1739 let shift{4} = 0; // Inst{4} = 0
1740 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1741 let Inst{19-16} = shift{16-13}; // Rn
1742 let Inst{15-12} = Rt;
1743 let Inst{11-0} = shift{11-0};
1749 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1750 InstrItinClass iir, PatFrag opnode> {
1751 // Note: We use the complex addrmode_imm12 rather than just an input
1752 // GPR and a constrained immediate so that we can use this to match
1753 // frame index references and avoid matching constant pool references.
1754 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1755 (ins GPR:$Rt, addrmode_imm12:$addr),
1756 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1757 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1760 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1761 let Inst{19-16} = addr{16-13}; // Rn
1762 let Inst{15-12} = Rt;
1763 let Inst{11-0} = addr{11-0}; // imm12
1765 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1766 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1767 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1770 let shift{4} = 0; // Inst{4} = 0
1771 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1772 let Inst{19-16} = shift{16-13}; // Rn
1773 let Inst{15-12} = Rt;
1774 let Inst{11-0} = shift{11-0};
1778 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1779 InstrItinClass iir, PatFrag opnode> {
1780 // Note: We use the complex addrmode_imm12 rather than just an input
1781 // GPR and a constrained immediate so that we can use this to match
1782 // frame index references and avoid matching constant pool references.
1783 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1784 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1785 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1786 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1789 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1790 let Inst{19-16} = addr{16-13}; // Rn
1791 let Inst{15-12} = Rt;
1792 let Inst{11-0} = addr{11-0}; // imm12
1794 def rs : AI2ldst<0b011, 0, isByte, (outs),
1795 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1796 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1797 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1800 let shift{4} = 0; // Inst{4} = 0
1801 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1802 let Inst{19-16} = shift{16-13}; // Rn
1803 let Inst{15-12} = Rt;
1804 let Inst{11-0} = shift{11-0};
1809 //===----------------------------------------------------------------------===//
1811 //===----------------------------------------------------------------------===//
1813 //===----------------------------------------------------------------------===//
1814 // Miscellaneous Instructions.
1817 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1818 /// the function. The first operand is the ID# for this instruction, the second
1819 /// is the index into the MachineConstantPool that this is, the third is the
1820 /// size in bytes of this constant pool entry.
1821 let hasSideEffects = 0, isNotDuplicable = 1 in
1822 def CONSTPOOL_ENTRY :
1823 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1824 i32imm:$size), NoItinerary, []>;
1826 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1827 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1828 /// mode). Used mostly in ARM and Thumb-1 modes.
1829 def JUMPTABLE_ADDRS :
1830 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1831 i32imm:$size), NoItinerary, []>;
1833 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1834 /// that cannot be optimised to use TBB or TBH.
1835 def JUMPTABLE_INSTS :
1836 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1837 i32imm:$size), NoItinerary, []>;
1839 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1840 /// a TBB instruction.
1842 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1843 i32imm:$size), NoItinerary, []>;
1845 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1846 /// a TBH instruction.
1848 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1849 i32imm:$size), NoItinerary, []>;
1852 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1853 // from removing one half of the matched pairs. That breaks PEI, which assumes
1854 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1855 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1856 def ADJCALLSTACKUP :
1857 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1858 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1860 def ADJCALLSTACKDOWN :
1861 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1862 [(ARMcallseq_start timm:$amt)]>;
1865 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1866 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1867 Requires<[IsARM, HasV6]> {
1869 let Inst{27-8} = 0b00110010000011110000;
1870 let Inst{7-0} = imm;
1873 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1874 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1875 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1876 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1877 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1878 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1880 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1881 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1886 let Inst{15-12} = Rd;
1887 let Inst{19-16} = Rn;
1888 let Inst{27-20} = 0b01101000;
1889 let Inst{7-4} = 0b1011;
1890 let Inst{11-8} = 0b1111;
1891 let Unpredictable{11-8} = 0b1111;
1894 // The 16-bit operand $val can be used by a debugger to store more information
1895 // about the breakpoint.
1896 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1897 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1899 let Inst{3-0} = val{3-0};
1900 let Inst{19-8} = val{15-4};
1901 let Inst{27-20} = 0b00010010;
1902 let Inst{31-28} = 0xe; // AL
1903 let Inst{7-4} = 0b0111;
1905 // default immediate for breakpoint mnemonic
1906 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1908 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1909 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1911 let Inst{3-0} = val{3-0};
1912 let Inst{19-8} = val{15-4};
1913 let Inst{27-20} = 0b00010000;
1914 let Inst{31-28} = 0xe; // AL
1915 let Inst{7-4} = 0b0111;
1918 // Change Processor State
1919 // FIXME: We should use InstAlias to handle the optional operands.
1920 class CPS<dag iops, string asm_ops>
1921 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1922 []>, Requires<[IsARM]> {
1928 let Inst{31-28} = 0b1111;
1929 let Inst{27-20} = 0b00010000;
1930 let Inst{19-18} = imod;
1931 let Inst{17} = M; // Enabled if mode is set;
1932 let Inst{16-9} = 0b00000000;
1933 let Inst{8-6} = iflags;
1935 let Inst{4-0} = mode;
1938 let DecoderMethod = "DecodeCPSInstruction" in {
1940 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1941 "$imod\t$iflags, $mode">;
1942 let mode = 0, M = 0 in
1943 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1945 let imod = 0, iflags = 0, M = 1 in
1946 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1949 // Preload signals the memory system of possible future data/instruction access.
1950 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1952 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1953 IIC_Preload, !strconcat(opc, "\t$addr"),
1954 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1955 Sched<[WritePreLd]> {
1958 let Inst{31-26} = 0b111101;
1959 let Inst{25} = 0; // 0 for immediate form
1960 let Inst{24} = data;
1961 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1962 let Inst{22} = read;
1963 let Inst{21-20} = 0b01;
1964 let Inst{19-16} = addr{16-13}; // Rn
1965 let Inst{15-12} = 0b1111;
1966 let Inst{11-0} = addr{11-0}; // imm12
1969 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1970 !strconcat(opc, "\t$shift"),
1971 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1972 Sched<[WritePreLd]> {
1974 let Inst{31-26} = 0b111101;
1975 let Inst{25} = 1; // 1 for register form
1976 let Inst{24} = data;
1977 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1978 let Inst{22} = read;
1979 let Inst{21-20} = 0b01;
1980 let Inst{19-16} = shift{16-13}; // Rn
1981 let Inst{15-12} = 0b1111;
1982 let Inst{11-0} = shift{11-0};
1987 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1988 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1989 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1991 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1992 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1994 let Inst{31-10} = 0b1111000100000001000000;
1999 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2000 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2002 let Inst{27-4} = 0b001100100000111100001111;
2003 let Inst{3-0} = opt;
2006 // A8.8.247 UDF - Undefined (Encoding A1)
2007 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2008 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2010 let Inst{31-28} = 0b1110; // AL
2011 let Inst{27-25} = 0b011;
2012 let Inst{24-20} = 0b11111;
2013 let Inst{19-8} = imm16{15-4};
2014 let Inst{7-4} = 0b1111;
2015 let Inst{3-0} = imm16{3-0};
2019 * A5.4 Permanently UNDEFINED instructions.
2021 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2022 * Other UDF encodings generate SIGILL.
2024 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2026 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2028 * 1101 1110 iiii iiii
2029 * It uses the following encoding:
2030 * 1110 0111 1111 1110 1101 1110 1111 0000
2031 * - In ARM: UDF #60896;
2032 * - In Thumb: UDF #254 followed by a branch-to-self.
2034 let isBarrier = 1, isTerminator = 1 in
2035 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2037 Requires<[IsARM,UseNaClTrap]> {
2038 let Inst = 0xe7fedef0;
2040 let isBarrier = 1, isTerminator = 1 in
2041 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2043 Requires<[IsARM,DontUseNaClTrap]> {
2044 let Inst = 0xe7ffdefe;
2047 // Address computation and loads and stores in PIC mode.
2048 let isNotDuplicable = 1 in {
2049 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2051 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2052 Sched<[WriteALU, ReadALU]>;
2054 let AddedComplexity = 10 in {
2055 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2057 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2059 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2061 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2063 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2065 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2067 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2069 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2071 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2073 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2075 let AddedComplexity = 10 in {
2076 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2077 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2079 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2080 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2081 addrmodepc:$addr)]>;
2083 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2084 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2086 } // isNotDuplicable = 1
2089 // LEApcrel - Load a pc-relative address into a register without offending the
2091 let hasSideEffects = 0, isReMaterializable = 1 in
2092 // The 'adr' mnemonic encodes differently if the label is before or after
2093 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2094 // know until then which form of the instruction will be used.
2095 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2096 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2097 Sched<[WriteALU, ReadALU]> {
2100 let Inst{27-25} = 0b001;
2102 let Inst{23-22} = label{13-12};
2105 let Inst{19-16} = 0b1111;
2106 let Inst{15-12} = Rd;
2107 let Inst{11-0} = label{11-0};
2110 let hasSideEffects = 1 in {
2111 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2112 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2114 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2115 (ins i32imm:$label, pred:$p),
2116 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2119 //===----------------------------------------------------------------------===//
2120 // Control Flow Instructions.
2123 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2125 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2126 "bx", "\tlr", [(ARMretflag)]>,
2127 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2128 let Inst{27-0} = 0b0001001011111111111100011110;
2132 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2133 "mov", "\tpc, lr", [(ARMretflag)]>,
2134 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2135 let Inst{27-0} = 0b0001101000001111000000001110;
2138 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2139 // the user-space one).
2140 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2142 [(ARMintretflag imm:$offset)]>;
2145 // Indirect branches
2146 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2148 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2149 [(brind GPR:$dst)]>,
2150 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2152 let Inst{31-4} = 0b1110000100101111111111110001;
2153 let Inst{3-0} = dst;
2156 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2157 "bx", "\t$dst", [/* pattern left blank */]>,
2158 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2160 let Inst{27-4} = 0b000100101111111111110001;
2161 let Inst{3-0} = dst;
2165 // SP is marked as a use to prevent stack-pointer assignments that appear
2166 // immediately before calls from potentially appearing dead.
2168 // FIXME: Do we really need a non-predicated version? If so, it should
2169 // at least be a pseudo instruction expanding to the predicated version
2170 // at MC lowering time.
2171 Defs = [LR], Uses = [SP] in {
2172 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2173 IIC_Br, "bl\t$func",
2174 [(ARMcall tglobaladdr:$func)]>,
2175 Requires<[IsARM]>, Sched<[WriteBrL]> {
2176 let Inst{31-28} = 0b1110;
2178 let Inst{23-0} = func;
2179 let DecoderMethod = "DecodeBranchImmInstruction";
2182 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2183 IIC_Br, "bl", "\t$func",
2184 [(ARMcall_pred tglobaladdr:$func)]>,
2185 Requires<[IsARM]>, Sched<[WriteBrL]> {
2187 let Inst{23-0} = func;
2188 let DecoderMethod = "DecodeBranchImmInstruction";
2192 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2193 IIC_Br, "blx\t$func",
2194 [(ARMcall GPR:$func)]>,
2195 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2197 let Inst{31-4} = 0b1110000100101111111111110011;
2198 let Inst{3-0} = func;
2201 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2202 IIC_Br, "blx", "\t$func",
2203 [(ARMcall_pred GPR:$func)]>,
2204 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2206 let Inst{27-4} = 0b000100101111111111110011;
2207 let Inst{3-0} = func;
2211 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2212 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2213 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2214 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2217 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2218 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2219 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2221 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2222 // return stack predictor.
2223 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2224 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2225 Requires<[IsARM]>, Sched<[WriteBr]>;
2228 let isBranch = 1, isTerminator = 1 in {
2229 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2230 // a two-value operand where a dag node expects two operands. :(
2231 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2232 IIC_Br, "b", "\t$target",
2233 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2236 let Inst{23-0} = target;
2237 let DecoderMethod = "DecodeBranchImmInstruction";
2240 let isBarrier = 1 in {
2241 // B is "predicable" since it's just a Bcc with an 'always' condition.
2242 let isPredicable = 1 in
2243 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2244 // should be sufficient.
2245 // FIXME: Is B really a Barrier? That doesn't seem right.
2246 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2247 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2250 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2251 def BR_JTr : ARMPseudoInst<(outs),
2252 (ins GPR:$target, i32imm:$jt),
2254 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2256 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2257 // into i12 and rs suffixed versions.
2258 def BR_JTm : ARMPseudoInst<(outs),
2259 (ins addrmode2:$target, i32imm:$jt),
2261 [(ARMbrjt (i32 (load addrmode2:$target)),
2262 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2263 def BR_JTadd : ARMPseudoInst<(outs),
2264 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2266 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2267 Sched<[WriteBrTbl]>;
2268 } // isNotDuplicable = 1, isIndirectBranch = 1
2274 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2275 "blx\t$target", []>,
2276 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2277 let Inst{31-25} = 0b1111101;
2279 let Inst{23-0} = target{24-1};
2280 let Inst{24} = target{0};
2284 // Branch and Exchange Jazelle
2285 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2286 [/* pattern left blank */]>, Sched<[WriteBr]> {
2288 let Inst{23-20} = 0b0010;
2289 let Inst{19-8} = 0xfff;
2290 let Inst{7-4} = 0b0010;
2291 let Inst{3-0} = func;
2297 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2298 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2301 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2304 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2306 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2307 Requires<[IsARM]>, Sched<[WriteBr]>;
2309 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2311 (BX GPR:$dst)>, Sched<[WriteBr]>,
2315 // Secure Monitor Call is a system instruction.
2316 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2317 []>, Requires<[IsARM, HasTrustZone]> {
2319 let Inst{23-4} = 0b01100000000000000111;
2320 let Inst{3-0} = opt;
2323 // Supervisor Call (Software Interrupt)
2324 let isCall = 1, Uses = [SP] in {
2325 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2328 let Inst{23-0} = svc;
2332 // Store Return State
2333 class SRSI<bit wb, string asm>
2334 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2335 NoItinerary, asm, "", []> {
2337 let Inst{31-28} = 0b1111;
2338 let Inst{27-25} = 0b100;
2342 let Inst{19-16} = 0b1101; // SP
2343 let Inst{15-5} = 0b00000101000;
2344 let Inst{4-0} = mode;
2347 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2348 let Inst{24-23} = 0;
2350 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2351 let Inst{24-23} = 0;
2353 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2354 let Inst{24-23} = 0b10;
2356 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2357 let Inst{24-23} = 0b10;
2359 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2360 let Inst{24-23} = 0b01;
2362 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2363 let Inst{24-23} = 0b01;
2365 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2366 let Inst{24-23} = 0b11;
2368 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2369 let Inst{24-23} = 0b11;
2372 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2373 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2375 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2376 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2378 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2379 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2381 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2382 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2384 // Return From Exception
2385 class RFEI<bit wb, string asm>
2386 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2387 NoItinerary, asm, "", []> {
2389 let Inst{31-28} = 0b1111;
2390 let Inst{27-25} = 0b100;
2394 let Inst{19-16} = Rn;
2395 let Inst{15-0} = 0xa00;
2398 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2399 let Inst{24-23} = 0;
2401 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2402 let Inst{24-23} = 0;
2404 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2405 let Inst{24-23} = 0b10;
2407 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2408 let Inst{24-23} = 0b10;
2410 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2411 let Inst{24-23} = 0b01;
2413 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2414 let Inst{24-23} = 0b01;
2416 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2417 let Inst{24-23} = 0b11;
2419 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2420 let Inst{24-23} = 0b11;
2423 // Hypervisor Call is a system instruction
2425 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2426 "hvc", "\t$imm", []>,
2427 Requires<[IsARM, HasVirtualization]> {
2430 // Even though HVC isn't predicable, it's encoding includes a condition field.
2431 // The instruction is undefined if the condition field is 0xf otherwise it is
2432 // unpredictable if it isn't condition AL (0xe).
2433 let Inst{31-28} = 0b1110;
2434 let Unpredictable{31-28} = 0b1111;
2435 let Inst{27-24} = 0b0001;
2436 let Inst{23-20} = 0b0100;
2437 let Inst{19-8} = imm{15-4};
2438 let Inst{7-4} = 0b0111;
2439 let Inst{3-0} = imm{3-0};
2443 // Return from exception in Hypervisor mode.
2444 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2445 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2446 Requires<[IsARM, HasVirtualization]> {
2447 let Inst{23-0} = 0b011000000000000001101110;
2450 //===----------------------------------------------------------------------===//
2451 // Load / Store Instructions.
2457 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2458 UnOpFrag<(load node:$Src)>>;
2459 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2460 UnOpFrag<(zextloadi8 node:$Src)>>;
2461 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2462 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2463 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2464 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2466 // Special LDR for loads from non-pc-relative constpools.
2467 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2468 isReMaterializable = 1, isCodeGenOnly = 1 in
2469 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2470 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2474 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2475 let Inst{19-16} = 0b1111;
2476 let Inst{15-12} = Rt;
2477 let Inst{11-0} = addr{11-0}; // imm12
2480 // Loads with zero extension
2481 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2482 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2483 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2485 // Loads with sign extension
2486 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2487 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2488 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2490 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2491 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2492 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2494 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2496 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2497 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2498 Requires<[IsARM, HasV5TE]>;
2501 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2502 NoItinerary, "lda", "\t$Rt, $addr", []>;
2503 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2504 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2505 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2506 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2509 multiclass AI2_ldridx<bit isByte, string opc,
2510 InstrItinClass iii, InstrItinClass iir> {
2511 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2512 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2513 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2516 let Inst{23} = addr{12};
2517 let Inst{19-16} = addr{16-13};
2518 let Inst{11-0} = addr{11-0};
2519 let DecoderMethod = "DecodeLDRPreImm";
2522 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2523 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2524 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2527 let Inst{23} = addr{12};
2528 let Inst{19-16} = addr{16-13};
2529 let Inst{11-0} = addr{11-0};
2531 let DecoderMethod = "DecodeLDRPreReg";
2534 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2535 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2536 IndexModePost, LdFrm, iir,
2537 opc, "\t$Rt, $addr, $offset",
2538 "$addr.base = $Rn_wb", []> {
2544 let Inst{23} = offset{12};
2545 let Inst{19-16} = addr;
2546 let Inst{11-0} = offset{11-0};
2549 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2552 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2553 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2554 IndexModePost, LdFrm, iii,
2555 opc, "\t$Rt, $addr, $offset",
2556 "$addr.base = $Rn_wb", []> {
2562 let Inst{23} = offset{12};
2563 let Inst{19-16} = addr;
2564 let Inst{11-0} = offset{11-0};
2566 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2571 let mayLoad = 1, hasSideEffects = 0 in {
2572 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2573 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2574 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2575 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2578 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2579 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2580 (ins addrmode3_pre:$addr), IndexModePre,
2582 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2584 let Inst{23} = addr{8}; // U bit
2585 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2586 let Inst{19-16} = addr{12-9}; // Rn
2587 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2588 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2589 let DecoderMethod = "DecodeAddrMode3Instruction";
2591 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2592 (ins addr_offset_none:$addr, am3offset:$offset),
2593 IndexModePost, LdMiscFrm, itin,
2594 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2598 let Inst{23} = offset{8}; // U bit
2599 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2600 let Inst{19-16} = addr;
2601 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2602 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2603 let DecoderMethod = "DecodeAddrMode3Instruction";
2607 let mayLoad = 1, hasSideEffects = 0 in {
2608 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2609 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2610 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2611 let hasExtraDefRegAllocReq = 1 in {
2612 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2613 (ins addrmode3_pre:$addr), IndexModePre,
2614 LdMiscFrm, IIC_iLoad_d_ru,
2615 "ldrd", "\t$Rt, $Rt2, $addr!",
2616 "$addr.base = $Rn_wb", []> {
2618 let Inst{23} = addr{8}; // U bit
2619 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2620 let Inst{19-16} = addr{12-9}; // Rn
2621 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2622 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2623 let DecoderMethod = "DecodeAddrMode3Instruction";
2625 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2626 (ins addr_offset_none:$addr, am3offset:$offset),
2627 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2628 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2629 "$addr.base = $Rn_wb", []> {
2632 let Inst{23} = offset{8}; // U bit
2633 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2634 let Inst{19-16} = addr;
2635 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2636 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2637 let DecoderMethod = "DecodeAddrMode3Instruction";
2639 } // hasExtraDefRegAllocReq = 1
2640 } // mayLoad = 1, hasSideEffects = 0
2642 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2643 let mayLoad = 1, hasSideEffects = 0 in {
2644 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2645 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2646 IndexModePost, LdFrm, IIC_iLoad_ru,
2647 "ldrt", "\t$Rt, $addr, $offset",
2648 "$addr.base = $Rn_wb", []> {
2654 let Inst{23} = offset{12};
2655 let Inst{21} = 1; // overwrite
2656 let Inst{19-16} = addr;
2657 let Inst{11-5} = offset{11-5};
2659 let Inst{3-0} = offset{3-0};
2660 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2664 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2665 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2666 IndexModePost, LdFrm, IIC_iLoad_ru,
2667 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2673 let Inst{23} = offset{12};
2674 let Inst{21} = 1; // overwrite
2675 let Inst{19-16} = addr;
2676 let Inst{11-0} = offset{11-0};
2677 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2680 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2681 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2682 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2683 "ldrbt", "\t$Rt, $addr, $offset",
2684 "$addr.base = $Rn_wb", []> {
2690 let Inst{23} = offset{12};
2691 let Inst{21} = 1; // overwrite
2692 let Inst{19-16} = addr;
2693 let Inst{11-5} = offset{11-5};
2695 let Inst{3-0} = offset{3-0};
2696 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2700 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2701 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2702 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2703 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2709 let Inst{23} = offset{12};
2710 let Inst{21} = 1; // overwrite
2711 let Inst{19-16} = addr;
2712 let Inst{11-0} = offset{11-0};
2713 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2716 multiclass AI3ldrT<bits<4> op, string opc> {
2717 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2718 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2719 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2720 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2722 let Inst{23} = offset{8};
2724 let Inst{11-8} = offset{7-4};
2725 let Inst{3-0} = offset{3-0};
2727 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2728 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2729 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2730 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2732 let Inst{23} = Rm{4};
2735 let Unpredictable{11-8} = 0b1111;
2736 let Inst{3-0} = Rm{3-0};
2737 let DecoderMethod = "DecodeLDR";
2741 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2742 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2743 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2747 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2751 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2756 // Stores with truncate
2757 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2758 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2759 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2762 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2763 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2764 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2765 Requires<[IsARM, HasV5TE]> {
2771 multiclass AI2_stridx<bit isByte, string opc,
2772 InstrItinClass iii, InstrItinClass iir> {
2773 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2774 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2776 opc, "\t$Rt, $addr!",
2777 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2780 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2781 let Inst{19-16} = addr{16-13}; // Rn
2782 let Inst{11-0} = addr{11-0}; // imm12
2783 let DecoderMethod = "DecodeSTRPreImm";
2786 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2787 (ins GPR:$Rt, ldst_so_reg:$addr),
2788 IndexModePre, StFrm, iir,
2789 opc, "\t$Rt, $addr!",
2790 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2793 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2794 let Inst{19-16} = addr{16-13}; // Rn
2795 let Inst{11-0} = addr{11-0};
2796 let Inst{4} = 0; // Inst{4} = 0
2797 let DecoderMethod = "DecodeSTRPreReg";
2799 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2800 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2801 IndexModePost, StFrm, iir,
2802 opc, "\t$Rt, $addr, $offset",
2803 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2809 let Inst{23} = offset{12};
2810 let Inst{19-16} = addr;
2811 let Inst{11-0} = offset{11-0};
2814 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2817 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2818 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2819 IndexModePost, StFrm, iii,
2820 opc, "\t$Rt, $addr, $offset",
2821 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2827 let Inst{23} = offset{12};
2828 let Inst{19-16} = addr;
2829 let Inst{11-0} = offset{11-0};
2831 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2835 let mayStore = 1, hasSideEffects = 0 in {
2836 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2837 // IIC_iStore_siu depending on whether it the offset register is shifted.
2838 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2839 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2842 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2843 am2offset_reg:$offset),
2844 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2845 am2offset_reg:$offset)>;
2846 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2847 am2offset_imm:$offset),
2848 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2849 am2offset_imm:$offset)>;
2850 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2851 am2offset_reg:$offset),
2852 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2853 am2offset_reg:$offset)>;
2854 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2855 am2offset_imm:$offset),
2856 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2857 am2offset_imm:$offset)>;
2859 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2860 // put the patterns on the instruction definitions directly as ISel wants
2861 // the address base and offset to be separate operands, not a single
2862 // complex operand like we represent the instructions themselves. The
2863 // pseudos map between the two.
2864 let usesCustomInserter = 1,
2865 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2866 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2867 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2870 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2871 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2872 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2875 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2876 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2877 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2880 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2881 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2882 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2885 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2886 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2887 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2890 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2895 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2896 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2897 StMiscFrm, IIC_iStore_bh_ru,
2898 "strh", "\t$Rt, $addr!",
2899 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2901 let Inst{23} = addr{8}; // U bit
2902 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2903 let Inst{19-16} = addr{12-9}; // Rn
2904 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2905 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2906 let DecoderMethod = "DecodeAddrMode3Instruction";
2909 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2910 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2911 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2912 "strh", "\t$Rt, $addr, $offset",
2913 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2914 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2915 addr_offset_none:$addr,
2916 am3offset:$offset))]> {
2919 let Inst{23} = offset{8}; // U bit
2920 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2921 let Inst{19-16} = addr;
2922 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2923 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2924 let DecoderMethod = "DecodeAddrMode3Instruction";
2927 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2928 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2929 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2930 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2931 "strd", "\t$Rt, $Rt2, $addr!",
2932 "$addr.base = $Rn_wb", []> {
2934 let Inst{23} = addr{8}; // U bit
2935 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2936 let Inst{19-16} = addr{12-9}; // Rn
2937 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2938 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2939 let DecoderMethod = "DecodeAddrMode3Instruction";
2942 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2943 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2945 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2946 "strd", "\t$Rt, $Rt2, $addr, $offset",
2947 "$addr.base = $Rn_wb", []> {
2950 let Inst{23} = offset{8}; // U bit
2951 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2952 let Inst{19-16} = addr;
2953 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2954 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2955 let DecoderMethod = "DecodeAddrMode3Instruction";
2957 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2959 // STRT, STRBT, and STRHT
2961 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2962 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2963 IndexModePost, StFrm, IIC_iStore_bh_ru,
2964 "strbt", "\t$Rt, $addr, $offset",
2965 "$addr.base = $Rn_wb", []> {
2971 let Inst{23} = offset{12};
2972 let Inst{21} = 1; // overwrite
2973 let Inst{19-16} = addr;
2974 let Inst{11-5} = offset{11-5};
2976 let Inst{3-0} = offset{3-0};
2977 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2981 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2982 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2983 IndexModePost, StFrm, IIC_iStore_bh_ru,
2984 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2990 let Inst{23} = offset{12};
2991 let Inst{21} = 1; // overwrite
2992 let Inst{19-16} = addr;
2993 let Inst{11-0} = offset{11-0};
2994 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2998 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2999 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3001 let mayStore = 1, hasSideEffects = 0 in {
3002 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3003 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3004 IndexModePost, StFrm, IIC_iStore_ru,
3005 "strt", "\t$Rt, $addr, $offset",
3006 "$addr.base = $Rn_wb", []> {
3012 let Inst{23} = offset{12};
3013 let Inst{21} = 1; // overwrite
3014 let Inst{19-16} = addr;
3015 let Inst{11-5} = offset{11-5};
3017 let Inst{3-0} = offset{3-0};
3018 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3022 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3023 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3024 IndexModePost, StFrm, IIC_iStore_ru,
3025 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3031 let Inst{23} = offset{12};
3032 let Inst{21} = 1; // overwrite
3033 let Inst{19-16} = addr;
3034 let Inst{11-0} = offset{11-0};
3035 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3040 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3041 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3043 multiclass AI3strT<bits<4> op, string opc> {
3044 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3045 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3046 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3047 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3049 let Inst{23} = offset{8};
3051 let Inst{11-8} = offset{7-4};
3052 let Inst{3-0} = offset{3-0};
3054 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3055 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3056 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3057 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3059 let Inst{23} = Rm{4};
3062 let Inst{3-0} = Rm{3-0};
3067 defm STRHT : AI3strT<0b1011, "strht">;
3069 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3070 NoItinerary, "stl", "\t$Rt, $addr", []>;
3071 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3072 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3073 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3074 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3076 //===----------------------------------------------------------------------===//
3077 // Load / store multiple Instructions.
3080 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3081 InstrItinClass itin, InstrItinClass itin_upd> {
3082 // IA is the default, so no need for an explicit suffix on the
3083 // mnemonic here. Without it is the canonical spelling.
3085 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3086 IndexModeNone, f, itin,
3087 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3088 let Inst{24-23} = 0b01; // Increment After
3089 let Inst{22} = P_bit;
3090 let Inst{21} = 0; // No writeback
3091 let Inst{20} = L_bit;
3094 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3095 IndexModeUpd, f, itin_upd,
3096 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3097 let Inst{24-23} = 0b01; // Increment After
3098 let Inst{22} = P_bit;
3099 let Inst{21} = 1; // Writeback
3100 let Inst{20} = L_bit;
3102 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3105 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3106 IndexModeNone, f, itin,
3107 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3108 let Inst{24-23} = 0b00; // Decrement After
3109 let Inst{22} = P_bit;
3110 let Inst{21} = 0; // No writeback
3111 let Inst{20} = L_bit;
3114 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3115 IndexModeUpd, f, itin_upd,
3116 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3117 let Inst{24-23} = 0b00; // Decrement After
3118 let Inst{22} = P_bit;
3119 let Inst{21} = 1; // Writeback
3120 let Inst{20} = L_bit;
3122 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3125 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3126 IndexModeNone, f, itin,
3127 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3128 let Inst{24-23} = 0b10; // Decrement Before
3129 let Inst{22} = P_bit;
3130 let Inst{21} = 0; // No writeback
3131 let Inst{20} = L_bit;
3134 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3135 IndexModeUpd, f, itin_upd,
3136 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3137 let Inst{24-23} = 0b10; // Decrement Before
3138 let Inst{22} = P_bit;
3139 let Inst{21} = 1; // Writeback
3140 let Inst{20} = L_bit;
3142 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3145 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3146 IndexModeNone, f, itin,
3147 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3148 let Inst{24-23} = 0b11; // Increment Before
3149 let Inst{22} = P_bit;
3150 let Inst{21} = 0; // No writeback
3151 let Inst{20} = L_bit;
3154 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3155 IndexModeUpd, f, itin_upd,
3156 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3157 let Inst{24-23} = 0b11; // Increment Before
3158 let Inst{22} = P_bit;
3159 let Inst{21} = 1; // Writeback
3160 let Inst{20} = L_bit;
3162 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3166 let hasSideEffects = 0 in {
3168 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3169 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3170 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3172 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3173 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3175 ComplexDeprecationPredicate<"ARMStore">;
3179 // FIXME: remove when we have a way to marking a MI with these properties.
3180 // FIXME: Should pc be an implicit operand like PICADD, etc?
3181 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3182 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3183 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3184 reglist:$regs, variable_ops),
3185 4, IIC_iLoad_mBr, [],
3186 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3187 RegConstraint<"$Rn = $wb">;
3189 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3190 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3193 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3194 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3199 //===----------------------------------------------------------------------===//
3200 // Move Instructions.
3203 let hasSideEffects = 0 in
3204 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3205 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3209 let Inst{19-16} = 0b0000;
3210 let Inst{11-4} = 0b00000000;
3213 let Inst{15-12} = Rd;
3216 // A version for the smaller set of tail call registers.
3217 let hasSideEffects = 0 in
3218 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3219 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3223 let Inst{11-4} = 0b00000000;
3226 let Inst{15-12} = Rd;
3229 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3230 DPSoRegRegFrm, IIC_iMOVsr,
3231 "mov", "\t$Rd, $src",
3232 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3236 let Inst{15-12} = Rd;
3237 let Inst{19-16} = 0b0000;
3238 let Inst{11-8} = src{11-8};
3240 let Inst{6-5} = src{6-5};
3242 let Inst{3-0} = src{3-0};
3246 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3247 DPSoRegImmFrm, IIC_iMOVsr,
3248 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3249 UnaryDP, Sched<[WriteALU]> {
3252 let Inst{15-12} = Rd;
3253 let Inst{19-16} = 0b0000;
3254 let Inst{11-5} = src{11-5};
3256 let Inst{3-0} = src{3-0};
3260 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3261 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3262 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3267 let Inst{15-12} = Rd;
3268 let Inst{19-16} = 0b0000;
3269 let Inst{11-0} = imm;
3272 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3273 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3275 "movw", "\t$Rd, $imm",
3276 [(set GPR:$Rd, imm0_65535:$imm)]>,
3277 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3280 let Inst{15-12} = Rd;
3281 let Inst{11-0} = imm{11-0};
3282 let Inst{19-16} = imm{15-12};
3285 let DecoderMethod = "DecodeArmMOVTWInstruction";
3288 def : InstAlias<"mov${p} $Rd, $imm",
3289 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3292 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3293 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3296 let Constraints = "$src = $Rd" in {
3297 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3298 (ins GPR:$src, imm0_65535_expr:$imm),
3300 "movt", "\t$Rd, $imm",
3302 (or (and GPR:$src, 0xffff),
3303 lo16AllZero:$imm))]>, UnaryDP,
3304 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3307 let Inst{15-12} = Rd;
3308 let Inst{11-0} = imm{11-0};
3309 let Inst{19-16} = imm{15-12};
3312 let DecoderMethod = "DecodeArmMOVTWInstruction";
3315 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3316 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3321 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3322 Requires<[IsARM, HasV6T2]>;
3324 let Uses = [CPSR] in
3325 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3326 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3327 Requires<[IsARM]>, Sched<[WriteALU]>;
3329 // These aren't really mov instructions, but we have to define them this way
3330 // due to flag operands.
3332 let Defs = [CPSR] in {
3333 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3334 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3335 Sched<[WriteALU]>, Requires<[IsARM]>;
3336 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3337 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3338 Sched<[WriteALU]>, Requires<[IsARM]>;
3341 //===----------------------------------------------------------------------===//
3342 // Extend Instructions.
3347 def SXTB : AI_ext_rrot<0b01101010,
3348 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3349 def SXTH : AI_ext_rrot<0b01101011,
3350 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3352 def SXTAB : AI_exta_rrot<0b01101010,
3353 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3354 def SXTAH : AI_exta_rrot<0b01101011,
3355 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3357 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3359 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3363 let AddedComplexity = 16 in {
3364 def UXTB : AI_ext_rrot<0b01101110,
3365 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3366 def UXTH : AI_ext_rrot<0b01101111,
3367 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3368 def UXTB16 : AI_ext_rrot<0b01101100,
3369 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3371 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3372 // The transformation should probably be done as a combiner action
3373 // instead so we can include a check for masking back in the upper
3374 // eight bits of the source into the lower eight bits of the result.
3375 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3376 // (UXTB16r_rot GPR:$Src, 3)>;
3377 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3378 (UXTB16 GPR:$Src, 1)>;
3380 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3381 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3382 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3383 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3386 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3387 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3390 def SBFX : I<(outs GPRnopc:$Rd),
3391 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3392 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3393 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3394 Requires<[IsARM, HasV6T2]> {
3399 let Inst{27-21} = 0b0111101;
3400 let Inst{6-4} = 0b101;
3401 let Inst{20-16} = width;
3402 let Inst{15-12} = Rd;
3403 let Inst{11-7} = lsb;
3407 def UBFX : I<(outs GPRnopc:$Rd),
3408 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3409 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3410 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3411 Requires<[IsARM, HasV6T2]> {
3416 let Inst{27-21} = 0b0111111;
3417 let Inst{6-4} = 0b101;
3418 let Inst{20-16} = width;
3419 let Inst{15-12} = Rd;
3420 let Inst{11-7} = lsb;
3424 //===----------------------------------------------------------------------===//
3425 // Arithmetic Instructions.
3428 defm ADD : AsI1_bin_irs<0b0100, "add",
3429 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3430 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3431 defm SUB : AsI1_bin_irs<0b0010, "sub",
3432 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3433 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3435 // ADD and SUB with 's' bit set.
3437 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3438 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3439 // AdjustInstrPostInstrSelection where we determine whether or not to
3440 // set the "s" bit based on CPSR liveness.
3442 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3443 // support for an optional CPSR definition that corresponds to the DAG
3444 // node's second value. We can then eliminate the implicit def of CPSR.
3445 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3446 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3447 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3448 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3450 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3451 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3452 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3453 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3455 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3456 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3457 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3459 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3460 // CPSR and the implicit def of CPSR is not needed.
3461 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3462 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3464 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3465 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3467 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3468 // The assume-no-carry-in form uses the negation of the input since add/sub
3469 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3470 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3472 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3473 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3474 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3475 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3477 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3478 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3479 Requires<[IsARM, HasV6T2]>;
3480 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3481 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3482 Requires<[IsARM, HasV6T2]>;
3484 // The with-carry-in form matches bitwise not instead of the negation.
3485 // Effectively, the inverse interpretation of the carry flag already accounts
3486 // for part of the negation.
3487 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3488 (SBCri GPR:$src, mod_imm_not:$imm)>;
3489 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3490 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3491 Requires<[IsARM, HasV6T2]>;
3493 // Note: These are implemented in C++ code, because they have to generate
3494 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3496 // (mul X, 2^n+1) -> (add (X << n), X)
3497 // (mul X, 2^n-1) -> (rsb X, (X << n))
3499 // ARM Arithmetic Instruction
3500 // GPR:$dst = GPR:$a op GPR:$b
3501 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3502 list<dag> pattern = [],
3503 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3504 string asm = "\t$Rd, $Rn, $Rm">
3505 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3506 Sched<[WriteALU, ReadALU, ReadALU]> {
3510 let Inst{27-20} = op27_20;
3511 let Inst{11-4} = op11_4;
3512 let Inst{19-16} = Rn;
3513 let Inst{15-12} = Rd;
3516 let Unpredictable{11-8} = 0b1111;
3519 // Saturating add/subtract
3521 let DecoderMethod = "DecodeQADDInstruction" in
3522 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3523 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3524 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3526 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3527 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3528 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3529 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3530 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3532 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3533 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3536 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3537 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3538 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3539 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3540 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3541 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3542 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3543 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3544 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3545 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3546 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3547 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3549 // Signed/Unsigned add/subtract
3551 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3552 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3553 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3554 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3555 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3556 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3557 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3558 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3559 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3560 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3561 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3562 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3564 // Signed/Unsigned halving add/subtract
3566 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3567 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3568 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3569 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3570 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3571 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3572 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3573 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3574 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3575 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3576 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3577 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3579 // Unsigned Sum of Absolute Differences [and Accumulate].
3581 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3582 MulFrm /* for convenience */, NoItinerary, "usad8",
3583 "\t$Rd, $Rn, $Rm", []>,
3584 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3588 let Inst{27-20} = 0b01111000;
3589 let Inst{15-12} = 0b1111;
3590 let Inst{7-4} = 0b0001;
3591 let Inst{19-16} = Rd;
3592 let Inst{11-8} = Rm;
3595 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3596 MulFrm /* for convenience */, NoItinerary, "usada8",
3597 "\t$Rd, $Rn, $Rm, $Ra", []>,
3598 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3603 let Inst{27-20} = 0b01111000;
3604 let Inst{7-4} = 0b0001;
3605 let Inst{19-16} = Rd;
3606 let Inst{15-12} = Ra;
3607 let Inst{11-8} = Rm;
3611 // Signed/Unsigned saturate
3613 def SSAT : AI<(outs GPRnopc:$Rd),
3614 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3615 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3620 let Inst{27-21} = 0b0110101;
3621 let Inst{5-4} = 0b01;
3622 let Inst{20-16} = sat_imm;
3623 let Inst{15-12} = Rd;
3624 let Inst{11-7} = sh{4-0};
3625 let Inst{6} = sh{5};
3629 def SSAT16 : AI<(outs GPRnopc:$Rd),
3630 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3631 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3635 let Inst{27-20} = 0b01101010;
3636 let Inst{11-4} = 0b11110011;
3637 let Inst{15-12} = Rd;
3638 let Inst{19-16} = sat_imm;
3642 def USAT : AI<(outs GPRnopc:$Rd),
3643 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3644 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3649 let Inst{27-21} = 0b0110111;
3650 let Inst{5-4} = 0b01;
3651 let Inst{15-12} = Rd;
3652 let Inst{11-7} = sh{4-0};
3653 let Inst{6} = sh{5};
3654 let Inst{20-16} = sat_imm;
3658 def USAT16 : AI<(outs GPRnopc:$Rd),
3659 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3660 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3664 let Inst{27-20} = 0b01101110;
3665 let Inst{11-4} = 0b11110011;
3666 let Inst{15-12} = Rd;
3667 let Inst{19-16} = sat_imm;
3671 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3672 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3673 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3674 (USAT imm:$pos, GPRnopc:$a, 0)>;
3676 //===----------------------------------------------------------------------===//
3677 // Bitwise Instructions.
3680 defm AND : AsI1_bin_irs<0b0000, "and",
3681 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3682 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3683 defm ORR : AsI1_bin_irs<0b1100, "orr",
3684 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3685 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3686 defm EOR : AsI1_bin_irs<0b0001, "eor",
3687 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3688 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3689 defm BIC : AsI1_bin_irs<0b1110, "bic",
3690 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3691 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3693 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3694 // like in the actual instruction encoding. The complexity of mapping the mask
3695 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3696 // instruction description.
3697 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3698 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3699 "bfc", "\t$Rd, $imm", "$src = $Rd",
3700 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3701 Requires<[IsARM, HasV6T2]> {
3704 let Inst{27-21} = 0b0111110;
3705 let Inst{6-0} = 0b0011111;
3706 let Inst{15-12} = Rd;
3707 let Inst{11-7} = imm{4-0}; // lsb
3708 let Inst{20-16} = imm{9-5}; // msb
3711 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3712 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3713 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3714 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3715 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3716 bf_inv_mask_imm:$imm))]>,
3717 Requires<[IsARM, HasV6T2]> {
3721 let Inst{27-21} = 0b0111110;
3722 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3723 let Inst{15-12} = Rd;
3724 let Inst{11-7} = imm{4-0}; // lsb
3725 let Inst{20-16} = imm{9-5}; // width
3729 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3730 "mvn", "\t$Rd, $Rm",
3731 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3735 let Inst{19-16} = 0b0000;
3736 let Inst{11-4} = 0b00000000;
3737 let Inst{15-12} = Rd;
3740 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3741 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3742 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3747 let Inst{19-16} = 0b0000;
3748 let Inst{15-12} = Rd;
3749 let Inst{11-5} = shift{11-5};
3751 let Inst{3-0} = shift{3-0};
3753 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3754 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3755 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3760 let Inst{19-16} = 0b0000;
3761 let Inst{15-12} = Rd;
3762 let Inst{11-8} = shift{11-8};
3764 let Inst{6-5} = shift{6-5};
3766 let Inst{3-0} = shift{3-0};
3768 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3769 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3770 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3771 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3775 let Inst{19-16} = 0b0000;
3776 let Inst{15-12} = Rd;
3777 let Inst{11-0} = imm;
3780 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3781 (BICri GPR:$src, mod_imm_not:$imm)>;
3783 //===----------------------------------------------------------------------===//
3784 // Multiply Instructions.
3786 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3787 string opc, string asm, list<dag> pattern>
3788 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3792 let Inst{19-16} = Rd;
3793 let Inst{11-8} = Rm;
3796 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3797 string opc, string asm, list<dag> pattern>
3798 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3803 let Inst{19-16} = RdHi;
3804 let Inst{15-12} = RdLo;
3805 let Inst{11-8} = Rm;
3808 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3809 string opc, string asm, list<dag> pattern>
3810 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3815 let Inst{19-16} = RdHi;
3816 let Inst{15-12} = RdLo;
3817 let Inst{11-8} = Rm;
3821 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3822 // property. Remove them when it's possible to add those properties
3823 // on an individual MachineInstr, not just an instruction description.
3824 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3825 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3826 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3827 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3828 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3829 Requires<[IsARM, HasV6]> {
3830 let Inst{15-12} = 0b0000;
3831 let Unpredictable{15-12} = 0b1111;
3834 let Constraints = "@earlyclobber $Rd" in
3835 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3836 pred:$p, cc_out:$s),
3838 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3839 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3840 Requires<[IsARM, NoV6, UseMulOps]>;
3843 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3844 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3845 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3846 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3847 Requires<[IsARM, HasV6, UseMulOps]> {
3849 let Inst{15-12} = Ra;
3852 let Constraints = "@earlyclobber $Rd" in
3853 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3854 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3855 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3856 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3857 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3858 Requires<[IsARM, NoV6]>;
3860 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3861 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3862 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3863 Requires<[IsARM, HasV6T2, UseMulOps]> {
3868 let Inst{19-16} = Rd;
3869 let Inst{15-12} = Ra;
3870 let Inst{11-8} = Rm;
3874 // Extra precision multiplies with low / high results
3875 let hasSideEffects = 0 in {
3876 let isCommutable = 1 in {
3877 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3878 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3879 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3880 Requires<[IsARM, HasV6]>;
3882 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3883 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3884 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3885 Requires<[IsARM, HasV6]>;
3887 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3888 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3889 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3891 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3892 Requires<[IsARM, NoV6]>;
3894 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3895 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3897 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3898 Requires<[IsARM, NoV6]>;
3902 // Multiply + accumulate
3903 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3904 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3905 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3906 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3907 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3908 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3909 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3910 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3912 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3913 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3914 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3915 Requires<[IsARM, HasV6]> {
3920 let Inst{19-16} = RdHi;
3921 let Inst{15-12} = RdLo;
3922 let Inst{11-8} = Rm;
3927 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3928 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3929 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3931 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3932 pred:$p, cc_out:$s)>,
3933 Requires<[IsARM, NoV6]>;
3934 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3935 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3937 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3938 pred:$p, cc_out:$s)>,
3939 Requires<[IsARM, NoV6]>;
3944 // Most significant word multiply
3945 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3946 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3947 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3948 Requires<[IsARM, HasV6]> {
3949 let Inst{15-12} = 0b1111;
3952 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3953 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3954 Requires<[IsARM, HasV6]> {
3955 let Inst{15-12} = 0b1111;
3958 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3959 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3960 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3961 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3962 Requires<[IsARM, HasV6, UseMulOps]>;
3964 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3965 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3966 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3967 Requires<[IsARM, HasV6]>;
3969 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3970 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3971 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3972 Requires<[IsARM, HasV6, UseMulOps]>;
3974 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3975 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3976 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3977 Requires<[IsARM, HasV6]>;
3979 multiclass AI_smul<string opc, PatFrag opnode> {
3980 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3981 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3982 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3983 (sext_inreg GPR:$Rm, i16)))]>,
3984 Requires<[IsARM, HasV5TE]>;
3986 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3987 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3988 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3989 (sra GPR:$Rm, (i32 16))))]>,
3990 Requires<[IsARM, HasV5TE]>;
3992 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3993 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3994 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3995 (sext_inreg GPR:$Rm, i16)))]>,
3996 Requires<[IsARM, HasV5TE]>;
3998 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3999 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4000 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4001 (sra GPR:$Rm, (i32 16))))]>,
4002 Requires<[IsARM, HasV5TE]>;
4004 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4005 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4007 Requires<[IsARM, HasV5TE]>;
4009 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4010 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4012 Requires<[IsARM, HasV5TE]>;
4016 multiclass AI_smla<string opc, PatFrag opnode> {
4017 let DecoderMethod = "DecodeSMLAInstruction" in {
4018 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4019 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4020 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4021 [(set GPRnopc:$Rd, (add GPR:$Ra,
4022 (opnode (sext_inreg GPRnopc:$Rn, i16),
4023 (sext_inreg GPRnopc:$Rm, i16))))]>,
4024 Requires<[IsARM, HasV5TE, UseMulOps]>;
4026 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4027 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4028 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4030 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4031 (sra GPRnopc:$Rm, (i32 16)))))]>,
4032 Requires<[IsARM, HasV5TE, UseMulOps]>;
4034 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4035 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4036 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4038 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4039 (sext_inreg GPRnopc:$Rm, i16))))]>,
4040 Requires<[IsARM, HasV5TE, UseMulOps]>;
4042 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4043 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4044 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4046 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4047 (sra GPRnopc:$Rm, (i32 16)))))]>,
4048 Requires<[IsARM, HasV5TE, UseMulOps]>;
4050 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4051 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4052 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4054 Requires<[IsARM, HasV5TE, UseMulOps]>;
4056 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4057 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4058 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4060 Requires<[IsARM, HasV5TE, UseMulOps]>;
4064 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4065 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4067 // Halfword multiply accumulate long: SMLAL<x><y>.
4068 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4069 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4070 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4071 Requires<[IsARM, HasV5TE]>;
4073 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4074 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4075 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4076 Requires<[IsARM, HasV5TE]>;
4078 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4079 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4080 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4081 Requires<[IsARM, HasV5TE]>;
4083 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4084 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4085 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4086 Requires<[IsARM, HasV5TE]>;
4088 // Helper class for AI_smld.
4089 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4090 InstrItinClass itin, string opc, string asm>
4091 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4094 let Inst{27-23} = 0b01110;
4095 let Inst{22} = long;
4096 let Inst{21-20} = 0b00;
4097 let Inst{11-8} = Rm;
4104 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4105 InstrItinClass itin, string opc, string asm>
4106 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4108 let Inst{15-12} = 0b1111;
4109 let Inst{19-16} = Rd;
4111 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4112 InstrItinClass itin, string opc, string asm>
4113 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4116 let Inst{19-16} = Rd;
4117 let Inst{15-12} = Ra;
4119 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4120 InstrItinClass itin, string opc, string asm>
4121 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4124 let Inst{19-16} = RdHi;
4125 let Inst{15-12} = RdLo;
4128 multiclass AI_smld<bit sub, string opc> {
4130 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4131 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4132 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4134 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4135 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4136 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4138 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4139 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4140 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4142 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4143 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4144 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4148 defm SMLA : AI_smld<0, "smla">;
4149 defm SMLS : AI_smld<1, "smls">;
4151 multiclass AI_sdml<bit sub, string opc> {
4153 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4154 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4155 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4156 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4159 defm SMUA : AI_sdml<0, "smua">;
4160 defm SMUS : AI_sdml<1, "smus">;
4162 //===----------------------------------------------------------------------===//
4163 // Division Instructions (ARMv7-A with virtualization extension)
4165 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4166 "sdiv", "\t$Rd, $Rn, $Rm",
4167 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4168 Requires<[IsARM, HasDivideInARM]>;
4170 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4171 "udiv", "\t$Rd, $Rn, $Rm",
4172 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4173 Requires<[IsARM, HasDivideInARM]>;
4175 //===----------------------------------------------------------------------===//
4176 // Misc. Arithmetic Instructions.
4179 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4180 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4181 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4184 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4185 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4186 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4187 Requires<[IsARM, HasV6T2]>,
4190 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4191 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4192 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4195 let AddedComplexity = 5 in
4196 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4197 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4198 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4199 Requires<[IsARM, HasV6]>,
4202 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4203 (REV16 (LDRH addrmode3:$addr))>;
4204 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4205 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4207 let AddedComplexity = 5 in
4208 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4209 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4210 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4211 Requires<[IsARM, HasV6]>,
4214 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4215 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4218 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4219 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4220 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4221 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4222 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4224 Requires<[IsARM, HasV6]>,
4225 Sched<[WriteALUsi, ReadALU]>;
4227 // Alternate cases for PKHBT where identities eliminate some nodes.
4228 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4229 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4230 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4231 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4233 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4234 // will match the pattern below.
4235 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4236 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4237 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4238 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4239 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4241 Requires<[IsARM, HasV6]>,
4242 Sched<[WriteALUsi, ReadALU]>;
4244 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4245 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4246 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4247 // pkhtb src1, src2, asr (17..31).
4248 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4249 (srl GPRnopc:$src2, imm16:$sh)),
4250 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4251 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4252 (sra GPRnopc:$src2, imm16_31:$sh)),
4253 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4254 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4255 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4256 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4258 //===----------------------------------------------------------------------===//
4262 // + CRC32{B,H,W} 0x04C11DB7
4263 // + CRC32C{B,H,W} 0x1EDC6F41
4266 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4267 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4268 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4269 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4270 Requires<[IsARM, HasV8, HasCRC]> {
4275 let Inst{31-28} = 0b1110;
4276 let Inst{27-23} = 0b00010;
4277 let Inst{22-21} = sz;
4279 let Inst{19-16} = Rn;
4280 let Inst{15-12} = Rd;
4281 let Inst{11-10} = 0b00;
4284 let Inst{7-4} = 0b0100;
4287 let Unpredictable{11-8} = 0b1101;
4290 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4291 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4292 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4293 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4294 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4295 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4297 //===----------------------------------------------------------------------===//
4298 // ARMv8.1a Privilege Access Never extension
4302 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4303 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4306 let Inst{31-28} = 0b1111;
4307 let Inst{27-20} = 0b00010001;
4308 let Inst{19-16} = 0b0000;
4309 let Inst{15-10} = 0b000000;
4312 let Inst{7-4} = 0b0000;
4313 let Inst{3-0} = 0b0000;
4315 let Unpredictable{19-16} = 0b1111;
4316 let Unpredictable{15-10} = 0b111111;
4317 let Unpredictable{8} = 0b1;
4318 let Unpredictable{3-0} = 0b1111;
4321 //===----------------------------------------------------------------------===//
4322 // Comparison Instructions...
4325 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4326 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4327 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4329 // ARMcmpZ can re-use the above instruction definitions.
4330 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4331 (CMPri GPR:$src, mod_imm:$imm)>;
4332 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4333 (CMPrr GPR:$src, GPR:$rhs)>;
4334 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4335 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4336 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4337 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4339 // CMN register-integer
4340 let isCompare = 1, Defs = [CPSR] in {
4341 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4342 "cmn", "\t$Rn, $imm",
4343 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4344 Sched<[WriteCMP, ReadALU]> {
4349 let Inst{19-16} = Rn;
4350 let Inst{15-12} = 0b0000;
4351 let Inst{11-0} = imm;
4353 let Unpredictable{15-12} = 0b1111;
4356 // CMN register-register/shift
4357 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4358 "cmn", "\t$Rn, $Rm",
4359 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4360 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4363 let isCommutable = 1;
4366 let Inst{19-16} = Rn;
4367 let Inst{15-12} = 0b0000;
4368 let Inst{11-4} = 0b00000000;
4371 let Unpredictable{15-12} = 0b1111;
4374 def CMNzrsi : AI1<0b1011, (outs),
4375 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4376 "cmn", "\t$Rn, $shift",
4377 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4378 GPR:$Rn, so_reg_imm:$shift)]>,
4379 Sched<[WriteCMPsi, ReadALU]> {
4384 let Inst{19-16} = Rn;
4385 let Inst{15-12} = 0b0000;
4386 let Inst{11-5} = shift{11-5};
4388 let Inst{3-0} = shift{3-0};
4390 let Unpredictable{15-12} = 0b1111;
4393 def CMNzrsr : AI1<0b1011, (outs),
4394 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4395 "cmn", "\t$Rn, $shift",
4396 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4397 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4398 Sched<[WriteCMPsr, ReadALU]> {
4403 let Inst{19-16} = Rn;
4404 let Inst{15-12} = 0b0000;
4405 let Inst{11-8} = shift{11-8};
4407 let Inst{6-5} = shift{6-5};
4409 let Inst{3-0} = shift{3-0};
4411 let Unpredictable{15-12} = 0b1111;
4416 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4417 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4419 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4420 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4422 // Note that TST/TEQ don't set all the same flags that CMP does!
4423 defm TST : AI1_cmp_irs<0b1000, "tst",
4424 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4425 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4426 "DecodeTSTInstruction">;
4427 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4428 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4429 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4431 // Pseudo i64 compares for some floating point compares.
4432 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4434 def BCCi64 : PseudoInst<(outs),
4435 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4437 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4440 def BCCZi64 : PseudoInst<(outs),
4441 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4442 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4444 } // usesCustomInserter
4447 // Conditional moves
4448 let hasSideEffects = 0 in {
4450 let isCommutable = 1, isSelect = 1 in
4451 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4452 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4454 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4456 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4458 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4459 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4462 (ARMcmov GPR:$false, so_reg_imm:$shift,
4464 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4465 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4466 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4468 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4470 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4473 let isMoveImm = 1 in
4475 : ARMPseudoInst<(outs GPR:$Rd),
4476 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4478 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4480 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4483 let isMoveImm = 1 in
4484 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4485 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4487 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4489 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4491 // Two instruction predicate mov immediate.
4492 let isMoveImm = 1 in
4494 : ARMPseudoInst<(outs GPR:$Rd),
4495 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4497 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4499 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4501 let isMoveImm = 1 in
4502 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4503 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4505 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4507 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4512 //===----------------------------------------------------------------------===//
4513 // Atomic operations intrinsics
4516 def MemBarrierOptOperand : AsmOperandClass {
4517 let Name = "MemBarrierOpt";
4518 let ParserMethod = "parseMemBarrierOptOperand";
4520 def memb_opt : Operand<i32> {
4521 let PrintMethod = "printMemBOption";
4522 let ParserMatchClass = MemBarrierOptOperand;
4523 let DecoderMethod = "DecodeMemBarrierOption";
4526 def InstSyncBarrierOptOperand : AsmOperandClass {
4527 let Name = "InstSyncBarrierOpt";
4528 let ParserMethod = "parseInstSyncBarrierOptOperand";
4530 def instsyncb_opt : Operand<i32> {
4531 let PrintMethod = "printInstSyncBOption";
4532 let ParserMatchClass = InstSyncBarrierOptOperand;
4533 let DecoderMethod = "DecodeInstSyncBarrierOption";
4536 // Memory barriers protect the atomic sequences
4537 let hasSideEffects = 1 in {
4538 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4539 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4540 Requires<[IsARM, HasDB]> {
4542 let Inst{31-4} = 0xf57ff05;
4543 let Inst{3-0} = opt;
4546 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4547 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4548 Requires<[IsARM, HasDB]> {
4550 let Inst{31-4} = 0xf57ff04;
4551 let Inst{3-0} = opt;
4554 // ISB has only full system option
4555 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4556 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4557 Requires<[IsARM, HasDB]> {
4559 let Inst{31-4} = 0xf57ff06;
4560 let Inst{3-0} = opt;
4564 let usesCustomInserter = 1, Defs = [CPSR] in {
4566 // Pseudo instruction that combines movs + predicated rsbmi
4567 // to implement integer ABS
4568 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4571 let usesCustomInserter = 1 in {
4572 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4573 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4575 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4578 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4579 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4582 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4583 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4586 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4587 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4590 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4591 (int_arm_strex node:$val, node:$ptr), [{
4592 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4595 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4596 (int_arm_strex node:$val, node:$ptr), [{
4597 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4600 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4601 (int_arm_strex node:$val, node:$ptr), [{
4602 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4605 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4606 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4609 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4610 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4613 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4614 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4617 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4618 (int_arm_stlex node:$val, node:$ptr), [{
4619 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4622 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4623 (int_arm_stlex node:$val, node:$ptr), [{
4624 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4627 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4628 (int_arm_stlex node:$val, node:$ptr), [{
4629 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4632 let mayLoad = 1 in {
4633 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4634 NoItinerary, "ldrexb", "\t$Rt, $addr",
4635 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4636 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4637 NoItinerary, "ldrexh", "\t$Rt, $addr",
4638 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4639 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4640 NoItinerary, "ldrex", "\t$Rt, $addr",
4641 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4642 let hasExtraDefRegAllocReq = 1 in
4643 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4644 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4645 let DecoderMethod = "DecodeDoubleRegLoad";
4648 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4649 NoItinerary, "ldaexb", "\t$Rt, $addr",
4650 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4651 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4652 NoItinerary, "ldaexh", "\t$Rt, $addr",
4653 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4654 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4655 NoItinerary, "ldaex", "\t$Rt, $addr",
4656 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4657 let hasExtraDefRegAllocReq = 1 in
4658 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4659 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4660 let DecoderMethod = "DecodeDoubleRegLoad";
4664 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4665 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4666 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4667 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4668 addr_offset_none:$addr))]>;
4669 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4670 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4671 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4672 addr_offset_none:$addr))]>;
4673 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4674 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4675 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4676 addr_offset_none:$addr))]>;
4677 let hasExtraSrcRegAllocReq = 1 in
4678 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4679 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4680 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4681 let DecoderMethod = "DecodeDoubleRegStore";
4683 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4684 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4686 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4687 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4688 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4690 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4691 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4692 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4694 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4695 let hasExtraSrcRegAllocReq = 1 in
4696 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4697 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4698 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4699 let DecoderMethod = "DecodeDoubleRegStore";
4703 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4705 Requires<[IsARM, HasV7]> {
4706 let Inst{31-0} = 0b11110101011111111111000000011111;
4709 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4710 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4711 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4712 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4714 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4715 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4716 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4717 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4719 class acquiring_load<PatFrag base>
4720 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4721 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4722 return isAtLeastAcquire(Ordering);
4725 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4726 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4727 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4729 class releasing_store<PatFrag base>
4730 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4731 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4732 return isAtLeastRelease(Ordering);
4735 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4736 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4737 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4739 let AddedComplexity = 8 in {
4740 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4741 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4742 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4743 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4744 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4745 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4748 // SWP/SWPB are deprecated in V6/V7.
4749 let mayLoad = 1, mayStore = 1 in {
4750 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4751 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4753 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4754 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4758 //===----------------------------------------------------------------------===//
4759 // Coprocessor Instructions.
4762 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4763 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4764 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4765 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4766 imm:$CRm, imm:$opc2)]>,
4775 let Inst{3-0} = CRm;
4777 let Inst{7-5} = opc2;
4778 let Inst{11-8} = cop;
4779 let Inst{15-12} = CRd;
4780 let Inst{19-16} = CRn;
4781 let Inst{23-20} = opc1;
4784 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4785 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4786 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4787 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4788 imm:$CRm, imm:$opc2)]>,
4790 let Inst{31-28} = 0b1111;
4798 let Inst{3-0} = CRm;
4800 let Inst{7-5} = opc2;
4801 let Inst{11-8} = cop;
4802 let Inst{15-12} = CRd;
4803 let Inst{19-16} = CRn;
4804 let Inst{23-20} = opc1;
4807 class ACI<dag oops, dag iops, string opc, string asm,
4808 IndexMode im = IndexModeNone>
4809 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4811 let Inst{27-25} = 0b110;
4813 class ACInoP<dag oops, dag iops, string opc, string asm,
4814 IndexMode im = IndexModeNone>
4815 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4817 let Inst{31-28} = 0b1111;
4818 let Inst{27-25} = 0b110;
4820 multiclass LdStCop<bit load, bit Dbit, string asm> {
4821 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4822 asm, "\t$cop, $CRd, $addr"> {
4826 let Inst{24} = 1; // P = 1
4827 let Inst{23} = addr{8};
4828 let Inst{22} = Dbit;
4829 let Inst{21} = 0; // W = 0
4830 let Inst{20} = load;
4831 let Inst{19-16} = addr{12-9};
4832 let Inst{15-12} = CRd;
4833 let Inst{11-8} = cop;
4834 let Inst{7-0} = addr{7-0};
4835 let DecoderMethod = "DecodeCopMemInstruction";
4837 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4838 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4842 let Inst{24} = 1; // P = 1
4843 let Inst{23} = addr{8};
4844 let Inst{22} = Dbit;
4845 let Inst{21} = 1; // W = 1
4846 let Inst{20} = load;
4847 let Inst{19-16} = addr{12-9};
4848 let Inst{15-12} = CRd;
4849 let Inst{11-8} = cop;
4850 let Inst{7-0} = addr{7-0};
4851 let DecoderMethod = "DecodeCopMemInstruction";
4853 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4854 postidx_imm8s4:$offset),
4855 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4860 let Inst{24} = 0; // P = 0
4861 let Inst{23} = offset{8};
4862 let Inst{22} = Dbit;
4863 let Inst{21} = 1; // W = 1
4864 let Inst{20} = load;
4865 let Inst{19-16} = addr;
4866 let Inst{15-12} = CRd;
4867 let Inst{11-8} = cop;
4868 let Inst{7-0} = offset{7-0};
4869 let DecoderMethod = "DecodeCopMemInstruction";
4871 def _OPTION : ACI<(outs),
4872 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4873 coproc_option_imm:$option),
4874 asm, "\t$cop, $CRd, $addr, $option"> {
4879 let Inst{24} = 0; // P = 0
4880 let Inst{23} = 1; // U = 1
4881 let Inst{22} = Dbit;
4882 let Inst{21} = 0; // W = 0
4883 let Inst{20} = load;
4884 let Inst{19-16} = addr;
4885 let Inst{15-12} = CRd;
4886 let Inst{11-8} = cop;
4887 let Inst{7-0} = option;
4888 let DecoderMethod = "DecodeCopMemInstruction";
4891 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4892 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4893 asm, "\t$cop, $CRd, $addr"> {
4897 let Inst{24} = 1; // P = 1
4898 let Inst{23} = addr{8};
4899 let Inst{22} = Dbit;
4900 let Inst{21} = 0; // W = 0
4901 let Inst{20} = load;
4902 let Inst{19-16} = addr{12-9};
4903 let Inst{15-12} = CRd;
4904 let Inst{11-8} = cop;
4905 let Inst{7-0} = addr{7-0};
4906 let DecoderMethod = "DecodeCopMemInstruction";
4908 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4909 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4913 let Inst{24} = 1; // P = 1
4914 let Inst{23} = addr{8};
4915 let Inst{22} = Dbit;
4916 let Inst{21} = 1; // W = 1
4917 let Inst{20} = load;
4918 let Inst{19-16} = addr{12-9};
4919 let Inst{15-12} = CRd;
4920 let Inst{11-8} = cop;
4921 let Inst{7-0} = addr{7-0};
4922 let DecoderMethod = "DecodeCopMemInstruction";
4924 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4925 postidx_imm8s4:$offset),
4926 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4931 let Inst{24} = 0; // P = 0
4932 let Inst{23} = offset{8};
4933 let Inst{22} = Dbit;
4934 let Inst{21} = 1; // W = 1
4935 let Inst{20} = load;
4936 let Inst{19-16} = addr;
4937 let Inst{15-12} = CRd;
4938 let Inst{11-8} = cop;
4939 let Inst{7-0} = offset{7-0};
4940 let DecoderMethod = "DecodeCopMemInstruction";
4942 def _OPTION : ACInoP<(outs),
4943 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4944 coproc_option_imm:$option),
4945 asm, "\t$cop, $CRd, $addr, $option"> {
4950 let Inst{24} = 0; // P = 0
4951 let Inst{23} = 1; // U = 1
4952 let Inst{22} = Dbit;
4953 let Inst{21} = 0; // W = 0
4954 let Inst{20} = load;
4955 let Inst{19-16} = addr;
4956 let Inst{15-12} = CRd;
4957 let Inst{11-8} = cop;
4958 let Inst{7-0} = option;
4959 let DecoderMethod = "DecodeCopMemInstruction";
4963 defm LDC : LdStCop <1, 0, "ldc">;
4964 defm LDCL : LdStCop <1, 1, "ldcl">;
4965 defm STC : LdStCop <0, 0, "stc">;
4966 defm STCL : LdStCop <0, 1, "stcl">;
4967 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4968 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4969 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4970 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4972 //===----------------------------------------------------------------------===//
4973 // Move between coprocessor and ARM core register.
4976 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4978 : ABI<0b1110, oops, iops, NoItinerary, opc,
4979 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4980 let Inst{20} = direction;
4990 let Inst{15-12} = Rt;
4991 let Inst{11-8} = cop;
4992 let Inst{23-21} = opc1;
4993 let Inst{7-5} = opc2;
4994 let Inst{3-0} = CRm;
4995 let Inst{19-16} = CRn;
4998 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5000 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5001 c_imm:$CRm, imm0_7:$opc2),
5002 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5003 imm:$CRm, imm:$opc2)]>,
5004 ComplexDeprecationPredicate<"MCR">;
5005 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5006 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5007 c_imm:$CRm, 0, pred:$p)>;
5008 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5009 (outs GPRwithAPSR:$Rt),
5010 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5012 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5013 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5014 c_imm:$CRm, 0, pred:$p)>;
5016 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5017 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5019 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5021 : ABXI<0b1110, oops, iops, NoItinerary,
5022 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5023 let Inst{31-24} = 0b11111110;
5024 let Inst{20} = direction;
5034 let Inst{15-12} = Rt;
5035 let Inst{11-8} = cop;
5036 let Inst{23-21} = opc1;
5037 let Inst{7-5} = opc2;
5038 let Inst{3-0} = CRm;
5039 let Inst{19-16} = CRn;
5042 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5044 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5045 c_imm:$CRm, imm0_7:$opc2),
5046 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5047 imm:$CRm, imm:$opc2)]>,
5049 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5050 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5052 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5053 (outs GPRwithAPSR:$Rt),
5054 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5057 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5058 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5061 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5062 imm:$CRm, imm:$opc2),
5063 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5065 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5067 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5070 let Inst{23-21} = 0b010;
5071 let Inst{20} = direction;
5079 let Inst{15-12} = Rt;
5080 let Inst{19-16} = Rt2;
5081 let Inst{11-8} = cop;
5082 let Inst{7-4} = opc1;
5083 let Inst{3-0} = CRm;
5086 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5087 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5088 GPRnopc:$Rt2, c_imm:$CRm),
5089 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5090 GPRnopc:$Rt2, imm:$CRm)]>;
5091 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5092 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5093 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5095 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5096 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5097 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5098 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5100 let Inst{31-28} = 0b1111;
5101 let Inst{23-21} = 0b010;
5102 let Inst{20} = direction;
5110 let Inst{15-12} = Rt;
5111 let Inst{19-16} = Rt2;
5112 let Inst{11-8} = cop;
5113 let Inst{7-4} = opc1;
5114 let Inst{3-0} = CRm;
5116 let DecoderMethod = "DecodeMRRC2";
5119 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5120 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5121 GPRnopc:$Rt2, imm:$CRm)]>;
5122 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5124 //===----------------------------------------------------------------------===//
5125 // Move between special register and ARM core register
5128 // Move to ARM core register from Special Register
5129 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5130 "mrs", "\t$Rd, apsr", []> {
5132 let Inst{23-16} = 0b00001111;
5133 let Unpredictable{19-17} = 0b111;
5135 let Inst{15-12} = Rd;
5137 let Inst{11-0} = 0b000000000000;
5138 let Unpredictable{11-0} = 0b110100001111;
5141 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5144 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5145 // section B9.3.9, with the R bit set to 1.
5146 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5147 "mrs", "\t$Rd, spsr", []> {
5149 let Inst{23-16} = 0b01001111;
5150 let Unpredictable{19-16} = 0b1111;
5152 let Inst{15-12} = Rd;
5154 let Inst{11-0} = 0b000000000000;
5155 let Unpredictable{11-0} = 0b110100001111;
5158 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5159 // separate encoding (distinguished by bit 5.
5160 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5161 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5162 Requires<[IsARM, HasVirtualization]> {
5167 let Inst{22} = banked{5}; // R bit
5168 let Inst{21-20} = 0b00;
5169 let Inst{19-16} = banked{3-0};
5170 let Inst{15-12} = Rd;
5171 let Inst{11-9} = 0b001;
5172 let Inst{8} = banked{4};
5173 let Inst{7-0} = 0b00000000;
5176 // Move from ARM core register to Special Register
5178 // No need to have both system and application versions of MSR (immediate) or
5179 // MSR (register), the encodings are the same and the assembly parser has no way
5180 // to distinguish between them. The mask operand contains the special register
5181 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5182 // accessed in the special register.
5183 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5184 "msr", "\t$mask, $Rn", []> {
5189 let Inst{22} = mask{4}; // R bit
5190 let Inst{21-20} = 0b10;
5191 let Inst{19-16} = mask{3-0};
5192 let Inst{15-12} = 0b1111;
5193 let Inst{11-4} = 0b00000000;
5197 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5198 "msr", "\t$mask, $imm", []> {
5203 let Inst{22} = mask{4}; // R bit
5204 let Inst{21-20} = 0b10;
5205 let Inst{19-16} = mask{3-0};
5206 let Inst{15-12} = 0b1111;
5207 let Inst{11-0} = imm;
5210 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5211 // separate encoding (distinguished by bit 5.
5212 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5213 NoItinerary, "msr", "\t$banked, $Rn", []>,
5214 Requires<[IsARM, HasVirtualization]> {
5219 let Inst{22} = banked{5}; // R bit
5220 let Inst{21-20} = 0b10;
5221 let Inst{19-16} = banked{3-0};
5222 let Inst{15-12} = 0b1111;
5223 let Inst{11-9} = 0b001;
5224 let Inst{8} = banked{4};
5225 let Inst{7-4} = 0b0000;
5229 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5230 // are needed to probe the stack when allocating more than
5231 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5232 // ensure that the guard pages used by the OS virtual memory manager are
5233 // allocated in correct sequence.
5234 // The main point of having separate instruction are extra unmodelled effects
5235 // (compared to ordinary calls) like stack pointer change.
5237 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5238 [SDNPHasChain, SDNPSideEffect]>;
5239 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5240 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5242 //===----------------------------------------------------------------------===//
5246 // __aeabi_read_tp preserves the registers r1-r3.
5247 // This is a pseudo inst so that we can get the encoding right,
5248 // complete with fixup for the aeabi_read_tp function.
5249 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5250 // is defined in "ARMInstrThumb.td".
5252 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5253 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5254 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5257 //===----------------------------------------------------------------------===//
5258 // SJLJ Exception handling intrinsics
5259 // eh_sjlj_setjmp() is an instruction sequence to store the return
5260 // address and save #0 in R0 for the non-longjmp case.
5261 // Since by its nature we may be coming from some other function to get
5262 // here, and we're using the stack frame for the containing function to
5263 // save/restore registers, we can't keep anything live in regs across
5264 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5265 // when we get here from a longjmp(). We force everything out of registers
5266 // except for our own input by listing the relevant registers in Defs. By
5267 // doing so, we also cause the prologue/epilogue code to actively preserve
5268 // all of the callee-saved resgisters, which is exactly what we want.
5269 // A constant value is passed in $val, and we use the location as a scratch.
5271 // These are pseudo-instructions and are lowered to individual MC-insts, so
5272 // no encoding information is necessary.
5274 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5275 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5276 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5277 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5279 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5280 Requires<[IsARM, HasVFP2]>;
5284 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5285 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5286 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5288 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5289 Requires<[IsARM, NoVFP]>;
5292 // FIXME: Non-IOS version(s)
5293 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5294 Defs = [ R7, LR, SP ] in {
5295 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5297 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5301 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5302 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5303 [(ARMeh_sjlj_setup_dispatch)]>;
5305 // eh.sjlj.dispatchsetup pseudo-instruction.
5306 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5307 // the pseudo is expanded (which happens before any passes that need the
5308 // instruction size).
5309 let isBarrier = 1 in
5310 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5313 //===----------------------------------------------------------------------===//
5314 // Non-Instruction Patterns
5317 // ARMv4 indirect branch using (MOVr PC, dst)
5318 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5319 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5320 4, IIC_Br, [(brind GPR:$dst)],
5321 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5322 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5324 // Large immediate handling.
5326 // 32-bit immediate using two piece mod_imms or movw + movt.
5327 // This is a single pseudo instruction, the benefit is that it can be remat'd
5328 // as a single unit instead of having to handle reg inputs.
5329 // FIXME: Remove this when we can do generalized remat.
5330 let isReMaterializable = 1, isMoveImm = 1 in
5331 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5332 [(set GPR:$dst, (arm_i32imm:$src))]>,
5335 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5336 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5337 Requires<[IsARM, DontUseMovt]>;
5339 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5340 // It also makes it possible to rematerialize the instructions.
5341 // FIXME: Remove this when we can do generalized remat and when machine licm
5342 // can properly the instructions.
5343 let isReMaterializable = 1 in {
5344 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5346 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5347 Requires<[IsARM, UseMovt]>;
5349 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5352 (ARMWrapperPIC tglobaladdr:$addr))]>,
5353 Requires<[IsARM, DontUseMovt]>;
5355 let AddedComplexity = 10 in
5356 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5359 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5360 Requires<[IsARM, DontUseMovt]>;
5362 let AddedComplexity = 10 in
5363 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5365 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5366 Requires<[IsARM, UseMovt]>;
5367 } // isReMaterializable
5369 // ConstantPool, GlobalAddress, and JumpTable
5370 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5371 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5372 Requires<[IsARM, UseMovt]>;
5373 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5374 (LEApcrelJT tjumptable:$dst)>;
5376 // TODO: add,sub,and, 3-instr forms?
5378 // Tail calls. These patterns also apply to Thumb mode.
5379 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5380 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5381 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5384 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5385 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5386 (BMOVPCB_CALL texternalsym:$func)>;
5388 // zextload i1 -> zextload i8
5389 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5390 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5392 // extload -> zextload
5393 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5394 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5395 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5396 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5398 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5400 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5401 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5404 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5405 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5406 (SMULBB GPR:$a, GPR:$b)>;
5407 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5408 (SMULBB GPR:$a, GPR:$b)>;
5409 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5410 (sra GPR:$b, (i32 16))),
5411 (SMULBT GPR:$a, GPR:$b)>;
5412 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5413 (SMULBT GPR:$a, GPR:$b)>;
5414 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5415 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5416 (SMULTB GPR:$a, GPR:$b)>;
5417 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5418 (SMULTB GPR:$a, GPR:$b)>;
5420 def : ARMV5MOPat<(add GPR:$acc,
5421 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5422 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5423 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5424 def : ARMV5MOPat<(add GPR:$acc,
5425 (mul sext_16_node:$a, sext_16_node:$b)),
5426 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5427 def : ARMV5MOPat<(add GPR:$acc,
5428 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5429 (sra GPR:$b, (i32 16)))),
5430 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5431 def : ARMV5MOPat<(add GPR:$acc,
5432 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5433 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5434 def : ARMV5MOPat<(add GPR:$acc,
5435 (mul (sra GPR:$a, (i32 16)),
5436 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5437 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5438 def : ARMV5MOPat<(add GPR:$acc,
5439 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5440 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5443 // Pre-v7 uses MCR for synchronization barriers.
5444 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5445 Requires<[IsARM, HasV6]>;
5447 // SXT/UXT with no rotate
5448 let AddedComplexity = 16 in {
5449 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5450 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5451 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5452 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5453 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5454 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5455 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5458 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5459 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5461 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5462 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5463 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5464 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5466 // Atomic load/store patterns
5467 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5468 (LDRBrs ldst_so_reg:$src)>;
5469 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5470 (LDRBi12 addrmode_imm12:$src)>;
5471 def : ARMPat<(atomic_load_16 addrmode3:$src),
5472 (LDRH addrmode3:$src)>;
5473 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5474 (LDRrs ldst_so_reg:$src)>;
5475 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5476 (LDRi12 addrmode_imm12:$src)>;
5477 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5478 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5479 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5480 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5481 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5482 (STRH GPR:$val, addrmode3:$ptr)>;
5483 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5484 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5485 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5486 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5489 //===----------------------------------------------------------------------===//
5493 include "ARMInstrThumb.td"
5495 //===----------------------------------------------------------------------===//
5499 include "ARMInstrThumb2.td"
5501 //===----------------------------------------------------------------------===//
5502 // Floating Point Support
5505 include "ARMInstrVFP.td"
5507 //===----------------------------------------------------------------------===//
5508 // Advanced SIMD (NEON) Support
5511 include "ARMInstrNEON.td"
5513 //===----------------------------------------------------------------------===//
5514 // Assembler aliases
5518 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5519 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5520 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5522 // System instructions
5523 def : MnemonicAlias<"swi", "svc">;
5525 // Load / Store Multiple
5526 def : MnemonicAlias<"ldmfd", "ldm">;
5527 def : MnemonicAlias<"ldmia", "ldm">;
5528 def : MnemonicAlias<"ldmea", "ldmdb">;
5529 def : MnemonicAlias<"stmfd", "stmdb">;
5530 def : MnemonicAlias<"stmia", "stm">;
5531 def : MnemonicAlias<"stmea", "stm">;
5533 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5534 // shift amount is zero (i.e., unspecified).
5535 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5536 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5537 Requires<[IsARM, HasV6]>;
5538 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5539 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5540 Requires<[IsARM, HasV6]>;
5542 // PUSH/POP aliases for STM/LDM
5543 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5544 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5546 // SSAT/USAT optional shift operand.
5547 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5548 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5549 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5550 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5553 // Extend instruction optional rotate operand.
5554 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5555 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5556 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5557 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5558 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5559 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5560 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5561 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5562 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5563 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5564 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5565 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5567 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5568 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5569 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5570 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5571 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5572 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5573 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5574 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5575 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5576 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5577 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5578 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5582 def : MnemonicAlias<"rfefa", "rfeda">;
5583 def : MnemonicAlias<"rfeea", "rfedb">;
5584 def : MnemonicAlias<"rfefd", "rfeia">;
5585 def : MnemonicAlias<"rfeed", "rfeib">;
5586 def : MnemonicAlias<"rfe", "rfeia">;
5589 def : MnemonicAlias<"srsfa", "srsib">;
5590 def : MnemonicAlias<"srsea", "srsia">;
5591 def : MnemonicAlias<"srsfd", "srsdb">;
5592 def : MnemonicAlias<"srsed", "srsda">;
5593 def : MnemonicAlias<"srs", "srsia">;
5596 def : MnemonicAlias<"qsubaddx", "qsax">;
5598 def : MnemonicAlias<"saddsubx", "sasx">;
5599 // SHASX == SHADDSUBX
5600 def : MnemonicAlias<"shaddsubx", "shasx">;
5601 // SHSAX == SHSUBADDX
5602 def : MnemonicAlias<"shsubaddx", "shsax">;
5604 def : MnemonicAlias<"ssubaddx", "ssax">;
5606 def : MnemonicAlias<"uaddsubx", "uasx">;
5607 // UHASX == UHADDSUBX
5608 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5609 // UHSAX == UHSUBADDX
5610 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5611 // UQASX == UQADDSUBX
5612 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5613 // UQSAX == UQSUBADDX
5614 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5616 def : MnemonicAlias<"usubaddx", "usax">;
5618 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5620 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5621 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5622 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5623 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5624 // Same for AND <--> BIC
5625 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5626 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5627 pred:$p, cc_out:$s)>;
5628 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5629 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5630 pred:$p, cc_out:$s)>;
5631 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5632 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5633 pred:$p, cc_out:$s)>;
5634 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5635 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5636 pred:$p, cc_out:$s)>;
5638 // Likewise, "add Rd, mod_imm_neg" -> sub
5639 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5640 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5641 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5642 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5643 // Same for CMP <--> CMN via mod_imm_neg
5644 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5645 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5646 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5647 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5649 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5650 // LSR, ROR, and RRX instructions.
5651 // FIXME: We need C++ parser hooks to map the alias to the MOV
5652 // encoding. It seems we should be able to do that sort of thing
5653 // in tblgen, but it could get ugly.
5654 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5655 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5656 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5658 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5659 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5661 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5662 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5664 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5665 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5668 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5669 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5670 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5671 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5672 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5674 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5675 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5677 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5678 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5680 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5681 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5685 // "neg" is and alias for "rsb rd, rn, #0"
5686 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5687 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5689 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5690 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5691 Requires<[IsARM, NoV6]>;
5693 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5694 // the instruction definitions need difference constraints pre-v6.
5695 // Use these aliases for the assembly parsing on pre-v6.
5696 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5697 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5698 Requires<[IsARM, NoV6]>;
5699 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5700 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5701 pred:$p, cc_out:$s)>,
5702 Requires<[IsARM, NoV6]>;
5703 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5704 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5705 Requires<[IsARM, NoV6]>;
5706 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5707 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5708 Requires<[IsARM, NoV6]>;
5709 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5710 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5711 Requires<[IsARM, NoV6]>;
5712 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5713 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5714 Requires<[IsARM, NoV6]>;
5716 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5718 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5719 ComplexDeprecationPredicate<"IT">;
5721 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5722 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5724 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;