1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
225 AssemblerPredicate<"FeatureTrustZone",
227 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
228 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
229 def IsThumb : Predicate<"Subtarget->isThumb()">,
230 AssemblerPredicate<"ModeThumb", "thumb">;
231 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
232 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
233 AssemblerPredicate<"ModeThumb,FeatureThumb2",
235 def IsMClass : Predicate<"Subtarget->isMClass()">,
236 AssemblerPredicate<"FeatureMClass", "armv7m">;
237 def IsARClass : Predicate<"!Subtarget->isMClass()">,
238 AssemblerPredicate<"!FeatureMClass",
240 def IsARM : Predicate<"!Subtarget->isThumb()">,
241 AssemblerPredicate<"!ModeThumb", "arm-mode">;
242 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
243 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
244 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
245 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
246 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
247 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
249 // FIXME: Eventually this will be just "hasV6T2Ops".
250 def UseMovt : Predicate<"Subtarget->useMovt()">;
251 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
252 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
253 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
255 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
256 // But only select them if more precision in FP computation is allowed.
257 // Do not use them for Darwin platforms.
258 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
259 " FPOpFusion::Fast) && "
260 "!Subtarget->isTargetDarwin()">;
261 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
262 "Subtarget->isTargetDarwin()">;
264 // VGETLNi32 is microcoded on Swift - prefer VMOV.
265 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
266 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
268 // VDUP.32 is microcoded on Swift - prefer VMOV.
269 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
270 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
272 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
273 // this allows more effective execution domain optimization. See
274 // setExecutionDomain().
275 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
276 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
278 def IsLE : Predicate<"TLI.isLittleEndian()">;
279 def IsBE : Predicate<"TLI.isBigEndian()">;
281 //===----------------------------------------------------------------------===//
282 // ARM Flag Definitions.
284 class RegConstraint<string C> {
285 string Constraints = C;
288 //===----------------------------------------------------------------------===//
289 // ARM specific transformation functions and pattern fragments.
292 // imm_neg_XFORM - Return the negation of an i32 immediate value.
293 def imm_neg_XFORM : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
297 // imm_not_XFORM - Return the complement of a i32 immediate value.
298 def imm_not_XFORM : SDNodeXForm<imm, [{
299 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
302 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
303 def imm16_31 : ImmLeaf<i32, [{
304 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
307 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
308 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
309 unsigned Value = -(unsigned)N->getZExtValue();
310 return Value && ARM_AM::getSOImmVal(Value) != -1;
312 let ParserMatchClass = so_imm_neg_asmoperand;
315 // Note: this pattern doesn't require an encoder method and such, as it's
316 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
317 // is handled by the destination instructions, which use so_imm.
318 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
319 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
320 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
322 let ParserMatchClass = so_imm_not_asmoperand;
325 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
326 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
327 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
330 /// Split a 32-bit immediate into two 16 bit parts.
331 def hi16 : SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
335 def lo16AllZero : PatLeaf<(i32 imm), [{
336 // Returns true if all low 16-bits are 0.
337 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
340 class BinOpWithFlagFrag<dag res> :
341 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
342 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
343 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
345 // An 'and' node with a single use.
346 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
347 return N->hasOneUse();
350 // An 'xor' node with a single use.
351 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
352 return N->hasOneUse();
355 // An 'fmul' node with a single use.
356 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
357 return N->hasOneUse();
360 // An 'fadd' node which checks for single non-hazardous use.
361 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
362 return hasNoVMLxHazardUse(N);
365 // An 'fsub' node which checks for single non-hazardous use.
366 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
367 return hasNoVMLxHazardUse(N);
370 //===----------------------------------------------------------------------===//
371 // Operand Definitions.
374 // Immediate operands with a shared generic asm render method.
375 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
378 // FIXME: rename brtarget to t2_brtarget
379 def brtarget : Operand<OtherVT> {
380 let EncoderMethod = "getBranchTargetOpValue";
381 let OperandType = "OPERAND_PCREL";
382 let DecoderMethod = "DecodeT2BROperand";
385 // FIXME: get rid of this one?
386 def uncondbrtarget : Operand<OtherVT> {
387 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
388 let OperandType = "OPERAND_PCREL";
391 // Branch target for ARM. Handles conditional/unconditional
392 def br_target : Operand<OtherVT> {
393 let EncoderMethod = "getARMBranchTargetOpValue";
394 let OperandType = "OPERAND_PCREL";
398 // FIXME: rename bltarget to t2_bl_target?
399 def bltarget : Operand<i32> {
400 // Encoded the same as branch targets.
401 let EncoderMethod = "getBranchTargetOpValue";
402 let OperandType = "OPERAND_PCREL";
405 // Call target for ARM. Handles conditional/unconditional
406 // FIXME: rename bl_target to t2_bltarget?
407 def bl_target : Operand<i32> {
408 let EncoderMethod = "getARMBLTargetOpValue";
409 let OperandType = "OPERAND_PCREL";
412 def blx_target : Operand<i32> {
413 let EncoderMethod = "getARMBLXTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // A list of registers separated by comma. Used by load/store multiple.
418 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
419 def reglist : Operand<i32> {
420 let EncoderMethod = "getRegisterListOpValue";
421 let ParserMatchClass = RegListAsmOperand;
422 let PrintMethod = "printRegisterList";
423 let DecoderMethod = "DecodeRegListOperand";
426 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
428 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
429 def dpr_reglist : Operand<i32> {
430 let EncoderMethod = "getRegisterListOpValue";
431 let ParserMatchClass = DPRRegListAsmOperand;
432 let PrintMethod = "printRegisterList";
433 let DecoderMethod = "DecodeDPRRegListOperand";
436 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
437 def spr_reglist : Operand<i32> {
438 let EncoderMethod = "getRegisterListOpValue";
439 let ParserMatchClass = SPRRegListAsmOperand;
440 let PrintMethod = "printRegisterList";
441 let DecoderMethod = "DecodeSPRRegListOperand";
444 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
445 def cpinst_operand : Operand<i32> {
446 let PrintMethod = "printCPInstOperand";
450 def pclabel : Operand<i32> {
451 let PrintMethod = "printPCLabel";
454 // ADR instruction labels.
455 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
456 def adrlabel : Operand<i32> {
457 let EncoderMethod = "getAdrLabelOpValue";
458 let ParserMatchClass = AdrLabelAsmOperand;
459 let PrintMethod = "printAdrLabelOperand";
462 def neon_vcvt_imm32 : Operand<i32> {
463 let EncoderMethod = "getNEONVcvtImm32OpValue";
464 let DecoderMethod = "DecodeVCVTImmOperand";
467 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
468 def rot_imm_XFORM: SDNodeXForm<imm, [{
469 switch (N->getZExtValue()){
471 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
472 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
473 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
474 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
477 def RotImmAsmOperand : AsmOperandClass {
479 let ParserMethod = "parseRotImm";
481 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
482 int32_t v = N->getZExtValue();
483 return v == 8 || v == 16 || v == 24; }],
485 let PrintMethod = "printRotImmOperand";
486 let ParserMatchClass = RotImmAsmOperand;
489 // shift_imm: An integer that encodes a shift amount and the type of shift
490 // (asr or lsl). The 6-bit immediate encodes as:
493 // {4-0} imm5 shift amount.
494 // asr #32 encoded as imm5 == 0.
495 def ShifterImmAsmOperand : AsmOperandClass {
496 let Name = "ShifterImm";
497 let ParserMethod = "parseShifterImm";
499 def shift_imm : Operand<i32> {
500 let PrintMethod = "printShiftImmOperand";
501 let ParserMatchClass = ShifterImmAsmOperand;
504 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
505 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
506 def so_reg_reg : Operand<i32>, // reg reg imm
507 ComplexPattern<i32, 3, "SelectRegShifterOperand",
508 [shl, srl, sra, rotr]> {
509 let EncoderMethod = "getSORegRegOpValue";
510 let PrintMethod = "printSORegRegOperand";
511 let DecoderMethod = "DecodeSORegRegOperand";
512 let ParserMatchClass = ShiftedRegAsmOperand;
513 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
516 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
517 def so_reg_imm : Operand<i32>, // reg imm
518 ComplexPattern<i32, 2, "SelectImmShifterOperand",
519 [shl, srl, sra, rotr]> {
520 let EncoderMethod = "getSORegImmOpValue";
521 let PrintMethod = "printSORegImmOperand";
522 let DecoderMethod = "DecodeSORegImmOperand";
523 let ParserMatchClass = ShiftedImmAsmOperand;
524 let MIOperandInfo = (ops GPR, i32imm);
527 // FIXME: Does this need to be distinct from so_reg?
528 def shift_so_reg_reg : Operand<i32>, // reg reg imm
529 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
530 [shl,srl,sra,rotr]> {
531 let EncoderMethod = "getSORegRegOpValue";
532 let PrintMethod = "printSORegRegOperand";
533 let DecoderMethod = "DecodeSORegRegOperand";
534 let ParserMatchClass = ShiftedRegAsmOperand;
535 let MIOperandInfo = (ops GPR, GPR, i32imm);
538 // FIXME: Does this need to be distinct from so_reg?
539 def shift_so_reg_imm : Operand<i32>, // reg reg imm
540 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
541 [shl,srl,sra,rotr]> {
542 let EncoderMethod = "getSORegImmOpValue";
543 let PrintMethod = "printSORegImmOperand";
544 let DecoderMethod = "DecodeSORegImmOperand";
545 let ParserMatchClass = ShiftedImmAsmOperand;
546 let MIOperandInfo = (ops GPR, i32imm);
550 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
551 // 8-bit immediate rotated by an arbitrary number of bits.
552 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
553 def so_imm : Operand<i32>, ImmLeaf<i32, [{
554 return ARM_AM::getSOImmVal(Imm) != -1;
556 let EncoderMethod = "getSOImmOpValue";
557 let ParserMatchClass = SOImmAsmOperand;
558 let DecoderMethod = "DecodeSOImmOperand";
561 // Break so_imm's up into two pieces. This handles immediates with up to 16
562 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
563 // get the first/second pieces.
564 def so_imm2part : PatLeaf<(imm), [{
565 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
568 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
570 def arm_i32imm : PatLeaf<(imm), [{
571 if (Subtarget->hasV6T2Ops())
573 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
576 /// imm0_1 predicate - Immediate in the range [0,1].
577 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
578 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
580 /// imm0_3 predicate - Immediate in the range [0,3].
581 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
582 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
584 /// imm0_7 predicate - Immediate in the range [0,7].
585 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
586 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
587 return Imm >= 0 && Imm < 8;
589 let ParserMatchClass = Imm0_7AsmOperand;
592 /// imm8 predicate - Immediate is exactly 8.
593 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
594 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
595 let ParserMatchClass = Imm8AsmOperand;
598 /// imm16 predicate - Immediate is exactly 16.
599 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
600 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
601 let ParserMatchClass = Imm16AsmOperand;
604 /// imm32 predicate - Immediate is exactly 32.
605 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
606 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
607 let ParserMatchClass = Imm32AsmOperand;
610 /// imm1_7 predicate - Immediate in the range [1,7].
611 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
612 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
613 let ParserMatchClass = Imm1_7AsmOperand;
616 /// imm1_15 predicate - Immediate in the range [1,15].
617 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
618 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
619 let ParserMatchClass = Imm1_15AsmOperand;
622 /// imm1_31 predicate - Immediate in the range [1,31].
623 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
624 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
625 let ParserMatchClass = Imm1_31AsmOperand;
628 /// imm0_15 predicate - Immediate in the range [0,15].
629 def Imm0_15AsmOperand: ImmAsmOperand {
630 let Name = "Imm0_15";
631 let DiagnosticType = "ImmRange0_15";
633 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
634 return Imm >= 0 && Imm < 16;
636 let ParserMatchClass = Imm0_15AsmOperand;
639 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
640 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
641 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
642 return Imm >= 0 && Imm < 32;
644 let ParserMatchClass = Imm0_31AsmOperand;
647 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
648 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
649 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
650 return Imm >= 0 && Imm < 32;
652 let ParserMatchClass = Imm0_32AsmOperand;
655 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
656 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
657 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
658 return Imm >= 0 && Imm < 64;
660 let ParserMatchClass = Imm0_63AsmOperand;
663 /// imm0_255 predicate - Immediate in the range [0,255].
664 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
665 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
666 let ParserMatchClass = Imm0_255AsmOperand;
669 /// imm0_65535 - An immediate is in the range [0.65535].
670 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
671 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
672 return Imm >= 0 && Imm < 65536;
674 let ParserMatchClass = Imm0_65535AsmOperand;
677 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
678 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
679 return -Imm >= 0 && -Imm < 65536;
682 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
683 // a relocatable expression.
685 // FIXME: This really needs a Thumb version separate from the ARM version.
686 // While the range is the same, and can thus use the same match class,
687 // the encoding is different so it should have a different encoder method.
688 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
689 def imm0_65535_expr : Operand<i32> {
690 let EncoderMethod = "getHiLo16ImmOpValue";
691 let ParserMatchClass = Imm0_65535ExprAsmOperand;
694 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
695 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
696 def imm24b : Operand<i32>, ImmLeaf<i32, [{
697 return Imm >= 0 && Imm <= 0xffffff;
699 let ParserMatchClass = Imm24bitAsmOperand;
703 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
705 def BitfieldAsmOperand : AsmOperandClass {
706 let Name = "Bitfield";
707 let ParserMethod = "parseBitfield";
710 def bf_inv_mask_imm : Operand<i32>,
712 return ARM::isBitFieldInvertedMask(N->getZExtValue());
714 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
715 let PrintMethod = "printBitfieldInvMaskImmOperand";
716 let DecoderMethod = "DecodeBitfieldMaskOperand";
717 let ParserMatchClass = BitfieldAsmOperand;
720 def imm1_32_XFORM: SDNodeXForm<imm, [{
721 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
723 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
724 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
725 uint64_t Imm = N->getZExtValue();
726 return Imm > 0 && Imm <= 32;
729 let PrintMethod = "printImmPlusOneOperand";
730 let ParserMatchClass = Imm1_32AsmOperand;
733 def imm1_16_XFORM: SDNodeXForm<imm, [{
734 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
736 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
737 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
739 let PrintMethod = "printImmPlusOneOperand";
740 let ParserMatchClass = Imm1_16AsmOperand;
743 // Define ARM specific addressing modes.
744 // addrmode_imm12 := reg +/- imm12
746 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
747 class AddrMode_Imm12 : Operand<i32>,
748 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
749 // 12-bit immediate operand. Note that instructions using this encode
750 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
751 // immediate values are as normal.
753 let EncoderMethod = "getAddrModeImm12OpValue";
754 let DecoderMethod = "DecodeAddrModeImm12Operand";
755 let ParserMatchClass = MemImm12OffsetAsmOperand;
756 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
759 def addrmode_imm12 : AddrMode_Imm12 {
760 let PrintMethod = "printAddrModeImm12Operand<false>";
763 def addrmode_imm12_pre : AddrMode_Imm12 {
764 let PrintMethod = "printAddrModeImm12Operand<true>";
767 // ldst_so_reg := reg +/- reg shop imm
769 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
770 def ldst_so_reg : Operand<i32>,
771 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
772 let EncoderMethod = "getLdStSORegOpValue";
773 // FIXME: Simplify the printer
774 let PrintMethod = "printAddrMode2Operand";
775 let DecoderMethod = "DecodeSORegMemOperand";
776 let ParserMatchClass = MemRegOffsetAsmOperand;
777 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
780 // postidx_imm8 := +/- [0,255]
783 // {8} 1 is imm8 is non-negative. 0 otherwise.
784 // {7-0} [0,255] imm8 value.
785 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
786 def postidx_imm8 : Operand<i32> {
787 let PrintMethod = "printPostIdxImm8Operand";
788 let ParserMatchClass = PostIdxImm8AsmOperand;
789 let MIOperandInfo = (ops i32imm);
792 // postidx_imm8s4 := +/- [0,1020]
795 // {8} 1 is imm8 is non-negative. 0 otherwise.
796 // {7-0} [0,255] imm8 value, scaled by 4.
797 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
798 def postidx_imm8s4 : Operand<i32> {
799 let PrintMethod = "printPostIdxImm8s4Operand";
800 let ParserMatchClass = PostIdxImm8s4AsmOperand;
801 let MIOperandInfo = (ops i32imm);
805 // postidx_reg := +/- reg
807 def PostIdxRegAsmOperand : AsmOperandClass {
808 let Name = "PostIdxReg";
809 let ParserMethod = "parsePostIdxReg";
811 def postidx_reg : Operand<i32> {
812 let EncoderMethod = "getPostIdxRegOpValue";
813 let DecoderMethod = "DecodePostIdxReg";
814 let PrintMethod = "printPostIdxRegOperand";
815 let ParserMatchClass = PostIdxRegAsmOperand;
816 let MIOperandInfo = (ops GPRnopc, i32imm);
820 // addrmode2 := reg +/- imm12
821 // := reg +/- reg shop imm
823 // FIXME: addrmode2 should be refactored the rest of the way to always
824 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
825 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
826 def addrmode2 : Operand<i32>,
827 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
828 let EncoderMethod = "getAddrMode2OpValue";
829 let PrintMethod = "printAddrMode2Operand";
830 let ParserMatchClass = AddrMode2AsmOperand;
831 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
834 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
835 let Name = "PostIdxRegShifted";
836 let ParserMethod = "parsePostIdxReg";
838 def am2offset_reg : Operand<i32>,
839 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
840 [], [SDNPWantRoot]> {
841 let EncoderMethod = "getAddrMode2OffsetOpValue";
842 let PrintMethod = "printAddrMode2OffsetOperand";
843 // When using this for assembly, it's always as a post-index offset.
844 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
845 let MIOperandInfo = (ops GPRnopc, i32imm);
848 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
849 // the GPR is purely vestigal at this point.
850 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
851 def am2offset_imm : Operand<i32>,
852 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
853 [], [SDNPWantRoot]> {
854 let EncoderMethod = "getAddrMode2OffsetOpValue";
855 let PrintMethod = "printAddrMode2OffsetOperand";
856 let ParserMatchClass = AM2OffsetImmAsmOperand;
857 let MIOperandInfo = (ops GPRnopc, i32imm);
861 // addrmode3 := reg +/- reg
862 // addrmode3 := reg +/- imm8
864 // FIXME: split into imm vs. reg versions.
865 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
866 class AddrMode3 : Operand<i32>,
867 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
868 let EncoderMethod = "getAddrMode3OpValue";
869 let ParserMatchClass = AddrMode3AsmOperand;
870 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
873 def addrmode3 : AddrMode3
875 let PrintMethod = "printAddrMode3Operand<false>";
878 def addrmode3_pre : AddrMode3
880 let PrintMethod = "printAddrMode3Operand<true>";
883 // FIXME: split into imm vs. reg versions.
884 // FIXME: parser method to handle +/- register.
885 def AM3OffsetAsmOperand : AsmOperandClass {
886 let Name = "AM3Offset";
887 let ParserMethod = "parseAM3Offset";
889 def am3offset : Operand<i32>,
890 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
891 [], [SDNPWantRoot]> {
892 let EncoderMethod = "getAddrMode3OffsetOpValue";
893 let PrintMethod = "printAddrMode3OffsetOperand";
894 let ParserMatchClass = AM3OffsetAsmOperand;
895 let MIOperandInfo = (ops GPR, i32imm);
898 // ldstm_mode := {ia, ib, da, db}
900 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
901 let EncoderMethod = "getLdStmModeOpValue";
902 let PrintMethod = "printLdStmModeOperand";
905 // addrmode5 := reg +/- imm8*4
907 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
908 class AddrMode5 : Operand<i32>,
909 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
910 let EncoderMethod = "getAddrMode5OpValue";
911 let DecoderMethod = "DecodeAddrMode5Operand";
912 let ParserMatchClass = AddrMode5AsmOperand;
913 let MIOperandInfo = (ops GPR:$base, i32imm);
916 def addrmode5 : AddrMode5 {
917 let PrintMethod = "printAddrMode5Operand<false>";
920 def addrmode5_pre : AddrMode5 {
921 let PrintMethod = "printAddrMode5Operand<true>";
924 // addrmode6 := reg with optional alignment
926 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
927 def addrmode6 : Operand<i32>,
928 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
929 let PrintMethod = "printAddrMode6Operand";
930 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
931 let EncoderMethod = "getAddrMode6AddressOpValue";
932 let DecoderMethod = "DecodeAddrMode6Operand";
933 let ParserMatchClass = AddrMode6AsmOperand;
936 def am6offset : Operand<i32>,
937 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
938 [], [SDNPWantRoot]> {
939 let PrintMethod = "printAddrMode6OffsetOperand";
940 let MIOperandInfo = (ops GPR);
941 let EncoderMethod = "getAddrMode6OffsetOpValue";
942 let DecoderMethod = "DecodeGPRRegisterClass";
945 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
946 // (single element from one lane) for size 32.
947 def addrmode6oneL32 : Operand<i32>,
948 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
949 let PrintMethod = "printAddrMode6Operand";
950 let MIOperandInfo = (ops GPR:$addr, i32imm);
951 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
954 // Special version of addrmode6 to handle alignment encoding for VLD-dup
955 // instructions, specifically VLD4-dup.
956 def addrmode6dup : Operand<i32>,
957 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
958 let PrintMethod = "printAddrMode6Operand";
959 let MIOperandInfo = (ops GPR:$addr, i32imm);
960 let EncoderMethod = "getAddrMode6DupAddressOpValue";
961 // FIXME: This is close, but not quite right. The alignment specifier is
963 let ParserMatchClass = AddrMode6AsmOperand;
966 // addrmodepc := pc + reg
968 def addrmodepc : Operand<i32>,
969 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
970 let PrintMethod = "printAddrModePCOperand";
971 let MIOperandInfo = (ops GPR, i32imm);
974 // addr_offset_none := reg
976 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
977 def addr_offset_none : Operand<i32>,
978 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
979 let PrintMethod = "printAddrMode7Operand";
980 let DecoderMethod = "DecodeAddrMode7Operand";
981 let ParserMatchClass = MemNoOffsetAsmOperand;
982 let MIOperandInfo = (ops GPR:$base);
985 def nohash_imm : Operand<i32> {
986 let PrintMethod = "printNoHashImmediate";
989 def CoprocNumAsmOperand : AsmOperandClass {
990 let Name = "CoprocNum";
991 let ParserMethod = "parseCoprocNumOperand";
993 def p_imm : Operand<i32> {
994 let PrintMethod = "printPImmediate";
995 let ParserMatchClass = CoprocNumAsmOperand;
996 let DecoderMethod = "DecodeCoprocessor";
999 def pf_imm : Operand<i32> {
1000 let PrintMethod = "printPImmediate";
1001 let ParserMatchClass = CoprocNumAsmOperand;
1004 def CoprocRegAsmOperand : AsmOperandClass {
1005 let Name = "CoprocReg";
1006 let ParserMethod = "parseCoprocRegOperand";
1008 def c_imm : Operand<i32> {
1009 let PrintMethod = "printCImmediate";
1010 let ParserMatchClass = CoprocRegAsmOperand;
1012 def CoprocOptionAsmOperand : AsmOperandClass {
1013 let Name = "CoprocOption";
1014 let ParserMethod = "parseCoprocOptionOperand";
1016 def coproc_option_imm : Operand<i32> {
1017 let PrintMethod = "printCoprocOptionImm";
1018 let ParserMatchClass = CoprocOptionAsmOperand;
1021 //===----------------------------------------------------------------------===//
1023 include "ARMInstrFormats.td"
1025 //===----------------------------------------------------------------------===//
1026 // Multiclass helpers...
1029 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1030 /// binop that produces a value.
1031 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1032 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1033 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1034 PatFrag opnode, bit Commutable = 0> {
1035 // The register-immediate version is re-materializable. This is useful
1036 // in particular for taking the address of a local.
1037 let isReMaterializable = 1 in {
1038 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1039 iii, opc, "\t$Rd, $Rn, $imm",
1040 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1041 Sched<[WriteALU, ReadALU]> {
1046 let Inst{19-16} = Rn;
1047 let Inst{15-12} = Rd;
1048 let Inst{11-0} = imm;
1051 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1052 iir, opc, "\t$Rd, $Rn, $Rm",
1053 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1054 Sched<[WriteALU, ReadALU, ReadALU]> {
1059 let isCommutable = Commutable;
1060 let Inst{19-16} = Rn;
1061 let Inst{15-12} = Rd;
1062 let Inst{11-4} = 0b00000000;
1066 def rsi : AsI1<opcod, (outs GPR:$Rd),
1067 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1068 iis, opc, "\t$Rd, $Rn, $shift",
1069 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1070 Sched<[WriteALUsi, ReadALU]> {
1075 let Inst{19-16} = Rn;
1076 let Inst{15-12} = Rd;
1077 let Inst{11-5} = shift{11-5};
1079 let Inst{3-0} = shift{3-0};
1082 def rsr : AsI1<opcod, (outs GPR:$Rd),
1083 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1084 iis, opc, "\t$Rd, $Rn, $shift",
1085 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1086 Sched<[WriteALUsr, ReadALUsr]> {
1091 let Inst{19-16} = Rn;
1092 let Inst{15-12} = Rd;
1093 let Inst{11-8} = shift{11-8};
1095 let Inst{6-5} = shift{6-5};
1097 let Inst{3-0} = shift{3-0};
1101 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1102 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1103 /// it is equivalent to the AsI1_bin_irs counterpart.
1104 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1105 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1106 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1107 PatFrag opnode, bit Commutable = 0> {
1108 // The register-immediate version is re-materializable. This is useful
1109 // in particular for taking the address of a local.
1110 let isReMaterializable = 1 in {
1111 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1112 iii, opc, "\t$Rd, $Rn, $imm",
1113 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1114 Sched<[WriteALU, ReadALU]> {
1119 let Inst{19-16} = Rn;
1120 let Inst{15-12} = Rd;
1121 let Inst{11-0} = imm;
1124 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1125 iir, opc, "\t$Rd, $Rn, $Rm",
1126 [/* pattern left blank */]>,
1127 Sched<[WriteALU, ReadALU, ReadALU]> {
1131 let Inst{11-4} = 0b00000000;
1134 let Inst{15-12} = Rd;
1135 let Inst{19-16} = Rn;
1138 def rsi : AsI1<opcod, (outs GPR:$Rd),
1139 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1140 iis, opc, "\t$Rd, $Rn, $shift",
1141 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1142 Sched<[WriteALUsi, ReadALU]> {
1147 let Inst{19-16} = Rn;
1148 let Inst{15-12} = Rd;
1149 let Inst{11-5} = shift{11-5};
1151 let Inst{3-0} = shift{3-0};
1154 def rsr : AsI1<opcod, (outs GPR:$Rd),
1155 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1156 iis, opc, "\t$Rd, $Rn, $shift",
1157 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1158 Sched<[WriteALUsr, ReadALUsr]> {
1163 let Inst{19-16} = Rn;
1164 let Inst{15-12} = Rd;
1165 let Inst{11-8} = shift{11-8};
1167 let Inst{6-5} = shift{6-5};
1169 let Inst{3-0} = shift{3-0};
1173 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1175 /// These opcodes will be converted to the real non-S opcodes by
1176 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1177 let hasPostISelHook = 1, Defs = [CPSR] in {
1178 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1179 InstrItinClass iis, PatFrag opnode,
1180 bit Commutable = 0> {
1181 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1183 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1184 Sched<[WriteALU, ReadALU]>;
1186 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1188 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1189 Sched<[WriteALU, ReadALU, ReadALU]> {
1190 let isCommutable = Commutable;
1192 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1193 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1195 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1196 so_reg_imm:$shift))]>,
1197 Sched<[WriteALUsi, ReadALU]>;
1199 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1200 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1202 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1203 so_reg_reg:$shift))]>,
1204 Sched<[WriteALUSsr, ReadALUsr]>;
1208 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1209 /// operands are reversed.
1210 let hasPostISelHook = 1, Defs = [CPSR] in {
1211 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1212 InstrItinClass iis, PatFrag opnode,
1213 bit Commutable = 0> {
1214 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1216 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1217 Sched<[WriteALU, ReadALU]>;
1219 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1220 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1222 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1224 Sched<[WriteALUsi, ReadALU]>;
1226 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1227 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1229 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1231 Sched<[WriteALUSsr, ReadALUsr]>;
1235 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1236 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1237 /// a explicit result, only implicitly set CPSR.
1238 let isCompare = 1, Defs = [CPSR] in {
1239 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1240 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1241 PatFrag opnode, bit Commutable = 0> {
1242 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1244 [(opnode GPR:$Rn, so_imm:$imm)]>,
1245 Sched<[WriteCMP, ReadALU]> {
1250 let Inst{19-16} = Rn;
1251 let Inst{15-12} = 0b0000;
1252 let Inst{11-0} = imm;
1254 let Unpredictable{15-12} = 0b1111;
1256 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1258 [(opnode GPR:$Rn, GPR:$Rm)]>,
1259 Sched<[WriteCMP, ReadALU, ReadALU]> {
1262 let isCommutable = Commutable;
1265 let Inst{19-16} = Rn;
1266 let Inst{15-12} = 0b0000;
1267 let Inst{11-4} = 0b00000000;
1270 let Unpredictable{15-12} = 0b1111;
1272 def rsi : AI1<opcod, (outs),
1273 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1274 opc, "\t$Rn, $shift",
1275 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1276 Sched<[WriteCMPsi, ReadALU]> {
1281 let Inst{19-16} = Rn;
1282 let Inst{15-12} = 0b0000;
1283 let Inst{11-5} = shift{11-5};
1285 let Inst{3-0} = shift{3-0};
1287 let Unpredictable{15-12} = 0b1111;
1289 def rsr : AI1<opcod, (outs),
1290 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1291 opc, "\t$Rn, $shift",
1292 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1293 Sched<[WriteCMPsr, ReadALU]> {
1298 let Inst{19-16} = Rn;
1299 let Inst{15-12} = 0b0000;
1300 let Inst{11-8} = shift{11-8};
1302 let Inst{6-5} = shift{6-5};
1304 let Inst{3-0} = shift{3-0};
1306 let Unpredictable{15-12} = 0b1111;
1312 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1313 /// register and one whose operand is a register rotated by 8/16/24.
1314 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1315 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1316 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1317 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1318 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1319 Requires<[IsARM, HasV6]> {
1323 let Inst{19-16} = 0b1111;
1324 let Inst{15-12} = Rd;
1325 let Inst{11-10} = rot;
1329 class AI_ext_rrot_np<bits<8> opcod, string opc>
1330 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1331 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1332 Requires<[IsARM, HasV6]> {
1334 let Inst{19-16} = 0b1111;
1335 let Inst{11-10} = rot;
1338 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1339 /// register and one whose operand is a register rotated by 8/16/24.
1340 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1341 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1342 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1343 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1344 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1345 Requires<[IsARM, HasV6]> {
1350 let Inst{19-16} = Rn;
1351 let Inst{15-12} = Rd;
1352 let Inst{11-10} = rot;
1353 let Inst{9-4} = 0b000111;
1357 class AI_exta_rrot_np<bits<8> opcod, string opc>
1358 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1359 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1360 Requires<[IsARM, HasV6]> {
1363 let Inst{19-16} = Rn;
1364 let Inst{11-10} = rot;
1367 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1368 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1369 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1370 bit Commutable = 0> {
1371 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1372 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1373 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1374 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1376 Sched<[WriteALU, ReadALU]> {
1381 let Inst{15-12} = Rd;
1382 let Inst{19-16} = Rn;
1383 let Inst{11-0} = imm;
1385 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1386 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1387 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1389 Sched<[WriteALU, ReadALU, ReadALU]> {
1393 let Inst{11-4} = 0b00000000;
1395 let isCommutable = Commutable;
1397 let Inst{15-12} = Rd;
1398 let Inst{19-16} = Rn;
1400 def rsi : AsI1<opcod, (outs GPR:$Rd),
1401 (ins GPR:$Rn, so_reg_imm:$shift),
1402 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1403 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1405 Sched<[WriteALUsi, ReadALU]> {
1410 let Inst{19-16} = Rn;
1411 let Inst{15-12} = Rd;
1412 let Inst{11-5} = shift{11-5};
1414 let Inst{3-0} = shift{3-0};
1416 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1417 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1418 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1419 [(set GPRnopc:$Rd, CPSR,
1420 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1422 Sched<[WriteALUsr, ReadALUsr]> {
1427 let Inst{19-16} = Rn;
1428 let Inst{15-12} = Rd;
1429 let Inst{11-8} = shift{11-8};
1431 let Inst{6-5} = shift{6-5};
1433 let Inst{3-0} = shift{3-0};
1438 /// AI1_rsc_irs - Define instructions and patterns for rsc
1439 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1440 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1441 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1442 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1443 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1444 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1446 Sched<[WriteALU, ReadALU]> {
1451 let Inst{15-12} = Rd;
1452 let Inst{19-16} = Rn;
1453 let Inst{11-0} = imm;
1455 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1456 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1457 [/* pattern left blank */]>,
1458 Sched<[WriteALU, ReadALU, ReadALU]> {
1462 let Inst{11-4} = 0b00000000;
1465 let Inst{15-12} = Rd;
1466 let Inst{19-16} = Rn;
1468 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1469 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1470 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1472 Sched<[WriteALUsi, ReadALU]> {
1477 let Inst{19-16} = Rn;
1478 let Inst{15-12} = Rd;
1479 let Inst{11-5} = shift{11-5};
1481 let Inst{3-0} = shift{3-0};
1483 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1484 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1485 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1487 Sched<[WriteALUsr, ReadALUsr]> {
1492 let Inst{19-16} = Rn;
1493 let Inst{15-12} = Rd;
1494 let Inst{11-8} = shift{11-8};
1496 let Inst{6-5} = shift{6-5};
1498 let Inst{3-0} = shift{3-0};
1503 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1504 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1505 InstrItinClass iir, PatFrag opnode> {
1506 // Note: We use the complex addrmode_imm12 rather than just an input
1507 // GPR and a constrained immediate so that we can use this to match
1508 // frame index references and avoid matching constant pool references.
1509 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1510 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1511 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1514 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1515 let Inst{19-16} = addr{16-13}; // Rn
1516 let Inst{15-12} = Rt;
1517 let Inst{11-0} = addr{11-0}; // imm12
1519 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1520 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1521 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1524 let shift{4} = 0; // Inst{4} = 0
1525 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1526 let Inst{19-16} = shift{16-13}; // Rn
1527 let Inst{15-12} = Rt;
1528 let Inst{11-0} = shift{11-0};
1533 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1534 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1535 InstrItinClass iir, PatFrag opnode> {
1536 // Note: We use the complex addrmode_imm12 rather than just an input
1537 // GPR and a constrained immediate so that we can use this to match
1538 // frame index references and avoid matching constant pool references.
1539 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1540 (ins addrmode_imm12:$addr),
1541 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1542 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1545 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1546 let Inst{19-16} = addr{16-13}; // Rn
1547 let Inst{15-12} = Rt;
1548 let Inst{11-0} = addr{11-0}; // imm12
1550 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1551 (ins ldst_so_reg:$shift),
1552 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1553 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1556 let shift{4} = 0; // Inst{4} = 0
1557 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1558 let Inst{19-16} = shift{16-13}; // Rn
1559 let Inst{15-12} = Rt;
1560 let Inst{11-0} = shift{11-0};
1566 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1567 InstrItinClass iir, PatFrag opnode> {
1568 // Note: We use the complex addrmode_imm12 rather than just an input
1569 // GPR and a constrained immediate so that we can use this to match
1570 // frame index references and avoid matching constant pool references.
1571 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1572 (ins GPR:$Rt, addrmode_imm12:$addr),
1573 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1574 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1577 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1578 let Inst{19-16} = addr{16-13}; // Rn
1579 let Inst{15-12} = Rt;
1580 let Inst{11-0} = addr{11-0}; // imm12
1582 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1583 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1584 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1587 let shift{4} = 0; // Inst{4} = 0
1588 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1589 let Inst{19-16} = shift{16-13}; // Rn
1590 let Inst{15-12} = Rt;
1591 let Inst{11-0} = shift{11-0};
1595 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1596 InstrItinClass iir, PatFrag opnode> {
1597 // Note: We use the complex addrmode_imm12 rather than just an input
1598 // GPR and a constrained immediate so that we can use this to match
1599 // frame index references and avoid matching constant pool references.
1600 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1601 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1602 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1603 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1606 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1607 let Inst{19-16} = addr{16-13}; // Rn
1608 let Inst{15-12} = Rt;
1609 let Inst{11-0} = addr{11-0}; // imm12
1611 def rs : AI2ldst<0b011, 0, isByte, (outs),
1612 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1613 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1614 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1617 let shift{4} = 0; // Inst{4} = 0
1618 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1619 let Inst{19-16} = shift{16-13}; // Rn
1620 let Inst{15-12} = Rt;
1621 let Inst{11-0} = shift{11-0};
1626 //===----------------------------------------------------------------------===//
1628 //===----------------------------------------------------------------------===//
1630 //===----------------------------------------------------------------------===//
1631 // Miscellaneous Instructions.
1634 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1635 /// the function. The first operand is the ID# for this instruction, the second
1636 /// is the index into the MachineConstantPool that this is, the third is the
1637 /// size in bytes of this constant pool entry.
1638 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1639 def CONSTPOOL_ENTRY :
1640 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1641 i32imm:$size), NoItinerary, []>;
1643 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1644 // from removing one half of the matched pairs. That breaks PEI, which assumes
1645 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1646 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1647 def ADJCALLSTACKUP :
1648 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1649 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1651 def ADJCALLSTACKDOWN :
1652 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1653 [(ARMcallseq_start timm:$amt)]>;
1656 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1657 // (These pseudos use a hand-written selection code).
1658 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1659 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1660 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1662 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1663 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1665 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1666 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1668 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1669 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1671 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1672 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1674 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1675 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1677 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1678 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1680 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1681 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1682 GPR:$set1, GPR:$set2),
1684 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1685 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1687 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1688 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1690 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1691 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1693 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1694 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1698 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1699 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1701 let Inst{27-8} = 0b00110010000011110000;
1702 let Inst{7-0} = imm;
1705 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1706 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1707 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1708 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1709 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1711 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1712 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1717 let Inst{15-12} = Rd;
1718 let Inst{19-16} = Rn;
1719 let Inst{27-20} = 0b01101000;
1720 let Inst{7-4} = 0b1011;
1721 let Inst{11-8} = 0b1111;
1722 let Unpredictable{11-8} = 0b1111;
1725 // The 16-bit operand $val can be used by a debugger to store more information
1726 // about the breakpoint.
1727 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1728 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1730 let Inst{3-0} = val{3-0};
1731 let Inst{19-8} = val{15-4};
1732 let Inst{27-20} = 0b00010010;
1733 let Inst{7-4} = 0b0111;
1736 // Change Processor State
1737 // FIXME: We should use InstAlias to handle the optional operands.
1738 class CPS<dag iops, string asm_ops>
1739 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1740 []>, Requires<[IsARM]> {
1746 let Inst{31-28} = 0b1111;
1747 let Inst{27-20} = 0b00010000;
1748 let Inst{19-18} = imod;
1749 let Inst{17} = M; // Enabled if mode is set;
1750 let Inst{16-9} = 0b00000000;
1751 let Inst{8-6} = iflags;
1753 let Inst{4-0} = mode;
1756 let DecoderMethod = "DecodeCPSInstruction" in {
1758 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1759 "$imod\t$iflags, $mode">;
1760 let mode = 0, M = 0 in
1761 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1763 let imod = 0, iflags = 0, M = 1 in
1764 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1767 // Preload signals the memory system of possible future data/instruction access.
1768 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1770 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1771 !strconcat(opc, "\t$addr"),
1772 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1775 let Inst{31-26} = 0b111101;
1776 let Inst{25} = 0; // 0 for immediate form
1777 let Inst{24} = data;
1778 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1779 let Inst{22} = read;
1780 let Inst{21-20} = 0b01;
1781 let Inst{19-16} = addr{16-13}; // Rn
1782 let Inst{15-12} = 0b1111;
1783 let Inst{11-0} = addr{11-0}; // imm12
1786 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1787 !strconcat(opc, "\t$shift"),
1788 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1790 let Inst{31-26} = 0b111101;
1791 let Inst{25} = 1; // 1 for register form
1792 let Inst{24} = data;
1793 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1794 let Inst{22} = read;
1795 let Inst{21-20} = 0b01;
1796 let Inst{19-16} = shift{16-13}; // Rn
1797 let Inst{15-12} = 0b1111;
1798 let Inst{11-0} = shift{11-0};
1803 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1804 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1805 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1807 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1808 "setend\t$end", []>, Requires<[IsARM]> {
1810 let Inst{31-10} = 0b1111000100000001000000;
1815 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1816 []>, Requires<[IsARM, HasV7]> {
1818 let Inst{27-4} = 0b001100100000111100001111;
1819 let Inst{3-0} = opt;
1823 * A5.4 Permanently UNDEFINED instructions.
1825 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1826 * Other UDF encodings generate SIGILL.
1828 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1830 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1832 * 1101 1110 iiii iiii
1833 * It uses the following encoding:
1834 * 1110 0111 1111 1110 1101 1110 1111 0000
1835 * - In ARM: UDF #60896;
1836 * - In Thumb: UDF #254 followed by a branch-to-self.
1838 let isBarrier = 1, isTerminator = 1 in
1839 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1841 Requires<[IsARM,UseNaClTrap]> {
1842 let Inst = 0xe7fedef0;
1844 let isBarrier = 1, isTerminator = 1 in
1845 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1847 Requires<[IsARM,DontUseNaClTrap]> {
1848 let Inst = 0xe7ffdefe;
1851 // Address computation and loads and stores in PIC mode.
1852 let isNotDuplicable = 1 in {
1853 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1855 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1857 let AddedComplexity = 10 in {
1858 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1860 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1862 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1864 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1866 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1868 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1870 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1872 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1874 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1876 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1878 let AddedComplexity = 10 in {
1879 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1880 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1882 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1883 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1884 addrmodepc:$addr)]>;
1886 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1887 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1889 } // isNotDuplicable = 1
1892 // LEApcrel - Load a pc-relative address into a register without offending the
1894 let neverHasSideEffects = 1, isReMaterializable = 1 in
1895 // The 'adr' mnemonic encodes differently if the label is before or after
1896 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1897 // know until then which form of the instruction will be used.
1898 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1899 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1900 Sched<[WriteALU, ReadALU]> {
1903 let Inst{27-25} = 0b001;
1905 let Inst{23-22} = label{13-12};
1908 let Inst{19-16} = 0b1111;
1909 let Inst{15-12} = Rd;
1910 let Inst{11-0} = label{11-0};
1913 let hasSideEffects = 1 in {
1914 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1917 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1918 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1922 //===----------------------------------------------------------------------===//
1923 // Control Flow Instructions.
1926 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1928 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1929 "bx", "\tlr", [(ARMretflag)]>,
1930 Requires<[IsARM, HasV4T]> {
1931 let Inst{27-0} = 0b0001001011111111111100011110;
1935 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1936 "mov", "\tpc, lr", [(ARMretflag)]>,
1937 Requires<[IsARM, NoV4T]> {
1938 let Inst{27-0} = 0b0001101000001111000000001110;
1942 // Indirect branches
1943 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1945 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1946 [(brind GPR:$dst)]>,
1947 Requires<[IsARM, HasV4T]> {
1949 let Inst{31-4} = 0b1110000100101111111111110001;
1950 let Inst{3-0} = dst;
1953 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1954 "bx", "\t$dst", [/* pattern left blank */]>,
1955 Requires<[IsARM, HasV4T]> {
1957 let Inst{27-4} = 0b000100101111111111110001;
1958 let Inst{3-0} = dst;
1962 // SP is marked as a use to prevent stack-pointer assignments that appear
1963 // immediately before calls from potentially appearing dead.
1965 // FIXME: Do we really need a non-predicated version? If so, it should
1966 // at least be a pseudo instruction expanding to the predicated version
1967 // at MC lowering time.
1968 Defs = [LR], Uses = [SP] in {
1969 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1970 IIC_Br, "bl\t$func",
1971 [(ARMcall tglobaladdr:$func)]>,
1973 let Inst{31-28} = 0b1110;
1975 let Inst{23-0} = func;
1976 let DecoderMethod = "DecodeBranchImmInstruction";
1979 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1980 IIC_Br, "bl", "\t$func",
1981 [(ARMcall_pred tglobaladdr:$func)]>,
1984 let Inst{23-0} = func;
1985 let DecoderMethod = "DecodeBranchImmInstruction";
1989 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1990 IIC_Br, "blx\t$func",
1991 [(ARMcall GPR:$func)]>,
1992 Requires<[IsARM, HasV5T]> {
1994 let Inst{31-4} = 0b1110000100101111111111110011;
1995 let Inst{3-0} = func;
1998 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1999 IIC_Br, "blx", "\t$func",
2000 [(ARMcall_pred GPR:$func)]>,
2001 Requires<[IsARM, HasV5T]> {
2003 let Inst{27-4} = 0b000100101111111111110011;
2004 let Inst{3-0} = func;
2008 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2009 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2010 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2011 Requires<[IsARM, HasV4T]>;
2014 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2015 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2016 Requires<[IsARM, NoV4T]>;
2018 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2019 // return stack predictor.
2020 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2021 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2025 let isBranch = 1, isTerminator = 1 in {
2026 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2027 // a two-value operand where a dag node expects two operands. :(
2028 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2029 IIC_Br, "b", "\t$target",
2030 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2032 let Inst{23-0} = target;
2033 let DecoderMethod = "DecodeBranchImmInstruction";
2036 let isBarrier = 1 in {
2037 // B is "predicable" since it's just a Bcc with an 'always' condition.
2038 let isPredicable = 1 in
2039 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2040 // should be sufficient.
2041 // FIXME: Is B really a Barrier? That doesn't seem right.
2042 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2043 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2045 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2046 def BR_JTr : ARMPseudoInst<(outs),
2047 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2049 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2050 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2051 // into i12 and rs suffixed versions.
2052 def BR_JTm : ARMPseudoInst<(outs),
2053 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2055 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2057 def BR_JTadd : ARMPseudoInst<(outs),
2058 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2060 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2062 } // isNotDuplicable = 1, isIndirectBranch = 1
2068 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2069 "blx\t$target", []>,
2070 Requires<[IsARM, HasV5T]> {
2071 let Inst{31-25} = 0b1111101;
2073 let Inst{23-0} = target{24-1};
2074 let Inst{24} = target{0};
2077 // Branch and Exchange Jazelle
2078 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2079 [/* pattern left blank */]> {
2081 let Inst{23-20} = 0b0010;
2082 let Inst{19-8} = 0xfff;
2083 let Inst{7-4} = 0b0010;
2084 let Inst{3-0} = func;
2089 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2090 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
2092 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
2094 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2096 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2099 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2105 // Secure Monitor Call is a system instruction.
2106 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2107 []>, Requires<[IsARM, HasTrustZone]> {
2109 let Inst{23-4} = 0b01100000000000000111;
2110 let Inst{3-0} = opt;
2113 // Supervisor Call (Software Interrupt)
2114 let isCall = 1, Uses = [SP] in {
2115 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2117 let Inst{23-0} = svc;
2121 // Store Return State
2122 class SRSI<bit wb, string asm>
2123 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2124 NoItinerary, asm, "", []> {
2126 let Inst{31-28} = 0b1111;
2127 let Inst{27-25} = 0b100;
2131 let Inst{19-16} = 0b1101; // SP
2132 let Inst{15-5} = 0b00000101000;
2133 let Inst{4-0} = mode;
2136 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2137 let Inst{24-23} = 0;
2139 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2140 let Inst{24-23} = 0;
2142 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2143 let Inst{24-23} = 0b10;
2145 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2146 let Inst{24-23} = 0b10;
2148 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2149 let Inst{24-23} = 0b01;
2151 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2152 let Inst{24-23} = 0b01;
2154 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2155 let Inst{24-23} = 0b11;
2157 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2158 let Inst{24-23} = 0b11;
2161 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2162 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2164 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2165 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2167 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2168 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2170 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2171 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2173 // Return From Exception
2174 class RFEI<bit wb, string asm>
2175 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2176 NoItinerary, asm, "", []> {
2178 let Inst{31-28} = 0b1111;
2179 let Inst{27-25} = 0b100;
2183 let Inst{19-16} = Rn;
2184 let Inst{15-0} = 0xa00;
2187 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2188 let Inst{24-23} = 0;
2190 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2191 let Inst{24-23} = 0;
2193 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2194 let Inst{24-23} = 0b10;
2196 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2197 let Inst{24-23} = 0b10;
2199 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2200 let Inst{24-23} = 0b01;
2202 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2203 let Inst{24-23} = 0b01;
2205 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2206 let Inst{24-23} = 0b11;
2208 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2209 let Inst{24-23} = 0b11;
2212 //===----------------------------------------------------------------------===//
2213 // Load / Store Instructions.
2219 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2220 UnOpFrag<(load node:$Src)>>;
2221 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2222 UnOpFrag<(zextloadi8 node:$Src)>>;
2223 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2224 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2225 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2226 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2228 // Special LDR for loads from non-pc-relative constpools.
2229 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2230 isReMaterializable = 1, isCodeGenOnly = 1 in
2231 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2232 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2236 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2237 let Inst{19-16} = 0b1111;
2238 let Inst{15-12} = Rt;
2239 let Inst{11-0} = addr{11-0}; // imm12
2242 // Loads with zero extension
2243 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2244 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2245 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2247 // Loads with sign extension
2248 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2249 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2250 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2252 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2253 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2254 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2256 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2258 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2259 (ins addrmode3:$addr), LdMiscFrm,
2260 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2261 []>, Requires<[IsARM, HasV5TE]>;
2265 multiclass AI2_ldridx<bit isByte, string opc,
2266 InstrItinClass iii, InstrItinClass iir> {
2267 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2268 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2269 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2272 let Inst{23} = addr{12};
2273 let Inst{19-16} = addr{16-13};
2274 let Inst{11-0} = addr{11-0};
2275 let DecoderMethod = "DecodeLDRPreImm";
2276 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2279 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2280 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2281 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2284 let Inst{23} = addr{12};
2285 let Inst{19-16} = addr{16-13};
2286 let Inst{11-0} = addr{11-0};
2288 let DecoderMethod = "DecodeLDRPreReg";
2289 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2292 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2293 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2294 IndexModePost, LdFrm, iir,
2295 opc, "\t$Rt, $addr, $offset",
2296 "$addr.base = $Rn_wb", []> {
2302 let Inst{23} = offset{12};
2303 let Inst{19-16} = addr;
2304 let Inst{11-0} = offset{11-0};
2306 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2309 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2310 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2311 IndexModePost, LdFrm, iii,
2312 opc, "\t$Rt, $addr, $offset",
2313 "$addr.base = $Rn_wb", []> {
2319 let Inst{23} = offset{12};
2320 let Inst{19-16} = addr;
2321 let Inst{11-0} = offset{11-0};
2323 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2328 let mayLoad = 1, neverHasSideEffects = 1 in {
2329 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2330 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2331 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2332 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2335 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2336 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2337 (ins addrmode3_pre:$addr), IndexModePre,
2339 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2341 let Inst{23} = addr{8}; // U bit
2342 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2343 let Inst{19-16} = addr{12-9}; // Rn
2344 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2345 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2346 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2347 let DecoderMethod = "DecodeAddrMode3Instruction";
2349 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2350 (ins addr_offset_none:$addr, am3offset:$offset),
2351 IndexModePost, LdMiscFrm, itin,
2352 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2356 let Inst{23} = offset{8}; // U bit
2357 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2358 let Inst{19-16} = addr;
2359 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2360 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2361 let DecoderMethod = "DecodeAddrMode3Instruction";
2365 let mayLoad = 1, neverHasSideEffects = 1 in {
2366 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2367 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2368 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2369 let hasExtraDefRegAllocReq = 1 in {
2370 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2371 (ins addrmode3_pre:$addr), IndexModePre,
2372 LdMiscFrm, IIC_iLoad_d_ru,
2373 "ldrd", "\t$Rt, $Rt2, $addr!",
2374 "$addr.base = $Rn_wb", []> {
2376 let Inst{23} = addr{8}; // U bit
2377 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2378 let Inst{19-16} = addr{12-9}; // Rn
2379 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2380 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2381 let DecoderMethod = "DecodeAddrMode3Instruction";
2382 let AsmMatchConverter = "cvtLdrdPre";
2384 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2385 (ins addr_offset_none:$addr, am3offset:$offset),
2386 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2387 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2388 "$addr.base = $Rn_wb", []> {
2391 let Inst{23} = offset{8}; // U bit
2392 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2393 let Inst{19-16} = addr;
2394 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2395 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2396 let DecoderMethod = "DecodeAddrMode3Instruction";
2398 } // hasExtraDefRegAllocReq = 1
2399 } // mayLoad = 1, neverHasSideEffects = 1
2401 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2402 let mayLoad = 1, neverHasSideEffects = 1 in {
2403 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2404 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2405 IndexModePost, LdFrm, IIC_iLoad_ru,
2406 "ldrt", "\t$Rt, $addr, $offset",
2407 "$addr.base = $Rn_wb", []> {
2413 let Inst{23} = offset{12};
2414 let Inst{21} = 1; // overwrite
2415 let Inst{19-16} = addr;
2416 let Inst{11-5} = offset{11-5};
2418 let Inst{3-0} = offset{3-0};
2419 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2422 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2423 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2424 IndexModePost, LdFrm, IIC_iLoad_ru,
2425 "ldrt", "\t$Rt, $addr, $offset",
2426 "$addr.base = $Rn_wb", []> {
2432 let Inst{23} = offset{12};
2433 let Inst{21} = 1; // overwrite
2434 let Inst{19-16} = addr;
2435 let Inst{11-0} = offset{11-0};
2436 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2439 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2440 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2441 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2442 "ldrbt", "\t$Rt, $addr, $offset",
2443 "$addr.base = $Rn_wb", []> {
2449 let Inst{23} = offset{12};
2450 let Inst{21} = 1; // overwrite
2451 let Inst{19-16} = addr;
2452 let Inst{11-5} = offset{11-5};
2454 let Inst{3-0} = offset{3-0};
2455 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2458 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2459 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2460 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2461 "ldrbt", "\t$Rt, $addr, $offset",
2462 "$addr.base = $Rn_wb", []> {
2468 let Inst{23} = offset{12};
2469 let Inst{21} = 1; // overwrite
2470 let Inst{19-16} = addr;
2471 let Inst{11-0} = offset{11-0};
2472 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2475 multiclass AI3ldrT<bits<4> op, string opc> {
2476 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2477 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2478 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2479 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2481 let Inst{23} = offset{8};
2483 let Inst{11-8} = offset{7-4};
2484 let Inst{3-0} = offset{3-0};
2485 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2487 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2488 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2489 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2490 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2492 let Inst{23} = Rm{4};
2495 let Unpredictable{11-8} = 0b1111;
2496 let Inst{3-0} = Rm{3-0};
2497 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2498 let DecoderMethod = "DecodeLDR";
2502 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2503 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2504 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2509 // Stores with truncate
2510 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2511 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2512 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2515 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2516 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2517 StMiscFrm, IIC_iStore_d_r,
2518 "strd", "\t$Rt, $src2, $addr", []>,
2519 Requires<[IsARM, HasV5TE]> {
2524 multiclass AI2_stridx<bit isByte, string opc,
2525 InstrItinClass iii, InstrItinClass iir> {
2526 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2527 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2529 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2532 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2533 let Inst{19-16} = addr{16-13}; // Rn
2534 let Inst{11-0} = addr{11-0}; // imm12
2535 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2536 let DecoderMethod = "DecodeSTRPreImm";
2539 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2540 (ins GPR:$Rt, ldst_so_reg:$addr),
2541 IndexModePre, StFrm, iir,
2542 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2545 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2546 let Inst{19-16} = addr{16-13}; // Rn
2547 let Inst{11-0} = addr{11-0};
2548 let Inst{4} = 0; // Inst{4} = 0
2549 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2550 let DecoderMethod = "DecodeSTRPreReg";
2552 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2553 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2554 IndexModePost, StFrm, iir,
2555 opc, "\t$Rt, $addr, $offset",
2556 "$addr.base = $Rn_wb", []> {
2562 let Inst{23} = offset{12};
2563 let Inst{19-16} = addr;
2564 let Inst{11-0} = offset{11-0};
2567 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2570 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2571 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2572 IndexModePost, StFrm, iii,
2573 opc, "\t$Rt, $addr, $offset",
2574 "$addr.base = $Rn_wb", []> {
2580 let Inst{23} = offset{12};
2581 let Inst{19-16} = addr;
2582 let Inst{11-0} = offset{11-0};
2584 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2588 let mayStore = 1, neverHasSideEffects = 1 in {
2589 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2590 // IIC_iStore_siu depending on whether it the offset register is shifted.
2591 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2592 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2595 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2596 am2offset_reg:$offset),
2597 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2598 am2offset_reg:$offset)>;
2599 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2600 am2offset_imm:$offset),
2601 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2602 am2offset_imm:$offset)>;
2603 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2604 am2offset_reg:$offset),
2605 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2606 am2offset_reg:$offset)>;
2607 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2608 am2offset_imm:$offset),
2609 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2610 am2offset_imm:$offset)>;
2612 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2613 // put the patterns on the instruction definitions directly as ISel wants
2614 // the address base and offset to be separate operands, not a single
2615 // complex operand like we represent the instructions themselves. The
2616 // pseudos map between the two.
2617 let usesCustomInserter = 1,
2618 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2619 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2620 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2623 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2624 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2625 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2628 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2629 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2630 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2633 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2634 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2635 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2638 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2639 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2640 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2643 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2648 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2649 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2650 StMiscFrm, IIC_iStore_bh_ru,
2651 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2653 let Inst{23} = addr{8}; // U bit
2654 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2655 let Inst{19-16} = addr{12-9}; // Rn
2656 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2657 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2658 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2659 let DecoderMethod = "DecodeAddrMode3Instruction";
2662 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2663 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2664 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2665 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2666 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2667 addr_offset_none:$addr,
2668 am3offset:$offset))]> {
2671 let Inst{23} = offset{8}; // U bit
2672 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2673 let Inst{19-16} = addr;
2674 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2675 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2676 let DecoderMethod = "DecodeAddrMode3Instruction";
2679 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2680 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2681 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2682 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2683 "strd", "\t$Rt, $Rt2, $addr!",
2684 "$addr.base = $Rn_wb", []> {
2686 let Inst{23} = addr{8}; // U bit
2687 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2688 let Inst{19-16} = addr{12-9}; // Rn
2689 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2690 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2691 let DecoderMethod = "DecodeAddrMode3Instruction";
2692 let AsmMatchConverter = "cvtStrdPre";
2695 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2696 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2698 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2699 "strd", "\t$Rt, $Rt2, $addr, $offset",
2700 "$addr.base = $Rn_wb", []> {
2703 let Inst{23} = offset{8}; // U bit
2704 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2705 let Inst{19-16} = addr;
2706 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2707 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2708 let DecoderMethod = "DecodeAddrMode3Instruction";
2710 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2712 // STRT, STRBT, and STRHT
2714 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2715 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2716 IndexModePost, StFrm, IIC_iStore_bh_ru,
2717 "strbt", "\t$Rt, $addr, $offset",
2718 "$addr.base = $Rn_wb", []> {
2724 let Inst{23} = offset{12};
2725 let Inst{21} = 1; // overwrite
2726 let Inst{19-16} = addr;
2727 let Inst{11-5} = offset{11-5};
2729 let Inst{3-0} = offset{3-0};
2730 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2733 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2734 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2735 IndexModePost, StFrm, IIC_iStore_bh_ru,
2736 "strbt", "\t$Rt, $addr, $offset",
2737 "$addr.base = $Rn_wb", []> {
2743 let Inst{23} = offset{12};
2744 let Inst{21} = 1; // overwrite
2745 let Inst{19-16} = addr;
2746 let Inst{11-0} = offset{11-0};
2747 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2750 let mayStore = 1, neverHasSideEffects = 1 in {
2751 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2752 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2753 IndexModePost, StFrm, IIC_iStore_ru,
2754 "strt", "\t$Rt, $addr, $offset",
2755 "$addr.base = $Rn_wb", []> {
2761 let Inst{23} = offset{12};
2762 let Inst{21} = 1; // overwrite
2763 let Inst{19-16} = addr;
2764 let Inst{11-5} = offset{11-5};
2766 let Inst{3-0} = offset{3-0};
2767 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2770 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2771 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2772 IndexModePost, StFrm, IIC_iStore_ru,
2773 "strt", "\t$Rt, $addr, $offset",
2774 "$addr.base = $Rn_wb", []> {
2780 let Inst{23} = offset{12};
2781 let Inst{21} = 1; // overwrite
2782 let Inst{19-16} = addr;
2783 let Inst{11-0} = offset{11-0};
2784 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2789 multiclass AI3strT<bits<4> op, string opc> {
2790 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2791 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2792 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2793 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2795 let Inst{23} = offset{8};
2797 let Inst{11-8} = offset{7-4};
2798 let Inst{3-0} = offset{3-0};
2799 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2801 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2802 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2803 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2804 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2806 let Inst{23} = Rm{4};
2809 let Inst{3-0} = Rm{3-0};
2810 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2815 defm STRHT : AI3strT<0b1011, "strht">;
2818 //===----------------------------------------------------------------------===//
2819 // Load / store multiple Instructions.
2822 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2823 InstrItinClass itin, InstrItinClass itin_upd> {
2824 // IA is the default, so no need for an explicit suffix on the
2825 // mnemonic here. Without it is the canonical spelling.
2827 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2828 IndexModeNone, f, itin,
2829 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2830 let Inst{24-23} = 0b01; // Increment After
2831 let Inst{22} = P_bit;
2832 let Inst{21} = 0; // No writeback
2833 let Inst{20} = L_bit;
2836 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2837 IndexModeUpd, f, itin_upd,
2838 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2839 let Inst{24-23} = 0b01; // Increment After
2840 let Inst{22} = P_bit;
2841 let Inst{21} = 1; // Writeback
2842 let Inst{20} = L_bit;
2844 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2847 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2848 IndexModeNone, f, itin,
2849 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2850 let Inst{24-23} = 0b00; // Decrement After
2851 let Inst{22} = P_bit;
2852 let Inst{21} = 0; // No writeback
2853 let Inst{20} = L_bit;
2856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2857 IndexModeUpd, f, itin_upd,
2858 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2859 let Inst{24-23} = 0b00; // Decrement After
2860 let Inst{22} = P_bit;
2861 let Inst{21} = 1; // Writeback
2862 let Inst{20} = L_bit;
2864 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2867 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2868 IndexModeNone, f, itin,
2869 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2870 let Inst{24-23} = 0b10; // Decrement Before
2871 let Inst{22} = P_bit;
2872 let Inst{21} = 0; // No writeback
2873 let Inst{20} = L_bit;
2876 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2877 IndexModeUpd, f, itin_upd,
2878 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2879 let Inst{24-23} = 0b10; // Decrement Before
2880 let Inst{22} = P_bit;
2881 let Inst{21} = 1; // Writeback
2882 let Inst{20} = L_bit;
2884 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2888 IndexModeNone, f, itin,
2889 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2890 let Inst{24-23} = 0b11; // Increment Before
2891 let Inst{22} = P_bit;
2892 let Inst{21} = 0; // No writeback
2893 let Inst{20} = L_bit;
2896 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2897 IndexModeUpd, f, itin_upd,
2898 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2899 let Inst{24-23} = 0b11; // Increment Before
2900 let Inst{22} = P_bit;
2901 let Inst{21} = 1; // Writeback
2902 let Inst{20} = L_bit;
2904 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2908 let neverHasSideEffects = 1 in {
2910 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2911 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2914 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2915 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2918 } // neverHasSideEffects
2920 // FIXME: remove when we have a way to marking a MI with these properties.
2921 // FIXME: Should pc be an implicit operand like PICADD, etc?
2922 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2923 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2924 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2925 reglist:$regs, variable_ops),
2926 4, IIC_iLoad_mBr, [],
2927 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2928 RegConstraint<"$Rn = $wb">;
2930 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2931 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2934 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2935 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2940 //===----------------------------------------------------------------------===//
2941 // Move Instructions.
2944 let neverHasSideEffects = 1 in
2945 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2946 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2950 let Inst{19-16} = 0b0000;
2951 let Inst{11-4} = 0b00000000;
2954 let Inst{15-12} = Rd;
2957 // A version for the smaller set of tail call registers.
2958 let neverHasSideEffects = 1 in
2959 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2960 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2964 let Inst{11-4} = 0b00000000;
2967 let Inst{15-12} = Rd;
2970 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2971 DPSoRegRegFrm, IIC_iMOVsr,
2972 "mov", "\t$Rd, $src",
2973 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2976 let Inst{15-12} = Rd;
2977 let Inst{19-16} = 0b0000;
2978 let Inst{11-8} = src{11-8};
2980 let Inst{6-5} = src{6-5};
2982 let Inst{3-0} = src{3-0};
2986 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2987 DPSoRegImmFrm, IIC_iMOVsr,
2988 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2992 let Inst{15-12} = Rd;
2993 let Inst{19-16} = 0b0000;
2994 let Inst{11-5} = src{11-5};
2996 let Inst{3-0} = src{3-0};
3000 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3001 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3002 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
3006 let Inst{15-12} = Rd;
3007 let Inst{19-16} = 0b0000;
3008 let Inst{11-0} = imm;
3011 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3012 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3014 "movw", "\t$Rd, $imm",
3015 [(set GPR:$Rd, imm0_65535:$imm)]>,
3016 Requires<[IsARM, HasV6T2]>, UnaryDP {
3019 let Inst{15-12} = Rd;
3020 let Inst{11-0} = imm{11-0};
3021 let Inst{19-16} = imm{15-12};
3024 let DecoderMethod = "DecodeArmMOVTWInstruction";
3027 def : InstAlias<"mov${p} $Rd, $imm",
3028 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3031 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3032 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3034 let Constraints = "$src = $Rd" in {
3035 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3036 (ins GPR:$src, imm0_65535_expr:$imm),
3038 "movt", "\t$Rd, $imm",
3040 (or (and GPR:$src, 0xffff),
3041 lo16AllZero:$imm))]>, UnaryDP,
3042 Requires<[IsARM, HasV6T2]> {
3045 let Inst{15-12} = Rd;
3046 let Inst{11-0} = imm{11-0};
3047 let Inst{19-16} = imm{15-12};
3050 let DecoderMethod = "DecodeArmMOVTWInstruction";
3053 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3054 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3058 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3059 Requires<[IsARM, HasV6T2]>;
3061 let Uses = [CPSR] in
3062 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3063 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3066 // These aren't really mov instructions, but we have to define them this way
3067 // due to flag operands.
3069 let Defs = [CPSR] in {
3070 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3071 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3073 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3074 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3078 //===----------------------------------------------------------------------===//
3079 // Extend Instructions.
3084 def SXTB : AI_ext_rrot<0b01101010,
3085 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3086 def SXTH : AI_ext_rrot<0b01101011,
3087 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3089 def SXTAB : AI_exta_rrot<0b01101010,
3090 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3091 def SXTAH : AI_exta_rrot<0b01101011,
3092 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3094 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3096 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3100 let AddedComplexity = 16 in {
3101 def UXTB : AI_ext_rrot<0b01101110,
3102 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3103 def UXTH : AI_ext_rrot<0b01101111,
3104 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3105 def UXTB16 : AI_ext_rrot<0b01101100,
3106 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3108 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3109 // The transformation should probably be done as a combiner action
3110 // instead so we can include a check for masking back in the upper
3111 // eight bits of the source into the lower eight bits of the result.
3112 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3113 // (UXTB16r_rot GPR:$Src, 3)>;
3114 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3115 (UXTB16 GPR:$Src, 1)>;
3117 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3118 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3119 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3120 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3123 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3124 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3127 def SBFX : I<(outs GPRnopc:$Rd),
3128 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3129 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3130 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3131 Requires<[IsARM, HasV6T2]> {
3136 let Inst{27-21} = 0b0111101;
3137 let Inst{6-4} = 0b101;
3138 let Inst{20-16} = width;
3139 let Inst{15-12} = Rd;
3140 let Inst{11-7} = lsb;
3144 def UBFX : I<(outs GPR:$Rd),
3145 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3146 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3147 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3148 Requires<[IsARM, HasV6T2]> {
3153 let Inst{27-21} = 0b0111111;
3154 let Inst{6-4} = 0b101;
3155 let Inst{20-16} = width;
3156 let Inst{15-12} = Rd;
3157 let Inst{11-7} = lsb;
3161 //===----------------------------------------------------------------------===//
3162 // Arithmetic Instructions.
3165 defm ADD : AsI1_bin_irs<0b0100, "add",
3166 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3167 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3168 defm SUB : AsI1_bin_irs<0b0010, "sub",
3169 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3170 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3172 // ADD and SUB with 's' bit set.
3174 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3175 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3176 // AdjustInstrPostInstrSelection where we determine whether or not to
3177 // set the "s" bit based on CPSR liveness.
3179 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3180 // support for an optional CPSR definition that corresponds to the DAG
3181 // node's second value. We can then eliminate the implicit def of CPSR.
3182 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3183 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3184 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3185 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3187 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3188 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3189 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3190 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3192 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3193 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3194 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3196 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3197 // CPSR and the implicit def of CPSR is not needed.
3198 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3199 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3201 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3202 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3204 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3205 // The assume-no-carry-in form uses the negation of the input since add/sub
3206 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3207 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3209 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3210 (SUBri GPR:$src, so_imm_neg:$imm)>;
3211 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3212 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3214 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3215 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3216 Requires<[IsARM, HasV6T2]>;
3217 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3218 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3219 Requires<[IsARM, HasV6T2]>;
3221 // The with-carry-in form matches bitwise not instead of the negation.
3222 // Effectively, the inverse interpretation of the carry flag already accounts
3223 // for part of the negation.
3224 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3225 (SBCri GPR:$src, so_imm_not:$imm)>;
3226 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3227 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3229 // Note: These are implemented in C++ code, because they have to generate
3230 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3232 // (mul X, 2^n+1) -> (add (X << n), X)
3233 // (mul X, 2^n-1) -> (rsb X, (X << n))
3235 // ARM Arithmetic Instruction
3236 // GPR:$dst = GPR:$a op GPR:$b
3237 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3238 list<dag> pattern = [],
3239 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3240 string asm = "\t$Rd, $Rn, $Rm">
3241 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3245 let Inst{27-20} = op27_20;
3246 let Inst{11-4} = op11_4;
3247 let Inst{19-16} = Rn;
3248 let Inst{15-12} = Rd;
3251 let Unpredictable{11-8} = 0b1111;
3254 // Saturating add/subtract
3256 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3257 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3258 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3259 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3260 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3261 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3262 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3263 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3265 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3266 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3269 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3270 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3271 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3272 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3273 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3274 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3275 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3276 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3277 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3278 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3279 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3280 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3282 // Signed/Unsigned add/subtract
3284 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3285 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3286 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3287 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3288 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3289 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3290 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3291 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3292 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3293 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3294 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3295 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3297 // Signed/Unsigned halving add/subtract
3299 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3300 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3301 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3302 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3303 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3304 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3305 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3306 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3307 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3308 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3309 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3310 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3312 // Unsigned Sum of Absolute Differences [and Accumulate].
3314 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3315 MulFrm /* for convenience */, NoItinerary, "usad8",
3316 "\t$Rd, $Rn, $Rm", []>,
3317 Requires<[IsARM, HasV6]> {
3321 let Inst{27-20} = 0b01111000;
3322 let Inst{15-12} = 0b1111;
3323 let Inst{7-4} = 0b0001;
3324 let Inst{19-16} = Rd;
3325 let Inst{11-8} = Rm;
3328 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3329 MulFrm /* for convenience */, NoItinerary, "usada8",
3330 "\t$Rd, $Rn, $Rm, $Ra", []>,
3331 Requires<[IsARM, HasV6]> {
3336 let Inst{27-20} = 0b01111000;
3337 let Inst{7-4} = 0b0001;
3338 let Inst{19-16} = Rd;
3339 let Inst{15-12} = Ra;
3340 let Inst{11-8} = Rm;
3344 // Signed/Unsigned saturate
3346 def SSAT : AI<(outs GPRnopc:$Rd),
3347 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3348 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3353 let Inst{27-21} = 0b0110101;
3354 let Inst{5-4} = 0b01;
3355 let Inst{20-16} = sat_imm;
3356 let Inst{15-12} = Rd;
3357 let Inst{11-7} = sh{4-0};
3358 let Inst{6} = sh{5};
3362 def SSAT16 : AI<(outs GPRnopc:$Rd),
3363 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3364 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3368 let Inst{27-20} = 0b01101010;
3369 let Inst{11-4} = 0b11110011;
3370 let Inst{15-12} = Rd;
3371 let Inst{19-16} = sat_imm;
3375 def USAT : AI<(outs GPRnopc:$Rd),
3376 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3377 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3382 let Inst{27-21} = 0b0110111;
3383 let Inst{5-4} = 0b01;
3384 let Inst{15-12} = Rd;
3385 let Inst{11-7} = sh{4-0};
3386 let Inst{6} = sh{5};
3387 let Inst{20-16} = sat_imm;
3391 def USAT16 : AI<(outs GPRnopc:$Rd),
3392 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3393 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3397 let Inst{27-20} = 0b01101110;
3398 let Inst{11-4} = 0b11110011;
3399 let Inst{15-12} = Rd;
3400 let Inst{19-16} = sat_imm;
3404 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3405 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3406 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3407 (USAT imm:$pos, GPRnopc:$a, 0)>;
3409 //===----------------------------------------------------------------------===//
3410 // Bitwise Instructions.
3413 defm AND : AsI1_bin_irs<0b0000, "and",
3414 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3415 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3416 defm ORR : AsI1_bin_irs<0b1100, "orr",
3417 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3418 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3419 defm EOR : AsI1_bin_irs<0b0001, "eor",
3420 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3421 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3422 defm BIC : AsI1_bin_irs<0b1110, "bic",
3423 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3424 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3426 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3427 // like in the actual instruction encoding. The complexity of mapping the mask
3428 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3429 // instruction description.
3430 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3431 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3432 "bfc", "\t$Rd, $imm", "$src = $Rd",
3433 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3434 Requires<[IsARM, HasV6T2]> {
3437 let Inst{27-21} = 0b0111110;
3438 let Inst{6-0} = 0b0011111;
3439 let Inst{15-12} = Rd;
3440 let Inst{11-7} = imm{4-0}; // lsb
3441 let Inst{20-16} = imm{9-5}; // msb
3444 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3445 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3446 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3447 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3448 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3449 bf_inv_mask_imm:$imm))]>,
3450 Requires<[IsARM, HasV6T2]> {
3454 let Inst{27-21} = 0b0111110;
3455 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3456 let Inst{15-12} = Rd;
3457 let Inst{11-7} = imm{4-0}; // lsb
3458 let Inst{20-16} = imm{9-5}; // width
3462 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3463 "mvn", "\t$Rd, $Rm",
3464 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3468 let Inst{19-16} = 0b0000;
3469 let Inst{11-4} = 0b00000000;
3470 let Inst{15-12} = Rd;
3473 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3474 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3475 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3479 let Inst{19-16} = 0b0000;
3480 let Inst{15-12} = Rd;
3481 let Inst{11-5} = shift{11-5};
3483 let Inst{3-0} = shift{3-0};
3485 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3486 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3487 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3491 let Inst{19-16} = 0b0000;
3492 let Inst{15-12} = Rd;
3493 let Inst{11-8} = shift{11-8};
3495 let Inst{6-5} = shift{6-5};
3497 let Inst{3-0} = shift{3-0};
3499 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3500 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3501 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3502 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3506 let Inst{19-16} = 0b0000;
3507 let Inst{15-12} = Rd;
3508 let Inst{11-0} = imm;
3511 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3512 (BICri GPR:$src, so_imm_not:$imm)>;
3514 //===----------------------------------------------------------------------===//
3515 // Multiply Instructions.
3517 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3518 string opc, string asm, list<dag> pattern>
3519 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3523 let Inst{19-16} = Rd;
3524 let Inst{11-8} = Rm;
3527 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3528 string opc, string asm, list<dag> pattern>
3529 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3534 let Inst{19-16} = RdHi;
3535 let Inst{15-12} = RdLo;
3536 let Inst{11-8} = Rm;
3539 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3540 string opc, string asm, list<dag> pattern>
3541 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3546 let Inst{19-16} = RdHi;
3547 let Inst{15-12} = RdLo;
3548 let Inst{11-8} = Rm;
3552 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3553 // property. Remove them when it's possible to add those properties
3554 // on an individual MachineInstr, not just an instruction description.
3555 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3556 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3557 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3558 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3559 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3560 Requires<[IsARM, HasV6]> {
3561 let Inst{15-12} = 0b0000;
3562 let Unpredictable{15-12} = 0b1111;
3565 let Constraints = "@earlyclobber $Rd" in
3566 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3567 pred:$p, cc_out:$s),
3569 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3570 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3571 Requires<[IsARM, NoV6, UseMulOps]>;
3574 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3575 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3576 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3577 Requires<[IsARM, HasV6, UseMulOps]> {
3579 let Inst{15-12} = Ra;
3582 let Constraints = "@earlyclobber $Rd" in
3583 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3584 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3586 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3587 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3588 Requires<[IsARM, NoV6]>;
3590 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3591 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3592 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3593 Requires<[IsARM, HasV6T2, UseMulOps]> {
3598 let Inst{19-16} = Rd;
3599 let Inst{15-12} = Ra;
3600 let Inst{11-8} = Rm;
3604 // Extra precision multiplies with low / high results
3605 let neverHasSideEffects = 1 in {
3606 let isCommutable = 1 in {
3607 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3608 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3609 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3610 Requires<[IsARM, HasV6]>;
3612 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3613 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3614 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3615 Requires<[IsARM, HasV6]>;
3617 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3618 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3619 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3621 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3622 Requires<[IsARM, NoV6]>;
3624 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3625 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3627 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3628 Requires<[IsARM, NoV6]>;
3632 // Multiply + accumulate
3633 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3634 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3635 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3636 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3637 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3638 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3639 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3640 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3642 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3643 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3644 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3645 Requires<[IsARM, HasV6]> {
3650 let Inst{19-16} = RdHi;
3651 let Inst{15-12} = RdLo;
3652 let Inst{11-8} = Rm;
3656 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3657 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3658 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3660 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3661 pred:$p, cc_out:$s)>,
3662 Requires<[IsARM, NoV6]>;
3663 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3664 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3666 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3667 pred:$p, cc_out:$s)>,
3668 Requires<[IsARM, NoV6]>;
3671 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3672 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3673 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3675 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3676 Requires<[IsARM, NoV6]>;
3679 } // neverHasSideEffects
3681 // Most significant word multiply
3682 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3683 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3684 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3685 Requires<[IsARM, HasV6]> {
3686 let Inst{15-12} = 0b1111;
3689 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3690 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3691 Requires<[IsARM, HasV6]> {
3692 let Inst{15-12} = 0b1111;
3695 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3696 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3697 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3698 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3699 Requires<[IsARM, HasV6, UseMulOps]>;
3701 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3702 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3703 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3704 Requires<[IsARM, HasV6]>;
3706 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3707 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3708 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3709 Requires<[IsARM, HasV6, UseMulOps]>;
3711 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3712 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3713 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3714 Requires<[IsARM, HasV6]>;
3716 multiclass AI_smul<string opc, PatFrag opnode> {
3717 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3718 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3719 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3720 (sext_inreg GPR:$Rm, i16)))]>,
3721 Requires<[IsARM, HasV5TE]>;
3723 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3724 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3725 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3726 (sra GPR:$Rm, (i32 16))))]>,
3727 Requires<[IsARM, HasV5TE]>;
3729 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3730 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3731 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3732 (sext_inreg GPR:$Rm, i16)))]>,
3733 Requires<[IsARM, HasV5TE]>;
3735 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3736 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3737 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3738 (sra GPR:$Rm, (i32 16))))]>,
3739 Requires<[IsARM, HasV5TE]>;
3741 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3742 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3743 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3744 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3745 Requires<[IsARM, HasV5TE]>;
3747 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3748 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3749 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3750 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3751 Requires<[IsARM, HasV5TE]>;
3755 multiclass AI_smla<string opc, PatFrag opnode> {
3756 let DecoderMethod = "DecodeSMLAInstruction" in {
3757 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3758 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3759 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3760 [(set GPRnopc:$Rd, (add GPR:$Ra,
3761 (opnode (sext_inreg GPRnopc:$Rn, i16),
3762 (sext_inreg GPRnopc:$Rm, i16))))]>,
3763 Requires<[IsARM, HasV5TE, UseMulOps]>;
3765 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3766 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3767 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3769 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3770 (sra GPRnopc:$Rm, (i32 16)))))]>,
3771 Requires<[IsARM, HasV5TE, UseMulOps]>;
3773 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3774 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3775 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3777 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3778 (sext_inreg GPRnopc:$Rm, i16))))]>,
3779 Requires<[IsARM, HasV5TE, UseMulOps]>;
3781 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3782 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3783 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3785 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3786 (sra GPRnopc:$Rm, (i32 16)))))]>,
3787 Requires<[IsARM, HasV5TE, UseMulOps]>;
3789 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3790 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3791 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3793 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3794 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3795 Requires<[IsARM, HasV5TE, UseMulOps]>;
3797 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3798 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3799 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3801 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3802 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3803 Requires<[IsARM, HasV5TE, UseMulOps]>;
3807 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3808 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3810 // Halfword multiply accumulate long: SMLAL<x><y>.
3811 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3812 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3813 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3814 Requires<[IsARM, HasV5TE]>;
3816 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3817 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3818 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3819 Requires<[IsARM, HasV5TE]>;
3821 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3822 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3823 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3824 Requires<[IsARM, HasV5TE]>;
3826 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3828 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3829 Requires<[IsARM, HasV5TE]>;
3831 // Helper class for AI_smld.
3832 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3833 InstrItinClass itin, string opc, string asm>
3834 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3837 let Inst{27-23} = 0b01110;
3838 let Inst{22} = long;
3839 let Inst{21-20} = 0b00;
3840 let Inst{11-8} = Rm;
3847 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3848 InstrItinClass itin, string opc, string asm>
3849 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3851 let Inst{15-12} = 0b1111;
3852 let Inst{19-16} = Rd;
3854 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3855 InstrItinClass itin, string opc, string asm>
3856 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3859 let Inst{19-16} = Rd;
3860 let Inst{15-12} = Ra;
3862 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3863 InstrItinClass itin, string opc, string asm>
3864 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3867 let Inst{19-16} = RdHi;
3868 let Inst{15-12} = RdLo;
3871 multiclass AI_smld<bit sub, string opc> {
3873 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3874 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3875 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3877 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3878 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3879 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3881 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3882 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3883 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3885 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3886 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3887 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3891 defm SMLA : AI_smld<0, "smla">;
3892 defm SMLS : AI_smld<1, "smls">;
3894 multiclass AI_sdml<bit sub, string opc> {
3896 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3897 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3898 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3899 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3902 defm SMUA : AI_sdml<0, "smua">;
3903 defm SMUS : AI_sdml<1, "smus">;
3905 //===----------------------------------------------------------------------===//
3906 // Division Instructions (ARMv7-A with virtualization extension)
3908 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3909 "sdiv", "\t$Rd, $Rn, $Rm",
3910 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3911 Requires<[IsARM, HasDivideInARM]>;
3913 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3914 "udiv", "\t$Rd, $Rn, $Rm",
3915 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3916 Requires<[IsARM, HasDivideInARM]>;
3918 //===----------------------------------------------------------------------===//
3919 // Misc. Arithmetic Instructions.
3922 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3923 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3924 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3927 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3928 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3929 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3930 Requires<[IsARM, HasV6T2]>,
3933 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3934 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3935 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3938 let AddedComplexity = 5 in
3939 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3940 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3941 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3942 Requires<[IsARM, HasV6]>,
3945 let AddedComplexity = 5 in
3946 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3947 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3948 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3949 Requires<[IsARM, HasV6]>,
3952 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3953 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3956 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3957 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3958 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3959 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3960 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3962 Requires<[IsARM, HasV6]>,
3963 Sched<[WriteALUsi, ReadALU]>;
3965 // Alternate cases for PKHBT where identities eliminate some nodes.
3966 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3967 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3968 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3969 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3971 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3972 // will match the pattern below.
3973 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3974 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3975 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3976 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3977 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3979 Requires<[IsARM, HasV6]>,
3980 Sched<[WriteALUsi, ReadALU]>;
3982 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3983 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3984 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3985 (srl GPRnopc:$src2, imm16_31:$sh)),
3986 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3987 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3988 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3989 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3991 //===----------------------------------------------------------------------===//
3992 // Comparison Instructions...
3995 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3996 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3997 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3999 // ARMcmpZ can re-use the above instruction definitions.
4000 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4001 (CMPri GPR:$src, so_imm:$imm)>;
4002 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4003 (CMPrr GPR:$src, GPR:$rhs)>;
4004 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4005 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4006 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4007 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4009 // CMN register-integer
4010 let isCompare = 1, Defs = [CPSR] in {
4011 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4012 "cmn", "\t$Rn, $imm",
4013 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
4018 let Inst{19-16} = Rn;
4019 let Inst{15-12} = 0b0000;
4020 let Inst{11-0} = imm;
4022 let Unpredictable{15-12} = 0b1111;
4025 // CMN register-register/shift
4026 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4027 "cmn", "\t$Rn, $Rm",
4028 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4029 GPR:$Rn, GPR:$Rm)]> {
4032 let isCommutable = 1;
4035 let Inst{19-16} = Rn;
4036 let Inst{15-12} = 0b0000;
4037 let Inst{11-4} = 0b00000000;
4040 let Unpredictable{15-12} = 0b1111;
4043 def CMNzrsi : AI1<0b1011, (outs),
4044 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4045 "cmn", "\t$Rn, $shift",
4046 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4047 GPR:$Rn, so_reg_imm:$shift)]> {
4052 let Inst{19-16} = Rn;
4053 let Inst{15-12} = 0b0000;
4054 let Inst{11-5} = shift{11-5};
4056 let Inst{3-0} = shift{3-0};
4058 let Unpredictable{15-12} = 0b1111;
4061 def CMNzrsr : AI1<0b1011, (outs),
4062 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4063 "cmn", "\t$Rn, $shift",
4064 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4065 GPRnopc:$Rn, so_reg_reg:$shift)]> {
4070 let Inst{19-16} = Rn;
4071 let Inst{15-12} = 0b0000;
4072 let Inst{11-8} = shift{11-8};
4074 let Inst{6-5} = shift{6-5};
4076 let Inst{3-0} = shift{3-0};
4078 let Unpredictable{15-12} = 0b1111;
4083 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4084 (CMNri GPR:$src, so_imm_neg:$imm)>;
4086 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4087 (CMNri GPR:$src, so_imm_neg:$imm)>;
4089 // Note that TST/TEQ don't set all the same flags that CMP does!
4090 defm TST : AI1_cmp_irs<0b1000, "tst",
4091 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4092 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4093 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4094 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4095 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4097 // Pseudo i64 compares for some floating point compares.
4098 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4100 def BCCi64 : PseudoInst<(outs),
4101 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4103 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4105 def BCCZi64 : PseudoInst<(outs),
4106 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4107 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4108 } // usesCustomInserter
4111 // Conditional moves
4112 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4113 // a two-value operand where a dag node expects two operands. :(
4114 let neverHasSideEffects = 1 in {
4116 let isCommutable = 1, isSelect = 1 in
4117 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4119 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4120 RegConstraint<"$false = $Rd">;
4122 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4123 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4125 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4126 imm:$cc, CCR:$ccr))*/]>,
4127 RegConstraint<"$false = $Rd">;
4128 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4129 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4131 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4132 imm:$cc, CCR:$ccr))*/]>,
4133 RegConstraint<"$false = $Rd">;
4136 let isMoveImm = 1 in
4137 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4138 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4141 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4143 let isMoveImm = 1 in
4144 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4145 (ins GPR:$false, so_imm:$imm, pred:$p),
4147 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4148 RegConstraint<"$false = $Rd">;
4150 // Two instruction predicate mov immediate.
4151 let isMoveImm = 1 in
4152 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4153 (ins GPR:$false, i32imm:$src, pred:$p),
4154 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4156 let isMoveImm = 1 in
4157 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4158 (ins GPR:$false, so_imm:$imm, pred:$p),
4160 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4161 RegConstraint<"$false = $Rd">;
4163 } // neverHasSideEffects
4166 //===----------------------------------------------------------------------===//
4167 // Atomic operations intrinsics
4170 def MemBarrierOptOperand : AsmOperandClass {
4171 let Name = "MemBarrierOpt";
4172 let ParserMethod = "parseMemBarrierOptOperand";
4174 def memb_opt : Operand<i32> {
4175 let PrintMethod = "printMemBOption";
4176 let ParserMatchClass = MemBarrierOptOperand;
4177 let DecoderMethod = "DecodeMemBarrierOption";
4180 // memory barriers protect the atomic sequences
4181 let hasSideEffects = 1 in {
4182 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4183 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4184 Requires<[IsARM, HasDB]> {
4186 let Inst{31-4} = 0xf57ff05;
4187 let Inst{3-0} = opt;
4191 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4192 "dsb", "\t$opt", []>,
4193 Requires<[IsARM, HasDB]> {
4195 let Inst{31-4} = 0xf57ff04;
4196 let Inst{3-0} = opt;
4199 // ISB has only full system option
4200 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4201 "isb", "\t$opt", []>,
4202 Requires<[IsARM, HasDB]> {
4204 let Inst{31-4} = 0xf57ff06;
4205 let Inst{3-0} = opt;
4208 // Pseudo instruction that combines movs + predicated rsbmi
4209 // to implement integer ABS
4210 let usesCustomInserter = 1, Defs = [CPSR] in
4211 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4213 let usesCustomInserter = 1 in {
4214 let Defs = [CPSR] in {
4215 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4216 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4217 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4218 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4219 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4220 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4221 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4222 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4223 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4224 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4225 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4226 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4227 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4228 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4229 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4230 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4231 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4232 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4233 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4234 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4235 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4236 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4237 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4238 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4239 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4240 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4241 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4242 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4243 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4244 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4245 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4246 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4247 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4248 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4249 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4250 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4251 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4252 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4253 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4254 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4255 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4256 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4257 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4258 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4259 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4260 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4261 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4262 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4263 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4264 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4265 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4266 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4267 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4268 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4269 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4270 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4271 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4272 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4273 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4274 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4275 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4277 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4278 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4279 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4280 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4281 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4282 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4283 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4284 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4285 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4286 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4287 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4289 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4290 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4292 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4293 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4294 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4295 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4296 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4297 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4298 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4299 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4301 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4302 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4304 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4306 def ATOMIC_SWAP_I8 : PseudoInst<
4307 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4308 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4309 def ATOMIC_SWAP_I16 : PseudoInst<
4310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4311 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4312 def ATOMIC_SWAP_I32 : PseudoInst<
4313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4314 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4316 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4318 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4319 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4321 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4322 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4324 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4328 let usesCustomInserter = 1 in {
4329 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4330 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4332 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4335 let mayLoad = 1 in {
4336 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4338 "ldrexb", "\t$Rt, $addr", []>;
4339 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4340 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4341 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4342 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4343 let hasExtraDefRegAllocReq = 1 in
4344 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4345 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4346 let DecoderMethod = "DecodeDoubleRegLoad";
4350 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4351 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4352 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4353 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4354 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4355 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4356 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4357 let hasExtraSrcRegAllocReq = 1 in
4358 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4359 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4360 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4361 let DecoderMethod = "DecodeDoubleRegStore";
4366 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4367 Requires<[IsARM, HasV7]> {
4368 let Inst{31-0} = 0b11110101011111111111000000011111;
4371 // SWP/SWPB are deprecated in V6/V7.
4372 let mayLoad = 1, mayStore = 1 in {
4373 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4374 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4375 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4376 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4379 //===----------------------------------------------------------------------===//
4380 // Coprocessor Instructions.
4383 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4384 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4385 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4386 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4387 imm:$CRm, imm:$opc2)]> {
4395 let Inst{3-0} = CRm;
4397 let Inst{7-5} = opc2;
4398 let Inst{11-8} = cop;
4399 let Inst{15-12} = CRd;
4400 let Inst{19-16} = CRn;
4401 let Inst{23-20} = opc1;
4404 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4405 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4406 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4407 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4408 imm:$CRm, imm:$opc2)]> {
4409 let Inst{31-28} = 0b1111;
4417 let Inst{3-0} = CRm;
4419 let Inst{7-5} = opc2;
4420 let Inst{11-8} = cop;
4421 let Inst{15-12} = CRd;
4422 let Inst{19-16} = CRn;
4423 let Inst{23-20} = opc1;
4426 class ACI<dag oops, dag iops, string opc, string asm,
4427 IndexMode im = IndexModeNone>
4428 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4430 let Inst{27-25} = 0b110;
4432 class ACInoP<dag oops, dag iops, string opc, string asm,
4433 IndexMode im = IndexModeNone>
4434 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4436 let Inst{31-28} = 0b1111;
4437 let Inst{27-25} = 0b110;
4439 multiclass LdStCop<bit load, bit Dbit, string asm> {
4440 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4441 asm, "\t$cop, $CRd, $addr"> {
4445 let Inst{24} = 1; // P = 1
4446 let Inst{23} = addr{8};
4447 let Inst{22} = Dbit;
4448 let Inst{21} = 0; // W = 0
4449 let Inst{20} = load;
4450 let Inst{19-16} = addr{12-9};
4451 let Inst{15-12} = CRd;
4452 let Inst{11-8} = cop;
4453 let Inst{7-0} = addr{7-0};
4454 let DecoderMethod = "DecodeCopMemInstruction";
4456 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4457 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4461 let Inst{24} = 1; // P = 1
4462 let Inst{23} = addr{8};
4463 let Inst{22} = Dbit;
4464 let Inst{21} = 1; // W = 1
4465 let Inst{20} = load;
4466 let Inst{19-16} = addr{12-9};
4467 let Inst{15-12} = CRd;
4468 let Inst{11-8} = cop;
4469 let Inst{7-0} = addr{7-0};
4470 let DecoderMethod = "DecodeCopMemInstruction";
4472 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4473 postidx_imm8s4:$offset),
4474 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4479 let Inst{24} = 0; // P = 0
4480 let Inst{23} = offset{8};
4481 let Inst{22} = Dbit;
4482 let Inst{21} = 1; // W = 1
4483 let Inst{20} = load;
4484 let Inst{19-16} = addr;
4485 let Inst{15-12} = CRd;
4486 let Inst{11-8} = cop;
4487 let Inst{7-0} = offset{7-0};
4488 let DecoderMethod = "DecodeCopMemInstruction";
4490 def _OPTION : ACI<(outs),
4491 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4492 coproc_option_imm:$option),
4493 asm, "\t$cop, $CRd, $addr, $option"> {
4498 let Inst{24} = 0; // P = 0
4499 let Inst{23} = 1; // U = 1
4500 let Inst{22} = Dbit;
4501 let Inst{21} = 0; // W = 0
4502 let Inst{20} = load;
4503 let Inst{19-16} = addr;
4504 let Inst{15-12} = CRd;
4505 let Inst{11-8} = cop;
4506 let Inst{7-0} = option;
4507 let DecoderMethod = "DecodeCopMemInstruction";
4510 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4511 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4512 asm, "\t$cop, $CRd, $addr"> {
4516 let Inst{24} = 1; // P = 1
4517 let Inst{23} = addr{8};
4518 let Inst{22} = Dbit;
4519 let Inst{21} = 0; // W = 0
4520 let Inst{20} = load;
4521 let Inst{19-16} = addr{12-9};
4522 let Inst{15-12} = CRd;
4523 let Inst{11-8} = cop;
4524 let Inst{7-0} = addr{7-0};
4525 let DecoderMethod = "DecodeCopMemInstruction";
4527 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4528 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4532 let Inst{24} = 1; // P = 1
4533 let Inst{23} = addr{8};
4534 let Inst{22} = Dbit;
4535 let Inst{21} = 1; // W = 1
4536 let Inst{20} = load;
4537 let Inst{19-16} = addr{12-9};
4538 let Inst{15-12} = CRd;
4539 let Inst{11-8} = cop;
4540 let Inst{7-0} = addr{7-0};
4541 let DecoderMethod = "DecodeCopMemInstruction";
4543 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4544 postidx_imm8s4:$offset),
4545 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4550 let Inst{24} = 0; // P = 0
4551 let Inst{23} = offset{8};
4552 let Inst{22} = Dbit;
4553 let Inst{21} = 1; // W = 1
4554 let Inst{20} = load;
4555 let Inst{19-16} = addr;
4556 let Inst{15-12} = CRd;
4557 let Inst{11-8} = cop;
4558 let Inst{7-0} = offset{7-0};
4559 let DecoderMethod = "DecodeCopMemInstruction";
4561 def _OPTION : ACInoP<(outs),
4562 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4563 coproc_option_imm:$option),
4564 asm, "\t$cop, $CRd, $addr, $option"> {
4569 let Inst{24} = 0; // P = 0
4570 let Inst{23} = 1; // U = 1
4571 let Inst{22} = Dbit;
4572 let Inst{21} = 0; // W = 0
4573 let Inst{20} = load;
4574 let Inst{19-16} = addr;
4575 let Inst{15-12} = CRd;
4576 let Inst{11-8} = cop;
4577 let Inst{7-0} = option;
4578 let DecoderMethod = "DecodeCopMemInstruction";
4582 defm LDC : LdStCop <1, 0, "ldc">;
4583 defm LDCL : LdStCop <1, 1, "ldcl">;
4584 defm STC : LdStCop <0, 0, "stc">;
4585 defm STCL : LdStCop <0, 1, "stcl">;
4586 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4587 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4588 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4589 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4591 //===----------------------------------------------------------------------===//
4592 // Move between coprocessor and ARM core register.
4595 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4597 : ABI<0b1110, oops, iops, NoItinerary, opc,
4598 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4599 let Inst{20} = direction;
4609 let Inst{15-12} = Rt;
4610 let Inst{11-8} = cop;
4611 let Inst{23-21} = opc1;
4612 let Inst{7-5} = opc2;
4613 let Inst{3-0} = CRm;
4614 let Inst{19-16} = CRn;
4617 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4619 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4620 c_imm:$CRm, imm0_7:$opc2),
4621 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4622 imm:$CRm, imm:$opc2)]>;
4623 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4624 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4625 c_imm:$CRm, 0, pred:$p)>;
4626 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4628 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4630 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4631 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4632 c_imm:$CRm, 0, pred:$p)>;
4634 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4635 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4637 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4639 : ABXI<0b1110, oops, iops, NoItinerary,
4640 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4641 let Inst{31-28} = 0b1111;
4642 let Inst{20} = direction;
4652 let Inst{15-12} = Rt;
4653 let Inst{11-8} = cop;
4654 let Inst{23-21} = opc1;
4655 let Inst{7-5} = opc2;
4656 let Inst{3-0} = CRm;
4657 let Inst{19-16} = CRn;
4660 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4662 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4663 c_imm:$CRm, imm0_7:$opc2),
4664 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4665 imm:$CRm, imm:$opc2)]>;
4666 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4667 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4669 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4671 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4673 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4674 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4677 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4678 imm:$CRm, imm:$opc2),
4679 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4681 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4682 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4683 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4684 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4685 let Inst{23-21} = 0b010;
4686 let Inst{20} = direction;
4694 let Inst{15-12} = Rt;
4695 let Inst{19-16} = Rt2;
4696 let Inst{11-8} = cop;
4697 let Inst{7-4} = opc1;
4698 let Inst{3-0} = CRm;
4701 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4702 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4703 GPRnopc:$Rt2, imm:$CRm)]>;
4704 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4706 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4707 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4708 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4709 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4710 let Inst{31-28} = 0b1111;
4711 let Inst{23-21} = 0b010;
4712 let Inst{20} = direction;
4720 let Inst{15-12} = Rt;
4721 let Inst{19-16} = Rt2;
4722 let Inst{11-8} = cop;
4723 let Inst{7-4} = opc1;
4724 let Inst{3-0} = CRm;
4726 let DecoderMethod = "DecodeMRRC2";
4729 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4730 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4731 GPRnopc:$Rt2, imm:$CRm)]>;
4732 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4734 //===----------------------------------------------------------------------===//
4735 // Move between special register and ARM core register
4738 // Move to ARM core register from Special Register
4739 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4740 "mrs", "\t$Rd, apsr", []> {
4742 let Inst{23-16} = 0b00001111;
4743 let Unpredictable{19-17} = 0b111;
4745 let Inst{15-12} = Rd;
4747 let Inst{11-0} = 0b000000000000;
4748 let Unpredictable{11-0} = 0b110100001111;
4751 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4754 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4755 // section B9.3.9, with the R bit set to 1.
4756 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4757 "mrs", "\t$Rd, spsr", []> {
4759 let Inst{23-16} = 0b01001111;
4760 let Unpredictable{19-16} = 0b1111;
4762 let Inst{15-12} = Rd;
4764 let Inst{11-0} = 0b000000000000;
4765 let Unpredictable{11-0} = 0b110100001111;
4768 // Move from ARM core register to Special Register
4770 // No need to have both system and application versions, the encodings are the
4771 // same and the assembly parser has no way to distinguish between them. The mask
4772 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4773 // the mask with the fields to be accessed in the special register.
4774 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4775 "msr", "\t$mask, $Rn", []> {
4780 let Inst{22} = mask{4}; // R bit
4781 let Inst{21-20} = 0b10;
4782 let Inst{19-16} = mask{3-0};
4783 let Inst{15-12} = 0b1111;
4784 let Inst{11-4} = 0b00000000;
4788 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4789 "msr", "\t$mask, $a", []> {
4794 let Inst{22} = mask{4}; // R bit
4795 let Inst{21-20} = 0b10;
4796 let Inst{19-16} = mask{3-0};
4797 let Inst{15-12} = 0b1111;
4801 //===----------------------------------------------------------------------===//
4805 // __aeabi_read_tp preserves the registers r1-r3.
4806 // This is a pseudo inst so that we can get the encoding right,
4807 // complete with fixup for the aeabi_read_tp function.
4809 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4810 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4811 [(set R0, ARMthread_pointer)]>;
4814 //===----------------------------------------------------------------------===//
4815 // SJLJ Exception handling intrinsics
4816 // eh_sjlj_setjmp() is an instruction sequence to store the return
4817 // address and save #0 in R0 for the non-longjmp case.
4818 // Since by its nature we may be coming from some other function to get
4819 // here, and we're using the stack frame for the containing function to
4820 // save/restore registers, we can't keep anything live in regs across
4821 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4822 // when we get here from a longjmp(). We force everything out of registers
4823 // except for our own input by listing the relevant registers in Defs. By
4824 // doing so, we also cause the prologue/epilogue code to actively preserve
4825 // all of the callee-saved resgisters, which is exactly what we want.
4826 // A constant value is passed in $val, and we use the location as a scratch.
4828 // These are pseudo-instructions and are lowered to individual MC-insts, so
4829 // no encoding information is necessary.
4831 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4832 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4833 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4834 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4836 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4837 Requires<[IsARM, HasVFP2]>;
4841 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4842 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4843 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4845 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4846 Requires<[IsARM, NoVFP]>;
4849 // FIXME: Non-IOS version(s)
4850 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4851 Defs = [ R7, LR, SP ] in {
4852 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4854 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4855 Requires<[IsARM, IsIOS]>;
4858 // eh.sjlj.dispatchsetup pseudo-instruction.
4859 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4860 // the pseudo is expanded (which happens before any passes that need the
4861 // instruction size).
4862 let isBarrier = 1 in
4863 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4866 //===----------------------------------------------------------------------===//
4867 // Non-Instruction Patterns
4870 // ARMv4 indirect branch using (MOVr PC, dst)
4871 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4872 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4873 4, IIC_Br, [(brind GPR:$dst)],
4874 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4875 Requires<[IsARM, NoV4T]>;
4877 // Large immediate handling.
4879 // 32-bit immediate using two piece so_imms or movw + movt.
4880 // This is a single pseudo instruction, the benefit is that it can be remat'd
4881 // as a single unit instead of having to handle reg inputs.
4882 // FIXME: Remove this when we can do generalized remat.
4883 let isReMaterializable = 1, isMoveImm = 1 in
4884 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4885 [(set GPR:$dst, (arm_i32imm:$src))]>,
4888 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4889 // It also makes it possible to rematerialize the instructions.
4890 // FIXME: Remove this when we can do generalized remat and when machine licm
4891 // can properly the instructions.
4892 let isReMaterializable = 1 in {
4893 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4895 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4896 Requires<[IsARM, UseMovt]>;
4898 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4900 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4901 Requires<[IsARM, UseMovt]>;
4903 let AddedComplexity = 10 in
4904 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4906 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4907 Requires<[IsARM, UseMovt]>;
4908 } // isReMaterializable
4910 // ConstantPool, GlobalAddress, and JumpTable
4911 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4912 Requires<[IsARM, DontUseMovt]>;
4913 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4914 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4915 Requires<[IsARM, UseMovt]>;
4916 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4917 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4919 // TODO: add,sub,and, 3-instr forms?
4921 // Tail calls. These patterns also apply to Thumb mode.
4922 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4923 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4924 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4927 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4928 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4929 (BMOVPCB_CALL texternalsym:$func)>;
4931 // zextload i1 -> zextload i8
4932 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4933 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4935 // extload -> zextload
4936 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4937 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4938 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4939 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4941 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4943 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4944 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4947 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4948 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4949 (SMULBB GPR:$a, GPR:$b)>;
4950 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4951 (SMULBB GPR:$a, GPR:$b)>;
4952 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4953 (sra GPR:$b, (i32 16))),
4954 (SMULBT GPR:$a, GPR:$b)>;
4955 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4956 (SMULBT GPR:$a, GPR:$b)>;
4957 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4958 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4959 (SMULTB GPR:$a, GPR:$b)>;
4960 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4961 (SMULTB GPR:$a, GPR:$b)>;
4962 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4964 (SMULWB GPR:$a, GPR:$b)>;
4965 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4966 (SMULWB GPR:$a, GPR:$b)>;
4968 def : ARMV5MOPat<(add GPR:$acc,
4969 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4970 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4971 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4972 def : ARMV5MOPat<(add GPR:$acc,
4973 (mul sext_16_node:$a, sext_16_node:$b)),
4974 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4975 def : ARMV5MOPat<(add GPR:$acc,
4976 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4977 (sra GPR:$b, (i32 16)))),
4978 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4979 def : ARMV5MOPat<(add GPR:$acc,
4980 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4981 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4982 def : ARMV5MOPat<(add GPR:$acc,
4983 (mul (sra GPR:$a, (i32 16)),
4984 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4985 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4986 def : ARMV5MOPat<(add GPR:$acc,
4987 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4988 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4989 def : ARMV5MOPat<(add GPR:$acc,
4990 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4992 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4993 def : ARMV5MOPat<(add GPR:$acc,
4994 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4995 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4998 // Pre-v7 uses MCR for synchronization barriers.
4999 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5000 Requires<[IsARM, HasV6]>;
5002 // SXT/UXT with no rotate
5003 let AddedComplexity = 16 in {
5004 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5005 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5006 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5007 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5008 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5009 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5010 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5013 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5014 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5016 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5017 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5018 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5019 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5021 // Atomic load/store patterns
5022 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5023 (LDRBrs ldst_so_reg:$src)>;
5024 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5025 (LDRBi12 addrmode_imm12:$src)>;
5026 def : ARMPat<(atomic_load_16 addrmode3:$src),
5027 (LDRH addrmode3:$src)>;
5028 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5029 (LDRrs ldst_so_reg:$src)>;
5030 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5031 (LDRi12 addrmode_imm12:$src)>;
5032 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5033 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5034 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5035 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5036 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5037 (STRH GPR:$val, addrmode3:$ptr)>;
5038 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5039 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5040 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5041 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5044 //===----------------------------------------------------------------------===//
5048 include "ARMInstrThumb.td"
5050 //===----------------------------------------------------------------------===//
5054 include "ARMInstrThumb2.td"
5056 //===----------------------------------------------------------------------===//
5057 // Floating Point Support
5060 include "ARMInstrVFP.td"
5062 //===----------------------------------------------------------------------===//
5063 // Advanced SIMD (NEON) Support
5066 include "ARMInstrNEON.td"
5068 //===----------------------------------------------------------------------===//
5069 // Assembler aliases
5073 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5074 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5075 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5077 // System instructions
5078 def : MnemonicAlias<"swi", "svc">;
5080 // Load / Store Multiple
5081 def : MnemonicAlias<"ldmfd", "ldm">;
5082 def : MnemonicAlias<"ldmia", "ldm">;
5083 def : MnemonicAlias<"ldmea", "ldmdb">;
5084 def : MnemonicAlias<"stmfd", "stmdb">;
5085 def : MnemonicAlias<"stmia", "stm">;
5086 def : MnemonicAlias<"stmea", "stm">;
5088 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5089 // shift amount is zero (i.e., unspecified).
5090 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5091 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5092 Requires<[IsARM, HasV6]>;
5093 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5094 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5095 Requires<[IsARM, HasV6]>;
5097 // PUSH/POP aliases for STM/LDM
5098 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5099 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5101 // SSAT/USAT optional shift operand.
5102 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5103 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5104 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5105 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5108 // Extend instruction optional rotate operand.
5109 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5110 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5111 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5112 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5113 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5114 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5115 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5116 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5117 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5118 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5119 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5120 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5122 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5123 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5124 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5125 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5126 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5127 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5128 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5129 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5130 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5131 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5132 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5133 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5137 def : MnemonicAlias<"rfefa", "rfeda">;
5138 def : MnemonicAlias<"rfeea", "rfedb">;
5139 def : MnemonicAlias<"rfefd", "rfeia">;
5140 def : MnemonicAlias<"rfeed", "rfeib">;
5141 def : MnemonicAlias<"rfe", "rfeia">;
5144 def : MnemonicAlias<"srsfa", "srsda">;
5145 def : MnemonicAlias<"srsea", "srsdb">;
5146 def : MnemonicAlias<"srsfd", "srsia">;
5147 def : MnemonicAlias<"srsed", "srsib">;
5148 def : MnemonicAlias<"srs", "srsia">;
5151 def : MnemonicAlias<"qsubaddx", "qsax">;
5153 def : MnemonicAlias<"saddsubx", "sasx">;
5154 // SHASX == SHADDSUBX
5155 def : MnemonicAlias<"shaddsubx", "shasx">;
5156 // SHSAX == SHSUBADDX
5157 def : MnemonicAlias<"shsubaddx", "shsax">;
5159 def : MnemonicAlias<"ssubaddx", "ssax">;
5161 def : MnemonicAlias<"uaddsubx", "uasx">;
5162 // UHASX == UHADDSUBX
5163 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5164 // UHSAX == UHSUBADDX
5165 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5166 // UQASX == UQADDSUBX
5167 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5168 // UQSAX == UQSUBADDX
5169 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5171 def : MnemonicAlias<"usubaddx", "usax">;
5173 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5175 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5176 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5177 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5178 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5179 // Same for AND <--> BIC
5180 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5181 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5182 pred:$p, cc_out:$s)>;
5183 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5184 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5185 pred:$p, cc_out:$s)>;
5186 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5187 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5188 pred:$p, cc_out:$s)>;
5189 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5190 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5191 pred:$p, cc_out:$s)>;
5193 // Likewise, "add Rd, so_imm_neg" -> sub
5194 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5195 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5196 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5197 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5198 // Same for CMP <--> CMN via so_imm_neg
5199 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5200 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5201 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5202 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5204 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5205 // LSR, ROR, and RRX instructions.
5206 // FIXME: We need C++ parser hooks to map the alias to the MOV
5207 // encoding. It seems we should be able to do that sort of thing
5208 // in tblgen, but it could get ugly.
5209 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5210 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5211 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5213 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5214 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5216 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5217 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5219 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5220 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5223 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5224 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5225 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5226 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5227 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5229 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5230 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5232 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5233 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5235 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5236 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5240 // "neg" is and alias for "rsb rd, rn, #0"
5241 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5242 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5244 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5245 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5246 Requires<[IsARM, NoV6]>;
5248 // UMULL/SMULL are available on all arches, but the instruction definitions
5249 // need difference constraints pre-v6. Use these aliases for the assembly
5250 // parsing on pre-v6.
5251 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5252 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5253 Requires<[IsARM, NoV6]>;
5254 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5255 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5256 Requires<[IsARM, NoV6]>;
5258 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5260 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;