1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def memri : Operand<iPTR> {
23 let PrintMethod = "printMemRegImm";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops i32imm, ptr_rc);
28 // Define ARM specific addressing mode.
29 //Addressing Mode 1: data processing operands
30 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
33 //register plus/minus 12 bit offset
34 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
35 //register plus scaled register
36 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
38 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
43 let Namespace = "ARM";
45 dag OperandList = ops;
46 let AsmString = asmstr;
47 let Pattern = pattern;
50 def brtarget : Operand<OtherVT>;
52 // Operand for printing out a condition code.
53 let PrintMethod = "printCCOperand" in
54 def CCOp : Operand<i32>;
56 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
57 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
58 [SDNPHasChain, SDNPOutFlag]>;
59 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
60 [SDNPHasChain, SDNPOutFlag]>;
62 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
63 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
64 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
69 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
71 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
72 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
74 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
75 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
77 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
78 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
80 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
81 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
82 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
83 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
84 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
85 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
86 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
87 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
89 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
90 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
94 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
96 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
97 "!ADJCALLSTACKUP $amt",
98 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
100 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
101 "!ADJCALLSTACKDOWN $amt",
102 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
104 let isReturn = 1 in {
105 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
108 let Defs = [R0, R1, R2, R3, R14] in {
109 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
112 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
114 [(set IntRegs:$dst, (load iaddr:$addr))]>;
116 def str : InstARM<(ops IntRegs:$src, memri:$addr),
118 [(store IntRegs:$src, iaddr:$addr)]>;
120 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
121 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
123 def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
125 [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
127 def ADCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
129 [(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
131 def ADDS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
133 [(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
135 // "LEA" forms of add
136 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
137 "add $dst, ${addr:arith}",
138 [(set IntRegs:$dst, iaddr:$addr)]>;
141 def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
143 [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
145 def SBCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
147 [(set IntRegs:$dst, (sube IntRegs:$a, addr_mode1:$b))]>;
149 def SUBS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
151 [(set IntRegs:$dst, (subc IntRegs:$a, addr_mode1:$b))]>;
153 def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
155 [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
157 def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
159 [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
161 def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
163 [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
165 let isTwoAddress = 1 in {
166 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
167 op_addr_mode1:$true, CCOp:$cc),
168 "mov$cc $dst, $true",
169 [(set IntRegs:$dst, (armselect addr_mode1:$true,
170 IntRegs:$false, imm:$cc))]>;
173 def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
175 [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
178 def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
179 "smull r12, $dst, $a, $b",
180 [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>;
182 def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
183 "umull r12, $dst, $a, $b",
184 [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>;
187 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
189 [(armbr bb:$dst, imm:$cc)]>;
191 def b : InstARM<(ops brtarget:$dst),
195 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
197 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
199 // Floating Point Compare
200 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
202 [(armcmp FPRegs:$a, FPRegs:$b)]>;
204 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
206 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
208 // Floating Point Conversion
209 // We use bitconvert for moving the data between the register classes.
210 // The format conversion is done with ARM specific nodes
212 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
213 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
215 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
216 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
218 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
219 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
221 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
222 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
224 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
225 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
227 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
228 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
230 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
231 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
233 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
234 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
236 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
237 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
239 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
240 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
242 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
243 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
245 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
246 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
248 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
249 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
251 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
252 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
254 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
256 // Floating Point Arithmetic
257 def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
258 "fadds $dst, $a, $b",
259 [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
261 def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
262 "faddd $dst, $a, $b",
263 [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
265 def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
266 "fsubs $dst, $a, $b",
267 [(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>;
269 def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
270 "fsubd $dst, $a, $b",
271 [(set DFPRegs:$dst, (fsub DFPRegs:$a, DFPRegs:$b))]>;
273 def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
275 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
277 def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
279 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
281 def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
282 "fmuls $dst, $a, $b",
283 [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
285 def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
286 "fmuld $dst, $a, $b",
287 [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;
290 // Floating Point Load
291 def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
293 [(set FPRegs:$dst, (load IntRegs:$addr))]>;
295 def FLDD : InstARM<(ops DFPRegs:$dst, IntRegs:$addr),
297 [(set DFPRegs:$dst, (load IntRegs:$addr))]>;