1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def op_addr_mode5 : Operand<iPTR> {
23 let PrintMethod = "printAddrMode5";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops ptr_rc, i32imm);
28 def memri : Operand<iPTR> {
29 let PrintMethod = "printMemRegImm";
30 let NumMIOperands = 2;
31 let MIOperandInfo = (ops i32imm, ptr_rc);
34 // Define ARM specific addressing mode.
35 //Addressing Mode 1: data processing operands
36 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
39 //Addressing Mode 5: VFP load/store
40 def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
42 //register plus/minus 12 bit offset
43 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
44 //register plus scaled register
45 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
47 //===----------------------------------------------------------------------===//
48 // Instruction Class Templates
49 //===----------------------------------------------------------------------===//
50 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
51 let Namespace = "ARM";
53 dag OperandList = ops;
54 let AsmString = asmstr;
55 let Pattern = pattern;
58 class IntBinOp<string OpcStr, SDNode OpNode> :
59 InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
60 !strconcat(OpcStr, " $dst, $a, $b"),
61 [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
63 class FPBinOp<string OpcStr, SDNode OpNode> :
64 InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
65 !strconcat(OpcStr, " $dst, $a, $b"),
66 [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
68 class DFPBinOp<string OpcStr, SDNode OpNode> :
69 InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
70 !strconcat(OpcStr, " $dst, $a, $b"),
71 [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
73 class Addr1BinOp<string OpcStr, SDNode OpNode> :
74 InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
75 !strconcat(OpcStr, " $dst, $a, $b"),
76 [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
82 def brtarget : Operand<OtherVT>;
84 // Operand for printing out a condition code.
85 let PrintMethod = "printCCOperand" in
86 def CCOp : Operand<i32>;
88 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
89 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
90 [SDNPHasChain, SDNPOutFlag]>;
91 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
92 [SDNPHasChain, SDNPOutFlag]>;
94 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
95 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
96 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
97 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
98 [SDNPHasChain, SDNPOptInFlag]>;
100 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
101 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
103 def SDTarmfmstat : SDTypeProfile<0, 0, []>;
104 def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
106 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
107 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
109 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
110 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
112 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
113 def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
114 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
115 def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
116 def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
117 def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
118 def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
119 def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
121 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
122 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
123 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
125 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
126 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
128 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
129 "!ADJCALLSTACKUP $amt",
130 [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
132 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
133 "!ADJCALLSTACKDOWN $amt",
134 [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
136 let isReturn = 1 in {
137 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
140 let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
141 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
144 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
146 [(set IntRegs:$dst, (load iaddr:$addr))]>;
148 def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
149 "ldrb $dst, [$addr]",
150 [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
152 def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
153 "ldrsb $dst, [$addr]",
154 [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
156 def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
157 "ldrh $dst, [$addr]",
158 [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
160 def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
161 "ldrsh $dst, [$addr]",
162 [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
164 def str : InstARM<(ops IntRegs:$src, memri:$addr),
166 [(store IntRegs:$src, iaddr:$addr)]>;
168 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
169 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
171 def ADD : Addr1BinOp<"add", add>;
172 def ADCS : Addr1BinOp<"adcs", adde>;
173 def ADDS : Addr1BinOp<"adds", addc>;
175 // "LEA" forms of add
176 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
177 "add $dst, ${addr:arith}",
178 [(set IntRegs:$dst, iaddr:$addr)]>;
181 def SUB : Addr1BinOp<"sub", sub>;
182 def SBCS : Addr1BinOp<"sbcs", sube>;
183 def SUBS : Addr1BinOp<"subs", subc>;
184 def AND : Addr1BinOp<"and", and>;
185 def EOR : Addr1BinOp<"eor", xor>;
186 def ORR : Addr1BinOp<"orr", or>;
188 let isTwoAddress = 1 in {
189 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
190 op_addr_mode1:$true, CCOp:$cc),
191 "mov$cc $dst, $true",
192 [(set IntRegs:$dst, (armselect addr_mode1:$true,
193 IntRegs:$false, imm:$cc))]>;
196 def MUL : IntBinOp<"mul", mul>;
199 def SMULL : IntBinOp<"smull r12,", mulhs>;
200 def UMULL : IntBinOp<"umull r12,", mulhu>;
203 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
205 [(armbr bb:$dst, imm:$cc)]>;
207 def b : InstARM<(ops brtarget:$dst),
211 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
213 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
215 // Floating Point Compare
216 def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
218 [(armcmp FPRegs:$a, FPRegs:$b)]>;
220 def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
222 [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
224 // Floating Point Copy
225 def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
227 def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
229 // Floating Point Conversion
230 // We use bitconvert for moving the data between the register classes.
231 // The format conversion is done with ARM specific nodes
233 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
234 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
236 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
237 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
239 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
240 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
242 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
243 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
245 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
246 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
248 def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
249 "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
251 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
252 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
254 def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
255 "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
257 def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
258 "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
260 def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
261 "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
263 def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
264 "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
266 def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
267 "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
269 def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
270 "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
272 def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
273 "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
275 def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
277 // Floating Point Arithmetic
278 def FADDS : FPBinOp<"fadds", fadd>;
279 def FADDD : DFPBinOp<"faddd", fadd>;
280 def FSUBS : FPBinOp<"fsubs", fsub>;
281 def FSUBD : DFPBinOp<"fsubd", fsub>;
283 def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
285 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
287 def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
289 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
291 def FMULS : FPBinOp<"fmuls", fmul>;
292 def FMULD : DFPBinOp<"fmuld", fmul>;
293 def FDIVS : FPBinOp<"fdivs", fdiv>;
294 def FDIVD : DFPBinOp<"fdivd", fdiv>;
296 // Floating Point Load
297 def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr),
299 [(set FPRegs:$dst, (load addr_mode5:$addr))]>;
301 def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr),
303 [(set DFPRegs:$dst, (load addr_mode5:$addr))]>;
305 // Floating Point Store
306 def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr),
308 [(store FPRegs:$src, addr_mode5:$addr)]>;
310 def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr),
312 [(store DFPRegs:$src, addr_mode5:$addr)]>;
314 def : Pat<(ARMcall tglobaladdr:$dst),
315 (bl tglobaladdr:$dst)>;
317 def : Pat<(ARMcall texternalsym:$dst),
318 (bl texternalsym:$dst)>;