1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
51 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getZExtValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
147 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
148 }], so_imm_neg_XFORM>;
152 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
153 }], so_imm_not_XFORM>;
155 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
156 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
157 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
160 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
161 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
163 //===----------------------------------------------------------------------===//
164 // Operand Definitions.
168 def brtarget : Operand<OtherVT>;
170 // A list of registers separated by comma. Used by load/store multiple.
171 def reglist : Operand<i32> {
172 let PrintMethod = "printRegisterList";
175 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
176 def cpinst_operand : Operand<i32> {
177 let PrintMethod = "printCPInstOperand";
180 def jtblock_operand : Operand<i32> {
181 let PrintMethod = "printJTBlockOperand";
185 def pclabel : Operand<i32> {
186 let PrintMethod = "printPCLabel";
189 // shifter_operand operands: so_reg and so_imm.
190 def so_reg : Operand<i32>, // reg reg imm
191 ComplexPattern<i32, 3, "SelectShifterOperandReg",
192 [shl,srl,sra,rotr]> {
193 let PrintMethod = "printSORegOperand";
194 let MIOperandInfo = (ops GPR, GPR, i32imm);
197 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
198 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
199 // represented in the imm field in the same 12-bit form that they are encoded
200 // into so_imm instructions: the 8-bit immediate is the least significant bits
201 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
202 def so_imm : Operand<i32>,
204 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
206 let PrintMethod = "printSOImmOperand";
209 // Break so_imm's up into two pieces. This handles immediates with up to 16
210 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
211 // get the first/second pieces.
212 def so_imm2part : Operand<i32>,
214 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
216 let PrintMethod = "printSOImm2PartOperand";
219 def so_imm2part_1 : SDNodeXForm<imm, [{
220 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
221 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
224 def so_imm2part_2 : SDNodeXForm<imm, [{
225 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
226 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
230 // Define ARM specific addressing modes.
232 // addrmode2 := reg +/- reg shop imm
233 // addrmode2 := reg +/- imm12
235 def addrmode2 : Operand<i32>,
236 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
237 let PrintMethod = "printAddrMode2Operand";
238 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
241 def am2offset : Operand<i32>,
242 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
243 let PrintMethod = "printAddrMode2OffsetOperand";
244 let MIOperandInfo = (ops GPR, i32imm);
247 // addrmode3 := reg +/- reg
248 // addrmode3 := reg +/- imm8
250 def addrmode3 : Operand<i32>,
251 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
252 let PrintMethod = "printAddrMode3Operand";
253 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
256 def am3offset : Operand<i32>,
257 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
258 let PrintMethod = "printAddrMode3OffsetOperand";
259 let MIOperandInfo = (ops GPR, i32imm);
262 // addrmode4 := reg, <mode|W>
264 def addrmode4 : Operand<i32>,
265 ComplexPattern<i32, 2, "", []> {
266 let PrintMethod = "printAddrMode4Operand";
267 let MIOperandInfo = (ops GPR, i32imm);
270 // addrmode5 := reg +/- imm8*4
272 def addrmode5 : Operand<i32>,
273 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
274 let PrintMethod = "printAddrMode5Operand";
275 let MIOperandInfo = (ops GPR, i32imm);
278 // addrmodepc := pc + reg
280 def addrmodepc : Operand<i32>,
281 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
282 let PrintMethod = "printAddrModePCOperand";
283 let MIOperandInfo = (ops GPR, i32imm);
286 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
287 // register whose default is 0 (no register).
288 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
289 (ops (i32 14), (i32 zero_reg))> {
290 let PrintMethod = "printPredicateOperand";
293 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
295 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
296 let PrintMethod = "printSBitModifierOperand";
299 //===----------------------------------------------------------------------===//
300 // ARM Instruction flags. These need to match ARMInstrInfo.h.
304 class AddrMode<bits<4> val> {
307 def AddrModeNone : AddrMode<0>;
308 def AddrMode1 : AddrMode<1>;
309 def AddrMode2 : AddrMode<2>;
310 def AddrMode3 : AddrMode<3>;
311 def AddrMode4 : AddrMode<4>;
312 def AddrMode5 : AddrMode<5>;
313 def AddrModeT1 : AddrMode<6>;
314 def AddrModeT2 : AddrMode<7>;
315 def AddrModeT4 : AddrMode<8>;
316 def AddrModeTs : AddrMode<9>;
319 class SizeFlagVal<bits<3> val> {
322 def SizeInvalid : SizeFlagVal<0>; // Unset.
323 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
324 def Size8Bytes : SizeFlagVal<2>;
325 def Size4Bytes : SizeFlagVal<3>;
326 def Size2Bytes : SizeFlagVal<4>;
328 // Load / store index mode.
329 class IndexMode<bits<2> val> {
332 def IndexModeNone : IndexMode<0>;
333 def IndexModePre : IndexMode<1>;
334 def IndexModePost : IndexMode<2>;
336 //===----------------------------------------------------------------------===//
338 include "ARMInstrFormats.td"
340 //===----------------------------------------------------------------------===//
341 // Multiclass helpers...
344 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
345 /// binop that produces a value.
346 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
347 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
348 opc, " $dst, $a, $b",
349 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
350 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
351 opc, " $dst, $a, $b",
352 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
353 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
354 opc, " $dst, $a, $b",
355 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
358 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
359 /// instruction modifies the CSPR register.
360 let Defs = [CPSR] in {
361 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
362 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
363 opc, "s $dst, $a, $b",
364 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
365 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
366 opc, "s $dst, $a, $b",
367 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
368 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
369 opc, "s $dst, $a, $b",
370 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
374 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
375 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
376 /// a explicit result, only implicitly set CPSR.
377 let Defs = [CPSR] in {
378 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
379 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
381 [(opnode GPR:$a, so_imm:$b)]>;
382 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
384 [(opnode GPR:$a, GPR:$b)]>;
385 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
387 [(opnode GPR:$a, so_reg:$b)]>;
391 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
392 /// register and one whose operand is a register rotated by 8/16/24.
393 multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
394 def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo,
396 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
397 def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
398 opc, " $dst, $Src, ror $rot",
399 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
400 Requires<[IsARM, HasV6]>;
403 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
404 /// register and one whose operand is a register rotated by 8/16/24.
405 multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
406 def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
407 Pseudo, opc, " $dst, $LHS, $RHS",
408 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
409 Requires<[IsARM, HasV6]>;
410 def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
411 Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
412 [(set GPR:$dst, (opnode GPR:$LHS,
413 (rotr GPR:$RHS, rot_imm:$rot)))]>,
414 Requires<[IsARM, HasV6]>;
417 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
418 /// setting carry bit. But it can optionally set CPSR.
419 let Uses = [CPSR] in {
420 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
421 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
422 DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
423 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
424 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
425 DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
426 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
427 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
428 DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
429 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
433 //===----------------------------------------------------------------------===//
435 //===----------------------------------------------------------------------===//
437 //===----------------------------------------------------------------------===//
438 // Miscellaneous Instructions.
441 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
442 /// the function. The first operand is the ID# for this instruction, the second
443 /// is the index into the MachineConstantPool that this is, the third is the
444 /// size in bytes of this constant pool entry.
445 let isNotDuplicable = 1 in
446 def CONSTPOOL_ENTRY :
447 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
449 "${instid:label} ${cpidx:cpentry}", []>;
451 let Defs = [SP], Uses = [SP] in {
453 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
454 "@ ADJCALLSTACKUP $amt1",
455 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
457 def ADJCALLSTACKDOWN :
458 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
459 "@ ADJCALLSTACKDOWN $amt",
460 [(ARMcallseq_start imm:$amt)]>;
464 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
465 ".loc $file, $line, $col",
466 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
468 let isNotDuplicable = 1 in {
469 def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
470 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
471 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
473 let AddedComplexity = 10 in {
474 let isSimpleLoad = 1 in
475 def PICLD : AXI2ldw<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
476 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
477 [(set GPR:$dst, (load addrmodepc:$addr))]>;
479 def PICLDZH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
480 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
481 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
483 def PICLDZB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
484 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
485 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
487 def PICLDH : AXI3ldh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
488 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
489 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
491 def PICLDB : AXI2ldb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
492 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
493 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
495 def PICLDSH : AXI3ldsh<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
496 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
497 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
499 def PICLDSB : AXI3ldsb<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
500 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
501 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
503 let AddedComplexity = 10 in {
504 def PICSTR : AXI2stw<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
505 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
506 [(store GPR:$src, addrmodepc:$addr)]>;
508 def PICSTRH : AXI3sth<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
509 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
510 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
512 def PICSTRB : AXI2stb<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
513 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
514 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
518 //===----------------------------------------------------------------------===//
519 // Control Flow Instructions.
522 let isReturn = 1, isTerminator = 1 in
523 def BX_RET : AI<0x0, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]> {
524 let Inst{4-7} = {1,0,0,0};
525 let Inst{8-19} = {1,1,1,1,1,1,1,1,1,1,1,1};
526 let Inst{20-27} = {0,1,0,0,1,0,0,0};
529 // FIXME: remove when we have a way to marking a MI with these properties.
530 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
532 let isReturn = 1, isTerminator = 1 in
533 def LDM_RET : AXI4ldpc<0x0, (outs),
534 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
535 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
539 Defs = [R0, R1, R2, R3, R12, LR,
540 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
541 def BL : ABLI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
543 [(ARMcall tglobaladdr:$func)]>;
545 def BL_pred : ABLpredI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch,
546 "bl", " ${func:call}",
547 [(ARMcall_pred tglobaladdr:$func)]>;
550 def BLX : AXI<0x0, (outs), (ins GPR:$func, variable_ops), BranchMisc,
552 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
553 let Inst{4-7} = {1,1,0,0};
554 let Inst{8-19} = {1,1,1,1,1,1,1,1,1,1,1,1};
555 let Inst{20-27} = {0,1,0,0,1,0,0,0};
560 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
561 BranchMisc, "mov lr, pc\n\tbx $func",
562 [(ARMcall_nolink GPR:$func)]>;
566 let isBranch = 1, isTerminator = 1 in {
567 // B is "predicable" since it can be xformed into a Bcc.
568 let isBarrier = 1 in {
569 let isPredicable = 1 in
570 def B : ABI<{0,1,0,1}, (outs), (ins brtarget:$target), Branch, "b $target",
573 let isNotDuplicable = 1, isIndirectBranch = 1 in {
574 def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
575 "mov pc, $target \n$jt",
576 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
577 def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
578 "ldr pc, $target \n$jt",
579 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
581 def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
583 "add pc, $target, $idx \n$jt",
584 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
589 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
590 // a two-value operand where a dag node expects two operands. :(
591 def Bcc : ABccI<0xA, (outs), (ins brtarget:$target), Branch,
593 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
596 //===----------------------------------------------------------------------===//
597 // Load / store Instructions.
601 let isSimpleLoad = 1 in
602 def LDR : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
603 "ldr", " $dst, $addr",
604 [(set GPR:$dst, (load addrmode2:$addr))]>;
606 // Special LDR for loads from non-pc-relative constpools.
607 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
608 def LDRcp : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
609 "ldr", " $dst, $addr", []>;
611 // Loads with zero extension
612 def LDRH : AI3ldh<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
613 "ldr", "h $dst, $addr",
614 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
616 def LDRB : AI2ldb<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
617 "ldr", "b $dst, $addr",
618 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
620 // Loads with sign extension
621 def LDRSH : AI3ldsh<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
622 "ldr", "sh $dst, $addr",
623 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
625 def LDRSB : AI3ldsb<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
626 "ldr", "sb $dst, $addr",
627 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
631 def LDRD : AI3ldd<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
632 "ldr", "d $dst, $addr",
633 []>, Requires<[IsARM, HasV5T]>;
636 def LDR_PRE : AI2ldwpr<0x0, (outs GPR:$dst, GPR:$base_wb),
637 (ins addrmode2:$addr), LdFrm,
638 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
640 def LDR_POST : AI2ldwpo<0x0, (outs GPR:$dst, GPR:$base_wb),
641 (ins GPR:$base, am2offset:$offset), LdFrm,
642 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
644 def LDRH_PRE : AI3ldhpr<0xB, (outs GPR:$dst, GPR:$base_wb),
645 (ins addrmode3:$addr), LdFrm,
646 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
648 def LDRH_POST : AI3ldhpo<0xB, (outs GPR:$dst, GPR:$base_wb),
649 (ins GPR:$base,am3offset:$offset), LdFrm,
650 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
652 def LDRB_PRE : AI2ldbpr<0x1, (outs GPR:$dst, GPR:$base_wb),
653 (ins addrmode2:$addr), LdFrm,
654 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
656 def LDRB_POST : AI2ldbpo<0x1, (outs GPR:$dst, GPR:$base_wb),
657 (ins GPR:$base,am2offset:$offset), LdFrm,
658 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
660 def LDRSH_PRE : AI3ldshpr<0xE, (outs GPR:$dst, GPR:$base_wb),
661 (ins addrmode3:$addr), LdFrm,
662 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
664 def LDRSH_POST: AI3ldshpo<0xE, (outs GPR:$dst, GPR:$base_wb),
665 (ins GPR:$base,am3offset:$offset), LdFrm,
666 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
668 def LDRSB_PRE : AI3ldsbpr<0xD, (outs GPR:$dst, GPR:$base_wb),
669 (ins addrmode3:$addr), LdFrm,
670 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
672 def LDRSB_POST: AI3ldsbpo<0xD, (outs GPR:$dst, GPR:$base_wb),
673 (ins GPR:$base,am3offset:$offset), LdFrm,
674 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
678 def STR : AI2stw<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
679 "str", " $src, $addr",
680 [(store GPR:$src, addrmode2:$addr)]>;
682 // Stores with truncate
683 def STRH : AI3sth<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
684 "str", "h $src, $addr",
685 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
687 def STRB : AI2stb<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
688 "str", "b $src, $addr",
689 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
693 def STRD : AI3std<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
694 "str", "d $src, $addr",
695 []>, Requires<[IsARM, HasV5T]>;
698 def STR_PRE : AI2stwpr<0x0, (outs GPR:$base_wb),
699 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
700 "str", " $src, [$base, $offset]!", "$base = $base_wb",
702 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
704 def STR_POST : AI2stwpo<0x0, (outs GPR:$base_wb),
705 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
706 "str", " $src, [$base], $offset", "$base = $base_wb",
708 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
710 def STRH_PRE : AI3sthpr<0xB, (outs GPR:$base_wb),
711 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
712 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
714 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
716 def STRH_POST: AI3sthpo<0xB, (outs GPR:$base_wb),
717 (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm,
718 "str", "h $src, [$base], $offset", "$base = $base_wb",
719 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
720 GPR:$base, am3offset:$offset))]>;
722 def STRB_PRE : AI2stbpr<0x1, (outs GPR:$base_wb),
723 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
724 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
725 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
726 GPR:$base, am2offset:$offset))]>;
728 def STRB_POST: AI2stbpo<0x1, (outs GPR:$base_wb),
729 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
730 "str", "b $src, [$base], $offset", "$base = $base_wb",
731 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
732 GPR:$base, am2offset:$offset))]>;
734 //===----------------------------------------------------------------------===//
735 // Load / store multiple Instructions.
738 // FIXME: $dst1 should be a def.
740 def LDM : AXI4ld<0x0, (outs),
741 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
742 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
746 def STM : AXI4st<0x0, (outs),
747 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
748 StFrm, "stm${p}${addr:submode} $addr, $src1",
751 //===----------------------------------------------------------------------===//
752 // Move Instructions.
755 def MOVr : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
756 "mov", " $dst, $src", []>;
757 def MOVs : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
758 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
760 let isReMaterializable = 1 in
761 def MOVi : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
762 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
764 def MOVrx : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
765 "mov", " $dst, $src, rrx",
766 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
768 // These aren't really mov instructions, but we have to define them this way
769 // due to flag operands.
771 let Defs = [CPSR] in {
772 def MOVsrl_flag : AI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
773 "mov", "s $dst, $src, lsr #1",
774 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
775 def MOVsra_flag : AI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
776 "mov", "s $dst, $src, asr #1",
777 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
780 //===----------------------------------------------------------------------===//
781 // Extend Instructions.
786 defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
787 defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
789 defm SXTAB : AI_bin_rrot<0x0, "sxtab",
790 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
791 defm SXTAH : AI_bin_rrot<0x0, "sxtah",
792 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
794 // TODO: SXT(A){B|H}16
798 let AddedComplexity = 16 in {
799 defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
800 defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
801 defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
803 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
804 (UXTB16r_rot GPR:$Src, 24)>;
805 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
806 (UXTB16r_rot GPR:$Src, 8)>;
808 defm UXTAB : AI_bin_rrot<0x0, "uxtab",
809 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
810 defm UXTAH : AI_bin_rrot<0x0, "uxtah",
811 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
814 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
815 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
817 // TODO: UXT(A){B|H}16
819 //===----------------------------------------------------------------------===//
820 // Arithmetic Instructions.
823 defm ADD : AsI1_bin_irs<{0,0,1,0}, "add",
824 BinOpFrag<(add node:$LHS, node:$RHS)>>;
825 defm SUB : AsI1_bin_irs<{0,1,0,0}, "sub",
826 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
828 // ADD and SUB with 's' bit set.
829 defm ADDS : ASI1_bin_s_irs<{0,0,1,0}, "add",
830 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
831 defm SUBS : ASI1_bin_s_irs<{0,1,0,0}, "sub",
832 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
834 // FIXME: Do not allow ADC / SBC to be predicated for now.
835 defm ADC : AsXI1_bin_c_irs<{1,0,1,0}, "adc",
836 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
837 defm SBC : AsXI1_bin_c_irs<{0,1,1,0}, "sbc",
838 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
840 // These don't define reg/reg forms, because they are handled above.
841 def RSBri : AsI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
842 "rsb", " $dst, $a, $b",
843 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
845 def RSBrs : AsI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
846 "rsb", " $dst, $a, $b",
847 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
849 // RSB with 's' bit set.
850 let Defs = [CPSR] in {
851 def RSBSri : AI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
852 "rsb", "s $dst, $a, $b",
853 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
854 def RSBSrs : AI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
855 "rsb", "s $dst, $a, $b",
856 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
859 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
860 let Uses = [CPSR] in {
861 def RSCri : AXI1<{1,1,1,0}, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
862 DPRIm, "rsc${s} $dst, $a, $b",
863 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
864 def RSCrs : AXI1<{1,1,1,0}, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
865 DPRSoReg, "rsc${s} $dst, $a, $b",
866 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
869 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
870 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
871 (SUBri GPR:$src, so_imm_neg:$imm)>;
873 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
874 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
875 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
876 // (SBCri GPR:$src, so_imm_neg:$imm)>;
878 // Note: These are implemented in C++ code, because they have to generate
879 // ADD/SUBrs instructions, which use a complex pattern that a xform function
881 // (mul X, 2^n+1) -> (add (X << n), X)
882 // (mul X, 2^n-1) -> (rsb X, (X << n))
885 //===----------------------------------------------------------------------===//
886 // Bitwise Instructions.
889 defm AND : AsI1_bin_irs<{0,0,0,0}, "and",
890 BinOpFrag<(and node:$LHS, node:$RHS)>>;
891 defm ORR : AsI1_bin_irs<{0,0,1,1}, "orr",
892 BinOpFrag<(or node:$LHS, node:$RHS)>>;
893 defm EOR : AsI1_bin_irs<{1,0,0,0}, "eor",
894 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
895 defm BIC : AsI1_bin_irs<{0,1,1,1}, "bic",
896 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
898 def MVNr : AsI1<{1,1,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
899 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
900 def MVNs : AsI1<{1,1,1,1}, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
901 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
902 let isReMaterializable = 1 in
903 def MVNi : AsI1<{1,1,1,1}, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
904 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
906 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
907 (BICri GPR:$src, so_imm_not:$imm)>;
909 //===----------------------------------------------------------------------===//
910 // Multiply Instructions.
913 def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
914 "mul", " $dst, $a, $b",
915 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
917 def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
918 MulFrm, "mla", " $dst, $a, $b, $c",
919 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
921 // Extra precision multiplies with low / high results
922 def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
923 MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
925 def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
926 MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
928 // Multiply + accumulate
929 def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
930 MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
932 def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
933 MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
935 def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
936 "umaal", " $ldst, $hdst, $a, $b", []>,
937 Requires<[IsARM, HasV6]>;
939 // Most significant word multiply
940 def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
941 "smmul", " $dst, $a, $b",
942 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
943 Requires<[IsARM, HasV6]>;
945 def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
946 "smmla", " $dst, $a, $b, $c",
947 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
948 Requires<[IsARM, HasV6]>;
951 def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
952 "smmls", " $dst, $a, $b, $c",
953 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
954 Requires<[IsARM, HasV6]>;
956 multiclass AI_smul<string opc, PatFrag opnode> {
957 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
958 !strconcat(opc, "bb"), " $dst, $a, $b",
959 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
960 (sext_inreg GPR:$b, i16)))]>,
961 Requires<[IsARM, HasV5TE]>;
963 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
964 !strconcat(opc, "bt"), " $dst, $a, $b",
965 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
966 (sra GPR:$b, 16)))]>,
967 Requires<[IsARM, HasV5TE]>;
969 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
970 !strconcat(opc, "tb"), " $dst, $a, $b",
971 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
972 (sext_inreg GPR:$b, i16)))]>,
973 Requires<[IsARM, HasV5TE]>;
975 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
976 !strconcat(opc, "tt"), " $dst, $a, $b",
977 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
978 (sra GPR:$b, 16)))]>,
979 Requires<[IsARM, HasV5TE]>;
981 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
982 !strconcat(opc, "wb"), " $dst, $a, $b",
983 [(set GPR:$dst, (sra (opnode GPR:$a,
984 (sext_inreg GPR:$b, i16)), 16))]>,
985 Requires<[IsARM, HasV5TE]>;
987 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
988 !strconcat(opc, "wt"), " $dst, $a, $b",
989 [(set GPR:$dst, (sra (opnode GPR:$a,
990 (sra GPR:$b, 16)), 16))]>,
991 Requires<[IsARM, HasV5TE]>;
995 multiclass AI_smla<string opc, PatFrag opnode> {
996 def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
997 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
998 [(set GPR:$dst, (add GPR:$acc,
999 (opnode (sext_inreg GPR:$a, i16),
1000 (sext_inreg GPR:$b, i16))))]>,
1001 Requires<[IsARM, HasV5TE]>;
1003 def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1004 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1005 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1006 (sra GPR:$b, 16))))]>,
1007 Requires<[IsARM, HasV5TE]>;
1009 def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1010 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1011 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1012 (sext_inreg GPR:$b, i16))))]>,
1013 Requires<[IsARM, HasV5TE]>;
1015 def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
1016 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1017 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1018 (sra GPR:$b, 16))))]>,
1019 Requires<[IsARM, HasV5TE]>;
1021 def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1022 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1023 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1024 (sext_inreg GPR:$b, i16)), 16)))]>,
1025 Requires<[IsARM, HasV5TE]>;
1027 def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
1028 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1029 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1030 (sra GPR:$b, 16)), 16)))]>,
1031 Requires<[IsARM, HasV5TE]>;
1034 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1035 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1037 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1038 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1040 //===----------------------------------------------------------------------===//
1041 // Misc. Arithmetic Instructions.
1044 def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1045 "clz", " $dst, $src",
1046 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1048 def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1049 "rev", " $dst, $src",
1050 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1052 def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1053 "rev16", " $dst, $src",
1055 (or (and (srl GPR:$src, 8), 0xFF),
1056 (or (and (shl GPR:$src, 8), 0xFF00),
1057 (or (and (srl GPR:$src, 8), 0xFF0000),
1058 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1059 Requires<[IsARM, HasV6]>;
1061 def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
1062 "revsh", " $dst, $src",
1065 (or (srl (and GPR:$src, 0xFF00), 8),
1066 (shl GPR:$src, 8)), i16))]>,
1067 Requires<[IsARM, HasV6]>;
1069 def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1070 Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1071 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1072 (and (shl GPR:$src2, (i32 imm:$shamt)),
1074 Requires<[IsARM, HasV6]>;
1076 // Alternate cases for PKHBT where identities eliminate some nodes.
1077 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1078 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1079 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1080 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1083 def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1084 Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1085 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1086 (and (sra GPR:$src2, imm16_31:$shamt),
1087 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1089 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1090 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1091 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1092 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1093 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1094 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1095 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1098 //===----------------------------------------------------------------------===//
1099 // Comparison Instructions...
1102 defm CMP : AI1_cmp_irs<{0,1,0,1}, "cmp",
1103 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1104 defm CMN : AI1_cmp_irs<{1,1,0,1}, "cmn",
1105 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1107 // Note that TST/TEQ don't set all the same flags that CMP does!
1108 defm TST : AI1_cmp_irs<0x8, "tst",
1109 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1110 defm TEQ : AI1_cmp_irs<0x9, "teq",
1111 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1113 defm CMPnz : AI1_cmp_irs<{0,1,0,1}, "cmp",
1114 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1115 defm CMNnz : AI1_cmp_irs<{1,1,0,1}, "cmn",
1116 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1118 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1119 (CMNri GPR:$src, so_imm_neg:$imm)>;
1121 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1122 (CMNri GPR:$src, so_imm_neg:$imm)>;
1125 // Conditional moves
1126 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1127 // a two-value operand where a dag node expects two operands. :(
1128 def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
1129 DPRdReg, "mov", " $dst, $true",
1130 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1131 RegConstraint<"$false = $dst">;
1133 def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
1134 DPRdSoReg, "mov", " $dst, $true",
1135 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1136 RegConstraint<"$false = $dst">;
1138 def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
1139 DPRdIm, "mov", " $dst, $true",
1140 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1141 RegConstraint<"$false = $dst">;
1144 // LEApcrel - Load a pc-relative address into a register without offending the
1146 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1147 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1148 "${:private}PCRELL${:uid}+8))\n"),
1149 !strconcat("${:private}PCRELL${:uid}:\n\t",
1150 "add$p $dst, pc, #PCRELV${:uid}")),
1153 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1155 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1156 "${:private}PCRELL${:uid}+8))\n"),
1157 !strconcat("${:private}PCRELL${:uid}:\n\t",
1158 "add$p $dst, pc, #PCRELV${:uid}")),
1161 //===----------------------------------------------------------------------===//
1165 // __aeabi_read_tp preserves the registers r1-r3.
1167 Defs = [R0, R12, LR, CPSR] in {
1168 def TPsoft : AXI<0x0, (outs), (ins), BranchMisc,
1169 "bl __aeabi_read_tp",
1170 [(set R0, ARMthread_pointer)]>;
1173 //===----------------------------------------------------------------------===//
1174 // Non-Instruction Patterns
1177 // ConstantPool, GlobalAddress, and JumpTable
1178 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1179 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1180 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1181 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1183 // Large immediate handling.
1185 // Two piece so_imms.
1186 let isReMaterializable = 1 in
1187 def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
1188 "mov", " $dst, $src",
1189 [(set GPR:$dst, so_imm2part:$src)]>;
1191 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1192 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1193 (so_imm2part_2 imm:$RHS))>;
1194 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1195 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1196 (so_imm2part_2 imm:$RHS))>;
1198 // TODO: add,sub,and, 3-instr forms?
1202 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1204 // zextload i1 -> zextload i8
1205 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1207 // extload -> zextload
1208 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1209 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1210 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1213 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1214 (SMULBB GPR:$a, GPR:$b)>;
1215 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1216 (SMULBB GPR:$a, GPR:$b)>;
1217 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1218 (SMULBT GPR:$a, GPR:$b)>;
1219 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1220 (SMULBT GPR:$a, GPR:$b)>;
1221 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1222 (SMULTB GPR:$a, GPR:$b)>;
1223 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1224 (SMULTB GPR:$a, GPR:$b)>;
1225 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1226 (SMULWB GPR:$a, GPR:$b)>;
1227 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1228 (SMULWB GPR:$a, GPR:$b)>;
1230 def : ARMV5TEPat<(add GPR:$acc,
1231 (mul (sra (shl GPR:$a, 16), 16),
1232 (sra (shl GPR:$b, 16), 16))),
1233 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1234 def : ARMV5TEPat<(add GPR:$acc,
1235 (mul sext_16_node:$a, sext_16_node:$b)),
1236 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1237 def : ARMV5TEPat<(add GPR:$acc,
1238 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1239 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1240 def : ARMV5TEPat<(add GPR:$acc,
1241 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1242 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1243 def : ARMV5TEPat<(add GPR:$acc,
1244 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1245 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1246 def : ARMV5TEPat<(add GPR:$acc,
1247 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1248 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1249 def : ARMV5TEPat<(add GPR:$acc,
1250 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1251 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1252 def : ARMV5TEPat<(add GPR:$acc,
1253 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1254 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1256 //===----------------------------------------------------------------------===//
1260 include "ARMInstrThumb.td"
1262 //===----------------------------------------------------------------------===//
1263 // Floating Point Support
1266 include "ARMInstrVFP.td"