1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 3;
19 let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
22 def memri : Operand<iPTR> {
23 let PrintMethod = "printMemRegImm";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops i32imm, ptr_rc);
28 // Define ARM specific addressing mode.
29 //Addressing Mode 1: data processing operands
30 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl]>;
32 //register plus/minus 12 bit offset
33 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
34 //register plus scaled register
35 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
42 let Namespace = "ARM";
44 dag OperandList = ops;
45 let AsmString = asmstr;
46 let Pattern = pattern;
49 def brtarget : Operand<OtherVT>;
51 // Operand for printing out a condition code.
52 let PrintMethod = "printCCOperand" in
53 def CCOp : Operand<i32>;
55 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
56 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
57 [SDNPHasChain, SDNPOutFlag]>;
58 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
59 [SDNPHasChain, SDNPOutFlag]>;
61 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
62 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
65 [SDNPHasChain, SDNPOptInFlag]>;
67 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
69 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
71 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
72 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
74 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
75 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
77 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
78 def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
80 def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
81 def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
82 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
84 def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
85 def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
87 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
88 "!ADJCALLSTACKUP $amt",
89 [(callseq_end imm:$amt)]>;
91 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
92 "!ADJCALLSTACKDOWN $amt",
93 [(callseq_start imm:$amt)]>;
96 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
99 let Defs = [R0, R1, R2, R3, R14] in {
100 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
103 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
105 [(set IntRegs:$dst, (load iaddr:$addr))]>;
107 def FLDS : InstARM<(ops FPRegs:$dst, IntRegs:$addr),
109 [(set FPRegs:$dst, (load IntRegs:$addr))]>;
111 def str : InstARM<(ops IntRegs:$src, memri:$addr),
113 [(store IntRegs:$src, iaddr:$addr)]>;
115 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
116 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
118 def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
120 [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
122 // "LEA" forms of add
123 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
124 "add $dst, ${addr:arith}",
125 [(set IntRegs:$dst, iaddr:$addr)]>;
128 def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
130 [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
132 def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
134 [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
136 def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
138 [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
140 def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
142 [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
144 let isTwoAddress = 1 in {
145 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
146 op_addr_mode1:$true, CCOp:$cc),
147 "mov$cc $dst, $true",
148 [(set IntRegs:$dst, (armselect addr_mode1:$true,
149 IntRegs:$false, imm:$cc))]>;
152 def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
154 [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
156 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
158 [(armbr bb:$dst, imm:$cc)]>;
160 def b : InstARM<(ops brtarget:$dst),
164 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
166 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
169 // Floating Point Conversion
170 // We use bitconvert for moving the data between the register classes.
171 // The format conversion is done with ARM specific nodes
173 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
174 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
176 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
177 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
179 def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
180 "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
182 def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
183 "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
185 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
186 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
188 def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
189 "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
192 // Floating Point Arithmetic
193 def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
194 "fadds $dst, $a, $b",
195 [(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
197 def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
198 "faddd $dst, $a, $b",
199 [(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
201 def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
202 "fmuls $dst, $a, $b",
203 [(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
205 def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
206 "fmuld $dst, $a, $b",
207 [(set DFPRegs:$dst, (fmul DFPRegs:$a, DFPRegs:$b))]>;