1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
62 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
76 def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
77 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
80 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
83 SDTCisInt<0>, SDTCisVT<1, i32>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
86 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
93 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
94 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
96 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
97 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
100 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
101 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
102 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
104 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
106 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
107 [SDNPHasChain, SDNPSideEffect,
108 SDNPOptInGlue, SDNPOutGlue]>;
109 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
112 SDNPMayStore, SDNPMayLoad]>;
114 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
124 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
131 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
134 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
136 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
139 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
142 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
145 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
149 [SDNPOutGlue, SDNPCommutative]>;
151 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
153 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
154 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
155 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
157 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
159 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
160 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
163 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
164 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
165 SDT_ARMEH_SJLJ_Setjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
168 SDT_ARMEH_SJLJ_Longjmp,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
171 SDT_ARMEH_SJLJ_SetupDispatch,
172 [SDNPHasChain, SDNPSideEffect]>;
174 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
175 [SDNPHasChain, SDNPSideEffect]>;
176 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
177 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
179 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
184 def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
186 SDNPMayStore, SDNPMayLoad]>;
188 //===----------------------------------------------------------------------===//
189 // ARM Instruction Predicate Definitions.
191 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
192 AssemblerPredicate<"HasV4TOps", "armv4t">;
193 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
194 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
195 AssemblerPredicate<"HasV5TOps", "armv5t">;
196 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
197 AssemblerPredicate<"HasV5TEOps", "armv5te">;
198 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
199 AssemblerPredicate<"HasV6Ops", "armv6">;
200 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
201 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
202 AssemblerPredicate<"HasV6MOps",
203 "armv6m or armv6t2">;
204 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
205 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
206 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
207 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
208 AssemblerPredicate<"HasV6KOps", "armv6k">;
209 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
210 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
211 AssemblerPredicate<"HasV7Ops", "armv7">;
212 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
213 AssemblerPredicate<"HasV8Ops", "armv8">;
214 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
215 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
216 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
217 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
218 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
219 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
220 AssemblerPredicate<"FeatureVFP2", "VFP2">;
221 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
222 AssemblerPredicate<"FeatureVFP3", "VFP3">;
223 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
224 AssemblerPredicate<"FeatureVFP4", "VFP4">;
225 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
226 AssemblerPredicate<"!FeatureVFPOnlySP",
227 "double precision VFP">;
228 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
229 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
230 def HasNEON : Predicate<"Subtarget->hasNEON()">,
231 AssemblerPredicate<"FeatureNEON", "NEON">;
232 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
233 AssemblerPredicate<"FeatureCrypto", "crypto">;
234 def HasCRC : Predicate<"Subtarget->hasCRC()">,
235 AssemblerPredicate<"FeatureCRC", "crc">;
236 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
237 AssemblerPredicate<"FeatureFP16","half-float">;
238 def HasDivide : Predicate<"Subtarget->hasDivide()">,
239 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
240 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
241 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
242 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
243 AssemblerPredicate<"FeatureT2XtPk",
245 def HasDSP : Predicate<"Subtarget->hasDSP()">,
246 AssemblerPredicate<"FeatureDSP", "dsp">;
247 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
248 AssemblerPredicate<"FeatureDB",
250 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
251 AssemblerPredicate<"FeatureMP",
253 def HasVirtualization: Predicate<"false">,
254 AssemblerPredicate<"FeatureVirtualization",
255 "virtualization-extensions">;
256 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
257 AssemblerPredicate<"FeatureTrustZone",
259 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
260 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
261 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
262 def IsThumb : Predicate<"Subtarget->isThumb()">,
263 AssemblerPredicate<"ModeThumb", "thumb">;
264 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
265 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
266 AssemblerPredicate<"ModeThumb,FeatureThumb2",
268 def IsMClass : Predicate<"Subtarget->isMClass()">,
269 AssemblerPredicate<"FeatureMClass", "armv*m">;
270 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
271 AssemblerPredicate<"!FeatureMClass",
273 def IsARM : Predicate<"!Subtarget->isThumb()">,
274 AssemblerPredicate<"!ModeThumb", "arm-mode">;
275 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
276 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
277 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
278 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
279 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
280 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
282 // FIXME: Eventually this will be just "hasV6T2Ops".
283 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
284 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
285 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
286 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
288 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
289 // But only select them if more precision in FP computation is allowed.
290 // Do not use them for Darwin platforms.
291 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
292 " FPOpFusion::Fast && "
293 " Subtarget->hasVFP4()) && "
294 "!Subtarget->isTargetDarwin()">;
295 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
296 " FPOpFusion::Fast &&"
297 " Subtarget->hasVFP4()) || "
298 "Subtarget->isTargetDarwin()">;
300 // VGETLNi32 is microcoded on Swift - prefer VMOV.
301 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
302 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
304 // VDUP.32 is microcoded on Swift - prefer VMOV.
305 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
306 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
308 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
309 // this allows more effective execution domain optimization. See
310 // setExecutionDomain().
311 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
312 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
314 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
315 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
317 //===----------------------------------------------------------------------===//
318 // ARM Flag Definitions.
320 class RegConstraint<string C> {
321 string Constraints = C;
324 //===----------------------------------------------------------------------===//
325 // ARM specific transformation functions and pattern fragments.
328 // imm_neg_XFORM - Return the negation of an i32 immediate value.
329 def imm_neg_XFORM : SDNodeXForm<imm, [{
330 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
333 // imm_not_XFORM - Return the complement of a i32 immediate value.
334 def imm_not_XFORM : SDNodeXForm<imm, [{
335 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
338 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
339 def imm16_31 : ImmLeaf<i32, [{
340 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
343 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
344 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
345 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
348 /// Split a 32-bit immediate into two 16 bit parts.
349 def hi16 : SDNodeXForm<imm, [{
350 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
354 def lo16AllZero : PatLeaf<(i32 imm), [{
355 // Returns true if all low 16-bits are 0.
356 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
359 class BinOpWithFlagFrag<dag res> :
360 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
361 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
362 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
364 // An 'and' node with a single use.
365 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
366 return N->hasOneUse();
369 // An 'xor' node with a single use.
370 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
371 return N->hasOneUse();
374 // An 'fmul' node with a single use.
375 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
376 return N->hasOneUse();
379 // An 'fadd' node which checks for single non-hazardous use.
380 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
381 return hasNoVMLxHazardUse(N);
384 // An 'fsub' node which checks for single non-hazardous use.
385 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
386 return hasNoVMLxHazardUse(N);
389 //===----------------------------------------------------------------------===//
390 // Operand Definitions.
393 // Immediate operands with a shared generic asm render method.
394 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
396 // Operands that are part of a memory addressing mode.
397 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
400 // FIXME: rename brtarget to t2_brtarget
401 def brtarget : Operand<OtherVT> {
402 let EncoderMethod = "getBranchTargetOpValue";
403 let OperandType = "OPERAND_PCREL";
404 let DecoderMethod = "DecodeT2BROperand";
407 // FIXME: get rid of this one?
408 def uncondbrtarget : Operand<OtherVT> {
409 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
410 let OperandType = "OPERAND_PCREL";
413 // Branch target for ARM. Handles conditional/unconditional
414 def br_target : Operand<OtherVT> {
415 let EncoderMethod = "getARMBranchTargetOpValue";
416 let OperandType = "OPERAND_PCREL";
420 // FIXME: rename bltarget to t2_bl_target?
421 def bltarget : Operand<i32> {
422 // Encoded the same as branch targets.
423 let EncoderMethod = "getBranchTargetOpValue";
424 let OperandType = "OPERAND_PCREL";
427 // Call target for ARM. Handles conditional/unconditional
428 // FIXME: rename bl_target to t2_bltarget?
429 def bl_target : Operand<i32> {
430 let EncoderMethod = "getARMBLTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 def blx_target : Operand<i32> {
435 let EncoderMethod = "getARMBLXTargetOpValue";
436 let OperandType = "OPERAND_PCREL";
439 // A list of registers separated by comma. Used by load/store multiple.
440 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
441 def reglist : Operand<i32> {
442 let EncoderMethod = "getRegisterListOpValue";
443 let ParserMatchClass = RegListAsmOperand;
444 let PrintMethod = "printRegisterList";
445 let DecoderMethod = "DecodeRegListOperand";
448 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
450 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
451 def dpr_reglist : Operand<i32> {
452 let EncoderMethod = "getRegisterListOpValue";
453 let ParserMatchClass = DPRRegListAsmOperand;
454 let PrintMethod = "printRegisterList";
455 let DecoderMethod = "DecodeDPRRegListOperand";
458 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
459 def spr_reglist : Operand<i32> {
460 let EncoderMethod = "getRegisterListOpValue";
461 let ParserMatchClass = SPRRegListAsmOperand;
462 let PrintMethod = "printRegisterList";
463 let DecoderMethod = "DecodeSPRRegListOperand";
466 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
467 def cpinst_operand : Operand<i32> {
468 let PrintMethod = "printCPInstOperand";
472 def pclabel : Operand<i32> {
473 let PrintMethod = "printPCLabel";
476 // ADR instruction labels.
477 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
478 def adrlabel : Operand<i32> {
479 let EncoderMethod = "getAdrLabelOpValue";
480 let ParserMatchClass = AdrLabelAsmOperand;
481 let PrintMethod = "printAdrLabelOperand<0>";
484 def neon_vcvt_imm32 : Operand<i32> {
485 let EncoderMethod = "getNEONVcvtImm32OpValue";
486 let DecoderMethod = "DecodeVCVTImmOperand";
489 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
490 def rot_imm_XFORM: SDNodeXForm<imm, [{
491 switch (N->getZExtValue()){
492 default: llvm_unreachable(nullptr);
493 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
494 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
495 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
496 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
499 def RotImmAsmOperand : AsmOperandClass {
501 let ParserMethod = "parseRotImm";
503 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
504 int32_t v = N->getZExtValue();
505 return v == 8 || v == 16 || v == 24; }],
507 let PrintMethod = "printRotImmOperand";
508 let ParserMatchClass = RotImmAsmOperand;
511 // shift_imm: An integer that encodes a shift amount and the type of shift
512 // (asr or lsl). The 6-bit immediate encodes as:
515 // {4-0} imm5 shift amount.
516 // asr #32 encoded as imm5 == 0.
517 def ShifterImmAsmOperand : AsmOperandClass {
518 let Name = "ShifterImm";
519 let ParserMethod = "parseShifterImm";
521 def shift_imm : Operand<i32> {
522 let PrintMethod = "printShiftImmOperand";
523 let ParserMatchClass = ShifterImmAsmOperand;
526 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
527 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
528 def so_reg_reg : Operand<i32>, // reg reg imm
529 ComplexPattern<i32, 3, "SelectRegShifterOperand",
530 [shl, srl, sra, rotr]> {
531 let EncoderMethod = "getSORegRegOpValue";
532 let PrintMethod = "printSORegRegOperand";
533 let DecoderMethod = "DecodeSORegRegOperand";
534 let ParserMatchClass = ShiftedRegAsmOperand;
535 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
538 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
539 def so_reg_imm : Operand<i32>, // reg imm
540 ComplexPattern<i32, 2, "SelectImmShifterOperand",
541 [shl, srl, sra, rotr]> {
542 let EncoderMethod = "getSORegImmOpValue";
543 let PrintMethod = "printSORegImmOperand";
544 let DecoderMethod = "DecodeSORegImmOperand";
545 let ParserMatchClass = ShiftedImmAsmOperand;
546 let MIOperandInfo = (ops GPR, i32imm);
549 // FIXME: Does this need to be distinct from so_reg?
550 def shift_so_reg_reg : Operand<i32>, // reg reg imm
551 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
552 [shl,srl,sra,rotr]> {
553 let EncoderMethod = "getSORegRegOpValue";
554 let PrintMethod = "printSORegRegOperand";
555 let DecoderMethod = "DecodeSORegRegOperand";
556 let ParserMatchClass = ShiftedRegAsmOperand;
557 let MIOperandInfo = (ops GPR, GPR, i32imm);
560 // FIXME: Does this need to be distinct from so_reg?
561 def shift_so_reg_imm : Operand<i32>, // reg reg imm
562 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
563 [shl,srl,sra,rotr]> {
564 let EncoderMethod = "getSORegImmOpValue";
565 let PrintMethod = "printSORegImmOperand";
566 let DecoderMethod = "DecodeSORegImmOperand";
567 let ParserMatchClass = ShiftedImmAsmOperand;
568 let MIOperandInfo = (ops GPR, i32imm);
571 // mod_imm: match a 32-bit immediate operand, which can be encoded into
572 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
573 // - "Modified Immediate Constants"). Within the MC layer we keep this
574 // immediate in its encoded form.
575 def ModImmAsmOperand: AsmOperandClass {
577 let ParserMethod = "parseModImm";
579 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
580 return ARM_AM::getSOImmVal(Imm) != -1;
582 let EncoderMethod = "getModImmOpValue";
583 let PrintMethod = "printModImmOperand";
584 let ParserMatchClass = ModImmAsmOperand;
587 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
588 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
589 // The actual parsing, encoding, decoding are handled by the destination
590 // instructions, which use mod_imm.
592 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
593 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
594 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
596 let ParserMatchClass = ModImmNotAsmOperand;
599 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
600 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
601 unsigned Value = -(unsigned)N->getZExtValue();
602 return Value && ARM_AM::getSOImmVal(Value) != -1;
604 let ParserMatchClass = ModImmNegAsmOperand;
607 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
608 def arm_i32imm : PatLeaf<(imm), [{
609 if (Subtarget->useMovt(*MF))
611 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
614 /// imm0_1 predicate - Immediate in the range [0,1].
615 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
616 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
618 /// imm0_3 predicate - Immediate in the range [0,3].
619 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
620 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
622 /// imm0_7 predicate - Immediate in the range [0,7].
623 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
624 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
625 return Imm >= 0 && Imm < 8;
627 let ParserMatchClass = Imm0_7AsmOperand;
630 /// imm8 predicate - Immediate is exactly 8.
631 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
632 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
633 let ParserMatchClass = Imm8AsmOperand;
636 /// imm16 predicate - Immediate is exactly 16.
637 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
638 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
639 let ParserMatchClass = Imm16AsmOperand;
642 /// imm32 predicate - Immediate is exactly 32.
643 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
644 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
645 let ParserMatchClass = Imm32AsmOperand;
648 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
650 /// imm1_7 predicate - Immediate in the range [1,7].
651 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
652 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
653 let ParserMatchClass = Imm1_7AsmOperand;
656 /// imm1_15 predicate - Immediate in the range [1,15].
657 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
658 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
659 let ParserMatchClass = Imm1_15AsmOperand;
662 /// imm1_31 predicate - Immediate in the range [1,31].
663 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
664 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
665 let ParserMatchClass = Imm1_31AsmOperand;
668 /// imm0_15 predicate - Immediate in the range [0,15].
669 def Imm0_15AsmOperand: ImmAsmOperand {
670 let Name = "Imm0_15";
671 let DiagnosticType = "ImmRange0_15";
673 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
674 return Imm >= 0 && Imm < 16;
676 let ParserMatchClass = Imm0_15AsmOperand;
679 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
680 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
681 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
682 return Imm >= 0 && Imm < 32;
684 let ParserMatchClass = Imm0_31AsmOperand;
687 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
688 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
689 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
690 return Imm >= 0 && Imm < 32;
692 let ParserMatchClass = Imm0_32AsmOperand;
695 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
696 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
697 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
698 return Imm >= 0 && Imm < 64;
700 let ParserMatchClass = Imm0_63AsmOperand;
703 /// imm0_239 predicate - Immediate in the range [0,239].
704 def Imm0_239AsmOperand : ImmAsmOperand {
705 let Name = "Imm0_239";
706 let DiagnosticType = "ImmRange0_239";
708 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
709 let ParserMatchClass = Imm0_239AsmOperand;
712 /// imm0_255 predicate - Immediate in the range [0,255].
713 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
714 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
715 let ParserMatchClass = Imm0_255AsmOperand;
718 /// imm0_65535 - An immediate is in the range [0.65535].
719 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
720 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
721 return Imm >= 0 && Imm < 65536;
723 let ParserMatchClass = Imm0_65535AsmOperand;
726 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
727 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
728 return -Imm >= 0 && -Imm < 65536;
731 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
732 // a relocatable expression.
734 // FIXME: This really needs a Thumb version separate from the ARM version.
735 // While the range is the same, and can thus use the same match class,
736 // the encoding is different so it should have a different encoder method.
737 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
738 def imm0_65535_expr : Operand<i32> {
739 let EncoderMethod = "getHiLo16ImmOpValue";
740 let ParserMatchClass = Imm0_65535ExprAsmOperand;
743 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
744 def imm256_65535_expr : Operand<i32> {
745 let ParserMatchClass = Imm256_65535ExprAsmOperand;
748 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
749 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
750 def imm24b : Operand<i32>, ImmLeaf<i32, [{
751 return Imm >= 0 && Imm <= 0xffffff;
753 let ParserMatchClass = Imm24bitAsmOperand;
757 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
759 def BitfieldAsmOperand : AsmOperandClass {
760 let Name = "Bitfield";
761 let ParserMethod = "parseBitfield";
764 def bf_inv_mask_imm : Operand<i32>,
766 return ARM::isBitFieldInvertedMask(N->getZExtValue());
768 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
769 let PrintMethod = "printBitfieldInvMaskImmOperand";
770 let DecoderMethod = "DecodeBitfieldMaskOperand";
771 let ParserMatchClass = BitfieldAsmOperand;
774 def imm1_32_XFORM: SDNodeXForm<imm, [{
775 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
778 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
779 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
780 uint64_t Imm = N->getZExtValue();
781 return Imm > 0 && Imm <= 32;
784 let PrintMethod = "printImmPlusOneOperand";
785 let ParserMatchClass = Imm1_32AsmOperand;
788 def imm1_16_XFORM: SDNodeXForm<imm, [{
789 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
792 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
793 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
795 let PrintMethod = "printImmPlusOneOperand";
796 let ParserMatchClass = Imm1_16AsmOperand;
799 // Define ARM specific addressing modes.
800 // addrmode_imm12 := reg +/- imm12
802 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
803 class AddrMode_Imm12 : MemOperand,
804 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
805 // 12-bit immediate operand. Note that instructions using this encode
806 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
807 // immediate values are as normal.
809 let EncoderMethod = "getAddrModeImm12OpValue";
810 let DecoderMethod = "DecodeAddrModeImm12Operand";
811 let ParserMatchClass = MemImm12OffsetAsmOperand;
812 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
815 def addrmode_imm12 : AddrMode_Imm12 {
816 let PrintMethod = "printAddrModeImm12Operand<false>";
819 def addrmode_imm12_pre : AddrMode_Imm12 {
820 let PrintMethod = "printAddrModeImm12Operand<true>";
823 // ldst_so_reg := reg +/- reg shop imm
825 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
826 def ldst_so_reg : MemOperand,
827 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
828 let EncoderMethod = "getLdStSORegOpValue";
829 // FIXME: Simplify the printer
830 let PrintMethod = "printAddrMode2Operand";
831 let DecoderMethod = "DecodeSORegMemOperand";
832 let ParserMatchClass = MemRegOffsetAsmOperand;
833 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
836 // postidx_imm8 := +/- [0,255]
839 // {8} 1 is imm8 is non-negative. 0 otherwise.
840 // {7-0} [0,255] imm8 value.
841 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
842 def postidx_imm8 : MemOperand {
843 let PrintMethod = "printPostIdxImm8Operand";
844 let ParserMatchClass = PostIdxImm8AsmOperand;
845 let MIOperandInfo = (ops i32imm);
848 // postidx_imm8s4 := +/- [0,1020]
851 // {8} 1 is imm8 is non-negative. 0 otherwise.
852 // {7-0} [0,255] imm8 value, scaled by 4.
853 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
854 def postidx_imm8s4 : MemOperand {
855 let PrintMethod = "printPostIdxImm8s4Operand";
856 let ParserMatchClass = PostIdxImm8s4AsmOperand;
857 let MIOperandInfo = (ops i32imm);
861 // postidx_reg := +/- reg
863 def PostIdxRegAsmOperand : AsmOperandClass {
864 let Name = "PostIdxReg";
865 let ParserMethod = "parsePostIdxReg";
867 def postidx_reg : MemOperand {
868 let EncoderMethod = "getPostIdxRegOpValue";
869 let DecoderMethod = "DecodePostIdxReg";
870 let PrintMethod = "printPostIdxRegOperand";
871 let ParserMatchClass = PostIdxRegAsmOperand;
872 let MIOperandInfo = (ops GPRnopc, i32imm);
876 // addrmode2 := reg +/- imm12
877 // := reg +/- reg shop imm
879 // FIXME: addrmode2 should be refactored the rest of the way to always
880 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
881 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
882 def addrmode2 : MemOperand,
883 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
884 let EncoderMethod = "getAddrMode2OpValue";
885 let PrintMethod = "printAddrMode2Operand";
886 let ParserMatchClass = AddrMode2AsmOperand;
887 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
890 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
891 let Name = "PostIdxRegShifted";
892 let ParserMethod = "parsePostIdxReg";
894 def am2offset_reg : MemOperand,
895 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
896 [], [SDNPWantRoot]> {
897 let EncoderMethod = "getAddrMode2OffsetOpValue";
898 let PrintMethod = "printAddrMode2OffsetOperand";
899 // When using this for assembly, it's always as a post-index offset.
900 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
901 let MIOperandInfo = (ops GPRnopc, i32imm);
904 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
905 // the GPR is purely vestigal at this point.
906 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
907 def am2offset_imm : MemOperand,
908 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
909 [], [SDNPWantRoot]> {
910 let EncoderMethod = "getAddrMode2OffsetOpValue";
911 let PrintMethod = "printAddrMode2OffsetOperand";
912 let ParserMatchClass = AM2OffsetImmAsmOperand;
913 let MIOperandInfo = (ops GPRnopc, i32imm);
917 // addrmode3 := reg +/- reg
918 // addrmode3 := reg +/- imm8
920 // FIXME: split into imm vs. reg versions.
921 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
922 class AddrMode3 : MemOperand,
923 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
924 let EncoderMethod = "getAddrMode3OpValue";
925 let ParserMatchClass = AddrMode3AsmOperand;
926 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
929 def addrmode3 : AddrMode3
931 let PrintMethod = "printAddrMode3Operand<false>";
934 def addrmode3_pre : AddrMode3
936 let PrintMethod = "printAddrMode3Operand<true>";
939 // FIXME: split into imm vs. reg versions.
940 // FIXME: parser method to handle +/- register.
941 def AM3OffsetAsmOperand : AsmOperandClass {
942 let Name = "AM3Offset";
943 let ParserMethod = "parseAM3Offset";
945 def am3offset : MemOperand,
946 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
947 [], [SDNPWantRoot]> {
948 let EncoderMethod = "getAddrMode3OffsetOpValue";
949 let PrintMethod = "printAddrMode3OffsetOperand";
950 let ParserMatchClass = AM3OffsetAsmOperand;
951 let MIOperandInfo = (ops GPR, i32imm);
954 // ldstm_mode := {ia, ib, da, db}
956 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
957 let EncoderMethod = "getLdStmModeOpValue";
958 let PrintMethod = "printLdStmModeOperand";
961 // addrmode5 := reg +/- imm8*4
963 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
964 class AddrMode5 : MemOperand,
965 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
966 let EncoderMethod = "getAddrMode5OpValue";
967 let DecoderMethod = "DecodeAddrMode5Operand";
968 let ParserMatchClass = AddrMode5AsmOperand;
969 let MIOperandInfo = (ops GPR:$base, i32imm);
972 def addrmode5 : AddrMode5 {
973 let PrintMethod = "printAddrMode5Operand<false>";
976 def addrmode5_pre : AddrMode5 {
977 let PrintMethod = "printAddrMode5Operand<true>";
980 // addrmode6 := reg with optional alignment
982 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
983 def addrmode6 : MemOperand,
984 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
985 let PrintMethod = "printAddrMode6Operand";
986 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
987 let EncoderMethod = "getAddrMode6AddressOpValue";
988 let DecoderMethod = "DecodeAddrMode6Operand";
989 let ParserMatchClass = AddrMode6AsmOperand;
992 def am6offset : MemOperand,
993 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
994 [], [SDNPWantRoot]> {
995 let PrintMethod = "printAddrMode6OffsetOperand";
996 let MIOperandInfo = (ops GPR);
997 let EncoderMethod = "getAddrMode6OffsetOpValue";
998 let DecoderMethod = "DecodeGPRRegisterClass";
1001 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1002 // (single element from one lane) for size 32.
1003 def addrmode6oneL32 : MemOperand,
1004 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1005 let PrintMethod = "printAddrMode6Operand";
1006 let MIOperandInfo = (ops GPR:$addr, i32imm);
1007 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1010 // Base class for addrmode6 with specific alignment restrictions.
1011 class AddrMode6Align : MemOperand,
1012 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1013 let PrintMethod = "printAddrMode6Operand";
1014 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1015 let EncoderMethod = "getAddrMode6AddressOpValue";
1016 let DecoderMethod = "DecodeAddrMode6Operand";
1019 // Special version of addrmode6 to handle no allowed alignment encoding for
1020 // VLD/VST instructions and checking the alignment is not specified.
1021 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1022 let Name = "AlignedMemoryNone";
1023 let DiagnosticType = "AlignedMemoryRequiresNone";
1025 def addrmode6alignNone : AddrMode6Align {
1026 // The alignment specifier can only be omitted.
1027 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1030 // Special version of addrmode6 to handle 16-bit alignment encoding for
1031 // VLD/VST instructions and checking the alignment value.
1032 def AddrMode6Align16AsmOperand : AsmOperandClass {
1033 let Name = "AlignedMemory16";
1034 let DiagnosticType = "AlignedMemoryRequires16";
1036 def addrmode6align16 : AddrMode6Align {
1037 // The alignment specifier can only be 16 or omitted.
1038 let ParserMatchClass = AddrMode6Align16AsmOperand;
1041 // Special version of addrmode6 to handle 32-bit alignment encoding for
1042 // VLD/VST instructions and checking the alignment value.
1043 def AddrMode6Align32AsmOperand : AsmOperandClass {
1044 let Name = "AlignedMemory32";
1045 let DiagnosticType = "AlignedMemoryRequires32";
1047 def addrmode6align32 : AddrMode6Align {
1048 // The alignment specifier can only be 32 or omitted.
1049 let ParserMatchClass = AddrMode6Align32AsmOperand;
1052 // Special version of addrmode6 to handle 64-bit alignment encoding for
1053 // VLD/VST instructions and checking the alignment value.
1054 def AddrMode6Align64AsmOperand : AsmOperandClass {
1055 let Name = "AlignedMemory64";
1056 let DiagnosticType = "AlignedMemoryRequires64";
1058 def addrmode6align64 : AddrMode6Align {
1059 // The alignment specifier can only be 64 or omitted.
1060 let ParserMatchClass = AddrMode6Align64AsmOperand;
1063 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1064 // for VLD/VST instructions and checking the alignment value.
1065 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1066 let Name = "AlignedMemory64or128";
1067 let DiagnosticType = "AlignedMemoryRequires64or128";
1069 def addrmode6align64or128 : AddrMode6Align {
1070 // The alignment specifier can only be 64, 128 or omitted.
1071 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1074 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1075 // encoding for VLD/VST instructions and checking the alignment value.
1076 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1077 let Name = "AlignedMemory64or128or256";
1078 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1080 def addrmode6align64or128or256 : AddrMode6Align {
1081 // The alignment specifier can only be 64, 128, 256 or omitted.
1082 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1085 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1086 // instructions, specifically VLD4-dup.
1087 def addrmode6dup : MemOperand,
1088 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1089 let PrintMethod = "printAddrMode6Operand";
1090 let MIOperandInfo = (ops GPR:$addr, i32imm);
1091 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1092 // FIXME: This is close, but not quite right. The alignment specifier is
1094 let ParserMatchClass = AddrMode6AsmOperand;
1097 // Base class for addrmode6dup with specific alignment restrictions.
1098 class AddrMode6DupAlign : MemOperand,
1099 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1100 let PrintMethod = "printAddrMode6Operand";
1101 let MIOperandInfo = (ops GPR:$addr, i32imm);
1102 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1105 // Special version of addrmode6 to handle no allowed alignment encoding for
1106 // VLD-dup instruction and checking the alignment is not specified.
1107 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1108 let Name = "DupAlignedMemoryNone";
1109 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1111 def addrmode6dupalignNone : AddrMode6DupAlign {
1112 // The alignment specifier can only be omitted.
1113 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1116 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1117 // instruction and checking the alignment value.
1118 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1119 let Name = "DupAlignedMemory16";
1120 let DiagnosticType = "DupAlignedMemoryRequires16";
1122 def addrmode6dupalign16 : AddrMode6DupAlign {
1123 // The alignment specifier can only be 16 or omitted.
1124 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1127 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1128 // instruction and checking the alignment value.
1129 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1130 let Name = "DupAlignedMemory32";
1131 let DiagnosticType = "DupAlignedMemoryRequires32";
1133 def addrmode6dupalign32 : AddrMode6DupAlign {
1134 // The alignment specifier can only be 32 or omitted.
1135 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1138 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1139 // instructions and checking the alignment value.
1140 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1141 let Name = "DupAlignedMemory64";
1142 let DiagnosticType = "DupAlignedMemoryRequires64";
1144 def addrmode6dupalign64 : AddrMode6DupAlign {
1145 // The alignment specifier can only be 64 or omitted.
1146 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1149 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1150 // for VLD instructions and checking the alignment value.
1151 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1152 let Name = "DupAlignedMemory64or128";
1153 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1155 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1156 // The alignment specifier can only be 64, 128 or omitted.
1157 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1160 // addrmodepc := pc + reg
1162 def addrmodepc : MemOperand,
1163 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1164 let PrintMethod = "printAddrModePCOperand";
1165 let MIOperandInfo = (ops GPR, i32imm);
1168 // addr_offset_none := reg
1170 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1171 def addr_offset_none : MemOperand,
1172 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1173 let PrintMethod = "printAddrMode7Operand";
1174 let DecoderMethod = "DecodeAddrMode7Operand";
1175 let ParserMatchClass = MemNoOffsetAsmOperand;
1176 let MIOperandInfo = (ops GPR:$base);
1179 def nohash_imm : Operand<i32> {
1180 let PrintMethod = "printNoHashImmediate";
1183 def CoprocNumAsmOperand : AsmOperandClass {
1184 let Name = "CoprocNum";
1185 let ParserMethod = "parseCoprocNumOperand";
1187 def p_imm : Operand<i32> {
1188 let PrintMethod = "printPImmediate";
1189 let ParserMatchClass = CoprocNumAsmOperand;
1190 let DecoderMethod = "DecodeCoprocessor";
1193 def CoprocRegAsmOperand : AsmOperandClass {
1194 let Name = "CoprocReg";
1195 let ParserMethod = "parseCoprocRegOperand";
1197 def c_imm : Operand<i32> {
1198 let PrintMethod = "printCImmediate";
1199 let ParserMatchClass = CoprocRegAsmOperand;
1201 def CoprocOptionAsmOperand : AsmOperandClass {
1202 let Name = "CoprocOption";
1203 let ParserMethod = "parseCoprocOptionOperand";
1205 def coproc_option_imm : Operand<i32> {
1206 let PrintMethod = "printCoprocOptionImm";
1207 let ParserMatchClass = CoprocOptionAsmOperand;
1210 //===----------------------------------------------------------------------===//
1212 include "ARMInstrFormats.td"
1214 //===----------------------------------------------------------------------===//
1215 // Multiclass helpers...
1218 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1219 /// binop that produces a value.
1220 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1221 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1222 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1223 PatFrag opnode, bit Commutable = 0> {
1224 // The register-immediate version is re-materializable. This is useful
1225 // in particular for taking the address of a local.
1226 let isReMaterializable = 1 in {
1227 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1228 iii, opc, "\t$Rd, $Rn, $imm",
1229 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1230 Sched<[WriteALU, ReadALU]> {
1235 let Inst{19-16} = Rn;
1236 let Inst{15-12} = Rd;
1237 let Inst{11-0} = imm;
1240 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1241 iir, opc, "\t$Rd, $Rn, $Rm",
1242 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1243 Sched<[WriteALU, ReadALU, ReadALU]> {
1248 let isCommutable = Commutable;
1249 let Inst{19-16} = Rn;
1250 let Inst{15-12} = Rd;
1251 let Inst{11-4} = 0b00000000;
1255 def rsi : AsI1<opcod, (outs GPR:$Rd),
1256 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1257 iis, opc, "\t$Rd, $Rn, $shift",
1258 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1259 Sched<[WriteALUsi, ReadALU]> {
1264 let Inst{19-16} = Rn;
1265 let Inst{15-12} = Rd;
1266 let Inst{11-5} = shift{11-5};
1268 let Inst{3-0} = shift{3-0};
1271 def rsr : AsI1<opcod, (outs GPR:$Rd),
1272 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1273 iis, opc, "\t$Rd, $Rn, $shift",
1274 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1275 Sched<[WriteALUsr, ReadALUsr]> {
1280 let Inst{19-16} = Rn;
1281 let Inst{15-12} = Rd;
1282 let Inst{11-8} = shift{11-8};
1284 let Inst{6-5} = shift{6-5};
1286 let Inst{3-0} = shift{3-0};
1290 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1291 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1292 /// it is equivalent to the AsI1_bin_irs counterpart.
1293 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1294 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1295 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1296 PatFrag opnode, bit Commutable = 0> {
1297 // The register-immediate version is re-materializable. This is useful
1298 // in particular for taking the address of a local.
1299 let isReMaterializable = 1 in {
1300 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1301 iii, opc, "\t$Rd, $Rn, $imm",
1302 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1303 Sched<[WriteALU, ReadALU]> {
1308 let Inst{19-16} = Rn;
1309 let Inst{15-12} = Rd;
1310 let Inst{11-0} = imm;
1313 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1314 iir, opc, "\t$Rd, $Rn, $Rm",
1315 [/* pattern left blank */]>,
1316 Sched<[WriteALU, ReadALU, ReadALU]> {
1320 let Inst{11-4} = 0b00000000;
1323 let Inst{15-12} = Rd;
1324 let Inst{19-16} = Rn;
1327 def rsi : AsI1<opcod, (outs GPR:$Rd),
1328 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1329 iis, opc, "\t$Rd, $Rn, $shift",
1330 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1331 Sched<[WriteALUsi, ReadALU]> {
1336 let Inst{19-16} = Rn;
1337 let Inst{15-12} = Rd;
1338 let Inst{11-5} = shift{11-5};
1340 let Inst{3-0} = shift{3-0};
1343 def rsr : AsI1<opcod, (outs GPR:$Rd),
1344 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1345 iis, opc, "\t$Rd, $Rn, $shift",
1346 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1347 Sched<[WriteALUsr, ReadALUsr]> {
1352 let Inst{19-16} = Rn;
1353 let Inst{15-12} = Rd;
1354 let Inst{11-8} = shift{11-8};
1356 let Inst{6-5} = shift{6-5};
1358 let Inst{3-0} = shift{3-0};
1362 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1364 /// These opcodes will be converted to the real non-S opcodes by
1365 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1366 let hasPostISelHook = 1, Defs = [CPSR] in {
1367 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1368 InstrItinClass iis, PatFrag opnode,
1369 bit Commutable = 0> {
1370 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1372 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1373 Sched<[WriteALU, ReadALU]>;
1375 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1377 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1378 Sched<[WriteALU, ReadALU, ReadALU]> {
1379 let isCommutable = Commutable;
1381 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1382 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1384 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1385 so_reg_imm:$shift))]>,
1386 Sched<[WriteALUsi, ReadALU]>;
1388 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1389 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1391 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1392 so_reg_reg:$shift))]>,
1393 Sched<[WriteALUSsr, ReadALUsr]>;
1397 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1398 /// operands are reversed.
1399 let hasPostISelHook = 1, Defs = [CPSR] in {
1400 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1401 InstrItinClass iis, PatFrag opnode,
1402 bit Commutable = 0> {
1403 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1405 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1406 Sched<[WriteALU, ReadALU]>;
1408 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1409 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1411 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1413 Sched<[WriteALUsi, ReadALU]>;
1415 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1416 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1418 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1420 Sched<[WriteALUSsr, ReadALUsr]>;
1424 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1425 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1426 /// a explicit result, only implicitly set CPSR.
1427 let isCompare = 1, Defs = [CPSR] in {
1428 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1429 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1430 PatFrag opnode, bit Commutable = 0,
1431 string rrDecoderMethod = ""> {
1432 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1434 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1435 Sched<[WriteCMP, ReadALU]> {
1440 let Inst{19-16} = Rn;
1441 let Inst{15-12} = 0b0000;
1442 let Inst{11-0} = imm;
1444 let Unpredictable{15-12} = 0b1111;
1446 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1448 [(opnode GPR:$Rn, GPR:$Rm)]>,
1449 Sched<[WriteCMP, ReadALU, ReadALU]> {
1452 let isCommutable = Commutable;
1455 let Inst{19-16} = Rn;
1456 let Inst{15-12} = 0b0000;
1457 let Inst{11-4} = 0b00000000;
1459 let DecoderMethod = rrDecoderMethod;
1461 let Unpredictable{15-12} = 0b1111;
1463 def rsi : AI1<opcod, (outs),
1464 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1465 opc, "\t$Rn, $shift",
1466 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1467 Sched<[WriteCMPsi, ReadALU]> {
1472 let Inst{19-16} = Rn;
1473 let Inst{15-12} = 0b0000;
1474 let Inst{11-5} = shift{11-5};
1476 let Inst{3-0} = shift{3-0};
1478 let Unpredictable{15-12} = 0b1111;
1480 def rsr : AI1<opcod, (outs),
1481 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1482 opc, "\t$Rn, $shift",
1483 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1484 Sched<[WriteCMPsr, ReadALU]> {
1489 let Inst{19-16} = Rn;
1490 let Inst{15-12} = 0b0000;
1491 let Inst{11-8} = shift{11-8};
1493 let Inst{6-5} = shift{6-5};
1495 let Inst{3-0} = shift{3-0};
1497 let Unpredictable{15-12} = 0b1111;
1503 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1504 /// register and one whose operand is a register rotated by 8/16/24.
1505 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1506 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1507 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1508 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1509 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1510 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1514 let Inst{19-16} = 0b1111;
1515 let Inst{15-12} = Rd;
1516 let Inst{11-10} = rot;
1520 class AI_ext_rrot_np<bits<8> opcod, string opc>
1521 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1522 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1523 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1525 let Inst{19-16} = 0b1111;
1526 let Inst{11-10} = rot;
1529 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1530 /// register and one whose operand is a register rotated by 8/16/24.
1531 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1532 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1533 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1534 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1535 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1536 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1541 let Inst{19-16} = Rn;
1542 let Inst{15-12} = Rd;
1543 let Inst{11-10} = rot;
1544 let Inst{9-4} = 0b000111;
1548 class AI_exta_rrot_np<bits<8> opcod, string opc>
1549 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1550 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1551 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1554 let Inst{19-16} = Rn;
1555 let Inst{11-10} = rot;
1558 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1559 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1560 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1561 bit Commutable = 0> {
1562 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1563 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1564 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1565 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1567 Sched<[WriteALU, ReadALU]> {
1572 let Inst{15-12} = Rd;
1573 let Inst{19-16} = Rn;
1574 let Inst{11-0} = imm;
1576 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1577 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1578 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1580 Sched<[WriteALU, ReadALU, ReadALU]> {
1584 let Inst{11-4} = 0b00000000;
1586 let isCommutable = Commutable;
1588 let Inst{15-12} = Rd;
1589 let Inst{19-16} = Rn;
1591 def rsi : AsI1<opcod, (outs GPR:$Rd),
1592 (ins GPR:$Rn, so_reg_imm:$shift),
1593 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1594 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1596 Sched<[WriteALUsi, ReadALU]> {
1601 let Inst{19-16} = Rn;
1602 let Inst{15-12} = Rd;
1603 let Inst{11-5} = shift{11-5};
1605 let Inst{3-0} = shift{3-0};
1607 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1608 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1609 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1610 [(set GPRnopc:$Rd, CPSR,
1611 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1613 Sched<[WriteALUsr, ReadALUsr]> {
1618 let Inst{19-16} = Rn;
1619 let Inst{15-12} = Rd;
1620 let Inst{11-8} = shift{11-8};
1622 let Inst{6-5} = shift{6-5};
1624 let Inst{3-0} = shift{3-0};
1629 /// AI1_rsc_irs - Define instructions and patterns for rsc
1630 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1631 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1632 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1633 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1634 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1635 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1637 Sched<[WriteALU, ReadALU]> {
1642 let Inst{15-12} = Rd;
1643 let Inst{19-16} = Rn;
1644 let Inst{11-0} = imm;
1646 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1647 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1648 [/* pattern left blank */]>,
1649 Sched<[WriteALU, ReadALU, ReadALU]> {
1653 let Inst{11-4} = 0b00000000;
1656 let Inst{15-12} = Rd;
1657 let Inst{19-16} = Rn;
1659 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1660 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1661 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1663 Sched<[WriteALUsi, ReadALU]> {
1668 let Inst{19-16} = Rn;
1669 let Inst{15-12} = Rd;
1670 let Inst{11-5} = shift{11-5};
1672 let Inst{3-0} = shift{3-0};
1674 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1675 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1676 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1678 Sched<[WriteALUsr, ReadALUsr]> {
1683 let Inst{19-16} = Rn;
1684 let Inst{15-12} = Rd;
1685 let Inst{11-8} = shift{11-8};
1687 let Inst{6-5} = shift{6-5};
1689 let Inst{3-0} = shift{3-0};
1694 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1695 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1696 InstrItinClass iir, PatFrag opnode> {
1697 // Note: We use the complex addrmode_imm12 rather than just an input
1698 // GPR and a constrained immediate so that we can use this to match
1699 // frame index references and avoid matching constant pool references.
1700 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1701 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1702 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1705 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1706 let Inst{19-16} = addr{16-13}; // Rn
1707 let Inst{15-12} = Rt;
1708 let Inst{11-0} = addr{11-0}; // imm12
1710 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1711 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1712 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1715 let shift{4} = 0; // Inst{4} = 0
1716 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1717 let Inst{19-16} = shift{16-13}; // Rn
1718 let Inst{15-12} = Rt;
1719 let Inst{11-0} = shift{11-0};
1724 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1725 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1726 InstrItinClass iir, PatFrag opnode> {
1727 // Note: We use the complex addrmode_imm12 rather than just an input
1728 // GPR and a constrained immediate so that we can use this to match
1729 // frame index references and avoid matching constant pool references.
1730 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1731 (ins addrmode_imm12:$addr),
1732 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1733 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1736 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1737 let Inst{19-16} = addr{16-13}; // Rn
1738 let Inst{15-12} = Rt;
1739 let Inst{11-0} = addr{11-0}; // imm12
1741 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1742 (ins ldst_so_reg:$shift),
1743 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1744 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1747 let shift{4} = 0; // Inst{4} = 0
1748 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1749 let Inst{19-16} = shift{16-13}; // Rn
1750 let Inst{15-12} = Rt;
1751 let Inst{11-0} = shift{11-0};
1757 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1758 InstrItinClass iir, PatFrag opnode> {
1759 // Note: We use the complex addrmode_imm12 rather than just an input
1760 // GPR and a constrained immediate so that we can use this to match
1761 // frame index references and avoid matching constant pool references.
1762 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1763 (ins GPR:$Rt, addrmode_imm12:$addr),
1764 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1765 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1768 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1769 let Inst{19-16} = addr{16-13}; // Rn
1770 let Inst{15-12} = Rt;
1771 let Inst{11-0} = addr{11-0}; // imm12
1773 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1774 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1775 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1778 let shift{4} = 0; // Inst{4} = 0
1779 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1780 let Inst{19-16} = shift{16-13}; // Rn
1781 let Inst{15-12} = Rt;
1782 let Inst{11-0} = shift{11-0};
1786 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1787 InstrItinClass iir, PatFrag opnode> {
1788 // Note: We use the complex addrmode_imm12 rather than just an input
1789 // GPR and a constrained immediate so that we can use this to match
1790 // frame index references and avoid matching constant pool references.
1791 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1792 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1793 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1794 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1797 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1798 let Inst{19-16} = addr{16-13}; // Rn
1799 let Inst{15-12} = Rt;
1800 let Inst{11-0} = addr{11-0}; // imm12
1802 def rs : AI2ldst<0b011, 0, isByte, (outs),
1803 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1804 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1805 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1808 let shift{4} = 0; // Inst{4} = 0
1809 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1810 let Inst{19-16} = shift{16-13}; // Rn
1811 let Inst{15-12} = Rt;
1812 let Inst{11-0} = shift{11-0};
1817 //===----------------------------------------------------------------------===//
1819 //===----------------------------------------------------------------------===//
1821 //===----------------------------------------------------------------------===//
1822 // Miscellaneous Instructions.
1825 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1826 /// the function. The first operand is the ID# for this instruction, the second
1827 /// is the index into the MachineConstantPool that this is, the third is the
1828 /// size in bytes of this constant pool entry.
1829 let hasSideEffects = 0, isNotDuplicable = 1 in
1830 def CONSTPOOL_ENTRY :
1831 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1832 i32imm:$size), NoItinerary, []>;
1834 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1835 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1836 /// mode). Used mostly in ARM and Thumb-1 modes.
1837 def JUMPTABLE_ADDRS :
1838 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1839 i32imm:$size), NoItinerary, []>;
1841 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1842 /// that cannot be optimised to use TBB or TBH.
1843 def JUMPTABLE_INSTS :
1844 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1845 i32imm:$size), NoItinerary, []>;
1847 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1848 /// a TBB instruction.
1850 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1851 i32imm:$size), NoItinerary, []>;
1853 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1854 /// a TBH instruction.
1856 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1857 i32imm:$size), NoItinerary, []>;
1860 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1861 // from removing one half of the matched pairs. That breaks PEI, which assumes
1862 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1863 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1864 def ADJCALLSTACKUP :
1865 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1866 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1868 def ADJCALLSTACKDOWN :
1869 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1870 [(ARMcallseq_start timm:$amt)]>;
1873 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1874 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1875 Requires<[IsARM, HasV6]> {
1877 let Inst{27-8} = 0b00110010000011110000;
1878 let Inst{7-0} = imm;
1881 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1882 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1883 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1884 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1885 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1886 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1888 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1889 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1894 let Inst{15-12} = Rd;
1895 let Inst{19-16} = Rn;
1896 let Inst{27-20} = 0b01101000;
1897 let Inst{7-4} = 0b1011;
1898 let Inst{11-8} = 0b1111;
1899 let Unpredictable{11-8} = 0b1111;
1902 // The 16-bit operand $val can be used by a debugger to store more information
1903 // about the breakpoint.
1904 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1905 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1907 let Inst{3-0} = val{3-0};
1908 let Inst{19-8} = val{15-4};
1909 let Inst{27-20} = 0b00010010;
1910 let Inst{31-28} = 0xe; // AL
1911 let Inst{7-4} = 0b0111;
1913 // default immediate for breakpoint mnemonic
1914 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1916 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1917 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1919 let Inst{3-0} = val{3-0};
1920 let Inst{19-8} = val{15-4};
1921 let Inst{27-20} = 0b00010000;
1922 let Inst{31-28} = 0xe; // AL
1923 let Inst{7-4} = 0b0111;
1926 // Change Processor State
1927 // FIXME: We should use InstAlias to handle the optional operands.
1928 class CPS<dag iops, string asm_ops>
1929 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1930 []>, Requires<[IsARM]> {
1936 let Inst{31-28} = 0b1111;
1937 let Inst{27-20} = 0b00010000;
1938 let Inst{19-18} = imod;
1939 let Inst{17} = M; // Enabled if mode is set;
1940 let Inst{16-9} = 0b00000000;
1941 let Inst{8-6} = iflags;
1943 let Inst{4-0} = mode;
1946 let DecoderMethod = "DecodeCPSInstruction" in {
1948 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1949 "$imod\t$iflags, $mode">;
1950 let mode = 0, M = 0 in
1951 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1953 let imod = 0, iflags = 0, M = 1 in
1954 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1957 // Preload signals the memory system of possible future data/instruction access.
1958 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1960 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1961 IIC_Preload, !strconcat(opc, "\t$addr"),
1962 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1963 Sched<[WritePreLd]> {
1966 let Inst{31-26} = 0b111101;
1967 let Inst{25} = 0; // 0 for immediate form
1968 let Inst{24} = data;
1969 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1970 let Inst{22} = read;
1971 let Inst{21-20} = 0b01;
1972 let Inst{19-16} = addr{16-13}; // Rn
1973 let Inst{15-12} = 0b1111;
1974 let Inst{11-0} = addr{11-0}; // imm12
1977 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1978 !strconcat(opc, "\t$shift"),
1979 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1980 Sched<[WritePreLd]> {
1982 let Inst{31-26} = 0b111101;
1983 let Inst{25} = 1; // 1 for register form
1984 let Inst{24} = data;
1985 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1986 let Inst{22} = read;
1987 let Inst{21-20} = 0b01;
1988 let Inst{19-16} = shift{16-13}; // Rn
1989 let Inst{15-12} = 0b1111;
1990 let Inst{11-0} = shift{11-0};
1995 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1996 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1997 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1999 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
2000 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2002 let Inst{31-10} = 0b1111000100000001000000;
2007 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2008 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2010 let Inst{27-4} = 0b001100100000111100001111;
2011 let Inst{3-0} = opt;
2014 // A8.8.247 UDF - Undefined (Encoding A1)
2015 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2016 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2018 let Inst{31-28} = 0b1110; // AL
2019 let Inst{27-25} = 0b011;
2020 let Inst{24-20} = 0b11111;
2021 let Inst{19-8} = imm16{15-4};
2022 let Inst{7-4} = 0b1111;
2023 let Inst{3-0} = imm16{3-0};
2027 * A5.4 Permanently UNDEFINED instructions.
2029 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2030 * Other UDF encodings generate SIGILL.
2032 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2034 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2036 * 1101 1110 iiii iiii
2037 * It uses the following encoding:
2038 * 1110 0111 1111 1110 1101 1110 1111 0000
2039 * - In ARM: UDF #60896;
2040 * - In Thumb: UDF #254 followed by a branch-to-self.
2042 let isBarrier = 1, isTerminator = 1 in
2043 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2045 Requires<[IsARM,UseNaClTrap]> {
2046 let Inst = 0xe7fedef0;
2048 let isBarrier = 1, isTerminator = 1 in
2049 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2051 Requires<[IsARM,DontUseNaClTrap]> {
2052 let Inst = 0xe7ffdefe;
2055 // Address computation and loads and stores in PIC mode.
2056 let isNotDuplicable = 1 in {
2057 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2059 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2060 Sched<[WriteALU, ReadALU]>;
2062 let AddedComplexity = 10 in {
2063 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2065 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2067 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2069 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2071 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2073 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2075 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2077 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2079 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2081 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2083 let AddedComplexity = 10 in {
2084 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2085 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2087 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2088 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2089 addrmodepc:$addr)]>;
2091 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2092 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2094 } // isNotDuplicable = 1
2097 // LEApcrel - Load a pc-relative address into a register without offending the
2099 let hasSideEffects = 0, isReMaterializable = 1 in
2100 // The 'adr' mnemonic encodes differently if the label is before or after
2101 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2102 // know until then which form of the instruction will be used.
2103 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2104 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2105 Sched<[WriteALU, ReadALU]> {
2108 let Inst{27-25} = 0b001;
2110 let Inst{23-22} = label{13-12};
2113 let Inst{19-16} = 0b1111;
2114 let Inst{15-12} = Rd;
2115 let Inst{11-0} = label{11-0};
2118 let hasSideEffects = 1 in {
2119 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2120 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2122 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2123 (ins i32imm:$label, pred:$p),
2124 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2127 //===----------------------------------------------------------------------===//
2128 // Control Flow Instructions.
2131 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2133 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2134 "bx", "\tlr", [(ARMretflag)]>,
2135 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2136 let Inst{27-0} = 0b0001001011111111111100011110;
2140 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2141 "mov", "\tpc, lr", [(ARMretflag)]>,
2142 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2143 let Inst{27-0} = 0b0001101000001111000000001110;
2146 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2147 // the user-space one).
2148 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2150 [(ARMintretflag imm:$offset)]>;
2153 // Indirect branches
2154 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2156 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2157 [(brind GPR:$dst)]>,
2158 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2160 let Inst{31-4} = 0b1110000100101111111111110001;
2161 let Inst{3-0} = dst;
2164 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2165 "bx", "\t$dst", [/* pattern left blank */]>,
2166 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2168 let Inst{27-4} = 0b000100101111111111110001;
2169 let Inst{3-0} = dst;
2173 // SP is marked as a use to prevent stack-pointer assignments that appear
2174 // immediately before calls from potentially appearing dead.
2176 // FIXME: Do we really need a non-predicated version? If so, it should
2177 // at least be a pseudo instruction expanding to the predicated version
2178 // at MC lowering time.
2179 Defs = [LR], Uses = [SP] in {
2180 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2181 IIC_Br, "bl\t$func",
2182 [(ARMcall tglobaladdr:$func)]>,
2183 Requires<[IsARM]>, Sched<[WriteBrL]> {
2184 let Inst{31-28} = 0b1110;
2186 let Inst{23-0} = func;
2187 let DecoderMethod = "DecodeBranchImmInstruction";
2190 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2191 IIC_Br, "bl", "\t$func",
2192 [(ARMcall_pred tglobaladdr:$func)]>,
2193 Requires<[IsARM]>, Sched<[WriteBrL]> {
2195 let Inst{23-0} = func;
2196 let DecoderMethod = "DecodeBranchImmInstruction";
2200 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2201 IIC_Br, "blx\t$func",
2202 [(ARMcall GPR:$func)]>,
2203 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2205 let Inst{31-4} = 0b1110000100101111111111110011;
2206 let Inst{3-0} = func;
2209 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2210 IIC_Br, "blx", "\t$func",
2211 [(ARMcall_pred GPR:$func)]>,
2212 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2214 let Inst{27-4} = 0b000100101111111111110011;
2215 let Inst{3-0} = func;
2219 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2220 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2221 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2222 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2225 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2226 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2227 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2229 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2230 // return stack predictor.
2231 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2232 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2233 Requires<[IsARM]>, Sched<[WriteBr]>;
2236 let isBranch = 1, isTerminator = 1 in {
2237 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2238 // a two-value operand where a dag node expects two operands. :(
2239 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2240 IIC_Br, "b", "\t$target",
2241 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2244 let Inst{23-0} = target;
2245 let DecoderMethod = "DecodeBranchImmInstruction";
2248 let isBarrier = 1 in {
2249 // B is "predicable" since it's just a Bcc with an 'always' condition.
2250 let isPredicable = 1 in
2251 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2252 // should be sufficient.
2253 // FIXME: Is B really a Barrier? That doesn't seem right.
2254 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2255 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2258 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2259 def BR_JTr : ARMPseudoInst<(outs),
2260 (ins GPR:$target, i32imm:$jt),
2262 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2264 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2265 // into i12 and rs suffixed versions.
2266 def BR_JTm : ARMPseudoInst<(outs),
2267 (ins addrmode2:$target, i32imm:$jt),
2269 [(ARMbrjt (i32 (load addrmode2:$target)),
2270 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2271 def BR_JTadd : ARMPseudoInst<(outs),
2272 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2274 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2275 Sched<[WriteBrTbl]>;
2276 } // isNotDuplicable = 1, isIndirectBranch = 1
2282 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2283 "blx\t$target", []>,
2284 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2285 let Inst{31-25} = 0b1111101;
2287 let Inst{23-0} = target{24-1};
2288 let Inst{24} = target{0};
2292 // Branch and Exchange Jazelle
2293 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2294 [/* pattern left blank */]>, Sched<[WriteBr]> {
2296 let Inst{23-20} = 0b0010;
2297 let Inst{19-8} = 0xfff;
2298 let Inst{7-4} = 0b0010;
2299 let Inst{3-0} = func;
2305 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2306 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2309 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2312 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2314 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2315 Requires<[IsARM]>, Sched<[WriteBr]>;
2317 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2319 (BX GPR:$dst)>, Sched<[WriteBr]>,
2323 // Secure Monitor Call is a system instruction.
2324 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2325 []>, Requires<[IsARM, HasTrustZone]> {
2327 let Inst{23-4} = 0b01100000000000000111;
2328 let Inst{3-0} = opt;
2330 def : MnemonicAlias<"smi", "smc">;
2332 // Supervisor Call (Software Interrupt)
2333 let isCall = 1, Uses = [SP] in {
2334 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2337 let Inst{23-0} = svc;
2341 // Store Return State
2342 class SRSI<bit wb, string asm>
2343 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2344 NoItinerary, asm, "", []> {
2346 let Inst{31-28} = 0b1111;
2347 let Inst{27-25} = 0b100;
2351 let Inst{19-16} = 0b1101; // SP
2352 let Inst{15-5} = 0b00000101000;
2353 let Inst{4-0} = mode;
2356 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2357 let Inst{24-23} = 0;
2359 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2360 let Inst{24-23} = 0;
2362 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2363 let Inst{24-23} = 0b10;
2365 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2366 let Inst{24-23} = 0b10;
2368 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2369 let Inst{24-23} = 0b01;
2371 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2372 let Inst{24-23} = 0b01;
2374 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2375 let Inst{24-23} = 0b11;
2377 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2378 let Inst{24-23} = 0b11;
2381 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2382 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2384 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2385 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2387 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2388 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2390 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2391 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2393 // Return From Exception
2394 class RFEI<bit wb, string asm>
2395 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2396 NoItinerary, asm, "", []> {
2398 let Inst{31-28} = 0b1111;
2399 let Inst{27-25} = 0b100;
2403 let Inst{19-16} = Rn;
2404 let Inst{15-0} = 0xa00;
2407 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2408 let Inst{24-23} = 0;
2410 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2411 let Inst{24-23} = 0;
2413 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2414 let Inst{24-23} = 0b10;
2416 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2417 let Inst{24-23} = 0b10;
2419 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2420 let Inst{24-23} = 0b01;
2422 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2423 let Inst{24-23} = 0b01;
2425 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2426 let Inst{24-23} = 0b11;
2428 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2429 let Inst{24-23} = 0b11;
2432 // Hypervisor Call is a system instruction
2434 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2435 "hvc", "\t$imm", []>,
2436 Requires<[IsARM, HasVirtualization]> {
2439 // Even though HVC isn't predicable, it's encoding includes a condition field.
2440 // The instruction is undefined if the condition field is 0xf otherwise it is
2441 // unpredictable if it isn't condition AL (0xe).
2442 let Inst{31-28} = 0b1110;
2443 let Unpredictable{31-28} = 0b1111;
2444 let Inst{27-24} = 0b0001;
2445 let Inst{23-20} = 0b0100;
2446 let Inst{19-8} = imm{15-4};
2447 let Inst{7-4} = 0b0111;
2448 let Inst{3-0} = imm{3-0};
2452 // Return from exception in Hypervisor mode.
2453 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2454 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2455 Requires<[IsARM, HasVirtualization]> {
2456 let Inst{23-0} = 0b011000000000000001101110;
2459 //===----------------------------------------------------------------------===//
2460 // Load / Store Instructions.
2466 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2467 UnOpFrag<(load node:$Src)>>;
2468 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2469 UnOpFrag<(zextloadi8 node:$Src)>>;
2470 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2471 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2472 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2473 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2475 // Special LDR for loads from non-pc-relative constpools.
2476 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2477 isReMaterializable = 1, isCodeGenOnly = 1 in
2478 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2479 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2483 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2484 let Inst{19-16} = 0b1111;
2485 let Inst{15-12} = Rt;
2486 let Inst{11-0} = addr{11-0}; // imm12
2489 // Loads with zero extension
2490 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2491 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2492 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2494 // Loads with sign extension
2495 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2496 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2497 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2499 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2500 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2501 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2503 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2505 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2506 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2507 Requires<[IsARM, HasV5TE]>;
2510 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2511 NoItinerary, "lda", "\t$Rt, $addr", []>;
2512 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2513 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2514 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2515 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2518 multiclass AI2_ldridx<bit isByte, string opc,
2519 InstrItinClass iii, InstrItinClass iir> {
2520 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2521 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2522 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2525 let Inst{23} = addr{12};
2526 let Inst{19-16} = addr{16-13};
2527 let Inst{11-0} = addr{11-0};
2528 let DecoderMethod = "DecodeLDRPreImm";
2531 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2532 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2533 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2536 let Inst{23} = addr{12};
2537 let Inst{19-16} = addr{16-13};
2538 let Inst{11-0} = addr{11-0};
2540 let DecoderMethod = "DecodeLDRPreReg";
2543 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2544 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2545 IndexModePost, LdFrm, iir,
2546 opc, "\t$Rt, $addr, $offset",
2547 "$addr.base = $Rn_wb", []> {
2553 let Inst{23} = offset{12};
2554 let Inst{19-16} = addr;
2555 let Inst{11-0} = offset{11-0};
2558 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2561 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2562 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2563 IndexModePost, LdFrm, iii,
2564 opc, "\t$Rt, $addr, $offset",
2565 "$addr.base = $Rn_wb", []> {
2571 let Inst{23} = offset{12};
2572 let Inst{19-16} = addr;
2573 let Inst{11-0} = offset{11-0};
2575 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2580 let mayLoad = 1, hasSideEffects = 0 in {
2581 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2582 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2583 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2584 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2587 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2588 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2589 (ins addrmode3_pre:$addr), IndexModePre,
2591 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2593 let Inst{23} = addr{8}; // U bit
2594 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2595 let Inst{19-16} = addr{12-9}; // Rn
2596 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2597 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2598 let DecoderMethod = "DecodeAddrMode3Instruction";
2600 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2601 (ins addr_offset_none:$addr, am3offset:$offset),
2602 IndexModePost, LdMiscFrm, itin,
2603 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2607 let Inst{23} = offset{8}; // U bit
2608 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2609 let Inst{19-16} = addr;
2610 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2611 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2612 let DecoderMethod = "DecodeAddrMode3Instruction";
2616 let mayLoad = 1, hasSideEffects = 0 in {
2617 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2618 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2619 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2620 let hasExtraDefRegAllocReq = 1 in {
2621 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2622 (ins addrmode3_pre:$addr), IndexModePre,
2623 LdMiscFrm, IIC_iLoad_d_ru,
2624 "ldrd", "\t$Rt, $Rt2, $addr!",
2625 "$addr.base = $Rn_wb", []> {
2627 let Inst{23} = addr{8}; // U bit
2628 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2629 let Inst{19-16} = addr{12-9}; // Rn
2630 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2631 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2632 let DecoderMethod = "DecodeAddrMode3Instruction";
2634 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2635 (ins addr_offset_none:$addr, am3offset:$offset),
2636 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2637 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2638 "$addr.base = $Rn_wb", []> {
2641 let Inst{23} = offset{8}; // U bit
2642 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2643 let Inst{19-16} = addr;
2644 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2645 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2646 let DecoderMethod = "DecodeAddrMode3Instruction";
2648 } // hasExtraDefRegAllocReq = 1
2649 } // mayLoad = 1, hasSideEffects = 0
2651 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2652 let mayLoad = 1, hasSideEffects = 0 in {
2653 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2654 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2655 IndexModePost, LdFrm, IIC_iLoad_ru,
2656 "ldrt", "\t$Rt, $addr, $offset",
2657 "$addr.base = $Rn_wb", []> {
2663 let Inst{23} = offset{12};
2664 let Inst{21} = 1; // overwrite
2665 let Inst{19-16} = addr;
2666 let Inst{11-5} = offset{11-5};
2668 let Inst{3-0} = offset{3-0};
2669 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2673 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2674 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2675 IndexModePost, LdFrm, IIC_iLoad_ru,
2676 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2682 let Inst{23} = offset{12};
2683 let Inst{21} = 1; // overwrite
2684 let Inst{19-16} = addr;
2685 let Inst{11-0} = offset{11-0};
2686 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2689 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2690 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2691 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2692 "ldrbt", "\t$Rt, $addr, $offset",
2693 "$addr.base = $Rn_wb", []> {
2699 let Inst{23} = offset{12};
2700 let Inst{21} = 1; // overwrite
2701 let Inst{19-16} = addr;
2702 let Inst{11-5} = offset{11-5};
2704 let Inst{3-0} = offset{3-0};
2705 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2709 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2710 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2711 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2712 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2718 let Inst{23} = offset{12};
2719 let Inst{21} = 1; // overwrite
2720 let Inst{19-16} = addr;
2721 let Inst{11-0} = offset{11-0};
2722 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2725 multiclass AI3ldrT<bits<4> op, string opc> {
2726 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2727 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2728 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2729 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2731 let Inst{23} = offset{8};
2733 let Inst{11-8} = offset{7-4};
2734 let Inst{3-0} = offset{3-0};
2736 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2737 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2738 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2739 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2741 let Inst{23} = Rm{4};
2744 let Unpredictable{11-8} = 0b1111;
2745 let Inst{3-0} = Rm{3-0};
2746 let DecoderMethod = "DecodeLDR";
2750 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2751 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2752 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2756 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2760 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2765 // Stores with truncate
2766 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2767 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2768 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2771 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2772 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2773 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2774 Requires<[IsARM, HasV5TE]> {
2780 multiclass AI2_stridx<bit isByte, string opc,
2781 InstrItinClass iii, InstrItinClass iir> {
2782 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2783 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2785 opc, "\t$Rt, $addr!",
2786 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2789 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2790 let Inst{19-16} = addr{16-13}; // Rn
2791 let Inst{11-0} = addr{11-0}; // imm12
2792 let DecoderMethod = "DecodeSTRPreImm";
2795 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2796 (ins GPR:$Rt, ldst_so_reg:$addr),
2797 IndexModePre, StFrm, iir,
2798 opc, "\t$Rt, $addr!",
2799 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2802 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2803 let Inst{19-16} = addr{16-13}; // Rn
2804 let Inst{11-0} = addr{11-0};
2805 let Inst{4} = 0; // Inst{4} = 0
2806 let DecoderMethod = "DecodeSTRPreReg";
2808 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2809 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2810 IndexModePost, StFrm, iir,
2811 opc, "\t$Rt, $addr, $offset",
2812 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2818 let Inst{23} = offset{12};
2819 let Inst{19-16} = addr;
2820 let Inst{11-0} = offset{11-0};
2823 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2826 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2827 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2828 IndexModePost, StFrm, iii,
2829 opc, "\t$Rt, $addr, $offset",
2830 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2836 let Inst{23} = offset{12};
2837 let Inst{19-16} = addr;
2838 let Inst{11-0} = offset{11-0};
2840 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2844 let mayStore = 1, hasSideEffects = 0 in {
2845 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2846 // IIC_iStore_siu depending on whether it the offset register is shifted.
2847 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2848 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2851 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2852 am2offset_reg:$offset),
2853 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2854 am2offset_reg:$offset)>;
2855 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2856 am2offset_imm:$offset),
2857 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2858 am2offset_imm:$offset)>;
2859 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2860 am2offset_reg:$offset),
2861 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2862 am2offset_reg:$offset)>;
2863 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2864 am2offset_imm:$offset),
2865 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2866 am2offset_imm:$offset)>;
2868 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2869 // put the patterns on the instruction definitions directly as ISel wants
2870 // the address base and offset to be separate operands, not a single
2871 // complex operand like we represent the instructions themselves. The
2872 // pseudos map between the two.
2873 let usesCustomInserter = 1,
2874 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2875 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2876 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2879 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2880 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2881 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2884 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2885 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2886 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2889 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2890 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2891 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2894 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2895 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2896 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2899 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2904 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2905 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2906 StMiscFrm, IIC_iStore_bh_ru,
2907 "strh", "\t$Rt, $addr!",
2908 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2910 let Inst{23} = addr{8}; // U bit
2911 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2912 let Inst{19-16} = addr{12-9}; // Rn
2913 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2914 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2915 let DecoderMethod = "DecodeAddrMode3Instruction";
2918 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2919 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2920 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2921 "strh", "\t$Rt, $addr, $offset",
2922 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2923 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2924 addr_offset_none:$addr,
2925 am3offset:$offset))]> {
2928 let Inst{23} = offset{8}; // U bit
2929 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2930 let Inst{19-16} = addr;
2931 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2932 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2933 let DecoderMethod = "DecodeAddrMode3Instruction";
2936 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2937 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2938 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2939 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2940 "strd", "\t$Rt, $Rt2, $addr!",
2941 "$addr.base = $Rn_wb", []> {
2943 let Inst{23} = addr{8}; // U bit
2944 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2945 let Inst{19-16} = addr{12-9}; // Rn
2946 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2947 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2948 let DecoderMethod = "DecodeAddrMode3Instruction";
2951 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2952 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2954 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2955 "strd", "\t$Rt, $Rt2, $addr, $offset",
2956 "$addr.base = $Rn_wb", []> {
2959 let Inst{23} = offset{8}; // U bit
2960 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2961 let Inst{19-16} = addr;
2962 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2963 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2964 let DecoderMethod = "DecodeAddrMode3Instruction";
2966 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2968 // STRT, STRBT, and STRHT
2970 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2971 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2972 IndexModePost, StFrm, IIC_iStore_bh_ru,
2973 "strbt", "\t$Rt, $addr, $offset",
2974 "$addr.base = $Rn_wb", []> {
2980 let Inst{23} = offset{12};
2981 let Inst{21} = 1; // overwrite
2982 let Inst{19-16} = addr;
2983 let Inst{11-5} = offset{11-5};
2985 let Inst{3-0} = offset{3-0};
2986 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2990 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2991 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2992 IndexModePost, StFrm, IIC_iStore_bh_ru,
2993 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2999 let Inst{23} = offset{12};
3000 let Inst{21} = 1; // overwrite
3001 let Inst{19-16} = addr;
3002 let Inst{11-0} = offset{11-0};
3003 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3007 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3008 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3010 let mayStore = 1, hasSideEffects = 0 in {
3011 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3012 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3013 IndexModePost, StFrm, IIC_iStore_ru,
3014 "strt", "\t$Rt, $addr, $offset",
3015 "$addr.base = $Rn_wb", []> {
3021 let Inst{23} = offset{12};
3022 let Inst{21} = 1; // overwrite
3023 let Inst{19-16} = addr;
3024 let Inst{11-5} = offset{11-5};
3026 let Inst{3-0} = offset{3-0};
3027 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3031 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3032 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3033 IndexModePost, StFrm, IIC_iStore_ru,
3034 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3040 let Inst{23} = offset{12};
3041 let Inst{21} = 1; // overwrite
3042 let Inst{19-16} = addr;
3043 let Inst{11-0} = offset{11-0};
3044 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3049 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3050 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3052 multiclass AI3strT<bits<4> op, string opc> {
3053 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3054 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3055 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3056 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3058 let Inst{23} = offset{8};
3060 let Inst{11-8} = offset{7-4};
3061 let Inst{3-0} = offset{3-0};
3063 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3064 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3065 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3066 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3068 let Inst{23} = Rm{4};
3071 let Inst{3-0} = Rm{3-0};
3076 defm STRHT : AI3strT<0b1011, "strht">;
3078 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3079 NoItinerary, "stl", "\t$Rt, $addr", []>;
3080 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3081 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3082 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3083 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3085 //===----------------------------------------------------------------------===//
3086 // Load / store multiple Instructions.
3089 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3090 InstrItinClass itin, InstrItinClass itin_upd> {
3091 // IA is the default, so no need for an explicit suffix on the
3092 // mnemonic here. Without it is the canonical spelling.
3094 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3095 IndexModeNone, f, itin,
3096 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3097 let Inst{24-23} = 0b01; // Increment After
3098 let Inst{22} = P_bit;
3099 let Inst{21} = 0; // No writeback
3100 let Inst{20} = L_bit;
3103 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3104 IndexModeUpd, f, itin_upd,
3105 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3106 let Inst{24-23} = 0b01; // Increment After
3107 let Inst{22} = P_bit;
3108 let Inst{21} = 1; // Writeback
3109 let Inst{20} = L_bit;
3111 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3114 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3115 IndexModeNone, f, itin,
3116 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3117 let Inst{24-23} = 0b00; // Decrement After
3118 let Inst{22} = P_bit;
3119 let Inst{21} = 0; // No writeback
3120 let Inst{20} = L_bit;
3123 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3124 IndexModeUpd, f, itin_upd,
3125 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3126 let Inst{24-23} = 0b00; // Decrement After
3127 let Inst{22} = P_bit;
3128 let Inst{21} = 1; // Writeback
3129 let Inst{20} = L_bit;
3131 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3134 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3135 IndexModeNone, f, itin,
3136 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3137 let Inst{24-23} = 0b10; // Decrement Before
3138 let Inst{22} = P_bit;
3139 let Inst{21} = 0; // No writeback
3140 let Inst{20} = L_bit;
3143 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3144 IndexModeUpd, f, itin_upd,
3145 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3146 let Inst{24-23} = 0b10; // Decrement Before
3147 let Inst{22} = P_bit;
3148 let Inst{21} = 1; // Writeback
3149 let Inst{20} = L_bit;
3151 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3154 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3155 IndexModeNone, f, itin,
3156 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3157 let Inst{24-23} = 0b11; // Increment Before
3158 let Inst{22} = P_bit;
3159 let Inst{21} = 0; // No writeback
3160 let Inst{20} = L_bit;
3163 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3164 IndexModeUpd, f, itin_upd,
3165 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3166 let Inst{24-23} = 0b11; // Increment Before
3167 let Inst{22} = P_bit;
3168 let Inst{21} = 1; // Writeback
3169 let Inst{20} = L_bit;
3171 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3175 let hasSideEffects = 0 in {
3177 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3178 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3179 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3181 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3182 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3184 ComplexDeprecationPredicate<"ARMStore">;
3188 // FIXME: remove when we have a way to marking a MI with these properties.
3189 // FIXME: Should pc be an implicit operand like PICADD, etc?
3190 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3191 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3192 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3193 reglist:$regs, variable_ops),
3194 4, IIC_iLoad_mBr, [],
3195 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3196 RegConstraint<"$Rn = $wb">;
3198 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3199 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3203 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3208 //===----------------------------------------------------------------------===//
3209 // Move Instructions.
3212 let hasSideEffects = 0 in
3213 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3214 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3218 let Inst{19-16} = 0b0000;
3219 let Inst{11-4} = 0b00000000;
3222 let Inst{15-12} = Rd;
3225 // A version for the smaller set of tail call registers.
3226 let hasSideEffects = 0 in
3227 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3228 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3232 let Inst{11-4} = 0b00000000;
3235 let Inst{15-12} = Rd;
3238 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3239 DPSoRegRegFrm, IIC_iMOVsr,
3240 "mov", "\t$Rd, $src",
3241 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3245 let Inst{15-12} = Rd;
3246 let Inst{19-16} = 0b0000;
3247 let Inst{11-8} = src{11-8};
3249 let Inst{6-5} = src{6-5};
3251 let Inst{3-0} = src{3-0};
3255 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3256 DPSoRegImmFrm, IIC_iMOVsr,
3257 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3258 UnaryDP, Sched<[WriteALU]> {
3261 let Inst{15-12} = Rd;
3262 let Inst{19-16} = 0b0000;
3263 let Inst{11-5} = src{11-5};
3265 let Inst{3-0} = src{3-0};
3269 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3270 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3271 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3276 let Inst{15-12} = Rd;
3277 let Inst{19-16} = 0b0000;
3278 let Inst{11-0} = imm;
3281 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3282 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3284 "movw", "\t$Rd, $imm",
3285 [(set GPR:$Rd, imm0_65535:$imm)]>,
3286 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3289 let Inst{15-12} = Rd;
3290 let Inst{11-0} = imm{11-0};
3291 let Inst{19-16} = imm{15-12};
3294 let DecoderMethod = "DecodeArmMOVTWInstruction";
3297 def : InstAlias<"mov${p} $Rd, $imm",
3298 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3301 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3302 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3305 let Constraints = "$src = $Rd" in {
3306 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3307 (ins GPR:$src, imm0_65535_expr:$imm),
3309 "movt", "\t$Rd, $imm",
3311 (or (and GPR:$src, 0xffff),
3312 lo16AllZero:$imm))]>, UnaryDP,
3313 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3316 let Inst{15-12} = Rd;
3317 let Inst{11-0} = imm{11-0};
3318 let Inst{19-16} = imm{15-12};
3321 let DecoderMethod = "DecodeArmMOVTWInstruction";
3324 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3325 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3330 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3331 Requires<[IsARM, HasV6T2]>;
3333 let Uses = [CPSR] in
3334 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3335 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3336 Requires<[IsARM]>, Sched<[WriteALU]>;
3338 // These aren't really mov instructions, but we have to define them this way
3339 // due to flag operands.
3341 let Defs = [CPSR] in {
3342 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3343 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3344 Sched<[WriteALU]>, Requires<[IsARM]>;
3345 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3346 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3347 Sched<[WriteALU]>, Requires<[IsARM]>;
3350 //===----------------------------------------------------------------------===//
3351 // Extend Instructions.
3356 def SXTB : AI_ext_rrot<0b01101010,
3357 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3358 def SXTH : AI_ext_rrot<0b01101011,
3359 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3361 def SXTAB : AI_exta_rrot<0b01101010,
3362 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3363 def SXTAH : AI_exta_rrot<0b01101011,
3364 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3366 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3368 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3372 let AddedComplexity = 16 in {
3373 def UXTB : AI_ext_rrot<0b01101110,
3374 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3375 def UXTH : AI_ext_rrot<0b01101111,
3376 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3377 def UXTB16 : AI_ext_rrot<0b01101100,
3378 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3380 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3381 // The transformation should probably be done as a combiner action
3382 // instead so we can include a check for masking back in the upper
3383 // eight bits of the source into the lower eight bits of the result.
3384 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3385 // (UXTB16r_rot GPR:$Src, 3)>;
3386 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3387 (UXTB16 GPR:$Src, 1)>;
3389 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3390 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3391 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3392 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3395 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3396 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3399 def SBFX : I<(outs GPRnopc:$Rd),
3400 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3401 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3402 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3403 Requires<[IsARM, HasV6T2]> {
3408 let Inst{27-21} = 0b0111101;
3409 let Inst{6-4} = 0b101;
3410 let Inst{20-16} = width;
3411 let Inst{15-12} = Rd;
3412 let Inst{11-7} = lsb;
3416 def UBFX : I<(outs GPRnopc:$Rd),
3417 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3418 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3419 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3420 Requires<[IsARM, HasV6T2]> {
3425 let Inst{27-21} = 0b0111111;
3426 let Inst{6-4} = 0b101;
3427 let Inst{20-16} = width;
3428 let Inst{15-12} = Rd;
3429 let Inst{11-7} = lsb;
3433 //===----------------------------------------------------------------------===//
3434 // Arithmetic Instructions.
3437 defm ADD : AsI1_bin_irs<0b0100, "add",
3438 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3439 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3440 defm SUB : AsI1_bin_irs<0b0010, "sub",
3441 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3442 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3444 // ADD and SUB with 's' bit set.
3446 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3447 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3448 // AdjustInstrPostInstrSelection where we determine whether or not to
3449 // set the "s" bit based on CPSR liveness.
3451 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3452 // support for an optional CPSR definition that corresponds to the DAG
3453 // node's second value. We can then eliminate the implicit def of CPSR.
3454 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3455 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3456 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3457 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3459 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3460 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3461 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3462 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3464 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3465 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3466 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3468 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3469 // CPSR and the implicit def of CPSR is not needed.
3470 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3471 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3473 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3474 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3476 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3477 // The assume-no-carry-in form uses the negation of the input since add/sub
3478 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3479 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3481 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3482 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3483 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3484 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3486 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3487 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3488 Requires<[IsARM, HasV6T2]>;
3489 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3490 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3491 Requires<[IsARM, HasV6T2]>;
3493 // The with-carry-in form matches bitwise not instead of the negation.
3494 // Effectively, the inverse interpretation of the carry flag already accounts
3495 // for part of the negation.
3496 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3497 (SBCri GPR:$src, mod_imm_not:$imm)>;
3498 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3499 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3500 Requires<[IsARM, HasV6T2]>;
3502 // Note: These are implemented in C++ code, because they have to generate
3503 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3505 // (mul X, 2^n+1) -> (add (X << n), X)
3506 // (mul X, 2^n-1) -> (rsb X, (X << n))
3508 // ARM Arithmetic Instruction
3509 // GPR:$dst = GPR:$a op GPR:$b
3510 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3511 list<dag> pattern = [],
3512 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3513 string asm = "\t$Rd, $Rn, $Rm">
3514 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3515 Sched<[WriteALU, ReadALU, ReadALU]> {
3519 let Inst{27-20} = op27_20;
3520 let Inst{11-4} = op11_4;
3521 let Inst{19-16} = Rn;
3522 let Inst{15-12} = Rd;
3525 let Unpredictable{11-8} = 0b1111;
3528 // Saturating add/subtract
3530 let DecoderMethod = "DecodeQADDInstruction" in
3531 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3532 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3533 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3535 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3536 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3537 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3538 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3539 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3541 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3542 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3545 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3546 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3547 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3548 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3549 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3550 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3551 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3552 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3553 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3554 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3555 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3556 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3558 // Signed/Unsigned add/subtract
3560 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3561 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3562 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3563 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3564 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3565 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3566 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3567 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3568 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3569 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3570 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3571 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3573 // Signed/Unsigned halving add/subtract
3575 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3576 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3577 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3578 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3579 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3580 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3581 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3582 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3583 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3584 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3585 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3586 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3588 // Unsigned Sum of Absolute Differences [and Accumulate].
3590 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3591 MulFrm /* for convenience */, NoItinerary, "usad8",
3592 "\t$Rd, $Rn, $Rm", []>,
3593 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3597 let Inst{27-20} = 0b01111000;
3598 let Inst{15-12} = 0b1111;
3599 let Inst{7-4} = 0b0001;
3600 let Inst{19-16} = Rd;
3601 let Inst{11-8} = Rm;
3604 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3605 MulFrm /* for convenience */, NoItinerary, "usada8",
3606 "\t$Rd, $Rn, $Rm, $Ra", []>,
3607 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3612 let Inst{27-20} = 0b01111000;
3613 let Inst{7-4} = 0b0001;
3614 let Inst{19-16} = Rd;
3615 let Inst{15-12} = Ra;
3616 let Inst{11-8} = Rm;
3620 // Signed/Unsigned saturate
3622 def SSAT : AI<(outs GPRnopc:$Rd),
3623 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3624 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3629 let Inst{27-21} = 0b0110101;
3630 let Inst{5-4} = 0b01;
3631 let Inst{20-16} = sat_imm;
3632 let Inst{15-12} = Rd;
3633 let Inst{11-7} = sh{4-0};
3634 let Inst{6} = sh{5};
3638 def SSAT16 : AI<(outs GPRnopc:$Rd),
3639 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3640 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3644 let Inst{27-20} = 0b01101010;
3645 let Inst{11-4} = 0b11110011;
3646 let Inst{15-12} = Rd;
3647 let Inst{19-16} = sat_imm;
3651 def USAT : AI<(outs GPRnopc:$Rd),
3652 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3653 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3658 let Inst{27-21} = 0b0110111;
3659 let Inst{5-4} = 0b01;
3660 let Inst{15-12} = Rd;
3661 let Inst{11-7} = sh{4-0};
3662 let Inst{6} = sh{5};
3663 let Inst{20-16} = sat_imm;
3667 def USAT16 : AI<(outs GPRnopc:$Rd),
3668 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3669 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3673 let Inst{27-20} = 0b01101110;
3674 let Inst{11-4} = 0b11110011;
3675 let Inst{15-12} = Rd;
3676 let Inst{19-16} = sat_imm;
3680 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
3681 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
3682 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
3683 (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
3685 //===----------------------------------------------------------------------===//
3686 // Bitwise Instructions.
3689 defm AND : AsI1_bin_irs<0b0000, "and",
3690 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3691 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3692 defm ORR : AsI1_bin_irs<0b1100, "orr",
3693 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3694 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3695 defm EOR : AsI1_bin_irs<0b0001, "eor",
3696 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3697 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3698 defm BIC : AsI1_bin_irs<0b1110, "bic",
3699 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3700 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3702 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3703 // like in the actual instruction encoding. The complexity of mapping the mask
3704 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3705 // instruction description.
3706 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3707 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3708 "bfc", "\t$Rd, $imm", "$src = $Rd",
3709 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3710 Requires<[IsARM, HasV6T2]> {
3713 let Inst{27-21} = 0b0111110;
3714 let Inst{6-0} = 0b0011111;
3715 let Inst{15-12} = Rd;
3716 let Inst{11-7} = imm{4-0}; // lsb
3717 let Inst{20-16} = imm{9-5}; // msb
3720 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3721 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3722 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3723 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3724 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3725 bf_inv_mask_imm:$imm))]>,
3726 Requires<[IsARM, HasV6T2]> {
3730 let Inst{27-21} = 0b0111110;
3731 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3732 let Inst{15-12} = Rd;
3733 let Inst{11-7} = imm{4-0}; // lsb
3734 let Inst{20-16} = imm{9-5}; // width
3738 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3739 "mvn", "\t$Rd, $Rm",
3740 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3744 let Inst{19-16} = 0b0000;
3745 let Inst{11-4} = 0b00000000;
3746 let Inst{15-12} = Rd;
3749 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3750 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3751 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3756 let Inst{19-16} = 0b0000;
3757 let Inst{15-12} = Rd;
3758 let Inst{11-5} = shift{11-5};
3760 let Inst{3-0} = shift{3-0};
3762 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3763 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3764 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3769 let Inst{19-16} = 0b0000;
3770 let Inst{15-12} = Rd;
3771 let Inst{11-8} = shift{11-8};
3773 let Inst{6-5} = shift{6-5};
3775 let Inst{3-0} = shift{3-0};
3777 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3778 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3779 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3780 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3784 let Inst{19-16} = 0b0000;
3785 let Inst{15-12} = Rd;
3786 let Inst{11-0} = imm;
3789 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3790 (BICri GPR:$src, mod_imm_not:$imm)>;
3792 //===----------------------------------------------------------------------===//
3793 // Multiply Instructions.
3795 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3796 string opc, string asm, list<dag> pattern>
3797 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3801 let Inst{19-16} = Rd;
3802 let Inst{11-8} = Rm;
3805 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3806 string opc, string asm, list<dag> pattern>
3807 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3812 let Inst{19-16} = RdHi;
3813 let Inst{15-12} = RdLo;
3814 let Inst{11-8} = Rm;
3817 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3818 string opc, string asm, list<dag> pattern>
3819 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3824 let Inst{19-16} = RdHi;
3825 let Inst{15-12} = RdLo;
3826 let Inst{11-8} = Rm;
3830 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3831 // property. Remove them when it's possible to add those properties
3832 // on an individual MachineInstr, not just an instruction description.
3833 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3834 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3835 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3836 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3837 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3838 Requires<[IsARM, HasV6]> {
3839 let Inst{15-12} = 0b0000;
3840 let Unpredictable{15-12} = 0b1111;
3843 let Constraints = "@earlyclobber $Rd" in
3844 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3845 pred:$p, cc_out:$s),
3847 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3848 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3849 Requires<[IsARM, NoV6, UseMulOps]>;
3852 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3853 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3854 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3855 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3856 Requires<[IsARM, HasV6, UseMulOps]> {
3858 let Inst{15-12} = Ra;
3861 let Constraints = "@earlyclobber $Rd" in
3862 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3863 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3864 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3865 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3866 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3867 Requires<[IsARM, NoV6]>;
3869 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3870 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3871 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3872 Requires<[IsARM, HasV6T2, UseMulOps]> {
3877 let Inst{19-16} = Rd;
3878 let Inst{15-12} = Ra;
3879 let Inst{11-8} = Rm;
3883 // Extra precision multiplies with low / high results
3884 let hasSideEffects = 0 in {
3885 let isCommutable = 1 in {
3886 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3887 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3888 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3889 Requires<[IsARM, HasV6]>;
3891 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3892 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3893 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3894 Requires<[IsARM, HasV6]>;
3896 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3897 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3898 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3900 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3901 Requires<[IsARM, NoV6]>;
3903 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3904 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3906 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3907 Requires<[IsARM, NoV6]>;
3911 // Multiply + accumulate
3912 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3913 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3914 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3915 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3916 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3917 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3918 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3919 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3921 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3922 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3923 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3924 Requires<[IsARM, HasV6]> {
3929 let Inst{19-16} = RdHi;
3930 let Inst{15-12} = RdLo;
3931 let Inst{11-8} = Rm;
3936 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3937 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3938 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3940 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3941 pred:$p, cc_out:$s)>,
3942 Requires<[IsARM, NoV6]>;
3943 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3944 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3946 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3947 pred:$p, cc_out:$s)>,
3948 Requires<[IsARM, NoV6]>;
3953 // Most significant word multiply
3954 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3955 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3956 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3957 Requires<[IsARM, HasV6]> {
3958 let Inst{15-12} = 0b1111;
3961 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3962 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3963 Requires<[IsARM, HasV6]> {
3964 let Inst{15-12} = 0b1111;
3967 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3968 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3969 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3970 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3971 Requires<[IsARM, HasV6, UseMulOps]>;
3973 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3974 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3975 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3976 Requires<[IsARM, HasV6]>;
3978 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3979 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3980 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3981 Requires<[IsARM, HasV6, UseMulOps]>;
3983 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3984 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3985 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3986 Requires<[IsARM, HasV6]>;
3988 multiclass AI_smul<string opc, PatFrag opnode> {
3989 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3990 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3991 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3992 (sext_inreg GPR:$Rm, i16)))]>,
3993 Requires<[IsARM, HasV5TE]>;
3995 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3996 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3997 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3998 (sra GPR:$Rm, (i32 16))))]>,
3999 Requires<[IsARM, HasV5TE]>;
4001 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4002 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4003 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4004 (sext_inreg GPR:$Rm, i16)))]>,
4005 Requires<[IsARM, HasV5TE]>;
4007 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4008 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4009 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4010 (sra GPR:$Rm, (i32 16))))]>,
4011 Requires<[IsARM, HasV5TE]>;
4013 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4014 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4016 Requires<[IsARM, HasV5TE]>;
4018 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4019 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4021 Requires<[IsARM, HasV5TE]>;
4025 multiclass AI_smla<string opc, PatFrag opnode> {
4026 let DecoderMethod = "DecodeSMLAInstruction" in {
4027 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4028 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4029 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4030 [(set GPRnopc:$Rd, (add GPR:$Ra,
4031 (opnode (sext_inreg GPRnopc:$Rn, i16),
4032 (sext_inreg GPRnopc:$Rm, i16))))]>,
4033 Requires<[IsARM, HasV5TE, UseMulOps]>;
4035 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4036 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4037 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4039 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4040 (sra GPRnopc:$Rm, (i32 16)))))]>,
4041 Requires<[IsARM, HasV5TE, UseMulOps]>;
4043 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4044 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4045 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4047 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4048 (sext_inreg GPRnopc:$Rm, i16))))]>,
4049 Requires<[IsARM, HasV5TE, UseMulOps]>;
4051 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4052 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4053 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4055 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4056 (sra GPRnopc:$Rm, (i32 16)))))]>,
4057 Requires<[IsARM, HasV5TE, UseMulOps]>;
4059 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4060 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4061 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4063 Requires<[IsARM, HasV5TE, UseMulOps]>;
4065 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4066 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4067 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4069 Requires<[IsARM, HasV5TE, UseMulOps]>;
4073 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4074 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4076 // Halfword multiply accumulate long: SMLAL<x><y>.
4077 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4078 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4079 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4080 Requires<[IsARM, HasV5TE]>;
4082 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4083 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4084 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4085 Requires<[IsARM, HasV5TE]>;
4087 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4088 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4089 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4090 Requires<[IsARM, HasV5TE]>;
4092 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4093 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4094 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4095 Requires<[IsARM, HasV5TE]>;
4097 // Helper class for AI_smld.
4098 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4099 InstrItinClass itin, string opc, string asm>
4100 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4103 let Inst{27-23} = 0b01110;
4104 let Inst{22} = long;
4105 let Inst{21-20} = 0b00;
4106 let Inst{11-8} = Rm;
4113 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4114 InstrItinClass itin, string opc, string asm>
4115 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4117 let Inst{15-12} = 0b1111;
4118 let Inst{19-16} = Rd;
4120 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4121 InstrItinClass itin, string opc, string asm>
4122 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4125 let Inst{19-16} = Rd;
4126 let Inst{15-12} = Ra;
4128 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4129 InstrItinClass itin, string opc, string asm>
4130 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4133 let Inst{19-16} = RdHi;
4134 let Inst{15-12} = RdLo;
4137 multiclass AI_smld<bit sub, string opc> {
4139 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4140 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4141 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4143 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4144 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4145 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4147 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4148 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4149 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4151 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4152 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4153 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4157 defm SMLA : AI_smld<0, "smla">;
4158 defm SMLS : AI_smld<1, "smls">;
4160 multiclass AI_sdml<bit sub, string opc> {
4162 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4163 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4164 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4165 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4168 defm SMUA : AI_sdml<0, "smua">;
4169 defm SMUS : AI_sdml<1, "smus">;
4171 //===----------------------------------------------------------------------===//
4172 // Division Instructions (ARMv7-A with virtualization extension)
4174 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4175 "sdiv", "\t$Rd, $Rn, $Rm",
4176 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4177 Requires<[IsARM, HasDivideInARM]>;
4179 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4180 "udiv", "\t$Rd, $Rn, $Rm",
4181 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4182 Requires<[IsARM, HasDivideInARM]>;
4184 //===----------------------------------------------------------------------===//
4185 // Misc. Arithmetic Instructions.
4188 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4189 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4190 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4193 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4194 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4195 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4196 Requires<[IsARM, HasV6T2]>,
4199 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4200 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4201 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4204 let AddedComplexity = 5 in
4205 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4206 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4207 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4208 Requires<[IsARM, HasV6]>,
4211 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4212 (REV16 (LDRH addrmode3:$addr))>;
4213 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4214 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4216 let AddedComplexity = 5 in
4217 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4218 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4219 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4220 Requires<[IsARM, HasV6]>,
4223 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4224 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4227 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4228 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4229 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4230 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4231 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4233 Requires<[IsARM, HasV6]>,
4234 Sched<[WriteALUsi, ReadALU]>;
4236 // Alternate cases for PKHBT where identities eliminate some nodes.
4237 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4238 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4239 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4240 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4242 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4243 // will match the pattern below.
4244 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4245 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4246 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4247 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4248 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4250 Requires<[IsARM, HasV6]>,
4251 Sched<[WriteALUsi, ReadALU]>;
4253 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4254 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4255 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4256 // pkhtb src1, src2, asr (17..31).
4257 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4258 (srl GPRnopc:$src2, imm16:$sh)),
4259 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4260 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4261 (sra GPRnopc:$src2, imm16_31:$sh)),
4262 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4263 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4264 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4265 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4267 //===----------------------------------------------------------------------===//
4271 // + CRC32{B,H,W} 0x04C11DB7
4272 // + CRC32C{B,H,W} 0x1EDC6F41
4275 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4276 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4277 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4278 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4279 Requires<[IsARM, HasV8, HasCRC]> {
4284 let Inst{31-28} = 0b1110;
4285 let Inst{27-23} = 0b00010;
4286 let Inst{22-21} = sz;
4288 let Inst{19-16} = Rn;
4289 let Inst{15-12} = Rd;
4290 let Inst{11-10} = 0b00;
4293 let Inst{7-4} = 0b0100;
4296 let Unpredictable{11-8} = 0b1101;
4299 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4300 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4301 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4302 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4303 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4304 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4306 //===----------------------------------------------------------------------===//
4307 // ARMv8.1a Privilege Access Never extension
4311 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4312 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4315 let Inst{31-28} = 0b1111;
4316 let Inst{27-20} = 0b00010001;
4317 let Inst{19-16} = 0b0000;
4318 let Inst{15-10} = 0b000000;
4321 let Inst{7-4} = 0b0000;
4322 let Inst{3-0} = 0b0000;
4324 let Unpredictable{19-16} = 0b1111;
4325 let Unpredictable{15-10} = 0b111111;
4326 let Unpredictable{8} = 0b1;
4327 let Unpredictable{3-0} = 0b1111;
4330 //===----------------------------------------------------------------------===//
4331 // Comparison Instructions...
4334 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4335 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4336 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4338 // ARMcmpZ can re-use the above instruction definitions.
4339 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4340 (CMPri GPR:$src, mod_imm:$imm)>;
4341 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4342 (CMPrr GPR:$src, GPR:$rhs)>;
4343 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4344 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4345 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4346 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4348 // CMN register-integer
4349 let isCompare = 1, Defs = [CPSR] in {
4350 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4351 "cmn", "\t$Rn, $imm",
4352 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4353 Sched<[WriteCMP, ReadALU]> {
4358 let Inst{19-16} = Rn;
4359 let Inst{15-12} = 0b0000;
4360 let Inst{11-0} = imm;
4362 let Unpredictable{15-12} = 0b1111;
4365 // CMN register-register/shift
4366 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4367 "cmn", "\t$Rn, $Rm",
4368 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4369 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4372 let isCommutable = 1;
4375 let Inst{19-16} = Rn;
4376 let Inst{15-12} = 0b0000;
4377 let Inst{11-4} = 0b00000000;
4380 let Unpredictable{15-12} = 0b1111;
4383 def CMNzrsi : AI1<0b1011, (outs),
4384 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4385 "cmn", "\t$Rn, $shift",
4386 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4387 GPR:$Rn, so_reg_imm:$shift)]>,
4388 Sched<[WriteCMPsi, ReadALU]> {
4393 let Inst{19-16} = Rn;
4394 let Inst{15-12} = 0b0000;
4395 let Inst{11-5} = shift{11-5};
4397 let Inst{3-0} = shift{3-0};
4399 let Unpredictable{15-12} = 0b1111;
4402 def CMNzrsr : AI1<0b1011, (outs),
4403 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4404 "cmn", "\t$Rn, $shift",
4405 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4406 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4407 Sched<[WriteCMPsr, ReadALU]> {
4412 let Inst{19-16} = Rn;
4413 let Inst{15-12} = 0b0000;
4414 let Inst{11-8} = shift{11-8};
4416 let Inst{6-5} = shift{6-5};
4418 let Inst{3-0} = shift{3-0};
4420 let Unpredictable{15-12} = 0b1111;
4425 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4426 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4428 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4429 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4431 // Note that TST/TEQ don't set all the same flags that CMP does!
4432 defm TST : AI1_cmp_irs<0b1000, "tst",
4433 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4434 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4435 "DecodeTSTInstruction">;
4436 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4437 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4438 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4440 // Pseudo i64 compares for some floating point compares.
4441 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4443 def BCCi64 : PseudoInst<(outs),
4444 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4446 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4449 def BCCZi64 : PseudoInst<(outs),
4450 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4451 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4453 } // usesCustomInserter
4456 // Conditional moves
4457 let hasSideEffects = 0 in {
4459 let isCommutable = 1, isSelect = 1 in
4460 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4461 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4463 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4465 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4467 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4468 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4471 (ARMcmov GPR:$false, so_reg_imm:$shift,
4473 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4474 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4475 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4477 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4479 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4482 let isMoveImm = 1 in
4484 : ARMPseudoInst<(outs GPR:$Rd),
4485 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4487 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4489 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4492 let isMoveImm = 1 in
4493 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4494 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4496 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4498 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4500 // Two instruction predicate mov immediate.
4501 let isMoveImm = 1 in
4503 : ARMPseudoInst<(outs GPR:$Rd),
4504 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4506 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4508 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4510 let isMoveImm = 1 in
4511 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4512 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4514 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4516 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4521 //===----------------------------------------------------------------------===//
4522 // Atomic operations intrinsics
4525 def MemBarrierOptOperand : AsmOperandClass {
4526 let Name = "MemBarrierOpt";
4527 let ParserMethod = "parseMemBarrierOptOperand";
4529 def memb_opt : Operand<i32> {
4530 let PrintMethod = "printMemBOption";
4531 let ParserMatchClass = MemBarrierOptOperand;
4532 let DecoderMethod = "DecodeMemBarrierOption";
4535 def InstSyncBarrierOptOperand : AsmOperandClass {
4536 let Name = "InstSyncBarrierOpt";
4537 let ParserMethod = "parseInstSyncBarrierOptOperand";
4539 def instsyncb_opt : Operand<i32> {
4540 let PrintMethod = "printInstSyncBOption";
4541 let ParserMatchClass = InstSyncBarrierOptOperand;
4542 let DecoderMethod = "DecodeInstSyncBarrierOption";
4545 // Memory barriers protect the atomic sequences
4546 let hasSideEffects = 1 in {
4547 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4548 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4549 Requires<[IsARM, HasDB]> {
4551 let Inst{31-4} = 0xf57ff05;
4552 let Inst{3-0} = opt;
4555 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4556 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4557 Requires<[IsARM, HasDB]> {
4559 let Inst{31-4} = 0xf57ff04;
4560 let Inst{3-0} = opt;
4563 // ISB has only full system option
4564 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4565 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4566 Requires<[IsARM, HasDB]> {
4568 let Inst{31-4} = 0xf57ff06;
4569 let Inst{3-0} = opt;
4573 let usesCustomInserter = 1, Defs = [CPSR] in {
4575 // Pseudo instruction that combines movs + predicated rsbmi
4576 // to implement integer ABS
4577 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4580 let usesCustomInserter = 1 in {
4581 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4582 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4584 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4587 let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in {
4588 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs...
4589 // Copies N registers worth of memory from address %src to address %dst
4590 // and returns the incremented addresses. N scratch register will
4591 // be attached for the copy to use.
4592 def MEMCPY : PseudoInst<
4593 (outs GPR:$newdst, GPR:$newsrc),
4594 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
4596 [(set GPR:$newdst, GPR:$newsrc,
4597 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4600 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4601 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4604 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4605 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4608 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4609 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4612 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4613 (int_arm_strex node:$val, node:$ptr), [{
4614 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4617 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4618 (int_arm_strex node:$val, node:$ptr), [{
4619 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4622 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4623 (int_arm_strex node:$val, node:$ptr), [{
4624 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4627 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4628 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4631 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4632 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4635 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4636 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4639 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4640 (int_arm_stlex node:$val, node:$ptr), [{
4641 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4644 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4645 (int_arm_stlex node:$val, node:$ptr), [{
4646 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4649 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4650 (int_arm_stlex node:$val, node:$ptr), [{
4651 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4654 let mayLoad = 1 in {
4655 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4656 NoItinerary, "ldrexb", "\t$Rt, $addr",
4657 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4658 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4659 NoItinerary, "ldrexh", "\t$Rt, $addr",
4660 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4661 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4662 NoItinerary, "ldrex", "\t$Rt, $addr",
4663 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4664 let hasExtraDefRegAllocReq = 1 in
4665 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4666 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4667 let DecoderMethod = "DecodeDoubleRegLoad";
4670 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4671 NoItinerary, "ldaexb", "\t$Rt, $addr",
4672 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4673 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4674 NoItinerary, "ldaexh", "\t$Rt, $addr",
4675 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4676 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4677 NoItinerary, "ldaex", "\t$Rt, $addr",
4678 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4679 let hasExtraDefRegAllocReq = 1 in
4680 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4681 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4682 let DecoderMethod = "DecodeDoubleRegLoad";
4686 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4687 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4688 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4689 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4690 addr_offset_none:$addr))]>;
4691 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4692 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4693 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4694 addr_offset_none:$addr))]>;
4695 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4696 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4697 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4698 addr_offset_none:$addr))]>;
4699 let hasExtraSrcRegAllocReq = 1 in
4700 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4701 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4702 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4703 let DecoderMethod = "DecodeDoubleRegStore";
4705 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4706 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4708 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4709 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4710 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4712 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4713 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4714 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4716 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4717 let hasExtraSrcRegAllocReq = 1 in
4718 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4719 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4720 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4721 let DecoderMethod = "DecodeDoubleRegStore";
4725 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4727 Requires<[IsARM, HasV7]> {
4728 let Inst{31-0} = 0b11110101011111111111000000011111;
4731 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4732 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4733 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4734 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4736 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4737 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4738 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4739 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4741 class acquiring_load<PatFrag base>
4742 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4743 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4744 return isAtLeastAcquire(Ordering);
4747 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4748 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4749 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4751 class releasing_store<PatFrag base>
4752 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4753 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4754 return isAtLeastRelease(Ordering);
4757 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4758 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4759 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4761 let AddedComplexity = 8 in {
4762 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4763 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4764 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4765 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4766 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4767 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4770 // SWP/SWPB are deprecated in V6/V7.
4771 let mayLoad = 1, mayStore = 1 in {
4772 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4773 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4775 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4776 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4780 //===----------------------------------------------------------------------===//
4781 // Coprocessor Instructions.
4784 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4785 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4786 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4787 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4788 imm:$CRm, imm:$opc2)]>,
4797 let Inst{3-0} = CRm;
4799 let Inst{7-5} = opc2;
4800 let Inst{11-8} = cop;
4801 let Inst{15-12} = CRd;
4802 let Inst{19-16} = CRn;
4803 let Inst{23-20} = opc1;
4806 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4807 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4808 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4809 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4810 imm:$CRm, imm:$opc2)]>,
4812 let Inst{31-28} = 0b1111;
4820 let Inst{3-0} = CRm;
4822 let Inst{7-5} = opc2;
4823 let Inst{11-8} = cop;
4824 let Inst{15-12} = CRd;
4825 let Inst{19-16} = CRn;
4826 let Inst{23-20} = opc1;
4829 class ACI<dag oops, dag iops, string opc, string asm,
4830 IndexMode im = IndexModeNone>
4831 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4833 let Inst{27-25} = 0b110;
4835 class ACInoP<dag oops, dag iops, string opc, string asm,
4836 IndexMode im = IndexModeNone>
4837 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4839 let Inst{31-28} = 0b1111;
4840 let Inst{27-25} = 0b110;
4842 multiclass LdStCop<bit load, bit Dbit, string asm> {
4843 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4844 asm, "\t$cop, $CRd, $addr"> {
4848 let Inst{24} = 1; // P = 1
4849 let Inst{23} = addr{8};
4850 let Inst{22} = Dbit;
4851 let Inst{21} = 0; // W = 0
4852 let Inst{20} = load;
4853 let Inst{19-16} = addr{12-9};
4854 let Inst{15-12} = CRd;
4855 let Inst{11-8} = cop;
4856 let Inst{7-0} = addr{7-0};
4857 let DecoderMethod = "DecodeCopMemInstruction";
4859 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4860 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4864 let Inst{24} = 1; // P = 1
4865 let Inst{23} = addr{8};
4866 let Inst{22} = Dbit;
4867 let Inst{21} = 1; // W = 1
4868 let Inst{20} = load;
4869 let Inst{19-16} = addr{12-9};
4870 let Inst{15-12} = CRd;
4871 let Inst{11-8} = cop;
4872 let Inst{7-0} = addr{7-0};
4873 let DecoderMethod = "DecodeCopMemInstruction";
4875 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4876 postidx_imm8s4:$offset),
4877 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4882 let Inst{24} = 0; // P = 0
4883 let Inst{23} = offset{8};
4884 let Inst{22} = Dbit;
4885 let Inst{21} = 1; // W = 1
4886 let Inst{20} = load;
4887 let Inst{19-16} = addr;
4888 let Inst{15-12} = CRd;
4889 let Inst{11-8} = cop;
4890 let Inst{7-0} = offset{7-0};
4891 let DecoderMethod = "DecodeCopMemInstruction";
4893 def _OPTION : ACI<(outs),
4894 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4895 coproc_option_imm:$option),
4896 asm, "\t$cop, $CRd, $addr, $option"> {
4901 let Inst{24} = 0; // P = 0
4902 let Inst{23} = 1; // U = 1
4903 let Inst{22} = Dbit;
4904 let Inst{21} = 0; // W = 0
4905 let Inst{20} = load;
4906 let Inst{19-16} = addr;
4907 let Inst{15-12} = CRd;
4908 let Inst{11-8} = cop;
4909 let Inst{7-0} = option;
4910 let DecoderMethod = "DecodeCopMemInstruction";
4913 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4914 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4915 asm, "\t$cop, $CRd, $addr"> {
4919 let Inst{24} = 1; // P = 1
4920 let Inst{23} = addr{8};
4921 let Inst{22} = Dbit;
4922 let Inst{21} = 0; // W = 0
4923 let Inst{20} = load;
4924 let Inst{19-16} = addr{12-9};
4925 let Inst{15-12} = CRd;
4926 let Inst{11-8} = cop;
4927 let Inst{7-0} = addr{7-0};
4928 let DecoderMethod = "DecodeCopMemInstruction";
4930 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4931 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4935 let Inst{24} = 1; // P = 1
4936 let Inst{23} = addr{8};
4937 let Inst{22} = Dbit;
4938 let Inst{21} = 1; // W = 1
4939 let Inst{20} = load;
4940 let Inst{19-16} = addr{12-9};
4941 let Inst{15-12} = CRd;
4942 let Inst{11-8} = cop;
4943 let Inst{7-0} = addr{7-0};
4944 let DecoderMethod = "DecodeCopMemInstruction";
4946 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4947 postidx_imm8s4:$offset),
4948 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4953 let Inst{24} = 0; // P = 0
4954 let Inst{23} = offset{8};
4955 let Inst{22} = Dbit;
4956 let Inst{21} = 1; // W = 1
4957 let Inst{20} = load;
4958 let Inst{19-16} = addr;
4959 let Inst{15-12} = CRd;
4960 let Inst{11-8} = cop;
4961 let Inst{7-0} = offset{7-0};
4962 let DecoderMethod = "DecodeCopMemInstruction";
4964 def _OPTION : ACInoP<(outs),
4965 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4966 coproc_option_imm:$option),
4967 asm, "\t$cop, $CRd, $addr, $option"> {
4972 let Inst{24} = 0; // P = 0
4973 let Inst{23} = 1; // U = 1
4974 let Inst{22} = Dbit;
4975 let Inst{21} = 0; // W = 0
4976 let Inst{20} = load;
4977 let Inst{19-16} = addr;
4978 let Inst{15-12} = CRd;
4979 let Inst{11-8} = cop;
4980 let Inst{7-0} = option;
4981 let DecoderMethod = "DecodeCopMemInstruction";
4985 defm LDC : LdStCop <1, 0, "ldc">;
4986 defm LDCL : LdStCop <1, 1, "ldcl">;
4987 defm STC : LdStCop <0, 0, "stc">;
4988 defm STCL : LdStCop <0, 1, "stcl">;
4989 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4990 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4991 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4992 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4994 //===----------------------------------------------------------------------===//
4995 // Move between coprocessor and ARM core register.
4998 class MovRCopro<string opc, bit direction, dag oops, dag iops,
5000 : ABI<0b1110, oops, iops, NoItinerary, opc,
5001 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5002 let Inst{20} = direction;
5012 let Inst{15-12} = Rt;
5013 let Inst{11-8} = cop;
5014 let Inst{23-21} = opc1;
5015 let Inst{7-5} = opc2;
5016 let Inst{3-0} = CRm;
5017 let Inst{19-16} = CRn;
5020 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5022 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5023 c_imm:$CRm, imm0_7:$opc2),
5024 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5025 imm:$CRm, imm:$opc2)]>,
5026 ComplexDeprecationPredicate<"MCR">;
5027 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5028 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5029 c_imm:$CRm, 0, pred:$p)>;
5030 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5031 (outs GPRwithAPSR:$Rt),
5032 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5034 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5035 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5036 c_imm:$CRm, 0, pred:$p)>;
5038 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5039 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5041 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5043 : ABXI<0b1110, oops, iops, NoItinerary,
5044 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5045 let Inst{31-24} = 0b11111110;
5046 let Inst{20} = direction;
5056 let Inst{15-12} = Rt;
5057 let Inst{11-8} = cop;
5058 let Inst{23-21} = opc1;
5059 let Inst{7-5} = opc2;
5060 let Inst{3-0} = CRm;
5061 let Inst{19-16} = CRn;
5064 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5066 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5067 c_imm:$CRm, imm0_7:$opc2),
5068 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5069 imm:$CRm, imm:$opc2)]>,
5071 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5072 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5074 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5075 (outs GPRwithAPSR:$Rt),
5076 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5079 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5080 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5083 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5084 imm:$CRm, imm:$opc2),
5085 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5087 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5089 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5092 let Inst{23-21} = 0b010;
5093 let Inst{20} = direction;
5101 let Inst{15-12} = Rt;
5102 let Inst{19-16} = Rt2;
5103 let Inst{11-8} = cop;
5104 let Inst{7-4} = opc1;
5105 let Inst{3-0} = CRm;
5108 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5109 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5110 GPRnopc:$Rt2, c_imm:$CRm),
5111 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5112 GPRnopc:$Rt2, imm:$CRm)]>;
5113 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5114 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5115 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5117 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5118 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5119 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5120 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5122 let Inst{31-28} = 0b1111;
5123 let Inst{23-21} = 0b010;
5124 let Inst{20} = direction;
5132 let Inst{15-12} = Rt;
5133 let Inst{19-16} = Rt2;
5134 let Inst{11-8} = cop;
5135 let Inst{7-4} = opc1;
5136 let Inst{3-0} = CRm;
5138 let DecoderMethod = "DecodeMRRC2";
5141 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5142 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5143 GPRnopc:$Rt2, imm:$CRm)]>;
5144 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5146 //===----------------------------------------------------------------------===//
5147 // Move between special register and ARM core register
5150 // Move to ARM core register from Special Register
5151 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5152 "mrs", "\t$Rd, apsr", []> {
5154 let Inst{23-16} = 0b00001111;
5155 let Unpredictable{19-17} = 0b111;
5157 let Inst{15-12} = Rd;
5159 let Inst{11-0} = 0b000000000000;
5160 let Unpredictable{11-0} = 0b110100001111;
5163 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5166 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5167 // section B9.3.9, with the R bit set to 1.
5168 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5169 "mrs", "\t$Rd, spsr", []> {
5171 let Inst{23-16} = 0b01001111;
5172 let Unpredictable{19-16} = 0b1111;
5174 let Inst{15-12} = Rd;
5176 let Inst{11-0} = 0b000000000000;
5177 let Unpredictable{11-0} = 0b110100001111;
5180 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5181 // separate encoding (distinguished by bit 5.
5182 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5183 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5184 Requires<[IsARM, HasVirtualization]> {
5189 let Inst{22} = banked{5}; // R bit
5190 let Inst{21-20} = 0b00;
5191 let Inst{19-16} = banked{3-0};
5192 let Inst{15-12} = Rd;
5193 let Inst{11-9} = 0b001;
5194 let Inst{8} = banked{4};
5195 let Inst{7-0} = 0b00000000;
5198 // Move from ARM core register to Special Register
5200 // No need to have both system and application versions of MSR (immediate) or
5201 // MSR (register), the encodings are the same and the assembly parser has no way
5202 // to distinguish between them. The mask operand contains the special register
5203 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5204 // accessed in the special register.
5205 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5206 "msr", "\t$mask, $Rn", []> {
5211 let Inst{22} = mask{4}; // R bit
5212 let Inst{21-20} = 0b10;
5213 let Inst{19-16} = mask{3-0};
5214 let Inst{15-12} = 0b1111;
5215 let Inst{11-4} = 0b00000000;
5219 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5220 "msr", "\t$mask, $imm", []> {
5225 let Inst{22} = mask{4}; // R bit
5226 let Inst{21-20} = 0b10;
5227 let Inst{19-16} = mask{3-0};
5228 let Inst{15-12} = 0b1111;
5229 let Inst{11-0} = imm;
5232 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5233 // separate encoding (distinguished by bit 5.
5234 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5235 NoItinerary, "msr", "\t$banked, $Rn", []>,
5236 Requires<[IsARM, HasVirtualization]> {
5241 let Inst{22} = banked{5}; // R bit
5242 let Inst{21-20} = 0b10;
5243 let Inst{19-16} = banked{3-0};
5244 let Inst{15-12} = 0b1111;
5245 let Inst{11-9} = 0b001;
5246 let Inst{8} = banked{4};
5247 let Inst{7-4} = 0b0000;
5251 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5252 // are needed to probe the stack when allocating more than
5253 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5254 // ensure that the guard pages used by the OS virtual memory manager are
5255 // allocated in correct sequence.
5256 // The main point of having separate instruction are extra unmodelled effects
5257 // (compared to ordinary calls) like stack pointer change.
5259 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5260 [SDNPHasChain, SDNPSideEffect]>;
5261 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5262 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5264 def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
5265 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
5266 let usesCustomInserter = 1, Defs = [CPSR] in
5267 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary,
5268 [(win__dbzchk GPR:$divisor)]>;
5270 //===----------------------------------------------------------------------===//
5274 // __aeabi_read_tp preserves the registers r1-r3.
5275 // This is a pseudo inst so that we can get the encoding right,
5276 // complete with fixup for the aeabi_read_tp function.
5277 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5278 // is defined in "ARMInstrThumb.td".
5280 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5281 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5282 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5285 //===----------------------------------------------------------------------===//
5286 // SJLJ Exception handling intrinsics
5287 // eh_sjlj_setjmp() is an instruction sequence to store the return
5288 // address and save #0 in R0 for the non-longjmp case.
5289 // Since by its nature we may be coming from some other function to get
5290 // here, and we're using the stack frame for the containing function to
5291 // save/restore registers, we can't keep anything live in regs across
5292 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5293 // when we get here from a longjmp(). We force everything out of registers
5294 // except for our own input by listing the relevant registers in Defs. By
5295 // doing so, we also cause the prologue/epilogue code to actively preserve
5296 // all of the callee-saved resgisters, which is exactly what we want.
5297 // A constant value is passed in $val, and we use the location as a scratch.
5299 // These are pseudo-instructions and are lowered to individual MC-insts, so
5300 // no encoding information is necessary.
5302 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5303 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5304 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5305 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5307 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5308 Requires<[IsARM, HasVFP2]>;
5312 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5313 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5314 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5316 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5317 Requires<[IsARM, NoVFP]>;
5320 // FIXME: Non-IOS version(s)
5321 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5322 Defs = [ R7, LR, SP ] in {
5323 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5325 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5329 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5330 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5331 [(ARMeh_sjlj_setup_dispatch)]>;
5333 // eh.sjlj.dispatchsetup pseudo-instruction.
5334 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5335 // the pseudo is expanded (which happens before any passes that need the
5336 // instruction size).
5337 let isBarrier = 1 in
5338 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5341 //===----------------------------------------------------------------------===//
5342 // Non-Instruction Patterns
5345 // ARMv4 indirect branch using (MOVr PC, dst)
5346 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5347 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5348 4, IIC_Br, [(brind GPR:$dst)],
5349 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5350 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5352 // Large immediate handling.
5354 // 32-bit immediate using two piece mod_imms or movw + movt.
5355 // This is a single pseudo instruction, the benefit is that it can be remat'd
5356 // as a single unit instead of having to handle reg inputs.
5357 // FIXME: Remove this when we can do generalized remat.
5358 let isReMaterializable = 1, isMoveImm = 1 in
5359 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5360 [(set GPR:$dst, (arm_i32imm:$src))]>,
5363 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5364 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5365 Requires<[IsARM, DontUseMovt]>;
5367 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5368 // It also makes it possible to rematerialize the instructions.
5369 // FIXME: Remove this when we can do generalized remat and when machine licm
5370 // can properly the instructions.
5371 let isReMaterializable = 1 in {
5372 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5374 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5375 Requires<[IsARM, UseMovt]>;
5377 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5380 (ARMWrapperPIC tglobaladdr:$addr))]>,
5381 Requires<[IsARM, DontUseMovt]>;
5383 let AddedComplexity = 10 in
5384 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5387 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5388 Requires<[IsARM, DontUseMovt]>;
5390 let AddedComplexity = 10 in
5391 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5393 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5394 Requires<[IsARM, UseMovt]>;
5395 } // isReMaterializable
5397 // ConstantPool, GlobalAddress, and JumpTable
5398 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5399 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5400 Requires<[IsARM, UseMovt]>;
5401 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5402 (LEApcrelJT tjumptable:$dst)>;
5404 // TODO: add,sub,and, 3-instr forms?
5406 // Tail calls. These patterns also apply to Thumb mode.
5407 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5408 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5409 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5412 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5413 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5414 (BMOVPCB_CALL texternalsym:$func)>;
5416 // zextload i1 -> zextload i8
5417 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5418 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5420 // extload -> zextload
5421 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5422 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5423 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5424 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5426 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5428 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5429 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5432 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5433 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5434 (SMULBB GPR:$a, GPR:$b)>;
5435 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5436 (SMULBB GPR:$a, GPR:$b)>;
5437 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5438 (sra GPR:$b, (i32 16))),
5439 (SMULBT GPR:$a, GPR:$b)>;
5440 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5441 (SMULBT GPR:$a, GPR:$b)>;
5442 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5443 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5444 (SMULTB GPR:$a, GPR:$b)>;
5445 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5446 (SMULTB GPR:$a, GPR:$b)>;
5448 def : ARMV5MOPat<(add GPR:$acc,
5449 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5450 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5451 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5452 def : ARMV5MOPat<(add GPR:$acc,
5453 (mul sext_16_node:$a, sext_16_node:$b)),
5454 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5455 def : ARMV5MOPat<(add GPR:$acc,
5456 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5457 (sra GPR:$b, (i32 16)))),
5458 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5459 def : ARMV5MOPat<(add GPR:$acc,
5460 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5461 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5462 def : ARMV5MOPat<(add GPR:$acc,
5463 (mul (sra GPR:$a, (i32 16)),
5464 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5465 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5466 def : ARMV5MOPat<(add GPR:$acc,
5467 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5468 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5471 // Pre-v7 uses MCR for synchronization barriers.
5472 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5473 Requires<[IsARM, HasV6]>;
5475 // SXT/UXT with no rotate
5476 let AddedComplexity = 16 in {
5477 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5478 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5479 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5480 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5481 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5482 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5483 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5486 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5487 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5489 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5490 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5491 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5492 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5494 // Atomic load/store patterns
5495 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5496 (LDRBrs ldst_so_reg:$src)>;
5497 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5498 (LDRBi12 addrmode_imm12:$src)>;
5499 def : ARMPat<(atomic_load_16 addrmode3:$src),
5500 (LDRH addrmode3:$src)>;
5501 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5502 (LDRrs ldst_so_reg:$src)>;
5503 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5504 (LDRi12 addrmode_imm12:$src)>;
5505 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5506 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5507 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5508 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5509 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5510 (STRH GPR:$val, addrmode3:$ptr)>;
5511 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5512 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5513 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5514 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5517 //===----------------------------------------------------------------------===//
5521 include "ARMInstrThumb.td"
5523 //===----------------------------------------------------------------------===//
5527 include "ARMInstrThumb2.td"
5529 //===----------------------------------------------------------------------===//
5530 // Floating Point Support
5533 include "ARMInstrVFP.td"
5535 //===----------------------------------------------------------------------===//
5536 // Advanced SIMD (NEON) Support
5539 include "ARMInstrNEON.td"
5541 //===----------------------------------------------------------------------===//
5542 // Assembler aliases
5546 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5547 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5548 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5550 // System instructions
5551 def : MnemonicAlias<"swi", "svc">;
5553 // Load / Store Multiple
5554 def : MnemonicAlias<"ldmfd", "ldm">;
5555 def : MnemonicAlias<"ldmia", "ldm">;
5556 def : MnemonicAlias<"ldmea", "ldmdb">;
5557 def : MnemonicAlias<"stmfd", "stmdb">;
5558 def : MnemonicAlias<"stmia", "stm">;
5559 def : MnemonicAlias<"stmea", "stm">;
5561 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5562 // shift amount is zero (i.e., unspecified).
5563 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5564 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5565 Requires<[IsARM, HasV6]>;
5566 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5567 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5568 Requires<[IsARM, HasV6]>;
5570 // PUSH/POP aliases for STM/LDM
5571 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5572 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5574 // SSAT/USAT optional shift operand.
5575 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5576 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5577 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5578 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5581 // Extend instruction optional rotate operand.
5582 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5583 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5584 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5585 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5586 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5587 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5588 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5589 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5590 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5591 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5592 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5593 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5595 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5596 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5597 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5598 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5599 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5600 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5601 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5602 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5603 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5604 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5605 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5606 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5610 def : MnemonicAlias<"rfefa", "rfeda">;
5611 def : MnemonicAlias<"rfeea", "rfedb">;
5612 def : MnemonicAlias<"rfefd", "rfeia">;
5613 def : MnemonicAlias<"rfeed", "rfeib">;
5614 def : MnemonicAlias<"rfe", "rfeia">;
5617 def : MnemonicAlias<"srsfa", "srsib">;
5618 def : MnemonicAlias<"srsea", "srsia">;
5619 def : MnemonicAlias<"srsfd", "srsdb">;
5620 def : MnemonicAlias<"srsed", "srsda">;
5621 def : MnemonicAlias<"srs", "srsia">;
5624 def : MnemonicAlias<"qsubaddx", "qsax">;
5626 def : MnemonicAlias<"saddsubx", "sasx">;
5627 // SHASX == SHADDSUBX
5628 def : MnemonicAlias<"shaddsubx", "shasx">;
5629 // SHSAX == SHSUBADDX
5630 def : MnemonicAlias<"shsubaddx", "shsax">;
5632 def : MnemonicAlias<"ssubaddx", "ssax">;
5634 def : MnemonicAlias<"uaddsubx", "uasx">;
5635 // UHASX == UHADDSUBX
5636 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5637 // UHSAX == UHSUBADDX
5638 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5639 // UQASX == UQADDSUBX
5640 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5641 // UQSAX == UQSUBADDX
5642 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5644 def : MnemonicAlias<"usubaddx", "usax">;
5646 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5648 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5649 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5650 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5651 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5652 // Same for AND <--> BIC
5653 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5654 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5655 pred:$p, cc_out:$s)>;
5656 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5657 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5658 pred:$p, cc_out:$s)>;
5659 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5660 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5661 pred:$p, cc_out:$s)>;
5662 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5663 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5664 pred:$p, cc_out:$s)>;
5666 // Likewise, "add Rd, mod_imm_neg" -> sub
5667 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5668 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5669 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5670 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5671 // Same for CMP <--> CMN via mod_imm_neg
5672 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5673 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5674 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5675 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5677 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5678 // LSR, ROR, and RRX instructions.
5679 // FIXME: We need C++ parser hooks to map the alias to the MOV
5680 // encoding. It seems we should be able to do that sort of thing
5681 // in tblgen, but it could get ugly.
5682 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5683 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5684 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5686 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5687 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5689 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5690 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5692 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5693 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5696 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5697 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5698 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5699 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5700 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5702 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5703 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5705 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5706 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5708 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5709 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5713 // "neg" is and alias for "rsb rd, rn, #0"
5714 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5715 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5717 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5718 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5719 Requires<[IsARM, NoV6]>;
5721 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5722 // the instruction definitions need difference constraints pre-v6.
5723 // Use these aliases for the assembly parsing on pre-v6.
5724 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5725 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5726 Requires<[IsARM, NoV6]>;
5727 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5728 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5729 pred:$p, cc_out:$s)>,
5730 Requires<[IsARM, NoV6]>;
5731 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5732 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5733 Requires<[IsARM, NoV6]>;
5734 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5735 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5736 Requires<[IsARM, NoV6]>;
5737 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5738 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5739 Requires<[IsARM, NoV6]>;
5740 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5741 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5742 Requires<[IsARM, NoV6]>;
5744 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5746 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5747 ComplexDeprecationPredicate<"IT">;
5749 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5750 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5752 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;