1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
225 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
226 def IsThumb : Predicate<"Subtarget->isThumb()">,
227 AssemblerPredicate<"ModeThumb", "thumb">;
228 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
229 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
230 AssemblerPredicate<"ModeThumb,FeatureThumb2",
232 def IsMClass : Predicate<"Subtarget->isMClass()">,
233 AssemblerPredicate<"FeatureMClass", "armv7m">;
234 def IsARClass : Predicate<"!Subtarget->isMClass()">,
235 AssemblerPredicate<"!FeatureMClass",
237 def IsARM : Predicate<"!Subtarget->isThumb()">,
238 AssemblerPredicate<"!ModeThumb", "arm-mode">;
239 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
240 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
241 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
242 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
243 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
244 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
246 // FIXME: Eventually this will be just "hasV6T2Ops".
247 def UseMovt : Predicate<"Subtarget->useMovt()">;
248 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
249 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
250 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
252 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
253 // But only select them if more precision in FP computation is allowed.
254 // Do not use them for Darwin platforms.
255 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
256 " FPOpFusion::Fast) && "
257 "!Subtarget->isTargetDarwin()">;
258 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
259 "Subtarget->isTargetDarwin()">;
261 // VGETLNi32 is microcoded on Swift - prefer VMOV.
262 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
263 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
265 // VDUP.32 is microcoded on Swift - prefer VMOV.
266 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
267 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
269 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
270 // this allows more effective execution domain optimization. See
271 // setExecutionDomain().
272 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
273 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
275 def IsLE : Predicate<"TLI.isLittleEndian()">;
276 def IsBE : Predicate<"TLI.isBigEndian()">;
278 //===----------------------------------------------------------------------===//
279 // ARM Flag Definitions.
281 class RegConstraint<string C> {
282 string Constraints = C;
285 //===----------------------------------------------------------------------===//
286 // ARM specific transformation functions and pattern fragments.
289 // imm_neg_XFORM - Return the negation of an i32 immediate value.
290 def imm_neg_XFORM : SDNodeXForm<imm, [{
291 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
294 // imm_not_XFORM - Return the complement of a i32 immediate value.
295 def imm_not_XFORM : SDNodeXForm<imm, [{
296 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
299 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
300 def imm16_31 : ImmLeaf<i32, [{
301 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
304 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
305 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
306 unsigned Value = -(unsigned)N->getZExtValue();
307 return Value && ARM_AM::getSOImmVal(Value) != -1;
309 let ParserMatchClass = so_imm_neg_asmoperand;
312 // Note: this pattern doesn't require an encoder method and such, as it's
313 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
314 // is handled by the destination instructions, which use so_imm.
315 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
316 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
317 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
319 let ParserMatchClass = so_imm_not_asmoperand;
322 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
323 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
324 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
327 /// Split a 32-bit immediate into two 16 bit parts.
328 def hi16 : SDNodeXForm<imm, [{
329 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
332 def lo16AllZero : PatLeaf<(i32 imm), [{
333 // Returns true if all low 16-bits are 0.
334 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
337 class BinOpWithFlagFrag<dag res> :
338 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
339 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
340 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
342 // An 'and' node with a single use.
343 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
344 return N->hasOneUse();
347 // An 'xor' node with a single use.
348 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
349 return N->hasOneUse();
352 // An 'fmul' node with a single use.
353 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
354 return N->hasOneUse();
357 // An 'fadd' node which checks for single non-hazardous use.
358 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
359 return hasNoVMLxHazardUse(N);
362 // An 'fsub' node which checks for single non-hazardous use.
363 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
364 return hasNoVMLxHazardUse(N);
367 //===----------------------------------------------------------------------===//
368 // Operand Definitions.
371 // Immediate operands with a shared generic asm render method.
372 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
375 // FIXME: rename brtarget to t2_brtarget
376 def brtarget : Operand<OtherVT> {
377 let EncoderMethod = "getBranchTargetOpValue";
378 let OperandType = "OPERAND_PCREL";
379 let DecoderMethod = "DecodeT2BROperand";
382 // FIXME: get rid of this one?
383 def uncondbrtarget : Operand<OtherVT> {
384 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
385 let OperandType = "OPERAND_PCREL";
388 // Branch target for ARM. Handles conditional/unconditional
389 def br_target : Operand<OtherVT> {
390 let EncoderMethod = "getARMBranchTargetOpValue";
391 let OperandType = "OPERAND_PCREL";
395 // FIXME: rename bltarget to t2_bl_target?
396 def bltarget : Operand<i32> {
397 // Encoded the same as branch targets.
398 let EncoderMethod = "getBranchTargetOpValue";
399 let OperandType = "OPERAND_PCREL";
402 // Call target for ARM. Handles conditional/unconditional
403 // FIXME: rename bl_target to t2_bltarget?
404 def bl_target : Operand<i32> {
405 let EncoderMethod = "getARMBLTargetOpValue";
406 let OperandType = "OPERAND_PCREL";
409 def blx_target : Operand<i32> {
410 let EncoderMethod = "getARMBLXTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
414 // A list of registers separated by comma. Used by load/store multiple.
415 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
416 def reglist : Operand<i32> {
417 let EncoderMethod = "getRegisterListOpValue";
418 let ParserMatchClass = RegListAsmOperand;
419 let PrintMethod = "printRegisterList";
420 let DecoderMethod = "DecodeRegListOperand";
423 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
425 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
426 def dpr_reglist : Operand<i32> {
427 let EncoderMethod = "getRegisterListOpValue";
428 let ParserMatchClass = DPRRegListAsmOperand;
429 let PrintMethod = "printRegisterList";
430 let DecoderMethod = "DecodeDPRRegListOperand";
433 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
434 def spr_reglist : Operand<i32> {
435 let EncoderMethod = "getRegisterListOpValue";
436 let ParserMatchClass = SPRRegListAsmOperand;
437 let PrintMethod = "printRegisterList";
438 let DecoderMethod = "DecodeSPRRegListOperand";
441 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
442 def cpinst_operand : Operand<i32> {
443 let PrintMethod = "printCPInstOperand";
447 def pclabel : Operand<i32> {
448 let PrintMethod = "printPCLabel";
451 // ADR instruction labels.
452 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
453 def adrlabel : Operand<i32> {
454 let EncoderMethod = "getAdrLabelOpValue";
455 let ParserMatchClass = AdrLabelAsmOperand;
456 let PrintMethod = "printAdrLabelOperand";
459 def neon_vcvt_imm32 : Operand<i32> {
460 let EncoderMethod = "getNEONVcvtImm32OpValue";
461 let DecoderMethod = "DecodeVCVTImmOperand";
464 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
465 def rot_imm_XFORM: SDNodeXForm<imm, [{
466 switch (N->getZExtValue()){
468 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
469 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
470 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
471 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
474 def RotImmAsmOperand : AsmOperandClass {
476 let ParserMethod = "parseRotImm";
478 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
479 int32_t v = N->getZExtValue();
480 return v == 8 || v == 16 || v == 24; }],
482 let PrintMethod = "printRotImmOperand";
483 let ParserMatchClass = RotImmAsmOperand;
486 // shift_imm: An integer that encodes a shift amount and the type of shift
487 // (asr or lsl). The 6-bit immediate encodes as:
490 // {4-0} imm5 shift amount.
491 // asr #32 encoded as imm5 == 0.
492 def ShifterImmAsmOperand : AsmOperandClass {
493 let Name = "ShifterImm";
494 let ParserMethod = "parseShifterImm";
496 def shift_imm : Operand<i32> {
497 let PrintMethod = "printShiftImmOperand";
498 let ParserMatchClass = ShifterImmAsmOperand;
501 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
502 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
503 def so_reg_reg : Operand<i32>, // reg reg imm
504 ComplexPattern<i32, 3, "SelectRegShifterOperand",
505 [shl, srl, sra, rotr]> {
506 let EncoderMethod = "getSORegRegOpValue";
507 let PrintMethod = "printSORegRegOperand";
508 let DecoderMethod = "DecodeSORegRegOperand";
509 let ParserMatchClass = ShiftedRegAsmOperand;
510 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
513 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
514 def so_reg_imm : Operand<i32>, // reg imm
515 ComplexPattern<i32, 2, "SelectImmShifterOperand",
516 [shl, srl, sra, rotr]> {
517 let EncoderMethod = "getSORegImmOpValue";
518 let PrintMethod = "printSORegImmOperand";
519 let DecoderMethod = "DecodeSORegImmOperand";
520 let ParserMatchClass = ShiftedImmAsmOperand;
521 let MIOperandInfo = (ops GPR, i32imm);
524 // FIXME: Does this need to be distinct from so_reg?
525 def shift_so_reg_reg : Operand<i32>, // reg reg imm
526 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
527 [shl,srl,sra,rotr]> {
528 let EncoderMethod = "getSORegRegOpValue";
529 let PrintMethod = "printSORegRegOperand";
530 let DecoderMethod = "DecodeSORegRegOperand";
531 let ParserMatchClass = ShiftedRegAsmOperand;
532 let MIOperandInfo = (ops GPR, GPR, i32imm);
535 // FIXME: Does this need to be distinct from so_reg?
536 def shift_so_reg_imm : Operand<i32>, // reg reg imm
537 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
538 [shl,srl,sra,rotr]> {
539 let EncoderMethod = "getSORegImmOpValue";
540 let PrintMethod = "printSORegImmOperand";
541 let DecoderMethod = "DecodeSORegImmOperand";
542 let ParserMatchClass = ShiftedImmAsmOperand;
543 let MIOperandInfo = (ops GPR, i32imm);
547 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
548 // 8-bit immediate rotated by an arbitrary number of bits.
549 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
550 def so_imm : Operand<i32>, ImmLeaf<i32, [{
551 return ARM_AM::getSOImmVal(Imm) != -1;
553 let EncoderMethod = "getSOImmOpValue";
554 let ParserMatchClass = SOImmAsmOperand;
555 let DecoderMethod = "DecodeSOImmOperand";
558 // Break so_imm's up into two pieces. This handles immediates with up to 16
559 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
560 // get the first/second pieces.
561 def so_imm2part : PatLeaf<(imm), [{
562 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
565 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
567 def arm_i32imm : PatLeaf<(imm), [{
568 if (Subtarget->hasV6T2Ops())
570 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
573 /// imm0_1 predicate - Immediate in the range [0,1].
574 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
575 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
577 /// imm0_3 predicate - Immediate in the range [0,3].
578 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
579 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
581 /// imm0_7 predicate - Immediate in the range [0,7].
582 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
583 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
584 return Imm >= 0 && Imm < 8;
586 let ParserMatchClass = Imm0_7AsmOperand;
589 /// imm8 predicate - Immediate is exactly 8.
590 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
591 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
592 let ParserMatchClass = Imm8AsmOperand;
595 /// imm16 predicate - Immediate is exactly 16.
596 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
597 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
598 let ParserMatchClass = Imm16AsmOperand;
601 /// imm32 predicate - Immediate is exactly 32.
602 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
603 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
604 let ParserMatchClass = Imm32AsmOperand;
607 /// imm1_7 predicate - Immediate in the range [1,7].
608 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
609 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
610 let ParserMatchClass = Imm1_7AsmOperand;
613 /// imm1_15 predicate - Immediate in the range [1,15].
614 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
615 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
616 let ParserMatchClass = Imm1_15AsmOperand;
619 /// imm1_31 predicate - Immediate in the range [1,31].
620 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
621 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
622 let ParserMatchClass = Imm1_31AsmOperand;
625 /// imm0_15 predicate - Immediate in the range [0,15].
626 def Imm0_15AsmOperand: ImmAsmOperand {
627 let Name = "Imm0_15";
628 let DiagnosticType = "ImmRange0_15";
630 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
631 return Imm >= 0 && Imm < 16;
633 let ParserMatchClass = Imm0_15AsmOperand;
636 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
637 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
638 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
639 return Imm >= 0 && Imm < 32;
641 let ParserMatchClass = Imm0_31AsmOperand;
644 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
645 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
646 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
647 return Imm >= 0 && Imm < 32;
649 let ParserMatchClass = Imm0_32AsmOperand;
652 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
653 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
654 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
655 return Imm >= 0 && Imm < 64;
657 let ParserMatchClass = Imm0_63AsmOperand;
660 /// imm0_255 predicate - Immediate in the range [0,255].
661 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
662 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
663 let ParserMatchClass = Imm0_255AsmOperand;
666 /// imm0_65535 - An immediate is in the range [0.65535].
667 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
668 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 65536;
671 let ParserMatchClass = Imm0_65535AsmOperand;
674 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
675 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
676 return -Imm >= 0 && -Imm < 65536;
679 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
680 // a relocatable expression.
682 // FIXME: This really needs a Thumb version separate from the ARM version.
683 // While the range is the same, and can thus use the same match class,
684 // the encoding is different so it should have a different encoder method.
685 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
686 def imm0_65535_expr : Operand<i32> {
687 let EncoderMethod = "getHiLo16ImmOpValue";
688 let ParserMatchClass = Imm0_65535ExprAsmOperand;
691 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
692 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
693 def imm24b : Operand<i32>, ImmLeaf<i32, [{
694 return Imm >= 0 && Imm <= 0xffffff;
696 let ParserMatchClass = Imm24bitAsmOperand;
700 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
702 def BitfieldAsmOperand : AsmOperandClass {
703 let Name = "Bitfield";
704 let ParserMethod = "parseBitfield";
707 def bf_inv_mask_imm : Operand<i32>,
709 return ARM::isBitFieldInvertedMask(N->getZExtValue());
711 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
712 let PrintMethod = "printBitfieldInvMaskImmOperand";
713 let DecoderMethod = "DecodeBitfieldMaskOperand";
714 let ParserMatchClass = BitfieldAsmOperand;
717 def imm1_32_XFORM: SDNodeXForm<imm, [{
718 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
720 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
721 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
722 uint64_t Imm = N->getZExtValue();
723 return Imm > 0 && Imm <= 32;
726 let PrintMethod = "printImmPlusOneOperand";
727 let ParserMatchClass = Imm1_32AsmOperand;
730 def imm1_16_XFORM: SDNodeXForm<imm, [{
731 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
733 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
734 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
736 let PrintMethod = "printImmPlusOneOperand";
737 let ParserMatchClass = Imm1_16AsmOperand;
740 // Define ARM specific addressing modes.
741 // addrmode_imm12 := reg +/- imm12
743 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
744 def addrmode_imm12 : Operand<i32>,
745 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
746 // 12-bit immediate operand. Note that instructions using this encode
747 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
748 // immediate values are as normal.
750 let EncoderMethod = "getAddrModeImm12OpValue";
751 let PrintMethod = "printAddrModeImm12Operand";
752 let DecoderMethod = "DecodeAddrModeImm12Operand";
753 let ParserMatchClass = MemImm12OffsetAsmOperand;
754 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
756 // ldst_so_reg := reg +/- reg shop imm
758 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
759 def ldst_so_reg : Operand<i32>,
760 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
761 let EncoderMethod = "getLdStSORegOpValue";
762 // FIXME: Simplify the printer
763 let PrintMethod = "printAddrMode2Operand";
764 let DecoderMethod = "DecodeSORegMemOperand";
765 let ParserMatchClass = MemRegOffsetAsmOperand;
766 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
769 // postidx_imm8 := +/- [0,255]
772 // {8} 1 is imm8 is non-negative. 0 otherwise.
773 // {7-0} [0,255] imm8 value.
774 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
775 def postidx_imm8 : Operand<i32> {
776 let PrintMethod = "printPostIdxImm8Operand";
777 let ParserMatchClass = PostIdxImm8AsmOperand;
778 let MIOperandInfo = (ops i32imm);
781 // postidx_imm8s4 := +/- [0,1020]
784 // {8} 1 is imm8 is non-negative. 0 otherwise.
785 // {7-0} [0,255] imm8 value, scaled by 4.
786 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
787 def postidx_imm8s4 : Operand<i32> {
788 let PrintMethod = "printPostIdxImm8s4Operand";
789 let ParserMatchClass = PostIdxImm8s4AsmOperand;
790 let MIOperandInfo = (ops i32imm);
794 // postidx_reg := +/- reg
796 def PostIdxRegAsmOperand : AsmOperandClass {
797 let Name = "PostIdxReg";
798 let ParserMethod = "parsePostIdxReg";
800 def postidx_reg : Operand<i32> {
801 let EncoderMethod = "getPostIdxRegOpValue";
802 let DecoderMethod = "DecodePostIdxReg";
803 let PrintMethod = "printPostIdxRegOperand";
804 let ParserMatchClass = PostIdxRegAsmOperand;
805 let MIOperandInfo = (ops GPRnopc, i32imm);
809 // addrmode2 := reg +/- imm12
810 // := reg +/- reg shop imm
812 // FIXME: addrmode2 should be refactored the rest of the way to always
813 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
814 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
815 def addrmode2 : Operand<i32>,
816 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
817 let EncoderMethod = "getAddrMode2OpValue";
818 let PrintMethod = "printAddrMode2Operand";
819 let ParserMatchClass = AddrMode2AsmOperand;
820 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
823 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
824 let Name = "PostIdxRegShifted";
825 let ParserMethod = "parsePostIdxReg";
827 def am2offset_reg : Operand<i32>,
828 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
829 [], [SDNPWantRoot]> {
830 let EncoderMethod = "getAddrMode2OffsetOpValue";
831 let PrintMethod = "printAddrMode2OffsetOperand";
832 // When using this for assembly, it's always as a post-index offset.
833 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
834 let MIOperandInfo = (ops GPRnopc, i32imm);
837 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
838 // the GPR is purely vestigal at this point.
839 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
840 def am2offset_imm : Operand<i32>,
841 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
842 [], [SDNPWantRoot]> {
843 let EncoderMethod = "getAddrMode2OffsetOpValue";
844 let PrintMethod = "printAddrMode2OffsetOperand";
845 let ParserMatchClass = AM2OffsetImmAsmOperand;
846 let MIOperandInfo = (ops GPRnopc, i32imm);
850 // addrmode3 := reg +/- reg
851 // addrmode3 := reg +/- imm8
853 // FIXME: split into imm vs. reg versions.
854 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
855 def addrmode3 : Operand<i32>,
856 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
857 let EncoderMethod = "getAddrMode3OpValue";
858 let PrintMethod = "printAddrMode3Operand";
859 let ParserMatchClass = AddrMode3AsmOperand;
860 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
863 // FIXME: split into imm vs. reg versions.
864 // FIXME: parser method to handle +/- register.
865 def AM3OffsetAsmOperand : AsmOperandClass {
866 let Name = "AM3Offset";
867 let ParserMethod = "parseAM3Offset";
869 def am3offset : Operand<i32>,
870 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
871 [], [SDNPWantRoot]> {
872 let EncoderMethod = "getAddrMode3OffsetOpValue";
873 let PrintMethod = "printAddrMode3OffsetOperand";
874 let ParserMatchClass = AM3OffsetAsmOperand;
875 let MIOperandInfo = (ops GPR, i32imm);
878 // ldstm_mode := {ia, ib, da, db}
880 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
881 let EncoderMethod = "getLdStmModeOpValue";
882 let PrintMethod = "printLdStmModeOperand";
885 // addrmode5 := reg +/- imm8*4
887 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
888 def addrmode5 : Operand<i32>,
889 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
890 let PrintMethod = "printAddrMode5Operand";
891 let EncoderMethod = "getAddrMode5OpValue";
892 let DecoderMethod = "DecodeAddrMode5Operand";
893 let ParserMatchClass = AddrMode5AsmOperand;
894 let MIOperandInfo = (ops GPR:$base, i32imm);
897 // addrmode6 := reg with optional alignment
899 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
900 def addrmode6 : Operand<i32>,
901 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
902 let PrintMethod = "printAddrMode6Operand";
903 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
904 let EncoderMethod = "getAddrMode6AddressOpValue";
905 let DecoderMethod = "DecodeAddrMode6Operand";
906 let ParserMatchClass = AddrMode6AsmOperand;
909 def am6offset : Operand<i32>,
910 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
911 [], [SDNPWantRoot]> {
912 let PrintMethod = "printAddrMode6OffsetOperand";
913 let MIOperandInfo = (ops GPR);
914 let EncoderMethod = "getAddrMode6OffsetOpValue";
915 let DecoderMethod = "DecodeGPRRegisterClass";
918 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
919 // (single element from one lane) for size 32.
920 def addrmode6oneL32 : Operand<i32>,
921 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
922 let PrintMethod = "printAddrMode6Operand";
923 let MIOperandInfo = (ops GPR:$addr, i32imm);
924 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
927 // Special version of addrmode6 to handle alignment encoding for VLD-dup
928 // instructions, specifically VLD4-dup.
929 def addrmode6dup : Operand<i32>,
930 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
931 let PrintMethod = "printAddrMode6Operand";
932 let MIOperandInfo = (ops GPR:$addr, i32imm);
933 let EncoderMethod = "getAddrMode6DupAddressOpValue";
934 // FIXME: This is close, but not quite right. The alignment specifier is
936 let ParserMatchClass = AddrMode6AsmOperand;
939 // addrmodepc := pc + reg
941 def addrmodepc : Operand<i32>,
942 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
943 let PrintMethod = "printAddrModePCOperand";
944 let MIOperandInfo = (ops GPR, i32imm);
947 // addr_offset_none := reg
949 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
950 def addr_offset_none : Operand<i32>,
951 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
952 let PrintMethod = "printAddrMode7Operand";
953 let DecoderMethod = "DecodeAddrMode7Operand";
954 let ParserMatchClass = MemNoOffsetAsmOperand;
955 let MIOperandInfo = (ops GPR:$base);
958 def nohash_imm : Operand<i32> {
959 let PrintMethod = "printNoHashImmediate";
962 def CoprocNumAsmOperand : AsmOperandClass {
963 let Name = "CoprocNum";
964 let ParserMethod = "parseCoprocNumOperand";
966 def p_imm : Operand<i32> {
967 let PrintMethod = "printPImmediate";
968 let ParserMatchClass = CoprocNumAsmOperand;
969 let DecoderMethod = "DecodeCoprocessor";
972 def pf_imm : Operand<i32> {
973 let PrintMethod = "printPImmediate";
974 let ParserMatchClass = CoprocNumAsmOperand;
977 def CoprocRegAsmOperand : AsmOperandClass {
978 let Name = "CoprocReg";
979 let ParserMethod = "parseCoprocRegOperand";
981 def c_imm : Operand<i32> {
982 let PrintMethod = "printCImmediate";
983 let ParserMatchClass = CoprocRegAsmOperand;
985 def CoprocOptionAsmOperand : AsmOperandClass {
986 let Name = "CoprocOption";
987 let ParserMethod = "parseCoprocOptionOperand";
989 def coproc_option_imm : Operand<i32> {
990 let PrintMethod = "printCoprocOptionImm";
991 let ParserMatchClass = CoprocOptionAsmOperand;
994 //===----------------------------------------------------------------------===//
996 include "ARMInstrFormats.td"
998 //===----------------------------------------------------------------------===//
999 // Multiclass helpers...
1002 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1003 /// binop that produces a value.
1004 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1005 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1006 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1007 PatFrag opnode, bit Commutable = 0> {
1008 // The register-immediate version is re-materializable. This is useful
1009 // in particular for taking the address of a local.
1010 let isReMaterializable = 1 in {
1011 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1012 iii, opc, "\t$Rd, $Rn, $imm",
1013 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1014 Sched<[WriteALU, ReadALU]> {
1019 let Inst{19-16} = Rn;
1020 let Inst{15-12} = Rd;
1021 let Inst{11-0} = imm;
1024 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1025 iir, opc, "\t$Rd, $Rn, $Rm",
1026 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1027 Sched<[WriteALU, ReadALU, ReadALU]> {
1032 let isCommutable = Commutable;
1033 let Inst{19-16} = Rn;
1034 let Inst{15-12} = Rd;
1035 let Inst{11-4} = 0b00000000;
1039 def rsi : AsI1<opcod, (outs GPR:$Rd),
1040 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1041 iis, opc, "\t$Rd, $Rn, $shift",
1042 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1043 Sched<[WriteALUsi, ReadALU]> {
1048 let Inst{19-16} = Rn;
1049 let Inst{15-12} = Rd;
1050 let Inst{11-5} = shift{11-5};
1052 let Inst{3-0} = shift{3-0};
1055 def rsr : AsI1<opcod, (outs GPR:$Rd),
1056 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1057 iis, opc, "\t$Rd, $Rn, $shift",
1058 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1059 Sched<[WriteALUsr, ReadALUsr]> {
1064 let Inst{19-16} = Rn;
1065 let Inst{15-12} = Rd;
1066 let Inst{11-8} = shift{11-8};
1068 let Inst{6-5} = shift{6-5};
1070 let Inst{3-0} = shift{3-0};
1074 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1075 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1076 /// it is equivalent to the AsI1_bin_irs counterpart.
1077 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1078 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1079 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1080 PatFrag opnode, bit Commutable = 0> {
1081 // The register-immediate version is re-materializable. This is useful
1082 // in particular for taking the address of a local.
1083 let isReMaterializable = 1 in {
1084 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1085 iii, opc, "\t$Rd, $Rn, $imm",
1086 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1087 Sched<[WriteALU, ReadALU]> {
1092 let Inst{19-16} = Rn;
1093 let Inst{15-12} = Rd;
1094 let Inst{11-0} = imm;
1097 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1098 iir, opc, "\t$Rd, $Rn, $Rm",
1099 [/* pattern left blank */]>,
1100 Sched<[WriteALU, ReadALU, ReadALU]> {
1104 let Inst{11-4} = 0b00000000;
1107 let Inst{15-12} = Rd;
1108 let Inst{19-16} = Rn;
1111 def rsi : AsI1<opcod, (outs GPR:$Rd),
1112 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1113 iis, opc, "\t$Rd, $Rn, $shift",
1114 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1115 Sched<[WriteALUsi, ReadALU]> {
1120 let Inst{19-16} = Rn;
1121 let Inst{15-12} = Rd;
1122 let Inst{11-5} = shift{11-5};
1124 let Inst{3-0} = shift{3-0};
1127 def rsr : AsI1<opcod, (outs GPR:$Rd),
1128 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1129 iis, opc, "\t$Rd, $Rn, $shift",
1130 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1131 Sched<[WriteALUsr, ReadALUsr]> {
1136 let Inst{19-16} = Rn;
1137 let Inst{15-12} = Rd;
1138 let Inst{11-8} = shift{11-8};
1140 let Inst{6-5} = shift{6-5};
1142 let Inst{3-0} = shift{3-0};
1146 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1148 /// These opcodes will be converted to the real non-S opcodes by
1149 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1150 let hasPostISelHook = 1, Defs = [CPSR] in {
1151 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1152 InstrItinClass iis, PatFrag opnode,
1153 bit Commutable = 0> {
1154 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1156 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1157 Sched<[WriteALU, ReadALU]>;
1159 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1161 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1162 Sched<[WriteALU, ReadALU, ReadALU]> {
1163 let isCommutable = Commutable;
1165 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1166 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1168 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1169 so_reg_imm:$shift))]>,
1170 Sched<[WriteALUsi, ReadALU]>;
1172 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1173 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1175 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1176 so_reg_reg:$shift))]>,
1177 Sched<[WriteALUSsr, ReadALUsr]>;
1181 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1182 /// operands are reversed.
1183 let hasPostISelHook = 1, Defs = [CPSR] in {
1184 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1185 InstrItinClass iis, PatFrag opnode,
1186 bit Commutable = 0> {
1187 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1189 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1190 Sched<[WriteALU, ReadALU]>;
1192 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1193 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1195 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1197 Sched<[WriteALUsi, ReadALU]>;
1199 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1200 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1202 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1204 Sched<[WriteALUSsr, ReadALUsr]>;
1208 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1209 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1210 /// a explicit result, only implicitly set CPSR.
1211 let isCompare = 1, Defs = [CPSR] in {
1212 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1213 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1214 PatFrag opnode, bit Commutable = 0> {
1215 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1217 [(opnode GPR:$Rn, so_imm:$imm)]>,
1218 Sched<[WriteCMP, ReadALU]> {
1223 let Inst{19-16} = Rn;
1224 let Inst{15-12} = 0b0000;
1225 let Inst{11-0} = imm;
1227 let Unpredictable{15-12} = 0b1111;
1229 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1231 [(opnode GPR:$Rn, GPR:$Rm)]>,
1232 Sched<[WriteCMP, ReadALU, ReadALU]> {
1235 let isCommutable = Commutable;
1238 let Inst{19-16} = Rn;
1239 let Inst{15-12} = 0b0000;
1240 let Inst{11-4} = 0b00000000;
1243 let Unpredictable{15-12} = 0b1111;
1245 def rsi : AI1<opcod, (outs),
1246 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1247 opc, "\t$Rn, $shift",
1248 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1249 Sched<[WriteCMPsi, ReadALU]> {
1254 let Inst{19-16} = Rn;
1255 let Inst{15-12} = 0b0000;
1256 let Inst{11-5} = shift{11-5};
1258 let Inst{3-0} = shift{3-0};
1260 let Unpredictable{15-12} = 0b1111;
1262 def rsr : AI1<opcod, (outs),
1263 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1264 opc, "\t$Rn, $shift",
1265 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1266 Sched<[WriteCMPsr, ReadALU]> {
1271 let Inst{19-16} = Rn;
1272 let Inst{15-12} = 0b0000;
1273 let Inst{11-8} = shift{11-8};
1275 let Inst{6-5} = shift{6-5};
1277 let Inst{3-0} = shift{3-0};
1279 let Unpredictable{15-12} = 0b1111;
1285 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1286 /// register and one whose operand is a register rotated by 8/16/24.
1287 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1288 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1289 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1290 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1291 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1292 Requires<[IsARM, HasV6]> {
1296 let Inst{19-16} = 0b1111;
1297 let Inst{15-12} = Rd;
1298 let Inst{11-10} = rot;
1302 class AI_ext_rrot_np<bits<8> opcod, string opc>
1303 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1304 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1305 Requires<[IsARM, HasV6]> {
1307 let Inst{19-16} = 0b1111;
1308 let Inst{11-10} = rot;
1311 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1312 /// register and one whose operand is a register rotated by 8/16/24.
1313 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1314 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1315 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1316 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1317 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1318 Requires<[IsARM, HasV6]> {
1323 let Inst{19-16} = Rn;
1324 let Inst{15-12} = Rd;
1325 let Inst{11-10} = rot;
1326 let Inst{9-4} = 0b000111;
1330 class AI_exta_rrot_np<bits<8> opcod, string opc>
1331 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1332 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1333 Requires<[IsARM, HasV6]> {
1336 let Inst{19-16} = Rn;
1337 let Inst{11-10} = rot;
1340 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1341 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1342 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1343 bit Commutable = 0> {
1344 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1345 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1346 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1347 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1349 Sched<[WriteALU, ReadALU]> {
1354 let Inst{15-12} = Rd;
1355 let Inst{19-16} = Rn;
1356 let Inst{11-0} = imm;
1358 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1359 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1360 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1362 Sched<[WriteALU, ReadALU, ReadALU]> {
1366 let Inst{11-4} = 0b00000000;
1368 let isCommutable = Commutable;
1370 let Inst{15-12} = Rd;
1371 let Inst{19-16} = Rn;
1373 def rsi : AsI1<opcod, (outs GPR:$Rd),
1374 (ins GPR:$Rn, so_reg_imm:$shift),
1375 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1376 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1378 Sched<[WriteALUsi, ReadALU]> {
1383 let Inst{19-16} = Rn;
1384 let Inst{15-12} = Rd;
1385 let Inst{11-5} = shift{11-5};
1387 let Inst{3-0} = shift{3-0};
1389 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1390 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1391 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1392 [(set GPRnopc:$Rd, CPSR,
1393 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1395 Sched<[WriteALUsr, ReadALUsr]> {
1400 let Inst{19-16} = Rn;
1401 let Inst{15-12} = Rd;
1402 let Inst{11-8} = shift{11-8};
1404 let Inst{6-5} = shift{6-5};
1406 let Inst{3-0} = shift{3-0};
1411 /// AI1_rsc_irs - Define instructions and patterns for rsc
1412 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1413 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1414 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1415 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1416 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1417 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1419 Sched<[WriteALU, ReadALU]> {
1424 let Inst{15-12} = Rd;
1425 let Inst{19-16} = Rn;
1426 let Inst{11-0} = imm;
1428 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1429 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1430 [/* pattern left blank */]>,
1431 Sched<[WriteALU, ReadALU, ReadALU]> {
1435 let Inst{11-4} = 0b00000000;
1438 let Inst{15-12} = Rd;
1439 let Inst{19-16} = Rn;
1441 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1442 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1443 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1445 Sched<[WriteALUsi, ReadALU]> {
1450 let Inst{19-16} = Rn;
1451 let Inst{15-12} = Rd;
1452 let Inst{11-5} = shift{11-5};
1454 let Inst{3-0} = shift{3-0};
1456 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1457 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1458 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1460 Sched<[WriteALUsr, ReadALUsr]> {
1465 let Inst{19-16} = Rn;
1466 let Inst{15-12} = Rd;
1467 let Inst{11-8} = shift{11-8};
1469 let Inst{6-5} = shift{6-5};
1471 let Inst{3-0} = shift{3-0};
1476 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1477 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1478 InstrItinClass iir, PatFrag opnode> {
1479 // Note: We use the complex addrmode_imm12 rather than just an input
1480 // GPR and a constrained immediate so that we can use this to match
1481 // frame index references and avoid matching constant pool references.
1482 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1483 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1484 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1487 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1488 let Inst{19-16} = addr{16-13}; // Rn
1489 let Inst{15-12} = Rt;
1490 let Inst{11-0} = addr{11-0}; // imm12
1492 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1493 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1494 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1497 let shift{4} = 0; // Inst{4} = 0
1498 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1499 let Inst{19-16} = shift{16-13}; // Rn
1500 let Inst{15-12} = Rt;
1501 let Inst{11-0} = shift{11-0};
1506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1507 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1508 InstrItinClass iir, PatFrag opnode> {
1509 // Note: We use the complex addrmode_imm12 rather than just an input
1510 // GPR and a constrained immediate so that we can use this to match
1511 // frame index references and avoid matching constant pool references.
1512 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1513 (ins addrmode_imm12:$addr),
1514 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1515 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1518 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1519 let Inst{19-16} = addr{16-13}; // Rn
1520 let Inst{15-12} = Rt;
1521 let Inst{11-0} = addr{11-0}; // imm12
1523 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1524 (ins ldst_so_reg:$shift),
1525 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1526 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1529 let shift{4} = 0; // Inst{4} = 0
1530 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1531 let Inst{19-16} = shift{16-13}; // Rn
1532 let Inst{15-12} = Rt;
1533 let Inst{11-0} = shift{11-0};
1539 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1540 InstrItinClass iir, PatFrag opnode> {
1541 // Note: We use the complex addrmode_imm12 rather than just an input
1542 // GPR and a constrained immediate so that we can use this to match
1543 // frame index references and avoid matching constant pool references.
1544 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1545 (ins GPR:$Rt, addrmode_imm12:$addr),
1546 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1547 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1550 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1551 let Inst{19-16} = addr{16-13}; // Rn
1552 let Inst{15-12} = Rt;
1553 let Inst{11-0} = addr{11-0}; // imm12
1555 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1556 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1557 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1560 let shift{4} = 0; // Inst{4} = 0
1561 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1562 let Inst{19-16} = shift{16-13}; // Rn
1563 let Inst{15-12} = Rt;
1564 let Inst{11-0} = shift{11-0};
1568 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1569 InstrItinClass iir, PatFrag opnode> {
1570 // Note: We use the complex addrmode_imm12 rather than just an input
1571 // GPR and a constrained immediate so that we can use this to match
1572 // frame index references and avoid matching constant pool references.
1573 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1574 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1575 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1576 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1579 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1580 let Inst{19-16} = addr{16-13}; // Rn
1581 let Inst{15-12} = Rt;
1582 let Inst{11-0} = addr{11-0}; // imm12
1584 def rs : AI2ldst<0b011, 0, isByte, (outs),
1585 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1586 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1587 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1590 let shift{4} = 0; // Inst{4} = 0
1591 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1592 let Inst{19-16} = shift{16-13}; // Rn
1593 let Inst{15-12} = Rt;
1594 let Inst{11-0} = shift{11-0};
1599 //===----------------------------------------------------------------------===//
1601 //===----------------------------------------------------------------------===//
1603 //===----------------------------------------------------------------------===//
1604 // Miscellaneous Instructions.
1607 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1608 /// the function. The first operand is the ID# for this instruction, the second
1609 /// is the index into the MachineConstantPool that this is, the third is the
1610 /// size in bytes of this constant pool entry.
1611 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1612 def CONSTPOOL_ENTRY :
1613 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1614 i32imm:$size), NoItinerary, []>;
1616 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1617 // from removing one half of the matched pairs. That breaks PEI, which assumes
1618 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1619 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1620 def ADJCALLSTACKUP :
1621 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1622 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1624 def ADJCALLSTACKDOWN :
1625 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1626 [(ARMcallseq_start timm:$amt)]>;
1629 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1630 // (These pseudos use a hand-written selection code).
1631 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1632 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1633 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1635 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1636 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1638 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1639 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1641 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1642 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1644 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1645 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1647 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1648 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1650 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1651 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1653 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1654 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1655 GPR:$set1, GPR:$set2),
1657 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1658 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1660 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1661 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1663 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1664 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1666 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1667 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1671 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1672 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1674 let Inst{27-8} = 0b00110010000011110000;
1675 let Inst{7-0} = imm;
1678 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1679 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1680 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1681 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1682 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1684 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1685 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1690 let Inst{15-12} = Rd;
1691 let Inst{19-16} = Rn;
1692 let Inst{27-20} = 0b01101000;
1693 let Inst{7-4} = 0b1011;
1694 let Inst{11-8} = 0b1111;
1695 let Unpredictable{11-8} = 0b1111;
1698 // The 16-bit operand $val can be used by a debugger to store more information
1699 // about the breakpoint.
1700 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1701 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1703 let Inst{3-0} = val{3-0};
1704 let Inst{19-8} = val{15-4};
1705 let Inst{27-20} = 0b00010010;
1706 let Inst{7-4} = 0b0111;
1709 // Change Processor State
1710 // FIXME: We should use InstAlias to handle the optional operands.
1711 class CPS<dag iops, string asm_ops>
1712 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1713 []>, Requires<[IsARM]> {
1719 let Inst{31-28} = 0b1111;
1720 let Inst{27-20} = 0b00010000;
1721 let Inst{19-18} = imod;
1722 let Inst{17} = M; // Enabled if mode is set;
1723 let Inst{16-9} = 0b00000000;
1724 let Inst{8-6} = iflags;
1726 let Inst{4-0} = mode;
1729 let DecoderMethod = "DecodeCPSInstruction" in {
1731 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1732 "$imod\t$iflags, $mode">;
1733 let mode = 0, M = 0 in
1734 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1736 let imod = 0, iflags = 0, M = 1 in
1737 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1740 // Preload signals the memory system of possible future data/instruction access.
1741 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1743 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1744 !strconcat(opc, "\t$addr"),
1745 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1748 let Inst{31-26} = 0b111101;
1749 let Inst{25} = 0; // 0 for immediate form
1750 let Inst{24} = data;
1751 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1752 let Inst{22} = read;
1753 let Inst{21-20} = 0b01;
1754 let Inst{19-16} = addr{16-13}; // Rn
1755 let Inst{15-12} = 0b1111;
1756 let Inst{11-0} = addr{11-0}; // imm12
1759 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1760 !strconcat(opc, "\t$shift"),
1761 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1763 let Inst{31-26} = 0b111101;
1764 let Inst{25} = 1; // 1 for register form
1765 let Inst{24} = data;
1766 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1767 let Inst{22} = read;
1768 let Inst{21-20} = 0b01;
1769 let Inst{19-16} = shift{16-13}; // Rn
1770 let Inst{15-12} = 0b1111;
1771 let Inst{11-0} = shift{11-0};
1776 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1777 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1778 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1780 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1781 "setend\t$end", []>, Requires<[IsARM]> {
1783 let Inst{31-10} = 0b1111000100000001000000;
1788 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1789 []>, Requires<[IsARM, HasV7]> {
1791 let Inst{27-4} = 0b001100100000111100001111;
1792 let Inst{3-0} = opt;
1796 * A5.4 Permanently UNDEFINED instructions.
1798 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1799 * Other UDF encodings generate SIGILL.
1801 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1803 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1805 * 1101 1110 iiii iiii
1806 * It uses the following encoding:
1807 * 1110 0111 1111 1110 1101 1110 1111 0000
1808 * - In ARM: UDF #60896;
1809 * - In Thumb: UDF #254 followed by a branch-to-self.
1811 let isBarrier = 1, isTerminator = 1 in
1812 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1814 Requires<[IsARM,UseNaClTrap]> {
1815 let Inst = 0xe7fedef0;
1817 let isBarrier = 1, isTerminator = 1 in
1818 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1820 Requires<[IsARM,DontUseNaClTrap]> {
1821 let Inst = 0xe7ffdefe;
1824 // Address computation and loads and stores in PIC mode.
1825 let isNotDuplicable = 1 in {
1826 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1828 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1830 let AddedComplexity = 10 in {
1831 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1833 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1835 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1837 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1839 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1841 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1843 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1845 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1847 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1849 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1851 let AddedComplexity = 10 in {
1852 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1853 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1855 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1856 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1857 addrmodepc:$addr)]>;
1859 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1860 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1862 } // isNotDuplicable = 1
1865 // LEApcrel - Load a pc-relative address into a register without offending the
1867 let neverHasSideEffects = 1, isReMaterializable = 1 in
1868 // The 'adr' mnemonic encodes differently if the label is before or after
1869 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1870 // know until then which form of the instruction will be used.
1871 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1872 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1873 Sched<[WriteALU, ReadALU]> {
1876 let Inst{27-25} = 0b001;
1878 let Inst{23-22} = label{13-12};
1881 let Inst{19-16} = 0b1111;
1882 let Inst{15-12} = Rd;
1883 let Inst{11-0} = label{11-0};
1886 let hasSideEffects = 1 in {
1887 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1890 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1891 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1895 //===----------------------------------------------------------------------===//
1896 // Control Flow Instructions.
1899 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1901 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1902 "bx", "\tlr", [(ARMretflag)]>,
1903 Requires<[IsARM, HasV4T]> {
1904 let Inst{27-0} = 0b0001001011111111111100011110;
1908 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1909 "mov", "\tpc, lr", [(ARMretflag)]>,
1910 Requires<[IsARM, NoV4T]> {
1911 let Inst{27-0} = 0b0001101000001111000000001110;
1915 // Indirect branches
1916 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1918 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1919 [(brind GPR:$dst)]>,
1920 Requires<[IsARM, HasV4T]> {
1922 let Inst{31-4} = 0b1110000100101111111111110001;
1923 let Inst{3-0} = dst;
1926 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1927 "bx", "\t$dst", [/* pattern left blank */]>,
1928 Requires<[IsARM, HasV4T]> {
1930 let Inst{27-4} = 0b000100101111111111110001;
1931 let Inst{3-0} = dst;
1935 // SP is marked as a use to prevent stack-pointer assignments that appear
1936 // immediately before calls from potentially appearing dead.
1938 // FIXME: Do we really need a non-predicated version? If so, it should
1939 // at least be a pseudo instruction expanding to the predicated version
1940 // at MC lowering time.
1941 Defs = [LR], Uses = [SP] in {
1942 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1943 IIC_Br, "bl\t$func",
1944 [(ARMcall tglobaladdr:$func)]>,
1946 let Inst{31-28} = 0b1110;
1948 let Inst{23-0} = func;
1949 let DecoderMethod = "DecodeBranchImmInstruction";
1952 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1953 IIC_Br, "bl", "\t$func",
1954 [(ARMcall_pred tglobaladdr:$func)]>,
1957 let Inst{23-0} = func;
1958 let DecoderMethod = "DecodeBranchImmInstruction";
1962 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1963 IIC_Br, "blx\t$func",
1964 [(ARMcall GPR:$func)]>,
1965 Requires<[IsARM, HasV5T]> {
1967 let Inst{31-4} = 0b1110000100101111111111110011;
1968 let Inst{3-0} = func;
1971 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1972 IIC_Br, "blx", "\t$func",
1973 [(ARMcall_pred GPR:$func)]>,
1974 Requires<[IsARM, HasV5T]> {
1976 let Inst{27-4} = 0b000100101111111111110011;
1977 let Inst{3-0} = func;
1981 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1982 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1983 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1984 Requires<[IsARM, HasV4T]>;
1987 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1988 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1989 Requires<[IsARM, NoV4T]>;
1991 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1992 // return stack predictor.
1993 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1994 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1998 let isBranch = 1, isTerminator = 1 in {
1999 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2000 // a two-value operand where a dag node expects two operands. :(
2001 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2002 IIC_Br, "b", "\t$target",
2003 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2005 let Inst{23-0} = target;
2006 let DecoderMethod = "DecodeBranchImmInstruction";
2009 let isBarrier = 1 in {
2010 // B is "predicable" since it's just a Bcc with an 'always' condition.
2011 let isPredicable = 1 in
2012 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2013 // should be sufficient.
2014 // FIXME: Is B really a Barrier? That doesn't seem right.
2015 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2016 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2018 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2019 def BR_JTr : ARMPseudoInst<(outs),
2020 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2022 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2023 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2024 // into i12 and rs suffixed versions.
2025 def BR_JTm : ARMPseudoInst<(outs),
2026 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2028 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2030 def BR_JTadd : ARMPseudoInst<(outs),
2031 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2033 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2035 } // isNotDuplicable = 1, isIndirectBranch = 1
2041 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2042 "blx\t$target", []>,
2043 Requires<[IsARM, HasV5T]> {
2044 let Inst{31-25} = 0b1111101;
2046 let Inst{23-0} = target{24-1};
2047 let Inst{24} = target{0};
2050 // Branch and Exchange Jazelle
2051 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2052 [/* pattern left blank */]> {
2054 let Inst{23-20} = 0b0010;
2055 let Inst{19-8} = 0xfff;
2056 let Inst{7-4} = 0b0010;
2057 let Inst{3-0} = func;
2062 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2063 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
2065 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
2067 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2069 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2072 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2078 // Secure Monitor Call is a system instruction.
2079 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2082 let Inst{23-4} = 0b01100000000000000111;
2083 let Inst{3-0} = opt;
2086 // Supervisor Call (Software Interrupt)
2087 let isCall = 1, Uses = [SP] in {
2088 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2090 let Inst{23-0} = svc;
2094 // Store Return State
2095 class SRSI<bit wb, string asm>
2096 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2097 NoItinerary, asm, "", []> {
2099 let Inst{31-28} = 0b1111;
2100 let Inst{27-25} = 0b100;
2104 let Inst{19-16} = 0b1101; // SP
2105 let Inst{15-5} = 0b00000101000;
2106 let Inst{4-0} = mode;
2109 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2110 let Inst{24-23} = 0;
2112 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2113 let Inst{24-23} = 0;
2115 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2116 let Inst{24-23} = 0b10;
2118 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2119 let Inst{24-23} = 0b10;
2121 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2122 let Inst{24-23} = 0b01;
2124 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2125 let Inst{24-23} = 0b01;
2127 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2128 let Inst{24-23} = 0b11;
2130 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2131 let Inst{24-23} = 0b11;
2134 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2135 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2137 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2138 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2140 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2141 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2143 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2144 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2146 // Return From Exception
2147 class RFEI<bit wb, string asm>
2148 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2149 NoItinerary, asm, "", []> {
2151 let Inst{31-28} = 0b1111;
2152 let Inst{27-25} = 0b100;
2156 let Inst{19-16} = Rn;
2157 let Inst{15-0} = 0xa00;
2160 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2161 let Inst{24-23} = 0;
2163 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2164 let Inst{24-23} = 0;
2166 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2167 let Inst{24-23} = 0b10;
2169 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2170 let Inst{24-23} = 0b10;
2172 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2173 let Inst{24-23} = 0b01;
2175 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2176 let Inst{24-23} = 0b01;
2178 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2179 let Inst{24-23} = 0b11;
2181 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2182 let Inst{24-23} = 0b11;
2185 //===----------------------------------------------------------------------===//
2186 // Load / Store Instructions.
2192 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2193 UnOpFrag<(load node:$Src)>>;
2194 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2195 UnOpFrag<(zextloadi8 node:$Src)>>;
2196 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2197 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2198 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2199 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2201 // Special LDR for loads from non-pc-relative constpools.
2202 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2203 isReMaterializable = 1, isCodeGenOnly = 1 in
2204 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2205 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2209 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2210 let Inst{19-16} = 0b1111;
2211 let Inst{15-12} = Rt;
2212 let Inst{11-0} = addr{11-0}; // imm12
2215 // Loads with zero extension
2216 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2217 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2218 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2220 // Loads with sign extension
2221 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2222 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2223 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2225 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2226 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2227 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2229 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2231 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2232 (ins addrmode3:$addr), LdMiscFrm,
2233 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2234 []>, Requires<[IsARM, HasV5TE]>;
2238 multiclass AI2_ldridx<bit isByte, string opc,
2239 InstrItinClass iii, InstrItinClass iir> {
2240 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2241 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2242 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2245 let Inst{23} = addr{12};
2246 let Inst{19-16} = addr{16-13};
2247 let Inst{11-0} = addr{11-0};
2248 let DecoderMethod = "DecodeLDRPreImm";
2249 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2252 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2253 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2254 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2257 let Inst{23} = addr{12};
2258 let Inst{19-16} = addr{16-13};
2259 let Inst{11-0} = addr{11-0};
2261 let DecoderMethod = "DecodeLDRPreReg";
2262 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2265 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2266 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2267 IndexModePost, LdFrm, iir,
2268 opc, "\t$Rt, $addr, $offset",
2269 "$addr.base = $Rn_wb", []> {
2275 let Inst{23} = offset{12};
2276 let Inst{19-16} = addr;
2277 let Inst{11-0} = offset{11-0};
2279 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2282 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2283 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2284 IndexModePost, LdFrm, iii,
2285 opc, "\t$Rt, $addr, $offset",
2286 "$addr.base = $Rn_wb", []> {
2292 let Inst{23} = offset{12};
2293 let Inst{19-16} = addr;
2294 let Inst{11-0} = offset{11-0};
2296 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2301 let mayLoad = 1, neverHasSideEffects = 1 in {
2302 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2303 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2304 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2305 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2308 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2309 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2310 (ins addrmode3:$addr), IndexModePre,
2312 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2314 let Inst{23} = addr{8}; // U bit
2315 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2316 let Inst{19-16} = addr{12-9}; // Rn
2317 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2318 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2319 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2320 let DecoderMethod = "DecodeAddrMode3Instruction";
2322 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2323 (ins addr_offset_none:$addr, am3offset:$offset),
2324 IndexModePost, LdMiscFrm, itin,
2325 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2329 let Inst{23} = offset{8}; // U bit
2330 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2331 let Inst{19-16} = addr;
2332 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2333 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2334 let DecoderMethod = "DecodeAddrMode3Instruction";
2338 let mayLoad = 1, neverHasSideEffects = 1 in {
2339 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2340 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2341 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2342 let hasExtraDefRegAllocReq = 1 in {
2343 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2344 (ins addrmode3:$addr), IndexModePre,
2345 LdMiscFrm, IIC_iLoad_d_ru,
2346 "ldrd", "\t$Rt, $Rt2, $addr!",
2347 "$addr.base = $Rn_wb", []> {
2349 let Inst{23} = addr{8}; // U bit
2350 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2351 let Inst{19-16} = addr{12-9}; // Rn
2352 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2353 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2354 let DecoderMethod = "DecodeAddrMode3Instruction";
2355 let AsmMatchConverter = "cvtLdrdPre";
2357 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2358 (ins addr_offset_none:$addr, am3offset:$offset),
2359 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2360 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2361 "$addr.base = $Rn_wb", []> {
2364 let Inst{23} = offset{8}; // U bit
2365 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2366 let Inst{19-16} = addr;
2367 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2368 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2369 let DecoderMethod = "DecodeAddrMode3Instruction";
2371 } // hasExtraDefRegAllocReq = 1
2372 } // mayLoad = 1, neverHasSideEffects = 1
2374 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2375 let mayLoad = 1, neverHasSideEffects = 1 in {
2376 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2377 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2378 IndexModePost, LdFrm, IIC_iLoad_ru,
2379 "ldrt", "\t$Rt, $addr, $offset",
2380 "$addr.base = $Rn_wb", []> {
2386 let Inst{23} = offset{12};
2387 let Inst{21} = 1; // overwrite
2388 let Inst{19-16} = addr;
2389 let Inst{11-5} = offset{11-5};
2391 let Inst{3-0} = offset{3-0};
2392 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2395 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2396 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2397 IndexModePost, LdFrm, IIC_iLoad_ru,
2398 "ldrt", "\t$Rt, $addr, $offset",
2399 "$addr.base = $Rn_wb", []> {
2405 let Inst{23} = offset{12};
2406 let Inst{21} = 1; // overwrite
2407 let Inst{19-16} = addr;
2408 let Inst{11-0} = offset{11-0};
2409 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2412 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2413 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2414 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2415 "ldrbt", "\t$Rt, $addr, $offset",
2416 "$addr.base = $Rn_wb", []> {
2422 let Inst{23} = offset{12};
2423 let Inst{21} = 1; // overwrite
2424 let Inst{19-16} = addr;
2425 let Inst{11-5} = offset{11-5};
2427 let Inst{3-0} = offset{3-0};
2428 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2431 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2432 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2433 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2434 "ldrbt", "\t$Rt, $addr, $offset",
2435 "$addr.base = $Rn_wb", []> {
2441 let Inst{23} = offset{12};
2442 let Inst{21} = 1; // overwrite
2443 let Inst{19-16} = addr;
2444 let Inst{11-0} = offset{11-0};
2445 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2448 multiclass AI3ldrT<bits<4> op, string opc> {
2449 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2450 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2451 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2452 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2454 let Inst{23} = offset{8};
2456 let Inst{11-8} = offset{7-4};
2457 let Inst{3-0} = offset{3-0};
2458 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2460 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2461 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2462 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2463 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2465 let Inst{23} = Rm{4};
2468 let Unpredictable{11-8} = 0b1111;
2469 let Inst{3-0} = Rm{3-0};
2470 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2471 let DecoderMethod = "DecodeLDR";
2475 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2476 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2477 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2482 // Stores with truncate
2483 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2484 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2485 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2488 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2489 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2490 StMiscFrm, IIC_iStore_d_r,
2491 "strd", "\t$Rt, $src2, $addr", []>,
2492 Requires<[IsARM, HasV5TE]> {
2497 multiclass AI2_stridx<bit isByte, string opc,
2498 InstrItinClass iii, InstrItinClass iir> {
2499 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2500 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2502 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2505 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2506 let Inst{19-16} = addr{16-13}; // Rn
2507 let Inst{11-0} = addr{11-0}; // imm12
2508 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2509 let DecoderMethod = "DecodeSTRPreImm";
2512 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2513 (ins GPR:$Rt, ldst_so_reg:$addr),
2514 IndexModePre, StFrm, iir,
2515 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2518 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2519 let Inst{19-16} = addr{16-13}; // Rn
2520 let Inst{11-0} = addr{11-0};
2521 let Inst{4} = 0; // Inst{4} = 0
2522 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2523 let DecoderMethod = "DecodeSTRPreReg";
2525 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2526 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2527 IndexModePost, StFrm, iir,
2528 opc, "\t$Rt, $addr, $offset",
2529 "$addr.base = $Rn_wb", []> {
2535 let Inst{23} = offset{12};
2536 let Inst{19-16} = addr;
2537 let Inst{11-0} = offset{11-0};
2540 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2543 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2544 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2545 IndexModePost, StFrm, iii,
2546 opc, "\t$Rt, $addr, $offset",
2547 "$addr.base = $Rn_wb", []> {
2553 let Inst{23} = offset{12};
2554 let Inst{19-16} = addr;
2555 let Inst{11-0} = offset{11-0};
2557 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2561 let mayStore = 1, neverHasSideEffects = 1 in {
2562 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2563 // IIC_iStore_siu depending on whether it the offset register is shifted.
2564 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2565 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2568 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2569 am2offset_reg:$offset),
2570 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2571 am2offset_reg:$offset)>;
2572 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2573 am2offset_imm:$offset),
2574 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2575 am2offset_imm:$offset)>;
2576 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2577 am2offset_reg:$offset),
2578 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2579 am2offset_reg:$offset)>;
2580 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2581 am2offset_imm:$offset),
2582 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2583 am2offset_imm:$offset)>;
2585 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2586 // put the patterns on the instruction definitions directly as ISel wants
2587 // the address base and offset to be separate operands, not a single
2588 // complex operand like we represent the instructions themselves. The
2589 // pseudos map between the two.
2590 let usesCustomInserter = 1,
2591 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2592 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2593 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2596 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2597 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2598 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2601 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2602 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2603 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2606 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2607 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2608 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2611 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2612 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2613 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2616 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2621 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2622 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2623 StMiscFrm, IIC_iStore_bh_ru,
2624 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2626 let Inst{23} = addr{8}; // U bit
2627 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2628 let Inst{19-16} = addr{12-9}; // Rn
2629 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2630 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2631 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2632 let DecoderMethod = "DecodeAddrMode3Instruction";
2635 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2636 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2637 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2638 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2639 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2640 addr_offset_none:$addr,
2641 am3offset:$offset))]> {
2644 let Inst{23} = offset{8}; // U bit
2645 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2646 let Inst{19-16} = addr;
2647 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2648 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2649 let DecoderMethod = "DecodeAddrMode3Instruction";
2652 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2653 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2654 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2655 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2656 "strd", "\t$Rt, $Rt2, $addr!",
2657 "$addr.base = $Rn_wb", []> {
2659 let Inst{23} = addr{8}; // U bit
2660 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2661 let Inst{19-16} = addr{12-9}; // Rn
2662 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2663 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2664 let DecoderMethod = "DecodeAddrMode3Instruction";
2665 let AsmMatchConverter = "cvtStrdPre";
2668 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2669 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2671 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2672 "strd", "\t$Rt, $Rt2, $addr, $offset",
2673 "$addr.base = $Rn_wb", []> {
2676 let Inst{23} = offset{8}; // U bit
2677 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2678 let Inst{19-16} = addr;
2679 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2680 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2681 let DecoderMethod = "DecodeAddrMode3Instruction";
2683 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2685 // STRT, STRBT, and STRHT
2687 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2688 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2689 IndexModePost, StFrm, IIC_iStore_bh_ru,
2690 "strbt", "\t$Rt, $addr, $offset",
2691 "$addr.base = $Rn_wb", []> {
2697 let Inst{23} = offset{12};
2698 let Inst{21} = 1; // overwrite
2699 let Inst{19-16} = addr;
2700 let Inst{11-5} = offset{11-5};
2702 let Inst{3-0} = offset{3-0};
2703 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2706 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2707 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2708 IndexModePost, StFrm, IIC_iStore_bh_ru,
2709 "strbt", "\t$Rt, $addr, $offset",
2710 "$addr.base = $Rn_wb", []> {
2716 let Inst{23} = offset{12};
2717 let Inst{21} = 1; // overwrite
2718 let Inst{19-16} = addr;
2719 let Inst{11-0} = offset{11-0};
2720 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2723 let mayStore = 1, neverHasSideEffects = 1 in {
2724 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2725 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2726 IndexModePost, StFrm, IIC_iStore_ru,
2727 "strt", "\t$Rt, $addr, $offset",
2728 "$addr.base = $Rn_wb", []> {
2734 let Inst{23} = offset{12};
2735 let Inst{21} = 1; // overwrite
2736 let Inst{19-16} = addr;
2737 let Inst{11-5} = offset{11-5};
2739 let Inst{3-0} = offset{3-0};
2740 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2743 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2744 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2745 IndexModePost, StFrm, IIC_iStore_ru,
2746 "strt", "\t$Rt, $addr, $offset",
2747 "$addr.base = $Rn_wb", []> {
2753 let Inst{23} = offset{12};
2754 let Inst{21} = 1; // overwrite
2755 let Inst{19-16} = addr;
2756 let Inst{11-0} = offset{11-0};
2757 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2762 multiclass AI3strT<bits<4> op, string opc> {
2763 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2764 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2765 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2766 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2768 let Inst{23} = offset{8};
2770 let Inst{11-8} = offset{7-4};
2771 let Inst{3-0} = offset{3-0};
2772 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2774 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2775 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2776 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2777 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2779 let Inst{23} = Rm{4};
2782 let Inst{3-0} = Rm{3-0};
2783 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2788 defm STRHT : AI3strT<0b1011, "strht">;
2791 //===----------------------------------------------------------------------===//
2792 // Load / store multiple Instructions.
2795 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2796 InstrItinClass itin, InstrItinClass itin_upd> {
2797 // IA is the default, so no need for an explicit suffix on the
2798 // mnemonic here. Without it is the canonical spelling.
2800 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2801 IndexModeNone, f, itin,
2802 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2803 let Inst{24-23} = 0b01; // Increment After
2804 let Inst{22} = P_bit;
2805 let Inst{21} = 0; // No writeback
2806 let Inst{20} = L_bit;
2809 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2810 IndexModeUpd, f, itin_upd,
2811 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2812 let Inst{24-23} = 0b01; // Increment After
2813 let Inst{22} = P_bit;
2814 let Inst{21} = 1; // Writeback
2815 let Inst{20} = L_bit;
2817 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2820 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2821 IndexModeNone, f, itin,
2822 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2823 let Inst{24-23} = 0b00; // Decrement After
2824 let Inst{22} = P_bit;
2825 let Inst{21} = 0; // No writeback
2826 let Inst{20} = L_bit;
2829 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2830 IndexModeUpd, f, itin_upd,
2831 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2832 let Inst{24-23} = 0b00; // Decrement After
2833 let Inst{22} = P_bit;
2834 let Inst{21} = 1; // Writeback
2835 let Inst{20} = L_bit;
2837 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2840 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2841 IndexModeNone, f, itin,
2842 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2843 let Inst{24-23} = 0b10; // Decrement Before
2844 let Inst{22} = P_bit;
2845 let Inst{21} = 0; // No writeback
2846 let Inst{20} = L_bit;
2849 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2850 IndexModeUpd, f, itin_upd,
2851 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2852 let Inst{24-23} = 0b10; // Decrement Before
2853 let Inst{22} = P_bit;
2854 let Inst{21} = 1; // Writeback
2855 let Inst{20} = L_bit;
2857 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2860 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2861 IndexModeNone, f, itin,
2862 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2863 let Inst{24-23} = 0b11; // Increment Before
2864 let Inst{22} = P_bit;
2865 let Inst{21} = 0; // No writeback
2866 let Inst{20} = L_bit;
2869 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2870 IndexModeUpd, f, itin_upd,
2871 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2872 let Inst{24-23} = 0b11; // Increment Before
2873 let Inst{22} = P_bit;
2874 let Inst{21} = 1; // Writeback
2875 let Inst{20} = L_bit;
2877 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2881 let neverHasSideEffects = 1 in {
2883 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2884 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2887 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2888 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2891 } // neverHasSideEffects
2893 // FIXME: remove when we have a way to marking a MI with these properties.
2894 // FIXME: Should pc be an implicit operand like PICADD, etc?
2895 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2896 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2897 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2898 reglist:$regs, variable_ops),
2899 4, IIC_iLoad_mBr, [],
2900 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2901 RegConstraint<"$Rn = $wb">;
2903 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2904 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2907 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2908 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2913 //===----------------------------------------------------------------------===//
2914 // Move Instructions.
2917 let neverHasSideEffects = 1 in
2918 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2919 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2923 let Inst{19-16} = 0b0000;
2924 let Inst{11-4} = 0b00000000;
2927 let Inst{15-12} = Rd;
2930 // A version for the smaller set of tail call registers.
2931 let neverHasSideEffects = 1 in
2932 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2933 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2937 let Inst{11-4} = 0b00000000;
2940 let Inst{15-12} = Rd;
2943 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2944 DPSoRegRegFrm, IIC_iMOVsr,
2945 "mov", "\t$Rd, $src",
2946 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2949 let Inst{15-12} = Rd;
2950 let Inst{19-16} = 0b0000;
2951 let Inst{11-8} = src{11-8};
2953 let Inst{6-5} = src{6-5};
2955 let Inst{3-0} = src{3-0};
2959 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2960 DPSoRegImmFrm, IIC_iMOVsr,
2961 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2965 let Inst{15-12} = Rd;
2966 let Inst{19-16} = 0b0000;
2967 let Inst{11-5} = src{11-5};
2969 let Inst{3-0} = src{3-0};
2973 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2974 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2975 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2979 let Inst{15-12} = Rd;
2980 let Inst{19-16} = 0b0000;
2981 let Inst{11-0} = imm;
2984 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2985 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2987 "movw", "\t$Rd, $imm",
2988 [(set GPR:$Rd, imm0_65535:$imm)]>,
2989 Requires<[IsARM, HasV6T2]>, UnaryDP {
2992 let Inst{15-12} = Rd;
2993 let Inst{11-0} = imm{11-0};
2994 let Inst{19-16} = imm{15-12};
2997 let DecoderMethod = "DecodeArmMOVTWInstruction";
3000 def : InstAlias<"mov${p} $Rd, $imm",
3001 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3004 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3005 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3007 let Constraints = "$src = $Rd" in {
3008 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3009 (ins GPR:$src, imm0_65535_expr:$imm),
3011 "movt", "\t$Rd, $imm",
3013 (or (and GPR:$src, 0xffff),
3014 lo16AllZero:$imm))]>, UnaryDP,
3015 Requires<[IsARM, HasV6T2]> {
3018 let Inst{15-12} = Rd;
3019 let Inst{11-0} = imm{11-0};
3020 let Inst{19-16} = imm{15-12};
3023 let DecoderMethod = "DecodeArmMOVTWInstruction";
3026 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3027 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3031 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3032 Requires<[IsARM, HasV6T2]>;
3034 let Uses = [CPSR] in
3035 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3036 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3039 // These aren't really mov instructions, but we have to define them this way
3040 // due to flag operands.
3042 let Defs = [CPSR] in {
3043 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3044 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3046 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3047 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3051 //===----------------------------------------------------------------------===//
3052 // Extend Instructions.
3057 def SXTB : AI_ext_rrot<0b01101010,
3058 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3059 def SXTH : AI_ext_rrot<0b01101011,
3060 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3062 def SXTAB : AI_exta_rrot<0b01101010,
3063 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3064 def SXTAH : AI_exta_rrot<0b01101011,
3065 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3067 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3069 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3073 let AddedComplexity = 16 in {
3074 def UXTB : AI_ext_rrot<0b01101110,
3075 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3076 def UXTH : AI_ext_rrot<0b01101111,
3077 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3078 def UXTB16 : AI_ext_rrot<0b01101100,
3079 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3081 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3082 // The transformation should probably be done as a combiner action
3083 // instead so we can include a check for masking back in the upper
3084 // eight bits of the source into the lower eight bits of the result.
3085 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3086 // (UXTB16r_rot GPR:$Src, 3)>;
3087 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3088 (UXTB16 GPR:$Src, 1)>;
3090 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3091 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3092 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3093 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3096 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3097 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3100 def SBFX : I<(outs GPRnopc:$Rd),
3101 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3102 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3103 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3104 Requires<[IsARM, HasV6T2]> {
3109 let Inst{27-21} = 0b0111101;
3110 let Inst{6-4} = 0b101;
3111 let Inst{20-16} = width;
3112 let Inst{15-12} = Rd;
3113 let Inst{11-7} = lsb;
3117 def UBFX : I<(outs GPR:$Rd),
3118 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3119 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3120 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3121 Requires<[IsARM, HasV6T2]> {
3126 let Inst{27-21} = 0b0111111;
3127 let Inst{6-4} = 0b101;
3128 let Inst{20-16} = width;
3129 let Inst{15-12} = Rd;
3130 let Inst{11-7} = lsb;
3134 //===----------------------------------------------------------------------===//
3135 // Arithmetic Instructions.
3138 defm ADD : AsI1_bin_irs<0b0100, "add",
3139 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3140 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3141 defm SUB : AsI1_bin_irs<0b0010, "sub",
3142 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3143 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3145 // ADD and SUB with 's' bit set.
3147 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3148 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3149 // AdjustInstrPostInstrSelection where we determine whether or not to
3150 // set the "s" bit based on CPSR liveness.
3152 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3153 // support for an optional CPSR definition that corresponds to the DAG
3154 // node's second value. We can then eliminate the implicit def of CPSR.
3155 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3156 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3157 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3158 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3160 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3161 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3162 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3163 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3165 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3166 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3167 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3169 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3170 // CPSR and the implicit def of CPSR is not needed.
3171 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3172 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3174 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3175 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3177 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3178 // The assume-no-carry-in form uses the negation of the input since add/sub
3179 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3180 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3182 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3183 (SUBri GPR:$src, so_imm_neg:$imm)>;
3184 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3185 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3187 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3188 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3189 Requires<[IsARM, HasV6T2]>;
3190 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3191 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3192 Requires<[IsARM, HasV6T2]>;
3194 // The with-carry-in form matches bitwise not instead of the negation.
3195 // Effectively, the inverse interpretation of the carry flag already accounts
3196 // for part of the negation.
3197 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3198 (SBCri GPR:$src, so_imm_not:$imm)>;
3199 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3200 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3202 // Note: These are implemented in C++ code, because they have to generate
3203 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3205 // (mul X, 2^n+1) -> (add (X << n), X)
3206 // (mul X, 2^n-1) -> (rsb X, (X << n))
3208 // ARM Arithmetic Instruction
3209 // GPR:$dst = GPR:$a op GPR:$b
3210 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3211 list<dag> pattern = [],
3212 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3213 string asm = "\t$Rd, $Rn, $Rm">
3214 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3218 let Inst{27-20} = op27_20;
3219 let Inst{11-4} = op11_4;
3220 let Inst{19-16} = Rn;
3221 let Inst{15-12} = Rd;
3224 let Unpredictable{11-8} = 0b1111;
3227 // Saturating add/subtract
3229 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3230 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3231 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3232 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3233 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3234 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3235 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3236 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3238 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3239 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3242 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3243 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3244 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3245 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3246 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3247 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3248 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3249 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3250 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3251 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3252 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3253 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3255 // Signed/Unsigned add/subtract
3257 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3258 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3259 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3260 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3261 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3262 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3263 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3264 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3265 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3266 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3267 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3268 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3270 // Signed/Unsigned halving add/subtract
3272 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3273 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3274 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3275 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3276 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3277 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3278 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3279 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3280 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3281 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3282 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3283 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3285 // Unsigned Sum of Absolute Differences [and Accumulate].
3287 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3288 MulFrm /* for convenience */, NoItinerary, "usad8",
3289 "\t$Rd, $Rn, $Rm", []>,
3290 Requires<[IsARM, HasV6]> {
3294 let Inst{27-20} = 0b01111000;
3295 let Inst{15-12} = 0b1111;
3296 let Inst{7-4} = 0b0001;
3297 let Inst{19-16} = Rd;
3298 let Inst{11-8} = Rm;
3301 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3302 MulFrm /* for convenience */, NoItinerary, "usada8",
3303 "\t$Rd, $Rn, $Rm, $Ra", []>,
3304 Requires<[IsARM, HasV6]> {
3309 let Inst{27-20} = 0b01111000;
3310 let Inst{7-4} = 0b0001;
3311 let Inst{19-16} = Rd;
3312 let Inst{15-12} = Ra;
3313 let Inst{11-8} = Rm;
3317 // Signed/Unsigned saturate
3319 def SSAT : AI<(outs GPRnopc:$Rd),
3320 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3321 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3326 let Inst{27-21} = 0b0110101;
3327 let Inst{5-4} = 0b01;
3328 let Inst{20-16} = sat_imm;
3329 let Inst{15-12} = Rd;
3330 let Inst{11-7} = sh{4-0};
3331 let Inst{6} = sh{5};
3335 def SSAT16 : AI<(outs GPRnopc:$Rd),
3336 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3337 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3341 let Inst{27-20} = 0b01101010;
3342 let Inst{11-4} = 0b11110011;
3343 let Inst{15-12} = Rd;
3344 let Inst{19-16} = sat_imm;
3348 def USAT : AI<(outs GPRnopc:$Rd),
3349 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3350 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3355 let Inst{27-21} = 0b0110111;
3356 let Inst{5-4} = 0b01;
3357 let Inst{15-12} = Rd;
3358 let Inst{11-7} = sh{4-0};
3359 let Inst{6} = sh{5};
3360 let Inst{20-16} = sat_imm;
3364 def USAT16 : AI<(outs GPRnopc:$Rd),
3365 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3366 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3370 let Inst{27-20} = 0b01101110;
3371 let Inst{11-4} = 0b11110011;
3372 let Inst{15-12} = Rd;
3373 let Inst{19-16} = sat_imm;
3377 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3378 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3379 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3380 (USAT imm:$pos, GPRnopc:$a, 0)>;
3382 //===----------------------------------------------------------------------===//
3383 // Bitwise Instructions.
3386 defm AND : AsI1_bin_irs<0b0000, "and",
3387 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3388 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3389 defm ORR : AsI1_bin_irs<0b1100, "orr",
3390 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3391 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3392 defm EOR : AsI1_bin_irs<0b0001, "eor",
3393 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3394 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3395 defm BIC : AsI1_bin_irs<0b1110, "bic",
3396 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3397 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3399 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3400 // like in the actual instruction encoding. The complexity of mapping the mask
3401 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3402 // instruction description.
3403 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3404 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3405 "bfc", "\t$Rd, $imm", "$src = $Rd",
3406 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3407 Requires<[IsARM, HasV6T2]> {
3410 let Inst{27-21} = 0b0111110;
3411 let Inst{6-0} = 0b0011111;
3412 let Inst{15-12} = Rd;
3413 let Inst{11-7} = imm{4-0}; // lsb
3414 let Inst{20-16} = imm{9-5}; // msb
3417 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3418 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3419 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3420 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3421 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3422 bf_inv_mask_imm:$imm))]>,
3423 Requires<[IsARM, HasV6T2]> {
3427 let Inst{27-21} = 0b0111110;
3428 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3429 let Inst{15-12} = Rd;
3430 let Inst{11-7} = imm{4-0}; // lsb
3431 let Inst{20-16} = imm{9-5}; // width
3435 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3436 "mvn", "\t$Rd, $Rm",
3437 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3441 let Inst{19-16} = 0b0000;
3442 let Inst{11-4} = 0b00000000;
3443 let Inst{15-12} = Rd;
3446 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3447 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3448 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3452 let Inst{19-16} = 0b0000;
3453 let Inst{15-12} = Rd;
3454 let Inst{11-5} = shift{11-5};
3456 let Inst{3-0} = shift{3-0};
3458 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3459 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3460 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3464 let Inst{19-16} = 0b0000;
3465 let Inst{15-12} = Rd;
3466 let Inst{11-8} = shift{11-8};
3468 let Inst{6-5} = shift{6-5};
3470 let Inst{3-0} = shift{3-0};
3472 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3473 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3474 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3475 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3479 let Inst{19-16} = 0b0000;
3480 let Inst{15-12} = Rd;
3481 let Inst{11-0} = imm;
3484 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3485 (BICri GPR:$src, so_imm_not:$imm)>;
3487 //===----------------------------------------------------------------------===//
3488 // Multiply Instructions.
3490 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3491 string opc, string asm, list<dag> pattern>
3492 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3496 let Inst{19-16} = Rd;
3497 let Inst{11-8} = Rm;
3500 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3501 string opc, string asm, list<dag> pattern>
3502 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3507 let Inst{19-16} = RdHi;
3508 let Inst{15-12} = RdLo;
3509 let Inst{11-8} = Rm;
3512 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3513 string opc, string asm, list<dag> pattern>
3514 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3519 let Inst{19-16} = RdHi;
3520 let Inst{15-12} = RdLo;
3521 let Inst{11-8} = Rm;
3525 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3526 // property. Remove them when it's possible to add those properties
3527 // on an individual MachineInstr, not just an instruction description.
3528 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3529 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3530 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3531 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3532 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3533 Requires<[IsARM, HasV6]> {
3534 let Inst{15-12} = 0b0000;
3535 let Unpredictable{15-12} = 0b1111;
3538 let Constraints = "@earlyclobber $Rd" in
3539 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3540 pred:$p, cc_out:$s),
3542 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3543 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3544 Requires<[IsARM, NoV6, UseMulOps]>;
3547 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3548 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3549 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3550 Requires<[IsARM, HasV6, UseMulOps]> {
3552 let Inst{15-12} = Ra;
3555 let Constraints = "@earlyclobber $Rd" in
3556 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3557 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3559 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3560 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3561 Requires<[IsARM, NoV6]>;
3563 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3564 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3565 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3566 Requires<[IsARM, HasV6T2, UseMulOps]> {
3571 let Inst{19-16} = Rd;
3572 let Inst{15-12} = Ra;
3573 let Inst{11-8} = Rm;
3577 // Extra precision multiplies with low / high results
3578 let neverHasSideEffects = 1 in {
3579 let isCommutable = 1 in {
3580 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3581 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3582 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3583 Requires<[IsARM, HasV6]>;
3585 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3586 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3587 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3588 Requires<[IsARM, HasV6]>;
3590 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3591 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3592 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3594 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3595 Requires<[IsARM, NoV6]>;
3597 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3598 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3600 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3601 Requires<[IsARM, NoV6]>;
3605 // Multiply + accumulate
3606 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3607 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3608 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3609 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3610 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3611 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3612 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3613 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3615 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3616 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3617 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3618 Requires<[IsARM, HasV6]> {
3623 let Inst{19-16} = RdHi;
3624 let Inst{15-12} = RdLo;
3625 let Inst{11-8} = Rm;
3629 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3630 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3631 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3633 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3634 pred:$p, cc_out:$s)>,
3635 Requires<[IsARM, NoV6]>;
3636 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3637 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3639 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3640 pred:$p, cc_out:$s)>,
3641 Requires<[IsARM, NoV6]>;
3644 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3645 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3646 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3648 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3649 Requires<[IsARM, NoV6]>;
3652 } // neverHasSideEffects
3654 // Most significant word multiply
3655 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3656 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3657 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3658 Requires<[IsARM, HasV6]> {
3659 let Inst{15-12} = 0b1111;
3662 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3663 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3664 Requires<[IsARM, HasV6]> {
3665 let Inst{15-12} = 0b1111;
3668 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3669 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3670 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3671 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3672 Requires<[IsARM, HasV6, UseMulOps]>;
3674 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3675 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3676 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3677 Requires<[IsARM, HasV6]>;
3679 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3680 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3681 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3682 Requires<[IsARM, HasV6, UseMulOps]>;
3684 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3685 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3686 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3687 Requires<[IsARM, HasV6]>;
3689 multiclass AI_smul<string opc, PatFrag opnode> {
3690 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3691 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3692 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3693 (sext_inreg GPR:$Rm, i16)))]>,
3694 Requires<[IsARM, HasV5TE]>;
3696 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3697 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3698 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3699 (sra GPR:$Rm, (i32 16))))]>,
3700 Requires<[IsARM, HasV5TE]>;
3702 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3703 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3704 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3705 (sext_inreg GPR:$Rm, i16)))]>,
3706 Requires<[IsARM, HasV5TE]>;
3708 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3709 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3710 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3711 (sra GPR:$Rm, (i32 16))))]>,
3712 Requires<[IsARM, HasV5TE]>;
3714 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3715 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3716 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3717 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3718 Requires<[IsARM, HasV5TE]>;
3720 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3721 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3722 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3723 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3724 Requires<[IsARM, HasV5TE]>;
3728 multiclass AI_smla<string opc, PatFrag opnode> {
3729 let DecoderMethod = "DecodeSMLAInstruction" in {
3730 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3731 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3732 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3733 [(set GPRnopc:$Rd, (add GPR:$Ra,
3734 (opnode (sext_inreg GPRnopc:$Rn, i16),
3735 (sext_inreg GPRnopc:$Rm, i16))))]>,
3736 Requires<[IsARM, HasV5TE, UseMulOps]>;
3738 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3739 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3740 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3742 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3743 (sra GPRnopc:$Rm, (i32 16)))))]>,
3744 Requires<[IsARM, HasV5TE, UseMulOps]>;
3746 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3747 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3748 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3750 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3751 (sext_inreg GPRnopc:$Rm, i16))))]>,
3752 Requires<[IsARM, HasV5TE, UseMulOps]>;
3754 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3755 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3756 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3758 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3759 (sra GPRnopc:$Rm, (i32 16)))))]>,
3760 Requires<[IsARM, HasV5TE, UseMulOps]>;
3762 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3763 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3764 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3766 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3767 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3768 Requires<[IsARM, HasV5TE, UseMulOps]>;
3770 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3771 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3772 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3774 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3775 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3776 Requires<[IsARM, HasV5TE, UseMulOps]>;
3780 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3781 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3783 // Halfword multiply accumulate long: SMLAL<x><y>.
3784 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3785 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3786 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3787 Requires<[IsARM, HasV5TE]>;
3789 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3790 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3791 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3792 Requires<[IsARM, HasV5TE]>;
3794 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3795 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3796 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3797 Requires<[IsARM, HasV5TE]>;
3799 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3800 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3801 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3802 Requires<[IsARM, HasV5TE]>;
3804 // Helper class for AI_smld.
3805 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3806 InstrItinClass itin, string opc, string asm>
3807 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3810 let Inst{27-23} = 0b01110;
3811 let Inst{22} = long;
3812 let Inst{21-20} = 0b00;
3813 let Inst{11-8} = Rm;
3820 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3821 InstrItinClass itin, string opc, string asm>
3822 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3824 let Inst{15-12} = 0b1111;
3825 let Inst{19-16} = Rd;
3827 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3828 InstrItinClass itin, string opc, string asm>
3829 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3832 let Inst{19-16} = Rd;
3833 let Inst{15-12} = Ra;
3835 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3836 InstrItinClass itin, string opc, string asm>
3837 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3840 let Inst{19-16} = RdHi;
3841 let Inst{15-12} = RdLo;
3844 multiclass AI_smld<bit sub, string opc> {
3846 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3847 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3848 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3850 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3851 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3852 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3854 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3856 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3858 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3859 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3860 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3864 defm SMLA : AI_smld<0, "smla">;
3865 defm SMLS : AI_smld<1, "smls">;
3867 multiclass AI_sdml<bit sub, string opc> {
3869 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3870 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3871 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3872 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3875 defm SMUA : AI_sdml<0, "smua">;
3876 defm SMUS : AI_sdml<1, "smus">;
3878 //===----------------------------------------------------------------------===//
3879 // Division Instructions (ARMv7-A with virtualization extension)
3881 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3882 "sdiv", "\t$Rd, $Rn, $Rm",
3883 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3884 Requires<[IsARM, HasDivideInARM]>;
3886 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3887 "udiv", "\t$Rd, $Rn, $Rm",
3888 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3889 Requires<[IsARM, HasDivideInARM]>;
3891 //===----------------------------------------------------------------------===//
3892 // Misc. Arithmetic Instructions.
3895 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3896 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3897 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3900 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3901 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3902 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3903 Requires<[IsARM, HasV6T2]>,
3906 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3907 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3908 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3911 let AddedComplexity = 5 in
3912 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3913 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3914 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3915 Requires<[IsARM, HasV6]>,
3918 let AddedComplexity = 5 in
3919 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3920 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3921 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3922 Requires<[IsARM, HasV6]>,
3925 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3926 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3929 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3930 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3931 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3932 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3933 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3935 Requires<[IsARM, HasV6]>,
3936 Sched<[WriteALUsi, ReadALU]>;
3938 // Alternate cases for PKHBT where identities eliminate some nodes.
3939 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3940 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3941 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3942 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3944 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3945 // will match the pattern below.
3946 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3947 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3948 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3949 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3950 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3952 Requires<[IsARM, HasV6]>,
3953 Sched<[WriteALUsi, ReadALU]>;
3955 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3956 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3957 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3958 (srl GPRnopc:$src2, imm16_31:$sh)),
3959 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3960 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3961 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3962 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3964 //===----------------------------------------------------------------------===//
3965 // Comparison Instructions...
3968 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3969 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3970 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3972 // ARMcmpZ can re-use the above instruction definitions.
3973 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3974 (CMPri GPR:$src, so_imm:$imm)>;
3975 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3976 (CMPrr GPR:$src, GPR:$rhs)>;
3977 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3978 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3979 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3980 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3982 // CMN register-integer
3983 let isCompare = 1, Defs = [CPSR] in {
3984 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3985 "cmn", "\t$Rn, $imm",
3986 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3991 let Inst{19-16} = Rn;
3992 let Inst{15-12} = 0b0000;
3993 let Inst{11-0} = imm;
3995 let Unpredictable{15-12} = 0b1111;
3998 // CMN register-register/shift
3999 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4000 "cmn", "\t$Rn, $Rm",
4001 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4002 GPR:$Rn, GPR:$Rm)]> {
4005 let isCommutable = 1;
4008 let Inst{19-16} = Rn;
4009 let Inst{15-12} = 0b0000;
4010 let Inst{11-4} = 0b00000000;
4013 let Unpredictable{15-12} = 0b1111;
4016 def CMNzrsi : AI1<0b1011, (outs),
4017 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4018 "cmn", "\t$Rn, $shift",
4019 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4020 GPR:$Rn, so_reg_imm:$shift)]> {
4025 let Inst{19-16} = Rn;
4026 let Inst{15-12} = 0b0000;
4027 let Inst{11-5} = shift{11-5};
4029 let Inst{3-0} = shift{3-0};
4031 let Unpredictable{15-12} = 0b1111;
4034 def CMNzrsr : AI1<0b1011, (outs),
4035 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4036 "cmn", "\t$Rn, $shift",
4037 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4038 GPRnopc:$Rn, so_reg_reg:$shift)]> {
4043 let Inst{19-16} = Rn;
4044 let Inst{15-12} = 0b0000;
4045 let Inst{11-8} = shift{11-8};
4047 let Inst{6-5} = shift{6-5};
4049 let Inst{3-0} = shift{3-0};
4051 let Unpredictable{15-12} = 0b1111;
4056 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4057 (CMNri GPR:$src, so_imm_neg:$imm)>;
4059 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4060 (CMNri GPR:$src, so_imm_neg:$imm)>;
4062 // Note that TST/TEQ don't set all the same flags that CMP does!
4063 defm TST : AI1_cmp_irs<0b1000, "tst",
4064 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4065 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4066 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4067 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4068 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4070 // Pseudo i64 compares for some floating point compares.
4071 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4073 def BCCi64 : PseudoInst<(outs),
4074 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4076 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4078 def BCCZi64 : PseudoInst<(outs),
4079 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4080 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4081 } // usesCustomInserter
4084 // Conditional moves
4085 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4086 // a two-value operand where a dag node expects two operands. :(
4087 let neverHasSideEffects = 1 in {
4089 let isCommutable = 1, isSelect = 1 in
4090 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4092 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4093 RegConstraint<"$false = $Rd">;
4095 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4096 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4098 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4099 imm:$cc, CCR:$ccr))*/]>,
4100 RegConstraint<"$false = $Rd">;
4101 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4102 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4104 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4105 imm:$cc, CCR:$ccr))*/]>,
4106 RegConstraint<"$false = $Rd">;
4109 let isMoveImm = 1 in
4110 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4111 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4114 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4116 let isMoveImm = 1 in
4117 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4118 (ins GPR:$false, so_imm:$imm, pred:$p),
4120 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4121 RegConstraint<"$false = $Rd">;
4123 // Two instruction predicate mov immediate.
4124 let isMoveImm = 1 in
4125 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4126 (ins GPR:$false, i32imm:$src, pred:$p),
4127 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4129 let isMoveImm = 1 in
4130 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4131 (ins GPR:$false, so_imm:$imm, pred:$p),
4133 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4134 RegConstraint<"$false = $Rd">;
4136 } // neverHasSideEffects
4139 //===----------------------------------------------------------------------===//
4140 // Atomic operations intrinsics
4143 def MemBarrierOptOperand : AsmOperandClass {
4144 let Name = "MemBarrierOpt";
4145 let ParserMethod = "parseMemBarrierOptOperand";
4147 def memb_opt : Operand<i32> {
4148 let PrintMethod = "printMemBOption";
4149 let ParserMatchClass = MemBarrierOptOperand;
4150 let DecoderMethod = "DecodeMemBarrierOption";
4153 // memory barriers protect the atomic sequences
4154 let hasSideEffects = 1 in {
4155 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4156 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4157 Requires<[IsARM, HasDB]> {
4159 let Inst{31-4} = 0xf57ff05;
4160 let Inst{3-0} = opt;
4164 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4165 "dsb", "\t$opt", []>,
4166 Requires<[IsARM, HasDB]> {
4168 let Inst{31-4} = 0xf57ff04;
4169 let Inst{3-0} = opt;
4172 // ISB has only full system option
4173 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4174 "isb", "\t$opt", []>,
4175 Requires<[IsARM, HasDB]> {
4177 let Inst{31-4} = 0xf57ff06;
4178 let Inst{3-0} = opt;
4181 // Pseudo instruction that combines movs + predicated rsbmi
4182 // to implement integer ABS
4183 let usesCustomInserter = 1, Defs = [CPSR] in
4184 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4186 let usesCustomInserter = 1 in {
4187 let Defs = [CPSR] in {
4188 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4189 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4190 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4191 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4192 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4193 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4194 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4195 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4196 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4197 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4198 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4199 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4200 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4201 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4202 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4203 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4204 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4205 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4206 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4207 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4208 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4209 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4210 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4211 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4212 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4213 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4214 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4215 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4216 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4217 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4218 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4219 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4220 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4221 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4222 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4223 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4224 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4225 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4226 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4227 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4228 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4229 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4230 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4231 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4232 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4233 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4234 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4235 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4236 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4237 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4238 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4239 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4240 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4241 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4242 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4243 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4244 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4245 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4246 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4247 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4248 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4249 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4250 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4251 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4252 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4253 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4254 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4255 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4256 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4257 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4258 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4259 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4260 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4261 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4262 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4263 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4264 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4265 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4266 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4267 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4268 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4269 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4270 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4271 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4272 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4273 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4274 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4275 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4277 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4279 def ATOMIC_SWAP_I8 : PseudoInst<
4280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4281 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4282 def ATOMIC_SWAP_I16 : PseudoInst<
4283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4284 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4285 def ATOMIC_SWAP_I32 : PseudoInst<
4286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4287 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4289 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4291 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4292 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4294 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4295 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4297 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4301 let usesCustomInserter = 1 in {
4302 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4303 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4305 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4308 let mayLoad = 1 in {
4309 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4311 "ldrexb", "\t$Rt, $addr", []>;
4312 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4313 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4314 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4315 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4316 let hasExtraDefRegAllocReq = 1 in
4317 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4318 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4319 let DecoderMethod = "DecodeDoubleRegLoad";
4323 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4324 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4325 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4326 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4327 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4328 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4329 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4330 let hasExtraSrcRegAllocReq = 1 in
4331 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4332 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4333 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4334 let DecoderMethod = "DecodeDoubleRegStore";
4339 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4340 Requires<[IsARM, HasV7]> {
4341 let Inst{31-0} = 0b11110101011111111111000000011111;
4344 // SWP/SWPB are deprecated in V6/V7.
4345 let mayLoad = 1, mayStore = 1 in {
4346 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4347 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4348 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4349 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4352 //===----------------------------------------------------------------------===//
4353 // Coprocessor Instructions.
4356 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4357 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4358 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4359 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4360 imm:$CRm, imm:$opc2)]> {
4368 let Inst{3-0} = CRm;
4370 let Inst{7-5} = opc2;
4371 let Inst{11-8} = cop;
4372 let Inst{15-12} = CRd;
4373 let Inst{19-16} = CRn;
4374 let Inst{23-20} = opc1;
4377 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4378 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4379 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4380 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4381 imm:$CRm, imm:$opc2)]> {
4382 let Inst{31-28} = 0b1111;
4390 let Inst{3-0} = CRm;
4392 let Inst{7-5} = opc2;
4393 let Inst{11-8} = cop;
4394 let Inst{15-12} = CRd;
4395 let Inst{19-16} = CRn;
4396 let Inst{23-20} = opc1;
4399 class ACI<dag oops, dag iops, string opc, string asm,
4400 IndexMode im = IndexModeNone>
4401 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4403 let Inst{27-25} = 0b110;
4405 class ACInoP<dag oops, dag iops, string opc, string asm,
4406 IndexMode im = IndexModeNone>
4407 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4409 let Inst{31-28} = 0b1111;
4410 let Inst{27-25} = 0b110;
4412 multiclass LdStCop<bit load, bit Dbit, string asm> {
4413 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4414 asm, "\t$cop, $CRd, $addr"> {
4418 let Inst{24} = 1; // P = 1
4419 let Inst{23} = addr{8};
4420 let Inst{22} = Dbit;
4421 let Inst{21} = 0; // W = 0
4422 let Inst{20} = load;
4423 let Inst{19-16} = addr{12-9};
4424 let Inst{15-12} = CRd;
4425 let Inst{11-8} = cop;
4426 let Inst{7-0} = addr{7-0};
4427 let DecoderMethod = "DecodeCopMemInstruction";
4429 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4430 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4434 let Inst{24} = 1; // P = 1
4435 let Inst{23} = addr{8};
4436 let Inst{22} = Dbit;
4437 let Inst{21} = 1; // W = 1
4438 let Inst{20} = load;
4439 let Inst{19-16} = addr{12-9};
4440 let Inst{15-12} = CRd;
4441 let Inst{11-8} = cop;
4442 let Inst{7-0} = addr{7-0};
4443 let DecoderMethod = "DecodeCopMemInstruction";
4445 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4446 postidx_imm8s4:$offset),
4447 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4452 let Inst{24} = 0; // P = 0
4453 let Inst{23} = offset{8};
4454 let Inst{22} = Dbit;
4455 let Inst{21} = 1; // W = 1
4456 let Inst{20} = load;
4457 let Inst{19-16} = addr;
4458 let Inst{15-12} = CRd;
4459 let Inst{11-8} = cop;
4460 let Inst{7-0} = offset{7-0};
4461 let DecoderMethod = "DecodeCopMemInstruction";
4463 def _OPTION : ACI<(outs),
4464 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4465 coproc_option_imm:$option),
4466 asm, "\t$cop, $CRd, $addr, $option"> {
4471 let Inst{24} = 0; // P = 0
4472 let Inst{23} = 1; // U = 1
4473 let Inst{22} = Dbit;
4474 let Inst{21} = 0; // W = 0
4475 let Inst{20} = load;
4476 let Inst{19-16} = addr;
4477 let Inst{15-12} = CRd;
4478 let Inst{11-8} = cop;
4479 let Inst{7-0} = option;
4480 let DecoderMethod = "DecodeCopMemInstruction";
4483 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4484 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4485 asm, "\t$cop, $CRd, $addr"> {
4489 let Inst{24} = 1; // P = 1
4490 let Inst{23} = addr{8};
4491 let Inst{22} = Dbit;
4492 let Inst{21} = 0; // W = 0
4493 let Inst{20} = load;
4494 let Inst{19-16} = addr{12-9};
4495 let Inst{15-12} = CRd;
4496 let Inst{11-8} = cop;
4497 let Inst{7-0} = addr{7-0};
4498 let DecoderMethod = "DecodeCopMemInstruction";
4500 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4501 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4505 let Inst{24} = 1; // P = 1
4506 let Inst{23} = addr{8};
4507 let Inst{22} = Dbit;
4508 let Inst{21} = 1; // W = 1
4509 let Inst{20} = load;
4510 let Inst{19-16} = addr{12-9};
4511 let Inst{15-12} = CRd;
4512 let Inst{11-8} = cop;
4513 let Inst{7-0} = addr{7-0};
4514 let DecoderMethod = "DecodeCopMemInstruction";
4516 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4517 postidx_imm8s4:$offset),
4518 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4523 let Inst{24} = 0; // P = 0
4524 let Inst{23} = offset{8};
4525 let Inst{22} = Dbit;
4526 let Inst{21} = 1; // W = 1
4527 let Inst{20} = load;
4528 let Inst{19-16} = addr;
4529 let Inst{15-12} = CRd;
4530 let Inst{11-8} = cop;
4531 let Inst{7-0} = offset{7-0};
4532 let DecoderMethod = "DecodeCopMemInstruction";
4534 def _OPTION : ACInoP<(outs),
4535 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4536 coproc_option_imm:$option),
4537 asm, "\t$cop, $CRd, $addr, $option"> {
4542 let Inst{24} = 0; // P = 0
4543 let Inst{23} = 1; // U = 1
4544 let Inst{22} = Dbit;
4545 let Inst{21} = 0; // W = 0
4546 let Inst{20} = load;
4547 let Inst{19-16} = addr;
4548 let Inst{15-12} = CRd;
4549 let Inst{11-8} = cop;
4550 let Inst{7-0} = option;
4551 let DecoderMethod = "DecodeCopMemInstruction";
4555 defm LDC : LdStCop <1, 0, "ldc">;
4556 defm LDCL : LdStCop <1, 1, "ldcl">;
4557 defm STC : LdStCop <0, 0, "stc">;
4558 defm STCL : LdStCop <0, 1, "stcl">;
4559 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4560 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4561 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4562 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4564 //===----------------------------------------------------------------------===//
4565 // Move between coprocessor and ARM core register.
4568 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4570 : ABI<0b1110, oops, iops, NoItinerary, opc,
4571 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4572 let Inst{20} = direction;
4582 let Inst{15-12} = Rt;
4583 let Inst{11-8} = cop;
4584 let Inst{23-21} = opc1;
4585 let Inst{7-5} = opc2;
4586 let Inst{3-0} = CRm;
4587 let Inst{19-16} = CRn;
4590 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4592 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4593 c_imm:$CRm, imm0_7:$opc2),
4594 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4595 imm:$CRm, imm:$opc2)]>;
4596 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4597 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4598 c_imm:$CRm, 0, pred:$p)>;
4599 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4601 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4603 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4604 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4605 c_imm:$CRm, 0, pred:$p)>;
4607 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4608 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4610 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4612 : ABXI<0b1110, oops, iops, NoItinerary,
4613 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4614 let Inst{31-28} = 0b1111;
4615 let Inst{20} = direction;
4625 let Inst{15-12} = Rt;
4626 let Inst{11-8} = cop;
4627 let Inst{23-21} = opc1;
4628 let Inst{7-5} = opc2;
4629 let Inst{3-0} = CRm;
4630 let Inst{19-16} = CRn;
4633 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4635 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4636 c_imm:$CRm, imm0_7:$opc2),
4637 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4638 imm:$CRm, imm:$opc2)]>;
4639 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4640 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4642 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4644 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4646 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4647 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4650 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4651 imm:$CRm, imm:$opc2),
4652 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4654 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4655 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4656 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4657 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4658 let Inst{23-21} = 0b010;
4659 let Inst{20} = direction;
4667 let Inst{15-12} = Rt;
4668 let Inst{19-16} = Rt2;
4669 let Inst{11-8} = cop;
4670 let Inst{7-4} = opc1;
4671 let Inst{3-0} = CRm;
4674 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4675 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4676 GPRnopc:$Rt2, imm:$CRm)]>;
4677 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4679 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4680 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4681 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4682 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4683 let Inst{31-28} = 0b1111;
4684 let Inst{23-21} = 0b010;
4685 let Inst{20} = direction;
4693 let Inst{15-12} = Rt;
4694 let Inst{19-16} = Rt2;
4695 let Inst{11-8} = cop;
4696 let Inst{7-4} = opc1;
4697 let Inst{3-0} = CRm;
4699 let DecoderMethod = "DecodeMRRC2";
4702 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4703 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4704 GPRnopc:$Rt2, imm:$CRm)]>;
4705 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4707 //===----------------------------------------------------------------------===//
4708 // Move between special register and ARM core register
4711 // Move to ARM core register from Special Register
4712 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4713 "mrs", "\t$Rd, apsr", []> {
4715 let Inst{23-16} = 0b00001111;
4716 let Unpredictable{19-17} = 0b111;
4718 let Inst{15-12} = Rd;
4720 let Inst{11-0} = 0b000000000000;
4721 let Unpredictable{11-0} = 0b110100001111;
4724 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4727 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4728 // section B9.3.9, with the R bit set to 1.
4729 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4730 "mrs", "\t$Rd, spsr", []> {
4732 let Inst{23-16} = 0b01001111;
4733 let Unpredictable{19-16} = 0b1111;
4735 let Inst{15-12} = Rd;
4737 let Inst{11-0} = 0b000000000000;
4738 let Unpredictable{11-0} = 0b110100001111;
4741 // Move from ARM core register to Special Register
4743 // No need to have both system and application versions, the encodings are the
4744 // same and the assembly parser has no way to distinguish between them. The mask
4745 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4746 // the mask with the fields to be accessed in the special register.
4747 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4748 "msr", "\t$mask, $Rn", []> {
4753 let Inst{22} = mask{4}; // R bit
4754 let Inst{21-20} = 0b10;
4755 let Inst{19-16} = mask{3-0};
4756 let Inst{15-12} = 0b1111;
4757 let Inst{11-4} = 0b00000000;
4761 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4762 "msr", "\t$mask, $a", []> {
4767 let Inst{22} = mask{4}; // R bit
4768 let Inst{21-20} = 0b10;
4769 let Inst{19-16} = mask{3-0};
4770 let Inst{15-12} = 0b1111;
4774 //===----------------------------------------------------------------------===//
4778 // __aeabi_read_tp preserves the registers r1-r3.
4779 // This is a pseudo inst so that we can get the encoding right,
4780 // complete with fixup for the aeabi_read_tp function.
4782 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4783 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4784 [(set R0, ARMthread_pointer)]>;
4787 //===----------------------------------------------------------------------===//
4788 // SJLJ Exception handling intrinsics
4789 // eh_sjlj_setjmp() is an instruction sequence to store the return
4790 // address and save #0 in R0 for the non-longjmp case.
4791 // Since by its nature we may be coming from some other function to get
4792 // here, and we're using the stack frame for the containing function to
4793 // save/restore registers, we can't keep anything live in regs across
4794 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4795 // when we get here from a longjmp(). We force everything out of registers
4796 // except for our own input by listing the relevant registers in Defs. By
4797 // doing so, we also cause the prologue/epilogue code to actively preserve
4798 // all of the callee-saved resgisters, which is exactly what we want.
4799 // A constant value is passed in $val, and we use the location as a scratch.
4801 // These are pseudo-instructions and are lowered to individual MC-insts, so
4802 // no encoding information is necessary.
4804 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4805 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4806 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4807 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4809 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4810 Requires<[IsARM, HasVFP2]>;
4814 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4815 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4816 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4818 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4819 Requires<[IsARM, NoVFP]>;
4822 // FIXME: Non-IOS version(s)
4823 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4824 Defs = [ R7, LR, SP ] in {
4825 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4827 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4828 Requires<[IsARM, IsIOS]>;
4831 // eh.sjlj.dispatchsetup pseudo-instruction.
4832 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4833 // the pseudo is expanded (which happens before any passes that need the
4834 // instruction size).
4835 let isBarrier = 1 in
4836 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4839 //===----------------------------------------------------------------------===//
4840 // Non-Instruction Patterns
4843 // ARMv4 indirect branch using (MOVr PC, dst)
4844 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4845 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4846 4, IIC_Br, [(brind GPR:$dst)],
4847 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4848 Requires<[IsARM, NoV4T]>;
4850 // Large immediate handling.
4852 // 32-bit immediate using two piece so_imms or movw + movt.
4853 // This is a single pseudo instruction, the benefit is that it can be remat'd
4854 // as a single unit instead of having to handle reg inputs.
4855 // FIXME: Remove this when we can do generalized remat.
4856 let isReMaterializable = 1, isMoveImm = 1 in
4857 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4858 [(set GPR:$dst, (arm_i32imm:$src))]>,
4861 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4862 // It also makes it possible to rematerialize the instructions.
4863 // FIXME: Remove this when we can do generalized remat and when machine licm
4864 // can properly the instructions.
4865 let isReMaterializable = 1 in {
4866 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4868 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4869 Requires<[IsARM, UseMovt]>;
4871 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4873 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4874 Requires<[IsARM, UseMovt]>;
4876 let AddedComplexity = 10 in
4877 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4879 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4880 Requires<[IsARM, UseMovt]>;
4881 } // isReMaterializable
4883 // ConstantPool, GlobalAddress, and JumpTable
4884 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4885 Requires<[IsARM, DontUseMovt]>;
4886 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4887 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4888 Requires<[IsARM, UseMovt]>;
4889 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4890 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4892 // TODO: add,sub,and, 3-instr forms?
4894 // Tail calls. These patterns also apply to Thumb mode.
4895 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4896 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4897 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4900 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4901 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4902 (BMOVPCB_CALL texternalsym:$func)>;
4904 // zextload i1 -> zextload i8
4905 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4906 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4908 // extload -> zextload
4909 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4910 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4911 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4912 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4914 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4916 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4917 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4920 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4921 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4922 (SMULBB GPR:$a, GPR:$b)>;
4923 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4924 (SMULBB GPR:$a, GPR:$b)>;
4925 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4926 (sra GPR:$b, (i32 16))),
4927 (SMULBT GPR:$a, GPR:$b)>;
4928 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4929 (SMULBT GPR:$a, GPR:$b)>;
4930 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4931 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4932 (SMULTB GPR:$a, GPR:$b)>;
4933 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4934 (SMULTB GPR:$a, GPR:$b)>;
4935 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4937 (SMULWB GPR:$a, GPR:$b)>;
4938 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4939 (SMULWB GPR:$a, GPR:$b)>;
4941 def : ARMV5MOPat<(add GPR:$acc,
4942 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4943 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4944 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4945 def : ARMV5MOPat<(add GPR:$acc,
4946 (mul sext_16_node:$a, sext_16_node:$b)),
4947 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4948 def : ARMV5MOPat<(add GPR:$acc,
4949 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4950 (sra GPR:$b, (i32 16)))),
4951 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4952 def : ARMV5MOPat<(add GPR:$acc,
4953 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4954 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4955 def : ARMV5MOPat<(add GPR:$acc,
4956 (mul (sra GPR:$a, (i32 16)),
4957 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4958 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4959 def : ARMV5MOPat<(add GPR:$acc,
4960 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4961 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4962 def : ARMV5MOPat<(add GPR:$acc,
4963 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4965 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4966 def : ARMV5MOPat<(add GPR:$acc,
4967 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4968 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4971 // Pre-v7 uses MCR for synchronization barriers.
4972 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4973 Requires<[IsARM, HasV6]>;
4975 // SXT/UXT with no rotate
4976 let AddedComplexity = 16 in {
4977 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4978 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4979 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4980 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4981 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4982 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4983 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4986 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4987 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4989 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4990 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4991 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4992 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4994 // Atomic load/store patterns
4995 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4996 (LDRBrs ldst_so_reg:$src)>;
4997 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4998 (LDRBi12 addrmode_imm12:$src)>;
4999 def : ARMPat<(atomic_load_16 addrmode3:$src),
5000 (LDRH addrmode3:$src)>;
5001 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5002 (LDRrs ldst_so_reg:$src)>;
5003 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5004 (LDRi12 addrmode_imm12:$src)>;
5005 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5006 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5007 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5008 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5009 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5010 (STRH GPR:$val, addrmode3:$ptr)>;
5011 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5012 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5013 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5014 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5017 //===----------------------------------------------------------------------===//
5021 include "ARMInstrThumb.td"
5023 //===----------------------------------------------------------------------===//
5027 include "ARMInstrThumb2.td"
5029 //===----------------------------------------------------------------------===//
5030 // Floating Point Support
5033 include "ARMInstrVFP.td"
5035 //===----------------------------------------------------------------------===//
5036 // Advanced SIMD (NEON) Support
5039 include "ARMInstrNEON.td"
5041 //===----------------------------------------------------------------------===//
5042 // Assembler aliases
5046 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5047 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5048 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5050 // System instructions
5051 def : MnemonicAlias<"swi", "svc">;
5053 // Load / Store Multiple
5054 def : MnemonicAlias<"ldmfd", "ldm">;
5055 def : MnemonicAlias<"ldmia", "ldm">;
5056 def : MnemonicAlias<"ldmea", "ldmdb">;
5057 def : MnemonicAlias<"stmfd", "stmdb">;
5058 def : MnemonicAlias<"stmia", "stm">;
5059 def : MnemonicAlias<"stmea", "stm">;
5061 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5062 // shift amount is zero (i.e., unspecified).
5063 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5064 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5065 Requires<[IsARM, HasV6]>;
5066 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5067 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5068 Requires<[IsARM, HasV6]>;
5070 // PUSH/POP aliases for STM/LDM
5071 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5072 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5074 // SSAT/USAT optional shift operand.
5075 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5076 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5077 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5078 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5081 // Extend instruction optional rotate operand.
5082 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5083 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5084 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5085 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5086 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5087 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5088 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5089 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5090 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5091 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5092 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5093 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5095 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5096 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5097 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5098 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5099 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5100 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5101 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5102 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5103 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5104 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5105 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5106 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5110 def : MnemonicAlias<"rfefa", "rfeda">;
5111 def : MnemonicAlias<"rfeea", "rfedb">;
5112 def : MnemonicAlias<"rfefd", "rfeia">;
5113 def : MnemonicAlias<"rfeed", "rfeib">;
5114 def : MnemonicAlias<"rfe", "rfeia">;
5117 def : MnemonicAlias<"srsfa", "srsda">;
5118 def : MnemonicAlias<"srsea", "srsdb">;
5119 def : MnemonicAlias<"srsfd", "srsia">;
5120 def : MnemonicAlias<"srsed", "srsib">;
5121 def : MnemonicAlias<"srs", "srsia">;
5124 def : MnemonicAlias<"qsubaddx", "qsax">;
5126 def : MnemonicAlias<"saddsubx", "sasx">;
5127 // SHASX == SHADDSUBX
5128 def : MnemonicAlias<"shaddsubx", "shasx">;
5129 // SHSAX == SHSUBADDX
5130 def : MnemonicAlias<"shsubaddx", "shsax">;
5132 def : MnemonicAlias<"ssubaddx", "ssax">;
5134 def : MnemonicAlias<"uaddsubx", "uasx">;
5135 // UHASX == UHADDSUBX
5136 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5137 // UHSAX == UHSUBADDX
5138 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5139 // UQASX == UQADDSUBX
5140 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5141 // UQSAX == UQSUBADDX
5142 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5144 def : MnemonicAlias<"usubaddx", "usax">;
5146 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5148 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5149 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5150 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5151 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5152 // Same for AND <--> BIC
5153 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5154 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5155 pred:$p, cc_out:$s)>;
5156 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5157 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5158 pred:$p, cc_out:$s)>;
5159 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5160 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5161 pred:$p, cc_out:$s)>;
5162 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5163 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5164 pred:$p, cc_out:$s)>;
5166 // Likewise, "add Rd, so_imm_neg" -> sub
5167 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5168 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5169 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5170 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5171 // Same for CMP <--> CMN via so_imm_neg
5172 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5173 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5174 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5175 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5177 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5178 // LSR, ROR, and RRX instructions.
5179 // FIXME: We need C++ parser hooks to map the alias to the MOV
5180 // encoding. It seems we should be able to do that sort of thing
5181 // in tblgen, but it could get ugly.
5182 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5183 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5184 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5186 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5187 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5189 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5190 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5192 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5193 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5196 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5197 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5198 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5199 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5200 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5202 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5203 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5205 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5206 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5208 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5209 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5213 // "neg" is and alias for "rsb rd, rn, #0"
5214 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5215 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5217 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5218 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5219 Requires<[IsARM, NoV6]>;
5221 // UMULL/SMULL are available on all arches, but the instruction definitions
5222 // need difference constraints pre-v6. Use these aliases for the assembly
5223 // parsing on pre-v6.
5224 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5225 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5226 Requires<[IsARM, NoV6]>;
5227 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5228 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5229 Requires<[IsARM, NoV6]>;
5231 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5233 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;