1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutGlue]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInGlue]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 def brtarget : Operand<OtherVT> {
295 let EncoderMethod = "getBranchTargetOpValue";
298 def uncondbrtarget : Operand<OtherVT> {
299 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
303 def bltarget : Operand<i32> {
304 // Encoded the same as branch targets.
305 let EncoderMethod = "getBranchTargetOpValue";
308 // A list of registers separated by comma. Used by load/store multiple.
309 def RegListAsmOperand : AsmOperandClass {
310 let Name = "RegList";
311 let SuperClasses = [];
314 def DPRRegListAsmOperand : AsmOperandClass {
315 let Name = "DPRRegList";
316 let SuperClasses = [];
319 def SPRRegListAsmOperand : AsmOperandClass {
320 let Name = "SPRRegList";
321 let SuperClasses = [];
324 def reglist : Operand<i32> {
325 let EncoderMethod = "getRegisterListOpValue";
326 let ParserMatchClass = RegListAsmOperand;
327 let PrintMethod = "printRegisterList";
330 def dpr_reglist : Operand<i32> {
331 let EncoderMethod = "getRegisterListOpValue";
332 let ParserMatchClass = DPRRegListAsmOperand;
333 let PrintMethod = "printRegisterList";
336 def spr_reglist : Operand<i32> {
337 let EncoderMethod = "getRegisterListOpValue";
338 let ParserMatchClass = SPRRegListAsmOperand;
339 let PrintMethod = "printRegisterList";
342 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
343 def cpinst_operand : Operand<i32> {
344 let PrintMethod = "printCPInstOperand";
348 def pclabel : Operand<i32> {
349 let PrintMethod = "printPCLabel";
352 // ADR instruction labels.
353 def adrlabel : Operand<i32> {
354 let EncoderMethod = "getAdrLabelOpValue";
357 def neon_vcvt_imm32 : Operand<i32> {
358 let EncoderMethod = "getNEONVcvtImm32OpValue";
361 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
362 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
363 int32_t v = (int32_t)N->getZExtValue();
364 return v == 8 || v == 16 || v == 24; }]> {
365 let EncoderMethod = "getRotImmOpValue";
368 // shift_imm: An integer that encodes a shift amount and the type of shift
369 // (currently either asr or lsl) using the same encoding used for the
370 // immediates in so_reg operands.
371 def shift_imm : Operand<i32> {
372 let PrintMethod = "printShiftImmOperand";
375 // shifter_operand operands: so_reg and so_imm.
376 def so_reg : Operand<i32>, // reg reg imm
377 ComplexPattern<i32, 3, "SelectShifterOperandReg",
378 [shl,srl,sra,rotr]> {
379 let EncoderMethod = "getSORegOpValue";
380 let PrintMethod = "printSORegOperand";
381 let MIOperandInfo = (ops GPR, GPR, i32imm);
383 def shift_so_reg : Operand<i32>, // reg reg imm
384 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
385 [shl,srl,sra,rotr]> {
386 let EncoderMethod = "getSORegOpValue";
387 let PrintMethod = "printSORegOperand";
388 let MIOperandInfo = (ops GPR, GPR, i32imm);
391 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
392 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
393 // represented in the imm field in the same 12-bit form that they are encoded
394 // into so_imm instructions: the 8-bit immediate is the least significant bits
395 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
396 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
397 let EncoderMethod = "getSOImmOpValue";
398 let PrintMethod = "printSOImmOperand";
401 // Break so_imm's up into two pieces. This handles immediates with up to 16
402 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
403 // get the first/second pieces.
404 def so_imm2part : PatLeaf<(imm), [{
405 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
408 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
410 def arm_i32imm : PatLeaf<(imm), [{
411 if (Subtarget->hasV6T2Ops())
413 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
416 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
417 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
418 return (int32_t)N->getZExtValue() < 32;
421 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
422 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
423 return (int32_t)N->getZExtValue() < 32;
425 let EncoderMethod = "getImmMinusOneOpValue";
428 // For movt/movw - sets the MC Encoder method.
429 // The imm is split into imm{15-12}, imm{11-0}
431 def movt_imm : Operand<i32> {
432 let EncoderMethod = "getMovtImmOpValue";
435 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
437 def bf_inv_mask_imm : Operand<i32>,
439 return ARM::isBitFieldInvertedMask(N->getZExtValue());
441 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
442 let PrintMethod = "printBitfieldInvMaskImmOperand";
445 // Define ARM specific addressing modes.
448 // addrmode_imm12 := reg +/- imm12
450 def addrmode_imm12 : Operand<i32>,
451 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
452 // 12-bit immediate operand. Note that instructions using this encode
453 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
454 // immediate values are as normal.
456 let EncoderMethod = "getAddrModeImm12OpValue";
457 let PrintMethod = "printAddrModeImm12Operand";
458 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
460 // ldst_so_reg := reg +/- reg shop imm
462 def ldst_so_reg : Operand<i32>,
463 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
464 let EncoderMethod = "getLdStSORegOpValue";
465 // FIXME: Simplify the printer
466 let PrintMethod = "printAddrMode2Operand";
467 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
470 // addrmode2 := reg +/- imm12
471 // := reg +/- reg shop imm
473 def addrmode2 : Operand<i32>,
474 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
475 let EncoderMethod = "getAddrMode2OpValue";
476 let PrintMethod = "printAddrMode2Operand";
477 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
480 def am2offset : Operand<i32>,
481 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
482 [], [SDNPWantRoot]> {
483 let EncoderMethod = "getAddrMode2OffsetOpValue";
484 let PrintMethod = "printAddrMode2OffsetOperand";
485 let MIOperandInfo = (ops GPR, i32imm);
488 // addrmode3 := reg +/- reg
489 // addrmode3 := reg +/- imm8
491 def addrmode3 : Operand<i32>,
492 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
493 let EncoderMethod = "getAddrMode3OpValue";
494 let PrintMethod = "printAddrMode3Operand";
495 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
498 def am3offset : Operand<i32>,
499 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
500 [], [SDNPWantRoot]> {
501 let EncoderMethod = "getAddrMode3OffsetOpValue";
502 let PrintMethod = "printAddrMode3OffsetOperand";
503 let MIOperandInfo = (ops GPR, i32imm);
506 // ldstm_mode := {ia, ib, da, db}
508 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
509 let EncoderMethod = "getLdStmModeOpValue";
510 let PrintMethod = "printLdStmModeOperand";
513 def MemMode5AsmOperand : AsmOperandClass {
514 let Name = "MemMode5";
515 let SuperClasses = [];
518 // addrmode5 := reg +/- imm8*4
520 def addrmode5 : Operand<i32>,
521 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
522 let PrintMethod = "printAddrMode5Operand";
523 let MIOperandInfo = (ops GPR:$base, i32imm);
524 let ParserMatchClass = MemMode5AsmOperand;
525 let EncoderMethod = "getAddrMode5OpValue";
528 // addrmode6 := reg with optional writeback
530 def addrmode6 : Operand<i32>,
531 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
532 let PrintMethod = "printAddrMode6Operand";
533 let MIOperandInfo = (ops GPR:$addr, i32imm);
534 let EncoderMethod = "getAddrMode6AddressOpValue";
537 def am6offset : Operand<i32> {
538 let PrintMethod = "printAddrMode6OffsetOperand";
539 let MIOperandInfo = (ops GPR);
540 let EncoderMethod = "getAddrMode6OffsetOpValue";
543 // Special version of addrmode6 to handle alignment encoding for VLD-dup
544 // instructions, specifically VLD4-dup.
545 def addrmode6dup : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
547 let PrintMethod = "printAddrMode6Operand";
548 let MIOperandInfo = (ops GPR:$addr, i32imm);
549 let EncoderMethod = "getAddrMode6DupAddressOpValue";
552 // addrmodepc := pc + reg
554 def addrmodepc : Operand<i32>,
555 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
556 let PrintMethod = "printAddrModePCOperand";
557 let MIOperandInfo = (ops GPR, i32imm);
560 def nohash_imm : Operand<i32> {
561 let PrintMethod = "printNoHashImmediate";
564 //===----------------------------------------------------------------------===//
566 include "ARMInstrFormats.td"
568 //===----------------------------------------------------------------------===//
569 // Multiclass helpers...
572 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
573 /// binop that produces a value.
574 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
575 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
576 PatFrag opnode, bit Commutable = 0> {
577 // The register-immediate version is re-materializable. This is useful
578 // in particular for taking the address of a local.
579 let isReMaterializable = 1 in {
580 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
581 iii, opc, "\t$Rd, $Rn, $imm",
582 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
587 let Inst{19-16} = Rn;
588 let Inst{15-12} = Rd;
589 let Inst{11-0} = imm;
592 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
593 iir, opc, "\t$Rd, $Rn, $Rm",
594 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
599 let isCommutable = Commutable;
600 let Inst{19-16} = Rn;
601 let Inst{15-12} = Rd;
602 let Inst{11-4} = 0b00000000;
605 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
606 iis, opc, "\t$Rd, $Rn, $shift",
607 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
612 let Inst{19-16} = Rn;
613 let Inst{15-12} = Rd;
614 let Inst{11-0} = shift;
618 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
619 /// instruction modifies the CPSR register.
620 let Defs = [CPSR] in {
621 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
622 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
623 PatFrag opnode, bit Commutable = 0> {
624 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
625 iii, opc, "\t$Rd, $Rn, $imm",
626 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
632 let Inst{19-16} = Rn;
633 let Inst{15-12} = Rd;
634 let Inst{11-0} = imm;
636 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
637 iir, opc, "\t$Rd, $Rn, $Rm",
638 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
642 let isCommutable = Commutable;
645 let Inst{19-16} = Rn;
646 let Inst{15-12} = Rd;
647 let Inst{11-4} = 0b00000000;
650 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
651 iis, opc, "\t$Rd, $Rn, $shift",
652 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
658 let Inst{19-16} = Rn;
659 let Inst{15-12} = Rd;
660 let Inst{11-0} = shift;
665 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
666 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
667 /// a explicit result, only implicitly set CPSR.
668 let isCompare = 1, Defs = [CPSR] in {
669 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
670 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
671 PatFrag opnode, bit Commutable = 0> {
672 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
674 [(opnode GPR:$Rn, so_imm:$imm)]> {
679 let Inst{19-16} = Rn;
680 let Inst{15-12} = 0b0000;
681 let Inst{11-0} = imm;
683 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
685 [(opnode GPR:$Rn, GPR:$Rm)]> {
688 let isCommutable = Commutable;
691 let Inst{19-16} = Rn;
692 let Inst{15-12} = 0b0000;
693 let Inst{11-4} = 0b00000000;
696 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
697 opc, "\t$Rn, $shift",
698 [(opnode GPR:$Rn, so_reg:$shift)]> {
703 let Inst{19-16} = Rn;
704 let Inst{15-12} = 0b0000;
705 let Inst{11-0} = shift;
710 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
711 /// register and one whose operand is a register rotated by 8/16/24.
712 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
713 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
714 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
715 IIC_iEXTr, opc, "\t$Rd, $Rm",
716 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
717 Requires<[IsARM, HasV6]> {
720 let Inst{19-16} = 0b1111;
721 let Inst{15-12} = Rd;
722 let Inst{11-10} = 0b00;
725 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
726 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
727 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
728 Requires<[IsARM, HasV6]> {
732 let Inst{19-16} = 0b1111;
733 let Inst{15-12} = Rd;
734 let Inst{11-10} = rot;
739 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
740 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
741 IIC_iEXTr, opc, "\t$Rd, $Rm",
742 [/* For disassembly only; pattern left blank */]>,
743 Requires<[IsARM, HasV6]> {
744 let Inst{19-16} = 0b1111;
745 let Inst{11-10} = 0b00;
747 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
748 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
749 [/* For disassembly only; pattern left blank */]>,
750 Requires<[IsARM, HasV6]> {
752 let Inst{19-16} = 0b1111;
753 let Inst{11-10} = rot;
757 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
758 /// register and one whose operand is a register rotated by 8/16/24.
759 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
760 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
761 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
762 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
763 Requires<[IsARM, HasV6]> {
767 let Inst{19-16} = Rn;
768 let Inst{15-12} = Rd;
769 let Inst{11-10} = 0b00;
770 let Inst{9-4} = 0b000111;
773 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
775 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
776 [(set GPR:$Rd, (opnode GPR:$Rn,
777 (rotr GPR:$Rm, rot_imm:$rot)))]>,
778 Requires<[IsARM, HasV6]> {
783 let Inst{19-16} = Rn;
784 let Inst{15-12} = Rd;
785 let Inst{11-10} = rot;
786 let Inst{9-4} = 0b000111;
791 // For disassembly only.
792 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
793 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
794 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
795 [/* For disassembly only; pattern left blank */]>,
796 Requires<[IsARM, HasV6]> {
797 let Inst{11-10} = 0b00;
799 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
801 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
802 [/* For disassembly only; pattern left blank */]>,
803 Requires<[IsARM, HasV6]> {
806 let Inst{19-16} = Rn;
807 let Inst{11-10} = rot;
811 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
812 let Uses = [CPSR] in {
813 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
814 bit Commutable = 0> {
815 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
816 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
817 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
823 let Inst{15-12} = Rd;
824 let Inst{19-16} = Rn;
825 let Inst{11-0} = imm;
827 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
828 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
829 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
834 let Inst{11-4} = 0b00000000;
836 let isCommutable = Commutable;
838 let Inst{15-12} = Rd;
839 let Inst{19-16} = Rn;
841 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
842 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
843 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
849 let Inst{11-0} = shift;
850 let Inst{15-12} = Rd;
851 let Inst{19-16} = Rn;
854 // Carry setting variants
855 let Defs = [CPSR] in {
856 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
857 bit Commutable = 0> {
858 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
859 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
860 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
865 let Inst{15-12} = Rd;
866 let Inst{19-16} = Rn;
867 let Inst{11-0} = imm;
871 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
872 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
873 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
878 let Inst{11-4} = 0b00000000;
879 let isCommutable = Commutable;
881 let Inst{15-12} = Rd;
882 let Inst{19-16} = Rn;
886 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
887 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
888 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
893 let Inst{11-0} = shift;
894 let Inst{15-12} = Rd;
895 let Inst{19-16} = Rn;
903 let canFoldAsLoad = 1, isReMaterializable = 1 in {
904 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
905 InstrItinClass iir, PatFrag opnode> {
906 // Note: We use the complex addrmode_imm12 rather than just an input
907 // GPR and a constrained immediate so that we can use this to match
908 // frame index references and avoid matching constant pool references.
909 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
910 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
911 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
914 let Inst{23} = addr{12}; // U (add = ('U' == 1))
915 let Inst{19-16} = addr{16-13}; // Rn
916 let Inst{15-12} = Rt;
917 let Inst{11-0} = addr{11-0}; // imm12
919 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
920 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
921 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
924 let Inst{23} = shift{12}; // U (add = ('U' == 1))
925 let Inst{19-16} = shift{16-13}; // Rn
926 let Inst{15-12} = Rt;
927 let Inst{11-0} = shift{11-0};
932 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
933 InstrItinClass iir, PatFrag opnode> {
934 // Note: We use the complex addrmode_imm12 rather than just an input
935 // GPR and a constrained immediate so that we can use this to match
936 // frame index references and avoid matching constant pool references.
937 def i12 : AI2ldst<0b010, 0, isByte, (outs),
938 (ins GPR:$Rt, addrmode_imm12:$addr),
939 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
940 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
943 let Inst{23} = addr{12}; // U (add = ('U' == 1))
944 let Inst{19-16} = addr{16-13}; // Rn
945 let Inst{15-12} = Rt;
946 let Inst{11-0} = addr{11-0}; // imm12
948 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
949 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
950 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
953 let Inst{23} = shift{12}; // U (add = ('U' == 1))
954 let Inst{19-16} = shift{16-13}; // Rn
955 let Inst{15-12} = Rt;
956 let Inst{11-0} = shift{11-0};
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
963 //===----------------------------------------------------------------------===//
964 // Miscellaneous Instructions.
967 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
968 /// the function. The first operand is the ID# for this instruction, the second
969 /// is the index into the MachineConstantPool that this is, the third is the
970 /// size in bytes of this constant pool entry.
971 let neverHasSideEffects = 1, isNotDuplicable = 1 in
972 def CONSTPOOL_ENTRY :
973 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
974 i32imm:$size), NoItinerary, []>;
976 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
977 // from removing one half of the matched pairs. That breaks PEI, which assumes
978 // these will always be in pairs, and asserts if it finds otherwise. Better way?
979 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
981 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
982 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
984 def ADJCALLSTACKDOWN :
985 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
986 [(ARMcallseq_start timm:$amt)]>;
989 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
990 [/* For disassembly only; pattern left blank */]>,
991 Requires<[IsARM, HasV6T2]> {
992 let Inst{27-16} = 0b001100100000;
993 let Inst{15-8} = 0b11110000;
994 let Inst{7-0} = 0b00000000;
997 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
998 [/* For disassembly only; pattern left blank */]>,
999 Requires<[IsARM, HasV6T2]> {
1000 let Inst{27-16} = 0b001100100000;
1001 let Inst{15-8} = 0b11110000;
1002 let Inst{7-0} = 0b00000001;
1005 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1006 [/* For disassembly only; pattern left blank */]>,
1007 Requires<[IsARM, HasV6T2]> {
1008 let Inst{27-16} = 0b001100100000;
1009 let Inst{15-8} = 0b11110000;
1010 let Inst{7-0} = 0b00000010;
1013 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1014 [/* For disassembly only; pattern left blank */]>,
1015 Requires<[IsARM, HasV6T2]> {
1016 let Inst{27-16} = 0b001100100000;
1017 let Inst{15-8} = 0b11110000;
1018 let Inst{7-0} = 0b00000011;
1021 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1023 [/* For disassembly only; pattern left blank */]>,
1024 Requires<[IsARM, HasV6]> {
1029 let Inst{15-12} = Rd;
1030 let Inst{19-16} = Rn;
1031 let Inst{27-20} = 0b01101000;
1032 let Inst{7-4} = 0b1011;
1033 let Inst{11-8} = 0b1111;
1036 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1037 [/* For disassembly only; pattern left blank */]>,
1038 Requires<[IsARM, HasV6T2]> {
1039 let Inst{27-16} = 0b001100100000;
1040 let Inst{15-8} = 0b11110000;
1041 let Inst{7-0} = 0b00000100;
1044 // The i32imm operand $val can be used by a debugger to store more information
1045 // about the breakpoint.
1046 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1047 [/* For disassembly only; pattern left blank */]>,
1050 let Inst{3-0} = val{3-0};
1051 let Inst{19-8} = val{15-4};
1052 let Inst{27-20} = 0b00010010;
1053 let Inst{7-4} = 0b0111;
1056 // Change Processor State is a system instruction -- for disassembly only.
1057 // The singleton $opt operand contains the following information:
1058 // opt{4-0} = mode from Inst{4-0}
1059 // opt{5} = changemode from Inst{17}
1060 // opt{8-6} = AIF from Inst{8-6}
1061 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1062 // FIXME: Integrated assembler will need these split out.
1063 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1064 [/* For disassembly only; pattern left blank */]>,
1066 let Inst{31-28} = 0b1111;
1067 let Inst{27-20} = 0b00010000;
1072 // Preload signals the memory system of possible future data/instruction access.
1073 // These are for disassembly only.
1074 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1076 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1077 !strconcat(opc, "\t$addr"),
1078 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1081 let Inst{31-26} = 0b111101;
1082 let Inst{25} = 0; // 0 for immediate form
1083 let Inst{24} = data;
1084 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1085 let Inst{22} = read;
1086 let Inst{21-20} = 0b01;
1087 let Inst{19-16} = addr{16-13}; // Rn
1088 let Inst{15-12} = Rt;
1089 let Inst{11-0} = addr{11-0}; // imm12
1092 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1093 !strconcat(opc, "\t$shift"),
1094 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1097 let Inst{31-26} = 0b111101;
1098 let Inst{25} = 1; // 1 for register form
1099 let Inst{24} = data;
1100 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1101 let Inst{22} = read;
1102 let Inst{21-20} = 0b01;
1103 let Inst{19-16} = shift{16-13}; // Rn
1104 let Inst{11-0} = shift{11-0};
1108 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1109 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1110 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1112 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1114 [/* For disassembly only; pattern left blank */]>,
1117 let Inst{31-10} = 0b1111000100000001000000;
1122 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1123 [/* For disassembly only; pattern left blank */]>,
1124 Requires<[IsARM, HasV7]> {
1126 let Inst{27-4} = 0b001100100000111100001111;
1127 let Inst{3-0} = opt;
1130 // A5.4 Permanently UNDEFINED instructions.
1131 let isBarrier = 1, isTerminator = 1 in
1132 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1135 let Inst = 0xe7ffdefe;
1138 // Address computation and loads and stores in PIC mode.
1139 let isNotDuplicable = 1 in {
1140 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1141 Size4Bytes, IIC_iALUr,
1142 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1144 let AddedComplexity = 10 in {
1145 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1146 Size4Bytes, IIC_iLoad_r,
1147 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1149 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1150 Size4Bytes, IIC_iLoad_bh_r,
1151 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1153 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1154 Size4Bytes, IIC_iLoad_bh_r,
1155 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1157 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1158 Size4Bytes, IIC_iLoad_bh_r,
1159 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1161 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1162 Size4Bytes, IIC_iLoad_bh_r,
1163 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1165 let AddedComplexity = 10 in {
1166 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1167 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1169 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1170 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1172 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1173 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1175 } // isNotDuplicable = 1
1178 // LEApcrel - Load a pc-relative address into a register without offending the
1180 let neverHasSideEffects = 1, isReMaterializable = 1 in
1181 // The 'adr' mnemonic encodes differently if the label is before or after
1182 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1183 // know until then which form of the instruction will be used.
1184 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1185 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1188 let Inst{27-25} = 0b001;
1190 let Inst{19-16} = 0b1111;
1191 let Inst{15-12} = Rd;
1192 let Inst{11-0} = label;
1194 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1195 Size4Bytes, IIC_iALUi, []>;
1197 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1198 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1199 Size4Bytes, IIC_iALUi, []>;
1201 //===----------------------------------------------------------------------===//
1202 // Control Flow Instructions.
1205 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1207 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1208 "bx", "\tlr", [(ARMretflag)]>,
1209 Requires<[IsARM, HasV4T]> {
1210 let Inst{27-0} = 0b0001001011111111111100011110;
1214 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1215 "mov", "\tpc, lr", [(ARMretflag)]>,
1216 Requires<[IsARM, NoV4T]> {
1217 let Inst{27-0} = 0b0001101000001111000000001110;
1221 // Indirect branches
1222 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1224 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1225 [(brind GPR:$dst)]>,
1226 Requires<[IsARM, HasV4T]> {
1228 let Inst{31-4} = 0b1110000100101111111111110001;
1229 let Inst{3-0} = dst;
1233 // FIXME: We would really like to define this as a vanilla ARMPat like:
1234 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1235 // With that, however, we can't set isBranch, isTerminator, etc..
1236 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1237 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1238 Requires<[IsARM, NoV4T]>;
1241 // All calls clobber the non-callee saved registers. SP is marked as
1242 // a use to prevent stack-pointer assignments that appear immediately
1243 // before calls from potentially appearing dead.
1245 // On non-Darwin platforms R9 is callee-saved.
1246 Defs = [R0, R1, R2, R3, R12, LR,
1247 D0, D1, D2, D3, D4, D5, D6, D7,
1248 D16, D17, D18, D19, D20, D21, D22, D23,
1249 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1251 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1252 IIC_Br, "bl\t$func",
1253 [(ARMcall tglobaladdr:$func)]>,
1254 Requires<[IsARM, IsNotDarwin]> {
1255 let Inst{31-28} = 0b1110;
1257 let Inst{23-0} = func;
1260 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1261 IIC_Br, "bl", "\t$func",
1262 [(ARMcall_pred tglobaladdr:$func)]>,
1263 Requires<[IsARM, IsNotDarwin]> {
1265 let Inst{23-0} = func;
1269 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1270 IIC_Br, "blx\t$func",
1271 [(ARMcall GPR:$func)]>,
1272 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1274 let Inst{31-4} = 0b1110000100101111111111110011;
1275 let Inst{3-0} = func;
1279 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1280 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1281 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1282 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1285 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1286 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1287 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1291 // On Darwin R9 is call-clobbered.
1292 // R7 is marked as a use to prevent frame-pointer assignments from being
1293 // moved above / below calls.
1294 Defs = [R0, R1, R2, R3, R9, R12, LR,
1295 D0, D1, D2, D3, D4, D5, D6, D7,
1296 D16, D17, D18, D19, D20, D21, D22, D23,
1297 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1298 Uses = [R7, SP] in {
1299 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1300 IIC_Br, "bl\t$func",
1301 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1302 let Inst{31-28} = 0b1110;
1304 let Inst{23-0} = func;
1307 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1308 IIC_Br, "bl", "\t$func",
1309 [(ARMcall_pred tglobaladdr:$func)]>,
1310 Requires<[IsARM, IsDarwin]> {
1312 let Inst{23-0} = func;
1316 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1317 IIC_Br, "blx\t$func",
1318 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1320 let Inst{31-4} = 0b1110000100101111111111110011;
1321 let Inst{3-0} = func;
1325 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1326 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1327 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1328 Requires<[IsARM, HasV4T, IsDarwin]>;
1331 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1332 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1333 Requires<[IsARM, NoV4T, IsDarwin]>;
1338 // FIXME: These should probably be xformed into the non-TC versions of the
1339 // instructions as part of MC lowering.
1340 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1341 // Thumb should have its own version since the instruction is actually
1342 // different, even though the mnemonic is the same.
1343 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1345 let Defs = [R0, R1, R2, R3, R9, R12,
1346 D0, D1, D2, D3, D4, D5, D6, D7,
1347 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1348 D27, D28, D29, D30, D31, PC],
1350 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1351 IIC_Br, []>, Requires<[IsDarwin]>;
1353 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1354 IIC_Br, []>, Requires<[IsDarwin]>;
1356 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1357 IIC_Br, "b\t$dst @ TAILCALL",
1358 []>, Requires<[IsARM, IsDarwin]>;
1360 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1361 IIC_Br, "b.w\t$dst @ TAILCALL",
1362 []>, Requires<[IsThumb, IsDarwin]>;
1364 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1365 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1366 []>, Requires<[IsDarwin]> {
1368 let Inst{31-4} = 0b1110000100101111111111110001;
1369 let Inst{3-0} = dst;
1373 // Non-Darwin versions (the difference is R9).
1374 let Defs = [R0, R1, R2, R3, R12,
1375 D0, D1, D2, D3, D4, D5, D6, D7,
1376 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1377 D27, D28, D29, D30, D31, PC],
1379 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1380 IIC_Br, []>, Requires<[IsNotDarwin]>;
1382 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1383 IIC_Br, []>, Requires<[IsNotDarwin]>;
1385 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1386 IIC_Br, "b\t$dst @ TAILCALL",
1387 []>, Requires<[IsARM, IsNotDarwin]>;
1389 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1390 IIC_Br, "b.w\t$dst @ TAILCALL",
1391 []>, Requires<[IsThumb, IsNotDarwin]>;
1393 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1394 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1395 []>, Requires<[IsNotDarwin]> {
1397 let Inst{31-4} = 0b1110000100101111111111110001;
1398 let Inst{3-0} = dst;
1403 let isBranch = 1, isTerminator = 1 in {
1404 // B is "predicable" since it can be xformed into a Bcc.
1405 let isBarrier = 1 in {
1406 let isPredicable = 1 in
1407 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1408 "b\t$target", [(br bb:$target)]> {
1410 let Inst{31-28} = 0b1110;
1411 let Inst{23-0} = target;
1414 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1415 def BR_JTr : ARMPseudoInst<(outs),
1416 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1417 SizeSpecial, IIC_Br,
1418 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1419 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1420 // into i12 and rs suffixed versions.
1421 def BR_JTm : ARMPseudoInst<(outs),
1422 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1423 SizeSpecial, IIC_Br,
1424 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1426 def BR_JTadd : ARMPseudoInst<(outs),
1427 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1428 SizeSpecial, IIC_Br,
1429 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1431 } // isNotDuplicable = 1, isIndirectBranch = 1
1434 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1435 // a two-value operand where a dag node expects two operands. :(
1436 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1437 IIC_Br, "b", "\t$target",
1438 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1440 let Inst{23-0} = target;
1444 // Branch and Exchange Jazelle -- for disassembly only
1445 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1446 [/* For disassembly only; pattern left blank */]> {
1447 let Inst{23-20} = 0b0010;
1448 //let Inst{19-8} = 0xfff;
1449 let Inst{7-4} = 0b0010;
1452 // Secure Monitor Call is a system instruction -- for disassembly only
1453 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1454 [/* For disassembly only; pattern left blank */]> {
1456 let Inst{23-4} = 0b01100000000000000111;
1457 let Inst{3-0} = opt;
1460 // Supervisor Call (Software Interrupt) -- for disassembly only
1461 let isCall = 1, Uses = [SP] in {
1462 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1463 [/* For disassembly only; pattern left blank */]> {
1465 let Inst{23-0} = svc;
1469 // Store Return State is a system instruction -- for disassembly only
1470 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1471 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1472 NoItinerary, "srs${amode}\tsp!, $mode",
1473 [/* For disassembly only; pattern left blank */]> {
1474 let Inst{31-28} = 0b1111;
1475 let Inst{22-20} = 0b110; // W = 1
1478 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1479 NoItinerary, "srs${amode}\tsp, $mode",
1480 [/* For disassembly only; pattern left blank */]> {
1481 let Inst{31-28} = 0b1111;
1482 let Inst{22-20} = 0b100; // W = 0
1485 // Return From Exception is a system instruction -- for disassembly only
1486 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1487 NoItinerary, "rfe${amode}\t$base!",
1488 [/* For disassembly only; pattern left blank */]> {
1489 let Inst{31-28} = 0b1111;
1490 let Inst{22-20} = 0b011; // W = 1
1493 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1494 NoItinerary, "rfe${amode}\t$base",
1495 [/* For disassembly only; pattern left blank */]> {
1496 let Inst{31-28} = 0b1111;
1497 let Inst{22-20} = 0b001; // W = 0
1499 } // isCodeGenOnly = 1
1501 //===----------------------------------------------------------------------===//
1502 // Load / store Instructions.
1508 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1509 UnOpFrag<(load node:$Src)>>;
1510 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1511 UnOpFrag<(zextloadi8 node:$Src)>>;
1512 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1513 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1514 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1515 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1517 // Special LDR for loads from non-pc-relative constpools.
1518 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1519 isReMaterializable = 1 in
1520 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1521 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1525 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1526 let Inst{19-16} = 0b1111;
1527 let Inst{15-12} = Rt;
1528 let Inst{11-0} = addr{11-0}; // imm12
1531 // Loads with zero extension
1532 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1533 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1534 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1536 // Loads with sign extension
1537 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1538 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1539 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1541 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1542 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1543 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1545 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1546 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1547 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1548 // how to represent that such that tblgen is happy and we don't
1549 // mark this codegen only?
1551 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1552 (ins addrmode3:$addr), LdMiscFrm,
1553 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1554 []>, Requires<[IsARM, HasV5TE]>;
1558 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1559 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1560 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1561 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1563 // {13} 1 == Rm, 0 == imm12
1567 let Inst{25} = addr{13};
1568 let Inst{23} = addr{12};
1569 let Inst{19-16} = addr{17-14};
1570 let Inst{11-0} = addr{11-0};
1572 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1573 (ins GPR:$Rn, am2offset:$offset),
1574 IndexModePost, LdFrm, itin,
1575 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1576 // {13} 1 == Rm, 0 == imm12
1581 let Inst{25} = offset{13};
1582 let Inst{23} = offset{12};
1583 let Inst{19-16} = Rn;
1584 let Inst{11-0} = offset{11-0};
1588 let mayLoad = 1, neverHasSideEffects = 1 in {
1589 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1590 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1593 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1594 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1595 (ins addrmode3:$addr), IndexModePre,
1597 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1599 let Inst{23} = addr{8}; // U bit
1600 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1601 let Inst{19-16} = addr{12-9}; // Rn
1602 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1603 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1605 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1606 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1608 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1611 let Inst{23} = offset{8}; // U bit
1612 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1613 let Inst{19-16} = Rn;
1614 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1615 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1619 let mayLoad = 1, neverHasSideEffects = 1 in {
1620 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1621 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1622 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1623 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1624 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1625 } // mayLoad = 1, neverHasSideEffects = 1
1627 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1628 let mayLoad = 1, neverHasSideEffects = 1 in {
1629 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1630 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1631 LdFrm, IIC_iLoad_ru,
1632 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1633 let Inst{21} = 1; // overwrite
1635 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1636 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1637 LdFrm, IIC_iLoad_bh_ru,
1638 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1639 let Inst{21} = 1; // overwrite
1641 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1642 (ins GPR:$base, am3offset:$offset), IndexModePost,
1643 LdMiscFrm, IIC_iLoad_bh_ru,
1644 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1645 let Inst{21} = 1; // overwrite
1647 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1648 (ins GPR:$base, am3offset:$offset), IndexModePost,
1649 LdMiscFrm, IIC_iLoad_bh_ru,
1650 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1651 let Inst{21} = 1; // overwrite
1653 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1654 (ins GPR:$base, am3offset:$offset), IndexModePost,
1655 LdMiscFrm, IIC_iLoad_bh_ru,
1656 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1657 let Inst{21} = 1; // overwrite
1663 // Stores with truncate
1664 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1665 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1666 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1669 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1670 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1671 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1672 StMiscFrm, IIC_iStore_d_r,
1673 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1676 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1677 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1678 IndexModePre, StFrm, IIC_iStore_ru,
1679 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1681 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1683 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1684 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1685 IndexModePost, StFrm, IIC_iStore_ru,
1686 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1688 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1690 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1691 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1692 IndexModePre, StFrm, IIC_iStore_bh_ru,
1693 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1694 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1695 GPR:$Rn, am2offset:$offset))]>;
1696 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1697 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1698 IndexModePost, StFrm, IIC_iStore_bh_ru,
1699 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1700 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1701 GPR:$Rn, am2offset:$offset))]>;
1703 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1704 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1705 IndexModePre, StMiscFrm, IIC_iStore_ru,
1706 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1708 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1710 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1711 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1712 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1713 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1714 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1715 GPR:$Rn, am3offset:$offset))]>;
1717 // For disassembly only
1718 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1719 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1720 StMiscFrm, IIC_iStore_d_ru,
1721 "strd", "\t$src1, $src2, [$base, $offset]!",
1722 "$base = $base_wb", []>;
1724 // For disassembly only
1725 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1726 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1727 StMiscFrm, IIC_iStore_d_ru,
1728 "strd", "\t$src1, $src2, [$base], $offset",
1729 "$base = $base_wb", []>;
1731 // STRT, STRBT, and STRHT are for disassembly only.
1733 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1734 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1735 IndexModeNone, StFrm, IIC_iStore_ru,
1736 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1737 [/* For disassembly only; pattern left blank */]> {
1738 let Inst{21} = 1; // overwrite
1741 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1742 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1743 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1744 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1745 [/* For disassembly only; pattern left blank */]> {
1746 let Inst{21} = 1; // overwrite
1749 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1750 (ins GPR:$src, GPR:$base,am3offset:$offset),
1751 StMiscFrm, IIC_iStore_bh_ru,
1752 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1753 [/* For disassembly only; pattern left blank */]> {
1754 let Inst{21} = 1; // overwrite
1757 //===----------------------------------------------------------------------===//
1758 // Load / store multiple Instructions.
1761 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1762 InstrItinClass itin, InstrItinClass itin_upd> {
1764 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1765 IndexModeNone, f, itin,
1766 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1767 let Inst{24-23} = 0b01; // Increment After
1768 let Inst{21} = 0; // No writeback
1769 let Inst{20} = L_bit;
1772 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1773 IndexModeUpd, f, itin_upd,
1774 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1775 let Inst{24-23} = 0b01; // Increment After
1776 let Inst{21} = 1; // Writeback
1777 let Inst{20} = L_bit;
1780 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1781 IndexModeNone, f, itin,
1782 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1783 let Inst{24-23} = 0b00; // Decrement After
1784 let Inst{21} = 0; // No writeback
1785 let Inst{20} = L_bit;
1788 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1789 IndexModeUpd, f, itin_upd,
1790 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1791 let Inst{24-23} = 0b00; // Decrement After
1792 let Inst{21} = 1; // Writeback
1793 let Inst{20} = L_bit;
1796 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1797 IndexModeNone, f, itin,
1798 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1799 let Inst{24-23} = 0b10; // Decrement Before
1800 let Inst{21} = 0; // No writeback
1801 let Inst{20} = L_bit;
1804 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1805 IndexModeUpd, f, itin_upd,
1806 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1807 let Inst{24-23} = 0b10; // Decrement Before
1808 let Inst{21} = 1; // Writeback
1809 let Inst{20} = L_bit;
1812 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1813 IndexModeNone, f, itin,
1814 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1815 let Inst{24-23} = 0b11; // Increment Before
1816 let Inst{21} = 0; // No writeback
1817 let Inst{20} = L_bit;
1820 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1821 IndexModeUpd, f, itin_upd,
1822 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1823 let Inst{24-23} = 0b11; // Increment Before
1824 let Inst{21} = 1; // Writeback
1825 let Inst{20} = L_bit;
1829 let neverHasSideEffects = 1 in {
1831 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1832 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1834 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1835 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1837 } // neverHasSideEffects
1839 // Load / Store Multiple Mnemnoic Aliases
1840 def : MnemonicAlias<"ldm", "ldmia">;
1841 def : MnemonicAlias<"stm", "stmia">;
1843 // FIXME: remove when we have a way to marking a MI with these properties.
1844 // FIXME: Should pc be an implicit operand like PICADD, etc?
1845 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1846 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1847 // FIXME: Should be a pseudo-instruction.
1848 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1849 reglist:$regs, variable_ops),
1850 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1851 "ldmia${p}\t$Rn!, $regs",
1853 let Inst{24-23} = 0b01; // Increment After
1854 let Inst{21} = 1; // Writeback
1855 let Inst{20} = 1; // Load
1858 //===----------------------------------------------------------------------===//
1859 // Move Instructions.
1862 let neverHasSideEffects = 1 in
1863 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1864 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1868 let Inst{11-4} = 0b00000000;
1871 let Inst{15-12} = Rd;
1874 // A version for the smaller set of tail call registers.
1875 let neverHasSideEffects = 1 in
1876 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1877 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1881 let Inst{11-4} = 0b00000000;
1884 let Inst{15-12} = Rd;
1887 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1888 DPSoRegFrm, IIC_iMOVsr,
1889 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1893 let Inst{15-12} = Rd;
1894 let Inst{11-0} = src;
1898 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1899 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1900 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1904 let Inst{15-12} = Rd;
1905 let Inst{19-16} = 0b0000;
1906 let Inst{11-0} = imm;
1909 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1910 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1912 "movw", "\t$Rd, $imm",
1913 [(set GPR:$Rd, imm0_65535:$imm)]>,
1914 Requires<[IsARM, HasV6T2]>, UnaryDP {
1917 let Inst{15-12} = Rd;
1918 let Inst{11-0} = imm{11-0};
1919 let Inst{19-16} = imm{15-12};
1924 let Constraints = "$src = $Rd" in
1925 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1927 "movt", "\t$Rd, $imm",
1929 (or (and GPR:$src, 0xffff),
1930 lo16AllZero:$imm))]>, UnaryDP,
1931 Requires<[IsARM, HasV6T2]> {
1934 let Inst{15-12} = Rd;
1935 let Inst{11-0} = imm{11-0};
1936 let Inst{19-16} = imm{15-12};
1941 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1942 Requires<[IsARM, HasV6T2]>;
1944 let Uses = [CPSR] in
1945 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1946 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1949 // These aren't really mov instructions, but we have to define them this way
1950 // due to flag operands.
1952 let Defs = [CPSR] in {
1953 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1954 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1956 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1957 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1961 //===----------------------------------------------------------------------===//
1962 // Extend Instructions.
1967 defm SXTB : AI_ext_rrot<0b01101010,
1968 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1969 defm SXTH : AI_ext_rrot<0b01101011,
1970 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1972 defm SXTAB : AI_exta_rrot<0b01101010,
1973 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1974 defm SXTAH : AI_exta_rrot<0b01101011,
1975 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1977 // For disassembly only
1978 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1980 // For disassembly only
1981 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1985 let AddedComplexity = 16 in {
1986 defm UXTB : AI_ext_rrot<0b01101110,
1987 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1988 defm UXTH : AI_ext_rrot<0b01101111,
1989 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1990 defm UXTB16 : AI_ext_rrot<0b01101100,
1991 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1993 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1994 // The transformation should probably be done as a combiner action
1995 // instead so we can include a check for masking back in the upper
1996 // eight bits of the source into the lower eight bits of the result.
1997 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1998 // (UXTB16r_rot GPR:$Src, 24)>;
1999 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2000 (UXTB16r_rot GPR:$Src, 8)>;
2002 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2003 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2004 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2005 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2008 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2009 // For disassembly only
2010 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2013 def SBFX : I<(outs GPR:$Rd),
2014 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2015 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2016 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2017 Requires<[IsARM, HasV6T2]> {
2022 let Inst{27-21} = 0b0111101;
2023 let Inst{6-4} = 0b101;
2024 let Inst{20-16} = width;
2025 let Inst{15-12} = Rd;
2026 let Inst{11-7} = lsb;
2030 def UBFX : I<(outs GPR:$Rd),
2031 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2032 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2033 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2034 Requires<[IsARM, HasV6T2]> {
2039 let Inst{27-21} = 0b0111111;
2040 let Inst{6-4} = 0b101;
2041 let Inst{20-16} = width;
2042 let Inst{15-12} = Rd;
2043 let Inst{11-7} = lsb;
2047 //===----------------------------------------------------------------------===//
2048 // Arithmetic Instructions.
2051 defm ADD : AsI1_bin_irs<0b0100, "add",
2052 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2053 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2054 defm SUB : AsI1_bin_irs<0b0010, "sub",
2055 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2056 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2058 // ADD and SUB with 's' bit set.
2059 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2060 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2061 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2062 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2063 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2064 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2066 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2067 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2068 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2069 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2070 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2071 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2072 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2073 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2075 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2076 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2077 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2082 let Inst{15-12} = Rd;
2083 let Inst{19-16} = Rn;
2084 let Inst{11-0} = imm;
2087 // The reg/reg form is only defined for the disassembler; for codegen it is
2088 // equivalent to SUBrr.
2089 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2090 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2091 [/* For disassembly only; pattern left blank */]> {
2095 let Inst{11-4} = 0b00000000;
2098 let Inst{15-12} = Rd;
2099 let Inst{19-16} = Rn;
2102 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2103 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2104 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2109 let Inst{11-0} = shift;
2110 let Inst{15-12} = Rd;
2111 let Inst{19-16} = Rn;
2114 // RSB with 's' bit set.
2115 let Defs = [CPSR] in {
2116 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2117 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2118 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2124 let Inst{15-12} = Rd;
2125 let Inst{19-16} = Rn;
2126 let Inst{11-0} = imm;
2128 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2129 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2130 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2136 let Inst{11-0} = shift;
2137 let Inst{15-12} = Rd;
2138 let Inst{19-16} = Rn;
2142 let Uses = [CPSR] in {
2143 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2144 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2145 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2151 let Inst{15-12} = Rd;
2152 let Inst{19-16} = Rn;
2153 let Inst{11-0} = imm;
2155 // The reg/reg form is only defined for the disassembler; for codegen it is
2156 // equivalent to SUBrr.
2157 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2158 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2159 [/* For disassembly only; pattern left blank */]> {
2163 let Inst{11-4} = 0b00000000;
2166 let Inst{15-12} = Rd;
2167 let Inst{19-16} = Rn;
2169 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2170 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2171 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2177 let Inst{11-0} = shift;
2178 let Inst{15-12} = Rd;
2179 let Inst{19-16} = Rn;
2183 // FIXME: Allow these to be predicated.
2184 let Defs = [CPSR], Uses = [CPSR] in {
2185 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2186 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2187 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2194 let Inst{15-12} = Rd;
2195 let Inst{19-16} = Rn;
2196 let Inst{11-0} = imm;
2198 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2199 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2200 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2207 let Inst{11-0} = shift;
2208 let Inst{15-12} = Rd;
2209 let Inst{19-16} = Rn;
2213 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2214 // The assume-no-carry-in form uses the negation of the input since add/sub
2215 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2216 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2218 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2219 (SUBri GPR:$src, so_imm_neg:$imm)>;
2220 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2221 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2222 // The with-carry-in form matches bitwise not instead of the negation.
2223 // Effectively, the inverse interpretation of the carry flag already accounts
2224 // for part of the negation.
2225 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2226 (SBCri GPR:$src, so_imm_not:$imm)>;
2228 // Note: These are implemented in C++ code, because they have to generate
2229 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2231 // (mul X, 2^n+1) -> (add (X << n), X)
2232 // (mul X, 2^n-1) -> (rsb X, (X << n))
2234 // ARM Arithmetic Instruction -- for disassembly only
2235 // GPR:$dst = GPR:$a op GPR:$b
2236 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2237 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2238 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2239 opc, "\t$Rd, $Rn, $Rm", pattern> {
2243 let Inst{27-20} = op27_20;
2244 let Inst{11-4} = op11_4;
2245 let Inst{19-16} = Rn;
2246 let Inst{15-12} = Rd;
2250 // Saturating add/subtract -- for disassembly only
2252 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2253 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2254 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2255 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2256 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2257 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2259 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2260 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2261 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2262 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2263 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2264 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2265 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2266 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2267 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2268 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2269 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2270 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2272 // Signed/Unsigned add/subtract -- for disassembly only
2274 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2275 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2276 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2277 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2278 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2279 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2280 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2281 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2282 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2283 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2284 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2285 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2287 // Signed/Unsigned halving add/subtract -- for disassembly only
2289 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2290 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2291 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2292 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2293 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2294 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2295 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2296 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2297 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2298 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2299 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2300 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2302 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2304 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2305 MulFrm /* for convenience */, NoItinerary, "usad8",
2306 "\t$Rd, $Rn, $Rm", []>,
2307 Requires<[IsARM, HasV6]> {
2311 let Inst{27-20} = 0b01111000;
2312 let Inst{15-12} = 0b1111;
2313 let Inst{7-4} = 0b0001;
2314 let Inst{19-16} = Rd;
2315 let Inst{11-8} = Rm;
2318 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2319 MulFrm /* for convenience */, NoItinerary, "usada8",
2320 "\t$Rd, $Rn, $Rm, $Ra", []>,
2321 Requires<[IsARM, HasV6]> {
2326 let Inst{27-20} = 0b01111000;
2327 let Inst{7-4} = 0b0001;
2328 let Inst{19-16} = Rd;
2329 let Inst{15-12} = Ra;
2330 let Inst{11-8} = Rm;
2334 // Signed/Unsigned saturate -- for disassembly only
2336 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2337 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2338 [/* For disassembly only; pattern left blank */]> {
2343 let Inst{27-21} = 0b0110101;
2344 let Inst{5-4} = 0b01;
2345 let Inst{20-16} = sat_imm;
2346 let Inst{15-12} = Rd;
2347 let Inst{11-7} = sh{7-3};
2348 let Inst{6} = sh{0};
2352 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2353 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2354 [/* For disassembly only; pattern left blank */]> {
2358 let Inst{27-20} = 0b01101010;
2359 let Inst{11-4} = 0b11110011;
2360 let Inst{15-12} = Rd;
2361 let Inst{19-16} = sat_imm;
2365 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2366 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2367 [/* For disassembly only; pattern left blank */]> {
2372 let Inst{27-21} = 0b0110111;
2373 let Inst{5-4} = 0b01;
2374 let Inst{15-12} = Rd;
2375 let Inst{11-7} = sh{7-3};
2376 let Inst{6} = sh{0};
2377 let Inst{20-16} = sat_imm;
2381 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2382 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2383 [/* For disassembly only; pattern left blank */]> {
2387 let Inst{27-20} = 0b01101110;
2388 let Inst{11-4} = 0b11110011;
2389 let Inst{15-12} = Rd;
2390 let Inst{19-16} = sat_imm;
2394 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2395 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2397 //===----------------------------------------------------------------------===//
2398 // Bitwise Instructions.
2401 defm AND : AsI1_bin_irs<0b0000, "and",
2402 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2403 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2404 defm ORR : AsI1_bin_irs<0b1100, "orr",
2405 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2406 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2407 defm EOR : AsI1_bin_irs<0b0001, "eor",
2408 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2409 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2410 defm BIC : AsI1_bin_irs<0b1110, "bic",
2411 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2412 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2414 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2415 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2416 "bfc", "\t$Rd, $imm", "$src = $Rd",
2417 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2418 Requires<[IsARM, HasV6T2]> {
2421 let Inst{27-21} = 0b0111110;
2422 let Inst{6-0} = 0b0011111;
2423 let Inst{15-12} = Rd;
2424 let Inst{11-7} = imm{4-0}; // lsb
2425 let Inst{20-16} = imm{9-5}; // width
2428 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2429 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2430 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2431 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2432 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2433 bf_inv_mask_imm:$imm))]>,
2434 Requires<[IsARM, HasV6T2]> {
2438 let Inst{27-21} = 0b0111110;
2439 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2440 let Inst{15-12} = Rd;
2441 let Inst{11-7} = imm{4-0}; // lsb
2442 let Inst{20-16} = imm{9-5}; // width
2446 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2447 "mvn", "\t$Rd, $Rm",
2448 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2452 let Inst{19-16} = 0b0000;
2453 let Inst{11-4} = 0b00000000;
2454 let Inst{15-12} = Rd;
2457 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2458 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2459 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2463 let Inst{19-16} = 0b0000;
2464 let Inst{15-12} = Rd;
2465 let Inst{11-0} = shift;
2467 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2468 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2469 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2470 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2474 let Inst{19-16} = 0b0000;
2475 let Inst{15-12} = Rd;
2476 let Inst{11-0} = imm;
2479 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2480 (BICri GPR:$src, so_imm_not:$imm)>;
2482 //===----------------------------------------------------------------------===//
2483 // Multiply Instructions.
2485 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2486 string opc, string asm, list<dag> pattern>
2487 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2491 let Inst{19-16} = Rd;
2492 let Inst{11-8} = Rm;
2495 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2496 string opc, string asm, list<dag> pattern>
2497 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2502 let Inst{19-16} = RdHi;
2503 let Inst{15-12} = RdLo;
2504 let Inst{11-8} = Rm;
2508 let isCommutable = 1 in {
2509 let Constraints = "@earlyclobber $Rd" in
2510 def MULv5: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2511 IIC_iMUL32, [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2512 Requires<[IsARM, NoV6]>;
2514 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2515 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2516 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2517 Requires<[IsARM, HasV6]>;
2520 let Constraints = "@earlyclobber $Rd" in
2521 def MLAv5: PseudoInst<(outs GPR:$Rd),
2522 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2523 IIC_iMAC32, [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm),
2525 Requires<[IsARM, NoV6]> {
2527 let Inst{15-12} = Ra;
2529 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2530 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2531 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2532 Requires<[IsARM, HasV6]> {
2534 let Inst{15-12} = Ra;
2537 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2538 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2540 Requires<[IsARM, HasV6T2]> {
2545 let Inst{19-16} = Rd;
2546 let Inst{15-12} = Ra;
2547 let Inst{11-8} = Rm;
2551 // Extra precision multiplies with low / high results
2553 let neverHasSideEffects = 1 in {
2554 let isCommutable = 1 in {
2555 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2556 def SMULLv5 : PseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2557 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2559 Requires<[IsARM, NoV6]>;
2561 def UMULLv5 : PseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2562 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2564 Requires<[IsARM, NoV6]>;
2567 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2568 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2569 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2570 Requires<[IsARM, HasV6]>;
2572 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2573 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2574 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2575 Requires<[IsARM, HasV6]>;
2578 // Multiply + accumulate
2579 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2580 def SMLALv5 : PseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2581 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2583 Requires<[IsARM, NoV6]>;
2584 def UMLALv5 : PseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2585 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2587 Requires<[IsARM, NoV6]>;
2588 def UMAALv5 : PseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2589 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2591 Requires<[IsARM, NoV6]>;
2595 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2596 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2597 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2598 Requires<[IsARM, HasV6]>;
2599 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2600 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2601 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2602 Requires<[IsARM, HasV6]>;
2604 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2605 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2606 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2607 Requires<[IsARM, HasV6]> {
2612 let Inst{19-16} = RdLo;
2613 let Inst{15-12} = RdHi;
2614 let Inst{11-8} = Rm;
2617 } // neverHasSideEffects
2619 // Most significant word multiply
2620 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2621 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2622 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2623 Requires<[IsARM, HasV6]> {
2624 let Inst{15-12} = 0b1111;
2627 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2628 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2629 [/* For disassembly only; pattern left blank */]>,
2630 Requires<[IsARM, HasV6]> {
2631 let Inst{15-12} = 0b1111;
2634 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2635 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2636 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2637 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2638 Requires<[IsARM, HasV6]>;
2640 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2641 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2642 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2643 [/* For disassembly only; pattern left blank */]>,
2644 Requires<[IsARM, HasV6]>;
2646 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2647 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2648 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2649 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2650 Requires<[IsARM, HasV6]>;
2652 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2653 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2654 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2655 [/* For disassembly only; pattern left blank */]>,
2656 Requires<[IsARM, HasV6]>;
2658 multiclass AI_smul<string opc, PatFrag opnode> {
2659 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2660 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2661 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2662 (sext_inreg GPR:$Rm, i16)))]>,
2663 Requires<[IsARM, HasV5TE]>;
2665 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2666 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2667 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2668 (sra GPR:$Rm, (i32 16))))]>,
2669 Requires<[IsARM, HasV5TE]>;
2671 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2672 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2673 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2674 (sext_inreg GPR:$Rm, i16)))]>,
2675 Requires<[IsARM, HasV5TE]>;
2677 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2678 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2679 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2680 (sra GPR:$Rm, (i32 16))))]>,
2681 Requires<[IsARM, HasV5TE]>;
2683 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2684 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2685 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2686 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2687 Requires<[IsARM, HasV5TE]>;
2689 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2690 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2691 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2692 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2693 Requires<[IsARM, HasV5TE]>;
2697 multiclass AI_smla<string opc, PatFrag opnode> {
2698 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2699 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2700 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2701 [(set GPR:$Rd, (add GPR:$Ra,
2702 (opnode (sext_inreg GPR:$Rn, i16),
2703 (sext_inreg GPR:$Rm, i16))))]>,
2704 Requires<[IsARM, HasV5TE]>;
2706 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2707 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2708 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2709 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2710 (sra GPR:$Rm, (i32 16)))))]>,
2711 Requires<[IsARM, HasV5TE]>;
2713 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2714 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2715 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2716 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2717 (sext_inreg GPR:$Rm, i16))))]>,
2718 Requires<[IsARM, HasV5TE]>;
2720 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2721 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2722 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2723 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2724 (sra GPR:$Rm, (i32 16)))))]>,
2725 Requires<[IsARM, HasV5TE]>;
2727 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2728 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2729 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2730 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2731 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2732 Requires<[IsARM, HasV5TE]>;
2734 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2735 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2736 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2737 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2738 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2739 Requires<[IsARM, HasV5TE]>;
2742 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2743 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2745 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2746 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm),
2748 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2749 [/* For disassembly only; pattern left blank */]>,
2750 Requires<[IsARM, HasV5TE]>;
2752 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2753 (ins GPR:$Rn, GPR:$Rm),
2754 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2755 [/* For disassembly only; pattern left blank */]>,
2756 Requires<[IsARM, HasV5TE]>;
2758 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2759 (ins GPR:$Rn, GPR:$Rm),
2760 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2761 [/* For disassembly only; pattern left blank */]>,
2762 Requires<[IsARM, HasV5TE]>;
2764 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2765 (ins GPR:$Rn, GPR:$Rm),
2766 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2767 [/* For disassembly only; pattern left blank */]>,
2768 Requires<[IsARM, HasV5TE]>;
2770 // Helper class for AI_smld -- for disassembly only
2771 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2772 InstrItinClass itin, string opc, string asm>
2773 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2780 let Inst{21-20} = 0b00;
2781 let Inst{22} = long;
2782 let Inst{27-23} = 0b01110;
2783 let Inst{11-8} = Rm;
2786 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2787 InstrItinClass itin, string opc, string asm>
2788 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2790 let Inst{15-12} = 0b1111;
2791 let Inst{19-16} = Rd;
2793 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2794 InstrItinClass itin, string opc, string asm>
2795 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2797 let Inst{15-12} = Ra;
2799 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2800 InstrItinClass itin, string opc, string asm>
2801 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2804 let Inst{19-16} = RdHi;
2805 let Inst{15-12} = RdLo;
2808 multiclass AI_smld<bit sub, string opc> {
2810 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2811 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2813 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2814 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2816 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2817 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2818 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2820 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2821 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2822 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2826 defm SMLA : AI_smld<0, "smla">;
2827 defm SMLS : AI_smld<1, "smls">;
2829 multiclass AI_sdml<bit sub, string opc> {
2831 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2832 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2833 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2834 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2837 defm SMUA : AI_sdml<0, "smua">;
2838 defm SMUS : AI_sdml<1, "smus">;
2840 //===----------------------------------------------------------------------===//
2841 // Misc. Arithmetic Instructions.
2844 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2845 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2846 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2848 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2849 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2850 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2851 Requires<[IsARM, HasV6T2]>;
2853 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2854 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2855 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2857 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2858 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2860 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2861 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2862 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2863 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2864 Requires<[IsARM, HasV6]>;
2866 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2867 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2870 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2871 (shl GPR:$Rm, (i32 8))), i16))]>,
2872 Requires<[IsARM, HasV6]>;
2874 def lsl_shift_imm : SDNodeXForm<imm, [{
2875 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2876 return CurDAG->getTargetConstant(Sh, MVT::i32);
2879 def lsl_amt : PatLeaf<(i32 imm), [{
2880 return (N->getZExtValue() < 32);
2883 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2884 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2885 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2886 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2887 (and (shl GPR:$Rm, lsl_amt:$sh),
2889 Requires<[IsARM, HasV6]>;
2891 // Alternate cases for PKHBT where identities eliminate some nodes.
2892 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2893 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2894 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2895 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2897 def asr_shift_imm : SDNodeXForm<imm, [{
2898 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2899 return CurDAG->getTargetConstant(Sh, MVT::i32);
2902 def asr_amt : PatLeaf<(i32 imm), [{
2903 return (N->getZExtValue() <= 32);
2906 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2907 // will match the pattern below.
2908 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2909 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2910 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2911 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2912 (and (sra GPR:$Rm, asr_amt:$sh),
2914 Requires<[IsARM, HasV6]>;
2916 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2917 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2918 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2919 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2920 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2921 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2922 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2924 //===----------------------------------------------------------------------===//
2925 // Comparison Instructions...
2928 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2929 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2930 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2932 // ARMcmpZ can re-use the above instruction definitions.
2933 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
2934 (CMPri GPR:$src, so_imm:$imm)>;
2935 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
2936 (CMPrr GPR:$src, GPR:$rhs)>;
2937 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
2938 (CMPrs GPR:$src, so_reg:$rhs)>;
2940 // FIXME: We have to be careful when using the CMN instruction and comparison
2941 // with 0. One would expect these two pieces of code should give identical
2957 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2958 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2959 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2960 // value of r0 and the carry bit (because the "carry bit" parameter to
2961 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2962 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2963 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2964 // parameter to AddWithCarry is defined as 0).
2966 // When x is 0 and unsigned:
2970 // ~x + 1 = 0x1 0000 0000
2971 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2973 // Therefore, we should disable CMN when comparing against zero, until we can
2974 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2975 // when it's a comparison which doesn't look at the 'carry' flag).
2977 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2979 // This is related to <rdar://problem/7569620>.
2981 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2982 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2984 // Note that TST/TEQ don't set all the same flags that CMP does!
2985 defm TST : AI1_cmp_irs<0b1000, "tst",
2986 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2987 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2988 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2989 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2990 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2992 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2993 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2994 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2996 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2997 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2999 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3000 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3002 // Pseudo i64 compares for some floating point compares.
3003 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3005 def BCCi64 : PseudoInst<(outs),
3006 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3008 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3010 def BCCZi64 : PseudoInst<(outs),
3011 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3012 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3013 } // usesCustomInserter
3016 // Conditional moves
3017 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3018 // a two-value operand where a dag node expects two operands. :(
3019 // FIXME: These should all be pseudo-instructions that get expanded to
3020 // the normal MOV instructions. That would fix the dependency on
3021 // special casing them in tblgen.
3022 let neverHasSideEffects = 1 in {
3023 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
3024 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
3025 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3026 RegConstraint<"$false = $Rd">, UnaryDP {
3031 let Inst{15-12} = Rd;
3032 let Inst{11-4} = 0b00000000;
3036 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3037 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3038 "mov", "\t$Rd, $shift",
3039 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3040 RegConstraint<"$false = $Rd">, UnaryDP {
3045 let Inst{19-16} = 0;
3046 let Inst{15-12} = Rd;
3047 let Inst{11-0} = shift;
3050 let isMoveImm = 1 in
3051 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3053 "movw", "\t$Rd, $imm",
3055 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3061 let Inst{19-16} = imm{15-12};
3062 let Inst{15-12} = Rd;
3063 let Inst{11-0} = imm{11-0};
3066 let isMoveImm = 1 in
3067 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3068 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3069 "mov", "\t$Rd, $imm",
3070 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3071 RegConstraint<"$false = $Rd">, UnaryDP {
3076 let Inst{19-16} = 0b0000;
3077 let Inst{15-12} = Rd;
3078 let Inst{11-0} = imm;
3081 // Two instruction predicate mov immediate.
3082 let isMoveImm = 1 in
3083 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3084 (ins GPR:$false, i32imm:$src, pred:$p),
3085 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3087 let isMoveImm = 1 in
3088 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3089 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3090 "mvn", "\t$Rd, $imm",
3091 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3092 RegConstraint<"$false = $Rd">, UnaryDP {
3097 let Inst{19-16} = 0b0000;
3098 let Inst{15-12} = Rd;
3099 let Inst{11-0} = imm;
3101 } // neverHasSideEffects
3103 //===----------------------------------------------------------------------===//
3104 // Atomic operations intrinsics
3107 def memb_opt : Operand<i32> {
3108 let PrintMethod = "printMemBOption";
3111 // memory barriers protect the atomic sequences
3112 let hasSideEffects = 1 in {
3113 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3114 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3115 Requires<[IsARM, HasDB]> {
3117 let Inst{31-4} = 0xf57ff05;
3118 let Inst{3-0} = opt;
3121 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3122 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3123 [(ARMMemBarrierMCR GPR:$zero)]>,
3124 Requires<[IsARM, HasV6]> {
3125 // FIXME: add encoding
3129 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3131 [/* For disassembly only; pattern left blank */]>,
3132 Requires<[IsARM, HasDB]> {
3134 let Inst{31-4} = 0xf57ff04;
3135 let Inst{3-0} = opt;
3138 // ISB has only full system option -- for disassembly only
3139 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3140 Requires<[IsARM, HasDB]> {
3141 let Inst{31-4} = 0xf57ff06;
3142 let Inst{3-0} = 0b1111;
3145 let usesCustomInserter = 1 in {
3146 let Uses = [CPSR] in {
3147 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3149 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3150 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3152 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3153 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3155 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3156 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3158 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3159 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3161 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3162 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3164 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3165 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3167 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3168 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3170 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3171 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3173 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3174 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3176 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3177 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3179 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3180 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3182 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3183 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3185 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3186 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3188 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3189 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3191 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3192 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3194 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3195 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3197 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3198 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3200 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3202 def ATOMIC_SWAP_I8 : PseudoInst<
3203 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3204 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3205 def ATOMIC_SWAP_I16 : PseudoInst<
3206 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3207 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3208 def ATOMIC_SWAP_I32 : PseudoInst<
3209 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3210 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3212 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3213 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3214 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3215 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3216 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3217 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3218 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3219 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3220 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3224 let mayLoad = 1 in {
3225 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3226 "ldrexb", "\t$Rt, [$Rn]",
3228 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3229 "ldrexh", "\t$Rt, [$Rn]",
3231 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3232 "ldrex", "\t$Rt, [$Rn]",
3234 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3236 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3240 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3241 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3243 "strexb", "\t$Rd, $src, [$Rn]",
3245 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3247 "strexh", "\t$Rd, $Rt, [$Rn]",
3249 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3251 "strex", "\t$Rd, $Rt, [$Rn]",
3253 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3254 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3256 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3260 // Clear-Exclusive is for disassembly only.
3261 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3262 [/* For disassembly only; pattern left blank */]>,
3263 Requires<[IsARM, HasV7]> {
3264 let Inst{31-0} = 0b11110101011111111111000000011111;
3267 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3268 let mayLoad = 1 in {
3269 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3270 [/* For disassembly only; pattern left blank */]>;
3271 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3272 [/* For disassembly only; pattern left blank */]>;
3275 //===----------------------------------------------------------------------===//
3279 // __aeabi_read_tp preserves the registers r1-r3.
3280 // This is a pseudo inst so that we can get the encoding right,
3281 // complete with fixup for the aeabi_read_tp function.
3283 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3284 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3285 [(set R0, ARMthread_pointer)]>;
3288 //===----------------------------------------------------------------------===//
3289 // SJLJ Exception handling intrinsics
3290 // eh_sjlj_setjmp() is an instruction sequence to store the return
3291 // address and save #0 in R0 for the non-longjmp case.
3292 // Since by its nature we may be coming from some other function to get
3293 // here, and we're using the stack frame for the containing function to
3294 // save/restore registers, we can't keep anything live in regs across
3295 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3296 // when we get here from a longjmp(). We force everthing out of registers
3297 // except for our own input by listing the relevant registers in Defs. By
3298 // doing so, we also cause the prologue/epilogue code to actively preserve
3299 // all of the callee-saved resgisters, which is exactly what we want.
3300 // A constant value is passed in $val, and we use the location as a scratch.
3302 // These are pseudo-instructions and are lowered to individual MC-insts, so
3303 // no encoding information is necessary.
3305 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3306 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3307 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3308 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3309 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3311 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3312 Requires<[IsARM, HasVFP2]>;
3316 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3317 hasSideEffects = 1, isBarrier = 1 in {
3318 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3320 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3321 Requires<[IsARM, NoVFP]>;
3324 // FIXME: Non-Darwin version(s)
3325 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3326 Defs = [ R7, LR, SP ] in {
3327 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3329 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3330 Requires<[IsARM, IsDarwin]>;
3333 // eh.sjlj.dispatchsetup pseudo-instruction.
3334 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3335 // handled when the pseudo is expanded (which happens before any passes
3336 // that need the instruction size).
3337 let isBarrier = 1, hasSideEffects = 1 in
3338 def Int_eh_sjlj_dispatchsetup :
3339 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3340 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3341 Requires<[IsDarwin]>;
3343 //===----------------------------------------------------------------------===//
3344 // Non-Instruction Patterns
3347 // Large immediate handling.
3349 // 32-bit immediate using two piece so_imms or movw + movt.
3350 // This is a single pseudo instruction, the benefit is that it can be remat'd
3351 // as a single unit instead of having to handle reg inputs.
3352 // FIXME: Remove this when we can do generalized remat.
3353 let isReMaterializable = 1, isMoveImm = 1 in
3354 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3355 [(set GPR:$dst, (arm_i32imm:$src))]>,
3358 // ConstantPool, GlobalAddress, and JumpTable
3359 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3360 Requires<[IsARM, DontUseMovt]>;
3361 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3362 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3363 Requires<[IsARM, UseMovt]>;
3364 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3365 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3367 // TODO: add,sub,and, 3-instr forms?
3370 def : ARMPat<(ARMtcret tcGPR:$dst),
3371 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3373 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3374 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3376 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3377 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3379 def : ARMPat<(ARMtcret tcGPR:$dst),
3380 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3382 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3383 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3385 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3386 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3389 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3390 Requires<[IsARM, IsNotDarwin]>;
3391 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3392 Requires<[IsARM, IsDarwin]>;
3394 // zextload i1 -> zextload i8
3395 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3396 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3398 // extload -> zextload
3399 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3400 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3401 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3402 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3404 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3406 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3407 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3410 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3411 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3412 (SMULBB GPR:$a, GPR:$b)>;
3413 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3414 (SMULBB GPR:$a, GPR:$b)>;
3415 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3416 (sra GPR:$b, (i32 16))),
3417 (SMULBT GPR:$a, GPR:$b)>;
3418 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3419 (SMULBT GPR:$a, GPR:$b)>;
3420 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3421 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3422 (SMULTB GPR:$a, GPR:$b)>;
3423 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3424 (SMULTB GPR:$a, GPR:$b)>;
3425 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3427 (SMULWB GPR:$a, GPR:$b)>;
3428 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3429 (SMULWB GPR:$a, GPR:$b)>;
3431 def : ARMV5TEPat<(add GPR:$acc,
3432 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3433 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3434 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3435 def : ARMV5TEPat<(add GPR:$acc,
3436 (mul sext_16_node:$a, sext_16_node:$b)),
3437 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3438 def : ARMV5TEPat<(add GPR:$acc,
3439 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3440 (sra GPR:$b, (i32 16)))),
3441 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3442 def : ARMV5TEPat<(add GPR:$acc,
3443 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3444 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3445 def : ARMV5TEPat<(add GPR:$acc,
3446 (mul (sra GPR:$a, (i32 16)),
3447 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3448 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3449 def : ARMV5TEPat<(add GPR:$acc,
3450 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3451 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3452 def : ARMV5TEPat<(add GPR:$acc,
3453 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3455 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3456 def : ARMV5TEPat<(add GPR:$acc,
3457 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3458 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3460 //===----------------------------------------------------------------------===//
3464 include "ARMInstrThumb.td"
3466 //===----------------------------------------------------------------------===//
3470 include "ARMInstrThumb2.td"
3472 //===----------------------------------------------------------------------===//
3473 // Floating Point Support
3476 include "ARMInstrVFP.td"
3478 //===----------------------------------------------------------------------===//
3479 // Advanced SIMD (NEON) Support
3482 include "ARMInstrNEON.td"
3484 //===----------------------------------------------------------------------===//
3485 // Coprocessor Instructions. For disassembly only.
3488 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3489 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3490 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3491 [/* For disassembly only; pattern left blank */]> {
3495 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3496 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3497 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3498 [/* For disassembly only; pattern left blank */]> {
3499 let Inst{31-28} = 0b1111;
3503 class ACI<dag oops, dag iops, string opc, string asm>
3504 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3505 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3506 let Inst{27-25} = 0b110;
3509 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3511 def _OFFSET : ACI<(outs),
3512 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3513 opc, "\tp$cop, cr$CRd, $addr"> {
3514 let Inst{31-28} = op31_28;
3515 let Inst{24} = 1; // P = 1
3516 let Inst{21} = 0; // W = 0
3517 let Inst{22} = 0; // D = 0
3518 let Inst{20} = load;
3521 def _PRE : ACI<(outs),
3522 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3523 opc, "\tp$cop, cr$CRd, $addr!"> {
3524 let Inst{31-28} = op31_28;
3525 let Inst{24} = 1; // P = 1
3526 let Inst{21} = 1; // W = 1
3527 let Inst{22} = 0; // D = 0
3528 let Inst{20} = load;
3531 def _POST : ACI<(outs),
3532 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3533 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3534 let Inst{31-28} = op31_28;
3535 let Inst{24} = 0; // P = 0
3536 let Inst{21} = 1; // W = 1
3537 let Inst{22} = 0; // D = 0
3538 let Inst{20} = load;
3541 def _OPTION : ACI<(outs),
3542 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3543 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3544 let Inst{31-28} = op31_28;
3545 let Inst{24} = 0; // P = 0
3546 let Inst{23} = 1; // U = 1
3547 let Inst{21} = 0; // W = 0
3548 let Inst{22} = 0; // D = 0
3549 let Inst{20} = load;
3552 def L_OFFSET : ACI<(outs),
3553 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3554 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3555 let Inst{31-28} = op31_28;
3556 let Inst{24} = 1; // P = 1
3557 let Inst{21} = 0; // W = 0
3558 let Inst{22} = 1; // D = 1
3559 let Inst{20} = load;
3562 def L_PRE : ACI<(outs),
3563 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3564 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3565 let Inst{31-28} = op31_28;
3566 let Inst{24} = 1; // P = 1
3567 let Inst{21} = 1; // W = 1
3568 let Inst{22} = 1; // D = 1
3569 let Inst{20} = load;
3572 def L_POST : ACI<(outs),
3573 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3574 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3575 let Inst{31-28} = op31_28;
3576 let Inst{24} = 0; // P = 0
3577 let Inst{21} = 1; // W = 1
3578 let Inst{22} = 1; // D = 1
3579 let Inst{20} = load;
3582 def L_OPTION : ACI<(outs),
3583 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3584 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3585 let Inst{31-28} = op31_28;
3586 let Inst{24} = 0; // P = 0
3587 let Inst{23} = 1; // U = 1
3588 let Inst{21} = 0; // W = 0
3589 let Inst{22} = 1; // D = 1
3590 let Inst{20} = load;
3594 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3595 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3596 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3597 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3599 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3600 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3601 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3602 [/* For disassembly only; pattern left blank */]> {
3607 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3608 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3609 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3610 [/* For disassembly only; pattern left blank */]> {
3611 let Inst{31-28} = 0b1111;
3616 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3617 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3618 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3619 [/* For disassembly only; pattern left blank */]> {
3624 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3625 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3626 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3627 [/* For disassembly only; pattern left blank */]> {
3628 let Inst{31-28} = 0b1111;
3633 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3634 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3635 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3636 [/* For disassembly only; pattern left blank */]> {
3637 let Inst{23-20} = 0b0100;
3640 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3641 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3642 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3643 [/* For disassembly only; pattern left blank */]> {
3644 let Inst{31-28} = 0b1111;
3645 let Inst{23-20} = 0b0100;
3648 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3649 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3650 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3651 [/* For disassembly only; pattern left blank */]> {
3652 let Inst{23-20} = 0b0101;
3655 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3656 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3657 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3658 [/* For disassembly only; pattern left blank */]> {
3659 let Inst{31-28} = 0b1111;
3660 let Inst{23-20} = 0b0101;
3663 //===----------------------------------------------------------------------===//
3664 // Move between special register and ARM core register -- for disassembly only
3667 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3668 [/* For disassembly only; pattern left blank */]> {
3669 let Inst{23-20} = 0b0000;
3670 let Inst{7-4} = 0b0000;
3673 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3674 [/* For disassembly only; pattern left blank */]> {
3675 let Inst{23-20} = 0b0100;
3676 let Inst{7-4} = 0b0000;
3679 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3680 "msr", "\tcpsr$mask, $src",
3681 [/* For disassembly only; pattern left blank */]> {
3682 let Inst{23-20} = 0b0010;
3683 let Inst{7-4} = 0b0000;
3686 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3687 "msr", "\tcpsr$mask, $a",
3688 [/* For disassembly only; pattern left blank */]> {
3689 let Inst{23-20} = 0b0010;
3690 let Inst{7-4} = 0b0000;
3693 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3694 "msr", "\tspsr$mask, $src",
3695 [/* For disassembly only; pattern left blank */]> {
3696 let Inst{23-20} = 0b0110;
3697 let Inst{7-4} = 0b0000;
3700 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3701 "msr", "\tspsr$mask, $a",
3702 [/* For disassembly only; pattern left blank */]> {
3703 let Inst{23-20} = 0b0110;
3704 let Inst{7-4} = 0b0000;