1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
62 //===------------------------------------------------------------------===//
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0xf << FormShift,
75 // Pseudo instructions
76 Pseudo = 1 << FormShift,
78 // Multiply instructions
79 MulFrm = 2 << FormShift,
81 // Branch instructions
82 Branch = 3 << FormShift,
83 BranchMisc = 4 << FormShift,
85 // Data Processing instructions
86 DPFrm = 5 << FormShift,
87 DPSoRegFrm = 6 << FormShift,
90 LdFrm = 7 << FormShift,
91 StFrm = 8 << FormShift,
92 LdMiscFrm = 9 << FormShift,
93 StMiscFrm = 10 << FormShift,
94 LdMulFrm = 11 << FormShift,
95 StMulFrm = 12 << FormShift,
97 // Miscellaneous arithmetic instructions
98 ArithMisc = 13 << FormShift,
101 ThumbFrm = 14 << FormShift,
104 VPFFrm = 15 << FormShift,
106 //===------------------------------------------------------------------===//
107 // Field shifts - such shifts are used to set field while generating
108 // machine instructions.
123 class ARMInstrInfo : public TargetInstrInfoImpl {
124 const ARMRegisterInfo RI;
126 explicit ARMInstrInfo(const ARMSubtarget &STI);
128 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
129 /// such, whenever a client has an instance of instruction info, it should
130 /// always be able to get register info as well (through this method).
132 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
134 /// getPointerRegClass - Return the register class to use to hold pointers.
135 /// This is used for addressing modes.
136 virtual const TargetRegisterClass *getPointerRegClass() const;
138 /// Return true if the instruction is a register to register move and
139 /// leave the source and dest operands in the passed parameters.
141 virtual bool isMoveInstr(const MachineInstr &MI,
142 unsigned &SrcReg, unsigned &DstReg) const;
143 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
144 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
146 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
147 unsigned DestReg, const MachineInstr *Orig) const;
149 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
150 MachineBasicBlock::iterator &MBBI,
151 LiveVariables *LV) const;
154 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
155 MachineBasicBlock *&FBB,
156 SmallVectorImpl<MachineOperand> &Cond) const;
157 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
158 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
159 MachineBasicBlock *FBB,
160 const SmallVectorImpl<MachineOperand> &Cond) const;
161 virtual bool copyRegToReg(MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator I,
163 unsigned DestReg, unsigned SrcReg,
164 const TargetRegisterClass *DestRC,
165 const TargetRegisterClass *SrcRC) const;
166 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MBBI,
168 unsigned SrcReg, bool isKill, int FrameIndex,
169 const TargetRegisterClass *RC) const;
171 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
172 SmallVectorImpl<MachineOperand> &Addr,
173 const TargetRegisterClass *RC,
174 SmallVectorImpl<MachineInstr*> &NewMIs) const;
176 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator MBBI,
178 unsigned DestReg, int FrameIndex,
179 const TargetRegisterClass *RC) const;
181 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
182 SmallVectorImpl<MachineOperand> &Addr,
183 const TargetRegisterClass *RC,
184 SmallVectorImpl<MachineInstr*> &NewMIs) const;
185 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MI,
187 const std::vector<CalleeSavedInfo> &CSI) const;
188 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
189 MachineBasicBlock::iterator MI,
190 const std::vector<CalleeSavedInfo> &CSI) const;
192 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
194 const SmallVectorImpl<unsigned> &Ops,
195 int FrameIndex) const;
197 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
199 const SmallVectorImpl<unsigned> &Ops,
200 MachineInstr* LoadMI) const {
204 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
205 const SmallVectorImpl<unsigned> &Ops) const;
207 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
209 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
211 // Predication support.
212 virtual bool isPredicated(const MachineInstr *MI) const;
214 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
215 int PIdx = MI->findFirstPredOperandIdx();
216 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
221 bool PredicateInstruction(MachineInstr *MI,
222 const SmallVectorImpl<MachineOperand> &Pred) const;
225 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
226 const SmallVectorImpl<MachineOperand> &Pred2) const;
228 virtual bool DefinesPredicate(MachineInstr *MI,
229 std::vector<MachineOperand> &Pred) const;
231 /// GetInstSize - Returns the size of the specified MachineInstr.
233 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;