1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
41 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
47 /// Return true if the instruction is a register to register move and
48 /// leave the source and dest operands in the passed parameters.
50 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
51 unsigned &SrcReg, unsigned &DstReg,
52 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
53 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
55 unsigned oc = MI.getOpcode();
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
66 assert(MI.getDesc().getNumOperands() >= 2 &&
67 MI.getOperand(0).isReg() &&
68 MI.getOperand(1).isReg() &&
69 "Invalid ARM MOV instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
76 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
77 int &FrameIndex) const {
78 switch (MI->getOpcode()) {
81 if (MI->getOperand(1).isFI() &&
82 MI->getOperand(2).isReg() &&
83 MI->getOperand(3).isImm() &&
84 MI->getOperand(2).getReg() == 0 &&
85 MI->getOperand(3).getImm() == 0) {
86 FrameIndex = MI->getOperand(1).getIndex();
87 return MI->getOperand(0).getReg();
92 if (MI->getOperand(1).isFI() &&
93 MI->getOperand(2).isImm() &&
94 MI->getOperand(2).getImm() == 0) {
95 FrameIndex = MI->getOperand(1).getIndex();
96 return MI->getOperand(0).getReg();
100 if (MI->getOperand(1).isFI() &&
101 MI->getOperand(2).isImm() &&
102 MI->getOperand(2).getImm() == 0) {
103 FrameIndex = MI->getOperand(1).getIndex();
104 return MI->getOperand(0).getReg();
111 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
112 int &FrameIndex) const {
113 switch (MI->getOpcode()) {
116 if (MI->getOperand(1).isFI() &&
117 MI->getOperand(2).isReg() &&
118 MI->getOperand(3).isImm() &&
119 MI->getOperand(2).getReg() == 0 &&
120 MI->getOperand(3).getImm() == 0) {
121 FrameIndex = MI->getOperand(1).getIndex();
122 return MI->getOperand(0).getReg();
127 if (MI->getOperand(1).isFI() &&
128 MI->getOperand(2).isImm() &&
129 MI->getOperand(2).getImm() == 0) {
130 FrameIndex = MI->getOperand(1).getIndex();
131 return MI->getOperand(0).getReg();
135 if (MI->getOperand(1).isFI() &&
136 MI->getOperand(2).isImm() &&
137 MI->getOperand(2).getImm() == 0) {
138 FrameIndex = MI->getOperand(1).getIndex();
139 return MI->getOperand(0).getReg();
146 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator I,
149 const MachineInstr *Orig) const {
150 if (Orig->getOpcode() == ARM::MOVi2pieces) {
151 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
152 Orig->getOperand(2).getImm(),
153 Orig->getOperand(3).getReg(), this, false);
157 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
158 MI->getOperand(0).setReg(DestReg);
162 static unsigned getUnindexedOpcode(unsigned Opc) {
175 case ARM::LDRSH_POST:
178 case ARM::LDRSB_POST:
194 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
195 MachineBasicBlock::iterator &MBBI,
196 LiveVariables *LV) const {
200 MachineInstr *MI = MBBI;
201 MachineFunction &MF = *MI->getParent()->getParent();
202 unsigned TSFlags = MI->getDesc().TSFlags;
204 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
205 default: return NULL;
206 case ARMII::IndexModePre:
209 case ARMII::IndexModePost:
213 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
215 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
219 MachineInstr *UpdateMI = NULL;
220 MachineInstr *MemMI = NULL;
221 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
222 const TargetInstrDesc &TID = MI->getDesc();
223 unsigned NumOps = TID.getNumOperands();
224 bool isLoad = !TID.mayStore();
225 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
226 const MachineOperand &Base = MI->getOperand(2);
227 const MachineOperand &Offset = MI->getOperand(NumOps-3);
228 unsigned WBReg = WB.getReg();
229 unsigned BaseReg = Base.getReg();
230 unsigned OffReg = Offset.getReg();
231 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
232 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
235 assert(false && "Unknown indexed op!");
237 case ARMII::AddrMode2: {
238 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
239 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
241 int SOImmVal = ARM_AM::getSOImmVal(Amt);
243 // Can't encode it in a so_imm operand. This transformation will
244 // add more than 1 instruction. Abandon!
246 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
247 .addReg(BaseReg).addImm(SOImmVal)
248 .addImm(Pred).addReg(0).addReg(0);
249 } else if (Amt != 0) {
250 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
251 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
252 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
253 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
254 .addImm(Pred).addReg(0).addReg(0);
256 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
257 .addReg(BaseReg).addReg(OffReg)
258 .addImm(Pred).addReg(0).addReg(0);
261 case ARMII::AddrMode3 : {
262 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
263 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
265 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
266 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
267 .addReg(BaseReg).addImm(Amt)
268 .addImm(Pred).addReg(0).addReg(0);
270 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
271 .addReg(BaseReg).addReg(OffReg)
272 .addImm(Pred).addReg(0).addReg(0);
277 std::vector<MachineInstr*> NewMIs;
280 MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg())
281 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
283 MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg())
284 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
285 NewMIs.push_back(MemMI);
286 NewMIs.push_back(UpdateMI);
289 MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg())
290 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
292 MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg())
293 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
295 UpdateMI->getOperand(0).setIsDead();
296 NewMIs.push_back(UpdateMI);
297 NewMIs.push_back(MemMI);
300 // Transfer LiveVariables states, kill / dead info.
302 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
303 MachineOperand &MO = MI->getOperand(i);
304 if (MO.isReg() && MO.getReg() &&
305 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
306 unsigned Reg = MO.getReg();
308 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
310 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
312 LV->addVirtualRegisterDead(Reg, NewMI);
314 if (MO.isUse() && MO.isKill()) {
315 for (unsigned j = 0; j < 2; ++j) {
316 // Look at the two new MI's in reverse order.
317 MachineInstr *NewMI = NewMIs[j];
318 if (!NewMI->readsRegister(Reg))
320 LV->addVirtualRegisterKilled(Reg, NewMI);
321 if (VI.removeKill(MI))
322 VI.Kills.push_back(NewMI);
330 MFI->insert(MBBI, NewMIs[1]);
331 MFI->insert(MBBI, NewMIs[0]);
336 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
337 MachineBasicBlock *&FBB,
338 SmallVectorImpl<MachineOperand> &Cond,
339 bool AllowModify) const {
340 // If the block has no terminators, it just falls into the block after it.
341 MachineBasicBlock::iterator I = MBB.end();
342 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
345 // Get the last instruction in the block.
346 MachineInstr *LastInst = I;
348 // If there is only one terminator instruction, process it.
349 unsigned LastOpc = LastInst->getOpcode();
350 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
351 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
352 TBB = LastInst->getOperand(0).getMBB();
355 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
356 // Block ends with fall-through condbranch.
357 TBB = LastInst->getOperand(0).getMBB();
358 Cond.push_back(LastInst->getOperand(1));
359 Cond.push_back(LastInst->getOperand(2));
362 return true; // Can't handle indirect branch.
365 // Get the instruction before it if it is a terminator.
366 MachineInstr *SecondLastInst = I;
368 // If there are three terminators, we don't know what sort of block this is.
369 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
372 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
373 unsigned SecondLastOpc = SecondLastInst->getOpcode();
374 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
375 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
376 TBB = SecondLastInst->getOperand(0).getMBB();
377 Cond.push_back(SecondLastInst->getOperand(1));
378 Cond.push_back(SecondLastInst->getOperand(2));
379 FBB = LastInst->getOperand(0).getMBB();
383 // If the block ends with two unconditional branches, handle it. The second
384 // one is not executed, so remove it.
385 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
386 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
387 TBB = SecondLastInst->getOperand(0).getMBB();
390 I->eraseFromParent();
394 // Likewise if it ends with a branch table followed by an unconditional branch.
395 // The branch folder can create these, and we must get rid of them for
396 // correctness of Thumb constant islands.
397 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
398 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
399 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
402 I->eraseFromParent();
406 // Otherwise, can't handle this.
411 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
412 MachineFunction &MF = *MBB.getParent();
413 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
414 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
415 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
417 MachineBasicBlock::iterator I = MBB.end();
418 if (I == MBB.begin()) return 0;
420 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
423 // Remove the branch.
424 I->eraseFromParent();
428 if (I == MBB.begin()) return 1;
430 if (I->getOpcode() != BccOpc)
433 // Remove the branch.
434 I->eraseFromParent();
438 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
439 MachineBasicBlock *FBB,
440 const SmallVectorImpl<MachineOperand> &Cond) const {
441 MachineFunction &MF = *MBB.getParent();
442 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
443 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
444 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
446 // Shouldn't be a fall through.
447 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
448 assert((Cond.size() == 2 || Cond.size() == 0) &&
449 "ARM branch conditions have two components!");
452 if (Cond.empty()) // Unconditional branch?
453 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
455 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
456 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
460 // Two-way conditional branch.
461 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
462 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
463 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
467 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
468 MachineBasicBlock::iterator I,
469 unsigned DestReg, unsigned SrcReg,
470 const TargetRegisterClass *DestRC,
471 const TargetRegisterClass *SrcRC) const {
472 if (DestRC != SrcRC) {
473 // Not yet supported!
477 if (DestRC == ARM::GPRRegisterClass) {
478 MachineFunction &MF = *MBB.getParent();
479 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
480 if (AFI->isThumbFunction())
481 BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg);
483 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg)
485 } else if (DestRC == ARM::SPRRegisterClass)
486 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg)
488 else if (DestRC == ARM::DPRRegisterClass)
489 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
497 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
498 MachineOperand &MO) {
500 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
502 MIB = MIB.addImm(MO.getImm());
504 MIB = MIB.addFrameIndex(MO.getIndex());
506 assert(0 && "Unknown operand for ARMInstrAddOperand!");
512 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
513 unsigned SrcReg, bool isKill, int FI,
514 const TargetRegisterClass *RC) const {
515 if (RC == ARM::GPRRegisterClass) {
516 MachineFunction &MF = *MBB.getParent();
517 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
518 if (AFI->isThumbFunction())
519 BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
520 .addFrameIndex(FI).addImm(0);
522 AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
523 .addReg(SrcReg, false, false, isKill)
524 .addFrameIndex(FI).addReg(0).addImm(0));
525 } else if (RC == ARM::DPRRegisterClass) {
526 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
527 .addReg(SrcReg, false, false, isKill)
528 .addFrameIndex(FI).addImm(0));
530 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
531 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
532 .addReg(SrcReg, false, false, isKill)
533 .addFrameIndex(FI).addImm(0));
537 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
539 SmallVectorImpl<MachineOperand> &Addr,
540 const TargetRegisterClass *RC,
541 SmallVectorImpl<MachineInstr*> &NewMIs) const {
543 if (RC == ARM::GPRRegisterClass) {
544 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
545 if (AFI->isThumbFunction()) {
546 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
547 MachineInstrBuilder MIB =
548 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
549 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
550 MIB = ARMInstrAddOperand(MIB, Addr[i]);
551 NewMIs.push_back(MIB);
555 } else if (RC == ARM::DPRRegisterClass) {
558 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
562 MachineInstrBuilder MIB =
563 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
564 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
565 MIB = ARMInstrAddOperand(MIB, Addr[i]);
567 NewMIs.push_back(MIB);
572 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
573 unsigned DestReg, int FI,
574 const TargetRegisterClass *RC) const {
575 if (RC == ARM::GPRRegisterClass) {
576 MachineFunction &MF = *MBB.getParent();
577 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
578 if (AFI->isThumbFunction())
579 BuildMI(MBB, I, get(ARM::tRestore), DestReg)
580 .addFrameIndex(FI).addImm(0);
582 AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
583 .addFrameIndex(FI).addReg(0).addImm(0));
584 } else if (RC == ARM::DPRRegisterClass) {
585 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
586 .addFrameIndex(FI).addImm(0));
588 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
589 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
590 .addFrameIndex(FI).addImm(0));
594 void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
595 SmallVectorImpl<MachineOperand> &Addr,
596 const TargetRegisterClass *RC,
597 SmallVectorImpl<MachineInstr*> &NewMIs) const {
599 if (RC == ARM::GPRRegisterClass) {
600 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
601 if (AFI->isThumbFunction()) {
602 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
603 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
604 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
605 MIB = ARMInstrAddOperand(MIB, Addr[i]);
606 NewMIs.push_back(MIB);
610 } else if (RC == ARM::DPRRegisterClass) {
613 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
617 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
618 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
619 MIB = ARMInstrAddOperand(MIB, Addr[i]);
621 NewMIs.push_back(MIB);
625 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
626 MachineBasicBlock::iterator MI,
627 const std::vector<CalleeSavedInfo> &CSI) const {
628 MachineFunction &MF = *MBB.getParent();
629 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
630 if (!AFI->isThumbFunction() || CSI.empty())
633 MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
634 for (unsigned i = CSI.size(); i != 0; --i) {
635 unsigned Reg = CSI[i-1].getReg();
636 // Add the callee-saved register as live-in. It's killed at the spill.
638 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
643 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
644 MachineBasicBlock::iterator MI,
645 const std::vector<CalleeSavedInfo> &CSI) const {
646 MachineFunction &MF = *MBB.getParent();
647 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
648 if (!AFI->isThumbFunction() || CSI.empty())
651 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
652 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
653 MBB.insert(MI, PopMI);
654 for (unsigned i = CSI.size(); i != 0; --i) {
655 unsigned Reg = CSI[i-1].getReg();
656 if (Reg == ARM::LR) {
657 // Special epilogue for vararg functions. See emitEpilogue
661 PopMI->setDesc(get(ARM::tPOP_RET));
664 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
669 MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
671 const SmallVectorImpl<unsigned> &Ops,
673 if (Ops.size() != 1) return NULL;
675 unsigned OpNum = Ops[0];
676 unsigned Opc = MI->getOpcode();
677 MachineInstr *NewMI = NULL;
681 if (MI->getOperand(4).getReg() == ARM::CPSR)
682 // If it is updating CPSR, then it cannot be foled.
684 unsigned Pred = MI->getOperand(2).getImm();
685 unsigned PredReg = MI->getOperand(3).getReg();
686 if (OpNum == 0) { // move -> store
687 unsigned SrcReg = MI->getOperand(1).getReg();
688 bool isKill = MI->getOperand(1).isKill();
689 NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill)
690 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
691 } else { // move -> load
692 unsigned DstReg = MI->getOperand(0).getReg();
693 bool isDead = MI->getOperand(0).isDead();
694 NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead)
695 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
700 if (OpNum == 0) { // move -> store
701 unsigned SrcReg = MI->getOperand(1).getReg();
702 bool isKill = MI->getOperand(1).isKill();
703 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
704 // tSpill cannot take a high register operand.
706 NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
707 .addFrameIndex(FI).addImm(0);
708 } else { // move -> load
709 unsigned DstReg = MI->getOperand(0).getReg();
710 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
711 // tRestore cannot target a high register operand.
713 bool isDead = MI->getOperand(0).isDead();
714 NewMI = BuildMI(MF, get(ARM::tRestore))
715 .addReg(DstReg, true, false, false, isDead)
716 .addFrameIndex(FI).addImm(0);
721 unsigned Pred = MI->getOperand(2).getImm();
722 unsigned PredReg = MI->getOperand(3).getReg();
723 if (OpNum == 0) { // move -> store
724 unsigned SrcReg = MI->getOperand(1).getReg();
725 NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
726 .addImm(0).addImm(Pred).addReg(PredReg);
727 } else { // move -> load
728 unsigned DstReg = MI->getOperand(0).getReg();
729 NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI)
730 .addImm(0).addImm(Pred).addReg(PredReg);
735 unsigned Pred = MI->getOperand(2).getImm();
736 unsigned PredReg = MI->getOperand(3).getReg();
737 if (OpNum == 0) { // move -> store
738 unsigned SrcReg = MI->getOperand(1).getReg();
739 bool isKill = MI->getOperand(1).isKill();
740 NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill)
741 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
742 } else { // move -> load
743 unsigned DstReg = MI->getOperand(0).getReg();
744 bool isDead = MI->getOperand(0).isDead();
745 NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead)
746 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
755 bool ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
756 const SmallVectorImpl<unsigned> &Ops) const {
757 if (Ops.size() != 1) return false;
759 unsigned OpNum = Ops[0];
760 unsigned Opc = MI->getOpcode();
764 // If it is updating CPSR, then it cannot be foled.
765 return MI->getOperand(4).getReg() != ARM::CPSR;
767 if (OpNum == 0) { // move -> store
768 unsigned SrcReg = MI->getOperand(1).getReg();
769 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
770 // tSpill cannot take a high register operand.
772 } else { // move -> load
773 unsigned DstReg = MI->getOperand(0).getReg();
774 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
775 // tRestore cannot target a high register operand.
788 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
789 if (MBB.empty()) return false;
791 switch (MBB.back().getOpcode()) {
792 case ARM::BX_RET: // Return.
795 case ARM::tBX_RET_vararg:
798 case ARM::tB: // Uncond branch.
800 case ARM::BR_JTr: // Jumptable branch.
801 case ARM::BR_JTm: // Jumptable branch through mem.
802 case ARM::BR_JTadd: // Jumptable branch add to pc.
804 default: return false;
809 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
810 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
811 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
815 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
816 int PIdx = MI->findFirstPredOperandIdx();
817 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
820 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
821 const SmallVectorImpl<MachineOperand> &Pred) const {
822 unsigned Opc = MI->getOpcode();
823 if (Opc == ARM::B || Opc == ARM::tB) {
824 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
825 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
826 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
830 int PIdx = MI->findFirstPredOperandIdx();
832 MachineOperand &PMO = MI->getOperand(PIdx);
833 PMO.setImm(Pred[0].getImm());
834 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
841 ARMInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
842 const SmallVectorImpl<MachineOperand> &Pred2) const{
843 if (Pred1.size() > 2 || Pred2.size() > 2)
846 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
847 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
857 return CC2 == ARMCC::HI;
859 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
861 return CC2 == ARMCC::GT;
863 return CC2 == ARMCC::LT;
867 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
868 std::vector<MachineOperand> &Pred) const {
869 const TargetInstrDesc &TID = MI->getDesc();
870 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
874 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
875 const MachineOperand &MO = MI->getOperand(i);
876 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
886 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
887 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
888 unsigned JTI) DISABLE_INLINE;
889 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
891 return JT[JTI].MBBs.size();
894 /// GetInstSize - Return the size of the specified MachineInstr.
896 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
897 const MachineBasicBlock &MBB = *MI->getParent();
898 const MachineFunction *MF = MBB.getParent();
899 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
901 // Basic size info comes from the TSFlags field.
902 const TargetInstrDesc &TID = MI->getDesc();
903 unsigned TSFlags = TID.TSFlags;
905 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
907 // If this machine instr is an inline asm, measure it.
908 if (MI->getOpcode() == ARM::INLINEASM)
909 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
912 switch (MI->getOpcode()) {
914 assert(0 && "Unknown or unset size field for instr!");
916 case TargetInstrInfo::IMPLICIT_DEF:
917 case TargetInstrInfo::DECLARE:
918 case TargetInstrInfo::DBG_LABEL:
919 case TargetInstrInfo::EH_LABEL:
924 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
925 case ARMII::Size4Bytes: return 4; // Arm instruction.
926 case ARMII::Size2Bytes: return 2; // Thumb instruction.
927 case ARMII::SizeSpecial: {
928 switch (MI->getOpcode()) {
929 case ARM::CONSTPOOL_ENTRY:
930 // If this machine instr is a constant pool entry, its size is recorded as
932 return MI->getOperand(2).getImm();
937 // These are jumptable branches, i.e. a branch followed by an inlined
938 // jumptable. The size is 4 + 4 * number of entries.
939 unsigned NumOps = TID.getNumOperands();
940 MachineOperand JTOP =
941 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
942 unsigned JTI = JTOP.getIndex();
943 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
944 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
945 assert(JTI < JT.size());
946 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
947 // 4 aligned. The assembler / linker may add 2 byte padding just before
948 // the JT entries. The size does not include this padding; the
949 // constant islands pass does separate bookkeeping for it.
950 // FIXME: If we know the size of the function is less than (1 << 16) *2
951 // bytes, we can use 16-bit entries instead. Then there won't be an
953 return getNumJTEntries(JT, JTI) * 4 +
954 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
957 // Otherwise, pseudo-instruction sizes are zero.
962 return 0; // Not reached