1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def Branch : Format<3>;
25 def BranchMisc : Format<4>;
27 def DPFrm : Format<5>;
28 def DPSoRegFrm : Format<6>;
30 def LdFrm : Format<7>;
31 def StFrm : Format<8>;
32 def LdMiscFrm : Format<9>;
33 def StMiscFrm : Format<10>;
34 def LdMulFrm : Format<11>;
35 def StMulFrm : Format<12>;
37 def ArithMisc : Format<13>;
38 def ThumbFrm : Format<14>;
39 def VFPFrm : Format<15>;
41 // Misc flag for data processing instructions that indicates whether
42 // the instruction has a Rn register operand.
43 class UnaryDP { bit isUnaryDataProc = 1; }
45 //===----------------------------------------------------------------------===//
47 // ARM Instruction templates.
50 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
51 Format f, string cstr>
55 let Namespace = "ARM";
59 bits<4> AddrModeBits = AM.Value;
62 bits<3> SizeFlag = SZ.Value;
65 bits<2> IndexModeBits = IM.Value;
68 bits<5> Form = F.Value;
71 // Attributes specific to ARM instructions...
73 bit isUnaryDataProc = 0;
75 let Constraints = cstr;
78 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
79 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
80 let OutOperandList = oops;
81 let InOperandList = iops;
83 let Pattern = pattern;
86 // Almost all ARM instructions are predicable.
87 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
88 IndexMode im, Format f, string opc, string asm, string cstr,
90 : InstARM<am, sz, im, f, cstr> {
91 let OutOperandList = oops;
92 let InOperandList = !con(iops, (ops pred:$p));
93 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
94 let Pattern = pattern;
95 list<Predicate> Predicates = [IsARM];
98 // Same as I except it can optionally modify CPSR. Note it's modeled as
99 // an input operand since by default it's a zero register. It will
100 // become an implicit def once it's "flipped".
101 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
102 IndexMode im, Format f, string opc, string asm, string cstr,
104 : InstARM<am, sz, im, f, cstr> {
105 let OutOperandList = oops;
106 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
107 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
108 let Pattern = pattern;
109 list<Predicate> Predicates = [IsARM];
113 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
114 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
115 : InstARM<am, sz, im, f, cstr> {
116 let OutOperandList = oops;
117 let InOperandList = iops;
119 let Pattern = pattern;
120 list<Predicate> Predicates = [IsARM];
123 class AI<dag oops, dag iops, Format f, string opc,
124 string asm, list<dag> pattern>
125 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
127 class AsI<dag oops, dag iops, Format f, string opc,
128 string asm, list<dag> pattern>
129 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
131 class AXI<dag oops, dag iops, Format f, string asm,
133 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
136 // Ctrl flow instructions
137 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
138 string asm, list<dag> pattern>
139 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
141 let Inst{27-24} = opcod;
143 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
145 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
147 let Inst{27-24} = opcod;
150 class AXIx2<dag oops, dag iops, Format f, string asm,
152 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
154 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
156 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
158 let Inst{27-24} = opcod;
160 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
161 string asm, list<dag> pattern>
162 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
164 let Inst{27-24} = opcod;
167 // BR_JT instructions
169 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
170 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
172 let Inst{20} = 0; // S Bit
173 let Inst{24-21} = opcod;
174 let Inst{27-26} = {0,0};
177 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
178 : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
180 let Inst{20} = 0; // S bit
181 let Inst{24-21} = opcod;
182 let Inst{27-26} = {0,0};
185 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
186 : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
188 let Inst{20} = 1; // L bit
189 let Inst{21} = 0; // W bit
190 let Inst{22} = 0; // B bit
191 let Inst{24} = 1; // P bit
192 let Inst{27-26} = {0,1};
196 // addrmode1 instructions
197 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
198 string asm, list<dag> pattern>
199 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
201 let Inst{24-21} = opcod;
202 let Inst{27-26} = {0,0};
204 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
205 string asm, list<dag> pattern>
206 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
208 let Inst{24-21} = opcod;
209 let Inst{27-26} = {0,0};
211 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
213 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
215 let Inst{24-21} = opcod;
216 let Inst{27-26} = {0,0};
218 class AI1x2<dag oops, dag iops, Format f, string opc,
219 string asm, list<dag> pattern>
220 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
224 // addrmode2 loads and stores
225 class AI2<dag oops, dag iops, Format f, string opc,
226 string asm, list<dag> pattern>
227 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
229 let Inst{27-26} = {0,1};
233 class AI2ldw<dag oops, dag iops, Format f, string opc,
234 string asm, list<dag> pattern>
235 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
237 let Inst{20} = 1; // L bit
238 let Inst{21} = 0; // W bit
239 let Inst{22} = 0; // B bit
240 let Inst{24} = 1; // P bit
241 let Inst{27-26} = {0,1};
243 class AXI2ldw<dag oops, dag iops, Format f, string asm,
245 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
247 let Inst{20} = 1; // L bit
248 let Inst{21} = 0; // W bit
249 let Inst{22} = 0; // B bit
250 let Inst{24} = 1; // P bit
251 let Inst{27-26} = {0,1};
253 class AI2ldb<dag oops, dag iops, Format f, string opc,
254 string asm, list<dag> pattern>
255 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
257 let Inst{20} = 1; // L bit
258 let Inst{21} = 0; // W bit
259 let Inst{22} = 1; // B bit
260 let Inst{24} = 1; // P bit
261 let Inst{27-26} = {0,1};
263 class AXI2ldb<dag oops, dag iops, Format f, string asm,
265 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
267 let Inst{20} = 1; // L bit
268 let Inst{21} = 0; // W bit
269 let Inst{22} = 1; // B bit
270 let Inst{24} = 1; // P bit
271 let Inst{27-26} = {0,1};
275 class AI2stw<dag oops, dag iops, Format f, string opc,
276 string asm, list<dag> pattern>
277 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
279 let Inst{20} = 0; // L bit
280 let Inst{21} = 0; // W bit
281 let Inst{22} = 0; // B bit
282 let Inst{24} = 1; // P bit
283 let Inst{27-26} = {0,1};
285 class AXI2stw<dag oops, dag iops, Format f, string asm,
287 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
289 let Inst{20} = 0; // L bit
290 let Inst{21} = 0; // W bit
291 let Inst{22} = 0; // B bit
292 let Inst{24} = 1; // P bit
293 let Inst{27-26} = {0,1};
295 class AI2stb<dag oops, dag iops, Format f, string opc,
296 string asm, list<dag> pattern>
297 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
299 let Inst{20} = 0; // L bit
300 let Inst{21} = 0; // W bit
301 let Inst{22} = 1; // B bit
302 let Inst{24} = 1; // P bit
303 let Inst{27-26} = {0,1};
305 class AXI2stb<dag oops, dag iops, Format f, string asm,
307 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
309 let Inst{20} = 0; // L bit
310 let Inst{21} = 0; // W bit
311 let Inst{22} = 1; // B bit
312 let Inst{24} = 1; // P bit
313 let Inst{27-26} = {0,1};
317 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
318 string asm, string cstr, list<dag> pattern>
319 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
320 asm, cstr, pattern> {
321 let Inst{20} = 1; // L bit
322 let Inst{21} = 1; // W bit
323 let Inst{22} = 0; // B bit
324 let Inst{24} = 1; // P bit
325 let Inst{27-26} = {0,1};
327 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
328 string asm, string cstr, list<dag> pattern>
329 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
330 asm, cstr, pattern> {
331 let Inst{20} = 1; // L bit
332 let Inst{21} = 1; // W bit
333 let Inst{22} = 1; // B bit
334 let Inst{24} = 1; // P bit
335 let Inst{27-26} = {0,1};
338 // Pre-indexed stores
339 class AI2stwpr<dag oops, dag iops, Format f, string opc,
340 string asm, string cstr, list<dag> pattern>
341 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
342 asm, cstr, pattern> {
343 let Inst{20} = 0; // L bit
344 let Inst{21} = 1; // W bit
345 let Inst{22} = 0; // B bit
346 let Inst{24} = 1; // P bit
347 let Inst{27-26} = {0,1};
349 class AI2stbpr<dag oops, dag iops, Format f, string opc,
350 string asm, string cstr, list<dag> pattern>
351 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
352 asm, cstr, pattern> {
353 let Inst{20} = 0; // L bit
354 let Inst{21} = 1; // W bit
355 let Inst{22} = 1; // B bit
356 let Inst{24} = 1; // P bit
357 let Inst{27-26} = {0,1};
360 // Post-indexed loads
361 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
362 string asm, string cstr, list<dag> pattern>
363 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
365 let Inst{20} = 1; // L bit
366 let Inst{21} = 0; // W bit
367 let Inst{22} = 0; // B bit
368 let Inst{24} = 0; // P bit
369 let Inst{27-26} = {0,1};
371 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
372 string asm, string cstr, list<dag> pattern>
373 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
375 let Inst{20} = 1; // L bit
376 let Inst{21} = 0; // W bit
377 let Inst{22} = 1; // B bit
378 let Inst{24} = 0; // P bit
379 let Inst{27-26} = {0,1};
382 // Post-indexed stores
383 class AI2stwpo<dag oops, dag iops, Format f, string opc,
384 string asm, string cstr, list<dag> pattern>
385 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
387 let Inst{20} = 0; // L bit
388 let Inst{21} = 0; // W bit
389 let Inst{22} = 0; // B bit
390 let Inst{24} = 0; // P bit
391 let Inst{27-26} = {0,1};
393 class AI2stbpo<dag oops, dag iops, Format f, string opc,
394 string asm, string cstr, list<dag> pattern>
395 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
397 let Inst{20} = 0; // L bit
398 let Inst{21} = 0; // W bit
399 let Inst{22} = 1; // B bit
400 let Inst{24} = 0; // P bit
401 let Inst{27-26} = {0,1};
404 // addrmode3 instructions
405 class AI3<dag oops, dag iops, Format f, string opc,
406 string asm, list<dag> pattern>
407 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
409 class AXI3<dag oops, dag iops, Format f, string asm,
411 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
415 class AI3ldh<dag oops, dag iops, Format f, string opc,
416 string asm, list<dag> pattern>
417 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
420 let Inst{5} = 1; // H bit
421 let Inst{6} = 0; // S bit
423 let Inst{20} = 1; // L bit
424 let Inst{21} = 0; // W bit
425 let Inst{24} = 1; // P bit
427 class AXI3ldh<dag oops, dag iops, Format f, string asm,
429 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
432 let Inst{5} = 1; // H bit
433 let Inst{6} = 0; // S bit
435 let Inst{20} = 1; // L bit
436 let Inst{21} = 0; // W bit
437 let Inst{24} = 1; // P bit
439 class AI3ldsh<dag oops, dag iops, Format f, string opc,
440 string asm, list<dag> pattern>
441 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
444 let Inst{5} = 1; // H bit
445 let Inst{6} = 1; // S bit
447 let Inst{20} = 1; // L bit
448 let Inst{21} = 0; // W bit
449 let Inst{24} = 1; // P bit
451 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
453 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
456 let Inst{5} = 1; // H bit
457 let Inst{6} = 1; // S bit
459 let Inst{20} = 1; // L bit
460 let Inst{21} = 0; // W bit
461 let Inst{24} = 1; // P bit
463 class AI3ldsb<dag oops, dag iops, Format f, string opc,
464 string asm, list<dag> pattern>
465 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
468 let Inst{5} = 0; // H bit
469 let Inst{6} = 1; // S bit
471 let Inst{20} = 1; // L bit
472 let Inst{21} = 0; // W bit
473 let Inst{24} = 1; // P bit
475 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
477 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
480 let Inst{5} = 0; // H bit
481 let Inst{6} = 1; // S bit
483 let Inst{20} = 1; // L bit
484 let Inst{21} = 0; // W bit
485 let Inst{24} = 1; // P bit
487 class AI3ldd<dag oops, dag iops, Format f, string opc,
488 string asm, list<dag> pattern>
489 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
492 let Inst{5} = 0; // H bit
493 let Inst{6} = 1; // S bit
495 let Inst{20} = 0; // L bit
496 let Inst{21} = 0; // W bit
497 let Inst{24} = 1; // P bit
501 class AI3sth<dag oops, dag iops, Format f, string opc,
502 string asm, list<dag> pattern>
503 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
506 let Inst{5} = 1; // H bit
507 let Inst{6} = 0; // S bit
509 let Inst{20} = 0; // L bit
510 let Inst{21} = 0; // W bit
511 let Inst{24} = 1; // P bit
513 class AXI3sth<dag oops, dag iops, Format f, string asm,
515 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
518 let Inst{5} = 1; // H bit
519 let Inst{6} = 0; // S bit
521 let Inst{20} = 0; // L bit
522 let Inst{21} = 0; // W bit
523 let Inst{24} = 1; // P bit
525 class AI3std<dag oops, dag iops, Format f, string opc,
526 string asm, list<dag> pattern>
527 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
530 let Inst{5} = 1; // H bit
531 let Inst{6} = 1; // S bit
533 let Inst{20} = 0; // L bit
534 let Inst{21} = 0; // W bit
535 let Inst{24} = 1; // P bit
539 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
540 string asm, string cstr, list<dag> pattern>
541 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
542 asm, cstr, pattern> {
544 let Inst{5} = 1; // H bit
545 let Inst{6} = 0; // S bit
547 let Inst{20} = 1; // L bit
548 let Inst{21} = 1; // W bit
549 let Inst{24} = 1; // P bit
551 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
552 string asm, string cstr, list<dag> pattern>
553 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
554 asm, cstr, pattern> {
556 let Inst{5} = 1; // H bit
557 let Inst{6} = 1; // S bit
559 let Inst{20} = 1; // L bit
560 let Inst{21} = 1; // W bit
561 let Inst{24} = 1; // P bit
563 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
564 string asm, string cstr, list<dag> pattern>
565 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
566 asm, cstr, pattern> {
568 let Inst{5} = 0; // H bit
569 let Inst{6} = 1; // S bit
571 let Inst{20} = 1; // L bit
572 let Inst{21} = 1; // W bit
573 let Inst{24} = 1; // P bit
576 // Pre-indexed stores
577 class AI3sthpr<dag oops, dag iops, Format f, string opc,
578 string asm, string cstr, list<dag> pattern>
579 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
580 asm, cstr, pattern> {
582 let Inst{5} = 1; // H bit
583 let Inst{6} = 0; // S bit
585 let Inst{20} = 0; // L bit
586 let Inst{21} = 1; // W bit
587 let Inst{24} = 1; // P bit
590 // Post-indexed loads
591 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
592 string asm, string cstr, list<dag> pattern>
593 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
596 let Inst{5} = 1; // H bit
597 let Inst{6} = 0; // S bit
599 let Inst{20} = 1; // L bit
600 let Inst{21} = 1; // W bit
601 let Inst{24} = 0; // P bit
603 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
604 string asm, string cstr, list<dag> pattern>
605 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
608 let Inst{5} = 1; // H bit
609 let Inst{6} = 1; // S bit
611 let Inst{20} = 1; // L bit
612 let Inst{21} = 1; // W bit
613 let Inst{24} = 0; // P bit
615 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
616 string asm, string cstr, list<dag> pattern>
617 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
620 let Inst{5} = 0; // H bit
621 let Inst{6} = 1; // S bit
623 let Inst{20} = 1; // L bit
624 let Inst{21} = 1; // W bit
625 let Inst{24} = 0; // P bit
628 // Post-indexed stores
629 class AI3sthpo<dag oops, dag iops, Format f, string opc,
630 string asm, string cstr, list<dag> pattern>
631 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
634 let Inst{5} = 1; // H bit
635 let Inst{6} = 0; // S bit
637 let Inst{20} = 0; // L bit
638 let Inst{21} = 1; // W bit
639 let Inst{24} = 0; // P bit
643 // addrmode4 instructions
644 class AI4<dag oops, dag iops, Format f, string opc,
645 string asm, list<dag> pattern>
646 : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
648 let Inst{25-27} = {0,0,1};
650 class AXI4ld<dag oops, dag iops, Format f, string asm,
652 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
654 let Inst{20} = 1; // L bit
655 let Inst{22} = 0; // S bit
656 let Inst{27-25} = 0b100;
658 class AXI4ldpc<dag oops, dag iops, Format f, string asm,
660 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
662 let Inst{20} = 1; // L bit
663 let Inst{27-25} = 0b100;
665 class AXI4st<dag oops, dag iops, Format f, string asm,
667 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
669 let Inst{20} = 0; // L bit
670 let Inst{22} = 0; // S bit
671 let Inst{27-25} = 0b100;
674 // Unsigned multiply, multiply-accumulate instructions.
675 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
676 string asm, list<dag> pattern>
677 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
679 let Inst{7-4} = 0b1001;
680 let Inst{20} = 0; // S bit
681 let Inst{27-21} = opcod;
683 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
684 string asm, list<dag> pattern>
685 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
687 let Inst{7-4} = 0b1001;
688 let Inst{27-21} = opcod;
691 // Most significant word multiply
692 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
693 string asm, list<dag> pattern>
694 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
696 let Inst{7-4} = 0b1001;
698 let Inst{27-21} = opcod;
701 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
702 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
703 string asm, list<dag> pattern>
704 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
709 let Inst{27-21} = opcod;
712 //===----------------------------------------------------------------------===//
714 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
715 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
716 list<Predicate> Predicates = [IsARM];
718 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
719 list<Predicate> Predicates = [IsARM, HasV5TE];
721 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
722 list<Predicate> Predicates = [IsARM, HasV6];
725 //===----------------------------------------------------------------------===//
727 // Thumb Instruction Format Definitions.
731 // TI - Thumb instruction.
733 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
734 string asm, string cstr, list<dag> pattern>
735 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
736 let OutOperandList = outs;
737 let InOperandList = ins;
739 let Pattern = pattern;
740 list<Predicate> Predicates = [IsThumb];
743 class TI<dag outs, dag ins, string asm, list<dag> pattern>
744 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
745 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
746 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
747 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
748 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
749 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
750 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
751 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
752 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
754 // Two-address instructions
755 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
756 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
758 // BL, BLX(1) are translated by assembler into two instructions
759 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
760 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
762 // BR_JT instructions
763 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
764 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
767 //===----------------------------------------------------------------------===//
770 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
771 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
772 list<Predicate> Predicates = [IsThumb];
775 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
776 list<Predicate> Predicates = [IsThumb, HasV5T];