1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def BrFrm : Format<3>;
25 def BrMiscFrm : Format<4>;
27 def DPFrm : Format<5>;
28 def DPSoRegFrm : Format<6>;
30 def LdFrm : Format<7>;
31 def StFrm : Format<8>;
32 def LdMiscFrm : Format<9>;
33 def StMiscFrm : Format<10>;
34 def LdMulFrm : Format<11>;
35 def StMulFrm : Format<12>;
37 def ArithMiscFrm: Format<13>;
38 def ExtFrm : Format<14>;
39 def ThumbFrm : Format<15>;
40 def VFPFrm : Format<16>;
42 // Misc flag for data processing instructions that indicates whether
43 // the instruction has a Rn register operand.
44 class UnaryDP { bit isUnaryDataProc = 1; }
46 //===----------------------------------------------------------------------===//
48 // ARM Instruction templates.
51 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
52 Format f, string cstr>
56 let Namespace = "ARM";
60 bits<4> AddrModeBits = AM.Value;
63 bits<3> SizeFlag = SZ.Value;
66 bits<2> IndexModeBits = IM.Value;
69 bits<5> Form = F.Value;
72 // Attributes specific to ARM instructions...
74 bit isUnaryDataProc = 0;
76 let Constraints = cstr;
79 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
80 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
81 let OutOperandList = oops;
82 let InOperandList = iops;
84 let Pattern = pattern;
87 // Almost all ARM instructions are predicable.
88 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
89 IndexMode im, Format f, string opc, string asm, string cstr,
91 : InstARM<am, sz, im, f, cstr> {
92 let OutOperandList = oops;
93 let InOperandList = !con(iops, (ops pred:$p));
94 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
95 let Pattern = pattern;
96 list<Predicate> Predicates = [IsARM];
99 // Same as I except it can optionally modify CPSR. Note it's modeled as
100 // an input operand since by default it's a zero register. It will
101 // become an implicit def once it's "flipped".
102 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
103 IndexMode im, Format f, string opc, string asm, string cstr,
105 : InstARM<am, sz, im, f, cstr> {
106 let OutOperandList = oops;
107 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
108 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
109 let Pattern = pattern;
110 list<Predicate> Predicates = [IsARM];
114 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
115 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
116 : InstARM<am, sz, im, f, cstr> {
117 let OutOperandList = oops;
118 let InOperandList = iops;
120 let Pattern = pattern;
121 list<Predicate> Predicates = [IsARM];
124 class AI<dag oops, dag iops, Format f, string opc,
125 string asm, list<dag> pattern>
126 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
128 class AsI<dag oops, dag iops, Format f, string opc,
129 string asm, list<dag> pattern>
130 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
132 class AXI<dag oops, dag iops, Format f, string asm,
134 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
137 // Ctrl flow instructions
138 class ABI<bits<4> opcod, dag oops, dag iops, string opc,
139 string asm, list<dag> pattern>
140 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
142 let Inst{27-24} = opcod;
144 class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
145 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
147 let Inst{27-24} = opcod;
149 class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
150 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
153 // BR_JT instructions
155 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
156 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
158 let Inst{20} = 0; // S Bit
159 let Inst{24-21} = opcod;
160 let Inst{27-26} = {0,0};
163 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
164 : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm,
166 let Inst{20} = 0; // S bit
167 let Inst{24-21} = opcod;
168 let Inst{27-26} = {0,0};
171 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
172 : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm,
174 let Inst{20} = 1; // L bit
175 let Inst{21} = 0; // W bit
176 let Inst{22} = 0; // B bit
177 let Inst{24} = 1; // P bit
178 let Inst{27-26} = {0,1};
182 // addrmode1 instructions
183 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
184 string asm, list<dag> pattern>
185 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
187 let Inst{24-21} = opcod;
188 let Inst{27-26} = {0,0};
190 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
191 string asm, list<dag> pattern>
192 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
194 let Inst{24-21} = opcod;
195 let Inst{27-26} = {0,0};
197 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
199 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
201 let Inst{24-21} = opcod;
202 let Inst{27-26} = {0,0};
204 class AI1x2<dag oops, dag iops, Format f, string opc,
205 string asm, list<dag> pattern>
206 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
210 // addrmode2 loads and stores
211 class AI2<dag oops, dag iops, Format f, string opc,
212 string asm, list<dag> pattern>
213 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
215 let Inst{27-26} = {0,1};
219 class AI2ldw<dag oops, dag iops, Format f, string opc,
220 string asm, list<dag> pattern>
221 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
223 let Inst{20} = 1; // L bit
224 let Inst{21} = 0; // W bit
225 let Inst{22} = 0; // B bit
226 let Inst{24} = 1; // P bit
227 let Inst{27-26} = {0,1};
229 class AXI2ldw<dag oops, dag iops, Format f, string asm,
231 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
233 let Inst{20} = 1; // L bit
234 let Inst{21} = 0; // W bit
235 let Inst{22} = 0; // B bit
236 let Inst{24} = 1; // P bit
237 let Inst{27-26} = {0,1};
239 class AI2ldb<dag oops, dag iops, Format f, string opc,
240 string asm, list<dag> pattern>
241 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
243 let Inst{20} = 1; // L bit
244 let Inst{21} = 0; // W bit
245 let Inst{22} = 1; // B bit
246 let Inst{24} = 1; // P bit
247 let Inst{27-26} = {0,1};
249 class AXI2ldb<dag oops, dag iops, Format f, string asm,
251 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
253 let Inst{20} = 1; // L bit
254 let Inst{21} = 0; // W bit
255 let Inst{22} = 1; // B bit
256 let Inst{24} = 1; // P bit
257 let Inst{27-26} = {0,1};
261 class AI2stw<dag oops, dag iops, Format f, string opc,
262 string asm, list<dag> pattern>
263 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
265 let Inst{20} = 0; // L bit
266 let Inst{21} = 0; // W bit
267 let Inst{22} = 0; // B bit
268 let Inst{24} = 1; // P bit
269 let Inst{27-26} = {0,1};
271 class AXI2stw<dag oops, dag iops, Format f, string asm,
273 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
275 let Inst{20} = 0; // L bit
276 let Inst{21} = 0; // W bit
277 let Inst{22} = 0; // B bit
278 let Inst{24} = 1; // P bit
279 let Inst{27-26} = {0,1};
281 class AI2stb<dag oops, dag iops, Format f, string opc,
282 string asm, list<dag> pattern>
283 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
285 let Inst{20} = 0; // L bit
286 let Inst{21} = 0; // W bit
287 let Inst{22} = 1; // B bit
288 let Inst{24} = 1; // P bit
289 let Inst{27-26} = {0,1};
291 class AXI2stb<dag oops, dag iops, Format f, string asm,
293 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
295 let Inst{20} = 0; // L bit
296 let Inst{21} = 0; // W bit
297 let Inst{22} = 1; // B bit
298 let Inst{24} = 1; // P bit
299 let Inst{27-26} = {0,1};
303 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
304 string asm, string cstr, list<dag> pattern>
305 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
306 asm, cstr, pattern> {
307 let Inst{20} = 1; // L bit
308 let Inst{21} = 1; // W bit
309 let Inst{22} = 0; // B bit
310 let Inst{24} = 1; // P bit
311 let Inst{27-26} = {0,1};
313 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
314 string asm, string cstr, list<dag> pattern>
315 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
316 asm, cstr, pattern> {
317 let Inst{20} = 1; // L bit
318 let Inst{21} = 1; // W bit
319 let Inst{22} = 1; // B bit
320 let Inst{24} = 1; // P bit
321 let Inst{27-26} = {0,1};
324 // Pre-indexed stores
325 class AI2stwpr<dag oops, dag iops, Format f, string opc,
326 string asm, string cstr, list<dag> pattern>
327 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
328 asm, cstr, pattern> {
329 let Inst{20} = 0; // L bit
330 let Inst{21} = 1; // W bit
331 let Inst{22} = 0; // B bit
332 let Inst{24} = 1; // P bit
333 let Inst{27-26} = {0,1};
335 class AI2stbpr<dag oops, dag iops, Format f, string opc,
336 string asm, string cstr, list<dag> pattern>
337 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
338 asm, cstr, pattern> {
339 let Inst{20} = 0; // L bit
340 let Inst{21} = 1; // W bit
341 let Inst{22} = 1; // B bit
342 let Inst{24} = 1; // P bit
343 let Inst{27-26} = {0,1};
346 // Post-indexed loads
347 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
348 string asm, string cstr, list<dag> pattern>
349 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
351 let Inst{20} = 1; // L bit
352 let Inst{21} = 0; // W bit
353 let Inst{22} = 0; // B bit
354 let Inst{24} = 0; // P bit
355 let Inst{27-26} = {0,1};
357 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
358 string asm, string cstr, list<dag> pattern>
359 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
361 let Inst{20} = 1; // L bit
362 let Inst{21} = 0; // W bit
363 let Inst{22} = 1; // B bit
364 let Inst{24} = 0; // P bit
365 let Inst{27-26} = {0,1};
368 // Post-indexed stores
369 class AI2stwpo<dag oops, dag iops, Format f, string opc,
370 string asm, string cstr, list<dag> pattern>
371 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
373 let Inst{20} = 0; // L bit
374 let Inst{21} = 0; // W bit
375 let Inst{22} = 0; // B bit
376 let Inst{24} = 0; // P bit
377 let Inst{27-26} = {0,1};
379 class AI2stbpo<dag oops, dag iops, Format f, string opc,
380 string asm, string cstr, list<dag> pattern>
381 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
383 let Inst{20} = 0; // L bit
384 let Inst{21} = 0; // W bit
385 let Inst{22} = 1; // B bit
386 let Inst{24} = 0; // P bit
387 let Inst{27-26} = {0,1};
390 // addrmode3 instructions
391 class AI3<dag oops, dag iops, Format f, string opc,
392 string asm, list<dag> pattern>
393 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
395 class AXI3<dag oops, dag iops, Format f, string asm,
397 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
401 class AI3ldh<dag oops, dag iops, Format f, string opc,
402 string asm, list<dag> pattern>
403 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
406 let Inst{5} = 1; // H bit
407 let Inst{6} = 0; // S bit
409 let Inst{20} = 1; // L bit
410 let Inst{21} = 0; // W bit
411 let Inst{24} = 1; // P bit
413 class AXI3ldh<dag oops, dag iops, Format f, string asm,
415 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
418 let Inst{5} = 1; // H bit
419 let Inst{6} = 0; // S bit
421 let Inst{20} = 1; // L bit
422 let Inst{21} = 0; // W bit
423 let Inst{24} = 1; // P bit
425 class AI3ldsh<dag oops, dag iops, Format f, string opc,
426 string asm, list<dag> pattern>
427 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
430 let Inst{5} = 1; // H bit
431 let Inst{6} = 1; // S bit
433 let Inst{20} = 1; // L bit
434 let Inst{21} = 0; // W bit
435 let Inst{24} = 1; // P bit
437 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
439 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
442 let Inst{5} = 1; // H bit
443 let Inst{6} = 1; // S bit
445 let Inst{20} = 1; // L bit
446 let Inst{21} = 0; // W bit
447 let Inst{24} = 1; // P bit
449 class AI3ldsb<dag oops, dag iops, Format f, string opc,
450 string asm, list<dag> pattern>
451 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
454 let Inst{5} = 0; // H bit
455 let Inst{6} = 1; // S bit
457 let Inst{20} = 1; // L bit
458 let Inst{21} = 0; // W bit
459 let Inst{24} = 1; // P bit
461 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
463 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
466 let Inst{5} = 0; // H bit
467 let Inst{6} = 1; // S bit
469 let Inst{20} = 1; // L bit
470 let Inst{21} = 0; // W bit
471 let Inst{24} = 1; // P bit
473 class AI3ldd<dag oops, dag iops, Format f, string opc,
474 string asm, list<dag> pattern>
475 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
478 let Inst{5} = 0; // H bit
479 let Inst{6} = 1; // S bit
481 let Inst{20} = 0; // L bit
482 let Inst{21} = 0; // W bit
483 let Inst{24} = 1; // P bit
487 class AI3sth<dag oops, dag iops, Format f, string opc,
488 string asm, list<dag> pattern>
489 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
492 let Inst{5} = 1; // H bit
493 let Inst{6} = 0; // S bit
495 let Inst{20} = 0; // L bit
496 let Inst{21} = 0; // W bit
497 let Inst{24} = 1; // P bit
499 class AXI3sth<dag oops, dag iops, Format f, string asm,
501 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
504 let Inst{5} = 1; // H bit
505 let Inst{6} = 0; // S bit
507 let Inst{20} = 0; // L bit
508 let Inst{21} = 0; // W bit
509 let Inst{24} = 1; // P bit
511 class AI3std<dag oops, dag iops, Format f, string opc,
512 string asm, list<dag> pattern>
513 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
516 let Inst{5} = 1; // H bit
517 let Inst{6} = 1; // S bit
519 let Inst{20} = 0; // L bit
520 let Inst{21} = 0; // W bit
521 let Inst{24} = 1; // P bit
525 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
526 string asm, string cstr, list<dag> pattern>
527 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
528 asm, cstr, pattern> {
530 let Inst{5} = 1; // H bit
531 let Inst{6} = 0; // S bit
533 let Inst{20} = 1; // L bit
534 let Inst{21} = 1; // W bit
535 let Inst{24} = 1; // P bit
537 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
538 string asm, string cstr, list<dag> pattern>
539 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
540 asm, cstr, pattern> {
542 let Inst{5} = 1; // H bit
543 let Inst{6} = 1; // S bit
545 let Inst{20} = 1; // L bit
546 let Inst{21} = 1; // W bit
547 let Inst{24} = 1; // P bit
549 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
550 string asm, string cstr, list<dag> pattern>
551 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
552 asm, cstr, pattern> {
554 let Inst{5} = 0; // H bit
555 let Inst{6} = 1; // S bit
557 let Inst{20} = 1; // L bit
558 let Inst{21} = 1; // W bit
559 let Inst{24} = 1; // P bit
562 // Pre-indexed stores
563 class AI3sthpr<dag oops, dag iops, Format f, string opc,
564 string asm, string cstr, list<dag> pattern>
565 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
566 asm, cstr, pattern> {
568 let Inst{5} = 1; // H bit
569 let Inst{6} = 0; // S bit
571 let Inst{20} = 0; // L bit
572 let Inst{21} = 1; // W bit
573 let Inst{24} = 1; // P bit
576 // Post-indexed loads
577 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
578 string asm, string cstr, list<dag> pattern>
579 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
582 let Inst{5} = 1; // H bit
583 let Inst{6} = 0; // S bit
585 let Inst{20} = 1; // L bit
586 let Inst{21} = 1; // W bit
587 let Inst{24} = 0; // P bit
589 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
590 string asm, string cstr, list<dag> pattern>
591 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
594 let Inst{5} = 1; // H bit
595 let Inst{6} = 1; // S bit
597 let Inst{20} = 1; // L bit
598 let Inst{21} = 1; // W bit
599 let Inst{24} = 0; // P bit
601 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
602 string asm, string cstr, list<dag> pattern>
603 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
606 let Inst{5} = 0; // H bit
607 let Inst{6} = 1; // S bit
609 let Inst{20} = 1; // L bit
610 let Inst{21} = 1; // W bit
611 let Inst{24} = 0; // P bit
614 // Post-indexed stores
615 class AI3sthpo<dag oops, dag iops, Format f, string opc,
616 string asm, string cstr, list<dag> pattern>
617 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
620 let Inst{5} = 1; // H bit
621 let Inst{6} = 0; // S bit
623 let Inst{20} = 0; // L bit
624 let Inst{21} = 1; // W bit
625 let Inst{24} = 0; // P bit
629 // addrmode4 instructions
630 class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
631 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
633 let Inst{20} = 1; // L bit
634 let Inst{22} = 0; // S bit
635 let Inst{27-25} = 0b100;
637 class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
638 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
640 let Inst{20} = 0; // L bit
641 let Inst{22} = 0; // S bit
642 let Inst{27-25} = 0b100;
645 // Unsigned multiply, multiply-accumulate instructions.
646 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
647 string asm, list<dag> pattern>
648 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
650 let Inst{7-4} = 0b1001;
651 let Inst{20} = 0; // S bit
652 let Inst{27-21} = opcod;
654 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
655 string asm, list<dag> pattern>
656 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
658 let Inst{7-4} = 0b1001;
659 let Inst{27-21} = opcod;
662 // Most significant word multiply
663 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
664 string asm, list<dag> pattern>
665 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
667 let Inst{7-4} = 0b1001;
669 let Inst{27-21} = opcod;
672 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
673 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
674 string asm, list<dag> pattern>
675 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
680 let Inst{27-21} = opcod;
683 // Extend instructions.
684 class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
685 string asm, list<dag> pattern>
686 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
688 let Inst{7-4} = 0b0111;
689 let Inst{27-20} = opcod;
692 //===----------------------------------------------------------------------===//
694 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
695 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
696 list<Predicate> Predicates = [IsARM];
698 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
699 list<Predicate> Predicates = [IsARM, HasV5TE];
701 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
702 list<Predicate> Predicates = [IsARM, HasV6];
705 //===----------------------------------------------------------------------===//
707 // Thumb Instruction Format Definitions.
711 // TI - Thumb instruction.
713 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
714 string asm, string cstr, list<dag> pattern>
715 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
716 let OutOperandList = outs;
717 let InOperandList = ins;
719 let Pattern = pattern;
720 list<Predicate> Predicates = [IsThumb];
723 class TI<dag outs, dag ins, string asm, list<dag> pattern>
724 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
725 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
726 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
727 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
728 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
729 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
730 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
731 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
732 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
734 // Two-address instructions
735 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
736 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
738 // BL, BLX(1) are translated by assembler into two instructions
739 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
740 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
742 // BR_JT instructions
743 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
744 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
747 //===----------------------------------------------------------------------===//
750 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
751 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
752 list<Predicate> Predicates = [IsThumb];
755 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
756 list<Predicate> Predicates = [IsThumb, HasV5T];