1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : ImmAsmOperand {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let DecoderMethod = "DecodeMSRMask";
193 let ParserMatchClass = MSRMaskOperand;
196 // Shift Right Immediate - A shift right immediate is encoded differently from
197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
204 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
205 def shr_imm8 : Operand<i32> {
206 let EncoderMethod = "getShiftRight8Imm";
207 let DecoderMethod = "DecodeShiftRight8Imm";
208 let ParserMatchClass = shr_imm8_asm_operand;
210 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
211 def shr_imm16 : Operand<i32> {
212 let EncoderMethod = "getShiftRight16Imm";
213 let DecoderMethod = "DecodeShiftRight16Imm";
214 let ParserMatchClass = shr_imm16_asm_operand;
216 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
217 def shr_imm32 : Operand<i32> {
218 let EncoderMethod = "getShiftRight32Imm";
219 let DecoderMethod = "DecodeShiftRight32Imm";
220 let ParserMatchClass = shr_imm32_asm_operand;
222 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
223 def shr_imm64 : Operand<i32> {
224 let EncoderMethod = "getShiftRight64Imm";
225 let DecoderMethod = "DecodeShiftRight64Imm";
226 let ParserMatchClass = shr_imm64_asm_operand;
229 //===----------------------------------------------------------------------===//
230 // ARM Assembler alias templates.
232 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
233 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
234 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
235 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
236 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
237 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
238 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
239 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
240 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
241 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
242 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
243 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
246 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
248 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
251 //===----------------------------------------------------------------------===//
252 // ARM Instruction templates.
256 class InstTemplate<AddrMode am, int sz, IndexMode im,
257 Format f, Domain d, string cstr, InstrItinClass itin>
259 let Namespace = "ARM";
264 bits<2> IndexModeBits = IM.Value;
266 bits<6> Form = F.Value;
268 bit isUnaryDataProc = 0;
269 bit canXformTo16Bit = 0;
270 // The instruction is a 16-bit flag setting Thumb instruction. Used
271 // by the parser to determine whether to require the 'S' suffix on the
272 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
273 bit thumbArithFlagSetting = 0;
275 // If this is a pseudo instruction, mark it isCodeGenOnly.
276 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
278 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
279 let TSFlags{4-0} = AM.Value;
280 let TSFlags{6-5} = IndexModeBits;
281 let TSFlags{12-7} = Form;
282 let TSFlags{13} = isUnaryDataProc;
283 let TSFlags{14} = canXformTo16Bit;
284 let TSFlags{17-15} = D.Value;
285 let TSFlags{18} = thumbArithFlagSetting;
287 let Constraints = cstr;
288 let Itinerary = itin;
293 // Mask of bits that cause an encoding to be UNPREDICTABLE.
294 // If a bit is set, then if the corresponding bit in the
295 // target encoding differs from its value in the "Inst" field,
296 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
297 field bits<32> Unpredictable = 0;
298 // SoftFail is the generic name for this field, but we alias it so
299 // as to make it more obvious what it means in ARM-land.
300 field bits<32> SoftFail = Unpredictable;
303 class InstARM<AddrMode am, int sz, IndexMode im,
304 Format f, Domain d, string cstr, InstrItinClass itin>
305 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
306 let DecoderNamespace = "ARM";
309 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
310 // on by adding flavors to specific instructions.
311 class InstThumb<AddrMode am, int sz, IndexMode im,
312 Format f, Domain d, string cstr, InstrItinClass itin>
313 : InstTemplate<am, sz, im, f, d, cstr, itin> {
314 let DecoderNamespace = "Thumb";
317 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
318 // These are aliases that require C++ handling to convert to the target
319 // instruction, while InstAliases can be handled directly by tblgen.
320 class AsmPseudoInst<string asm, dag iops>
321 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
323 let OutOperandList = (outs);
324 let InOperandList = iops;
326 let isCodeGenOnly = 0; // So we get asm matcher for it.
331 class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
333 class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
335 class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
336 Requires<[IsThumb2]>;
337 class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
339 class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
342 // Pseudo instructions for the code generator.
343 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
344 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
345 GenericDomain, "", itin> {
346 let OutOperandList = oops;
347 let InOperandList = iops;
348 let Pattern = pattern;
349 let isCodeGenOnly = 1;
353 // PseudoInst that's ARM-mode only.
354 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
356 : PseudoInst<oops, iops, itin, pattern> {
358 list<Predicate> Predicates = [IsARM];
361 // PseudoInst that's Thumb-mode only.
362 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
364 : PseudoInst<oops, iops, itin, pattern> {
366 list<Predicate> Predicates = [IsThumb];
369 // PseudoInst that's Thumb2-mode only.
370 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
372 : PseudoInst<oops, iops, itin, pattern> {
374 list<Predicate> Predicates = [IsThumb2];
377 class ARMPseudoExpand<dag oops, dag iops, int sz,
378 InstrItinClass itin, list<dag> pattern,
380 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
381 PseudoInstExpansion<Result>;
383 class tPseudoExpand<dag oops, dag iops, int sz,
384 InstrItinClass itin, list<dag> pattern,
386 : tPseudoInst<oops, iops, sz, itin, pattern>,
387 PseudoInstExpansion<Result>;
389 class t2PseudoExpand<dag oops, dag iops, int sz,
390 InstrItinClass itin, list<dag> pattern,
392 : t2PseudoInst<oops, iops, sz, itin, pattern>,
393 PseudoInstExpansion<Result>;
395 // Almost all ARM instructions are predicable.
396 class I<dag oops, dag iops, AddrMode am, int sz,
397 IndexMode im, Format f, InstrItinClass itin,
398 string opc, string asm, string cstr,
400 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
403 let OutOperandList = oops;
404 let InOperandList = !con(iops, (ins pred:$p));
405 let AsmString = !strconcat(opc, "${p}", asm);
406 let Pattern = pattern;
407 list<Predicate> Predicates = [IsARM];
410 // A few are not predicable
411 class InoP<dag oops, dag iops, AddrMode am, int sz,
412 IndexMode im, Format f, InstrItinClass itin,
413 string opc, string asm, string cstr,
415 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
416 let OutOperandList = oops;
417 let InOperandList = iops;
418 let AsmString = !strconcat(opc, asm);
419 let Pattern = pattern;
420 let isPredicable = 0;
421 list<Predicate> Predicates = [IsARM];
424 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
425 // operand since by default it's a zero register. It will become an implicit def
426 // once it's "flipped".
427 class sI<dag oops, dag iops, AddrMode am, int sz,
428 IndexMode im, Format f, InstrItinClass itin,
429 string opc, string asm, string cstr,
431 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
432 bits<4> p; // Predicate operand
433 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
437 let OutOperandList = oops;
438 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
439 let AsmString = !strconcat(opc, "${s}${p}", asm);
440 let Pattern = pattern;
441 list<Predicate> Predicates = [IsARM];
445 class XI<dag oops, dag iops, AddrMode am, int sz,
446 IndexMode im, Format f, InstrItinClass itin,
447 string asm, string cstr, list<dag> pattern>
448 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
449 let OutOperandList = oops;
450 let InOperandList = iops;
452 let Pattern = pattern;
453 list<Predicate> Predicates = [IsARM];
456 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
457 string opc, string asm, list<dag> pattern>
458 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
459 opc, asm, "", pattern>;
460 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
461 string opc, string asm, list<dag> pattern>
462 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
463 opc, asm, "", pattern>;
464 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
465 string asm, list<dag> pattern>
466 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
468 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
471 opc, asm, "", pattern>;
473 // Ctrl flow instructions
474 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
475 string opc, string asm, list<dag> pattern>
476 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
477 opc, asm, "", pattern> {
478 let Inst{27-24} = opcod;
480 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
481 string asm, list<dag> pattern>
482 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
484 let Inst{27-24} = opcod;
487 // BR_JT instructions
488 class JTI<dag oops, dag iops, InstrItinClass itin,
489 string asm, list<dag> pattern>
490 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
493 // Atomic load/store instructions
494 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
497 opc, asm, "", pattern> {
500 let Inst{27-23} = 0b00011;
501 let Inst{22-21} = opcod;
503 let Inst{19-16} = addr;
504 let Inst{15-12} = Rt;
505 let Inst{11-0} = 0b111110011111;
507 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
508 string opc, string asm, list<dag> pattern>
509 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
510 opc, asm, "", pattern> {
514 let Inst{27-23} = 0b00011;
515 let Inst{22-21} = opcod;
517 let Inst{19-16} = addr;
518 let Inst{15-12} = Rd;
519 let Inst{11-4} = 0b11111001;
522 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
523 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
527 let Inst{27-23} = 0b00010;
529 let Inst{21-20} = 0b00;
530 let Inst{19-16} = addr;
531 let Inst{15-12} = Rt;
532 let Inst{11-4} = 0b00001001;
535 let Unpredictable{11-8} = 0b1111;
536 let DecoderMethod = "DecodeSwap";
539 // addrmode1 instructions
540 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
541 string opc, string asm, list<dag> pattern>
542 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
543 opc, asm, "", pattern> {
544 let Inst{24-21} = opcod;
545 let Inst{27-26} = 0b00;
547 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
548 string opc, string asm, list<dag> pattern>
549 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
550 opc, asm, "", pattern> {
551 let Inst{24-21} = opcod;
552 let Inst{27-26} = 0b00;
554 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
555 string asm, list<dag> pattern>
556 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
558 let Inst{24-21} = opcod;
559 let Inst{27-26} = 0b00;
564 // LDR/LDRB/STR/STRB/...
565 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
566 Format f, InstrItinClass itin, string opc, string asm,
568 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
570 let Inst{27-25} = op;
571 let Inst{24} = 1; // 24 == P
573 let Inst{22} = isByte;
574 let Inst{21} = 0; // 21 == W
577 // Indexed load/stores
578 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
579 IndexMode im, Format f, InstrItinClass itin, string opc,
580 string asm, string cstr, list<dag> pattern>
581 : I<oops, iops, AddrMode2, 4, im, f, itin,
582 opc, asm, cstr, pattern> {
584 let Inst{27-26} = 0b01;
585 let Inst{24} = isPre; // P bit
586 let Inst{22} = isByte; // B bit
587 let Inst{21} = isPre; // W bit
588 let Inst{20} = isLd; // L bit
589 let Inst{15-12} = Rt;
591 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
592 IndexMode im, Format f, InstrItinClass itin, string opc,
593 string asm, string cstr, list<dag> pattern>
594 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
596 // AM2 store w/ two operands: (GPR, am2offset)
602 let Inst{23} = offset{12};
603 let Inst{19-16} = Rn;
604 let Inst{11-5} = offset{11-5};
606 let Inst{3-0} = offset{3-0};
609 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
610 IndexMode im, Format f, InstrItinClass itin, string opc,
611 string asm, string cstr, list<dag> pattern>
612 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
614 // AM2 store w/ two operands: (GPR, am2offset)
620 let Inst{23} = offset{12};
621 let Inst{19-16} = Rn;
622 let Inst{11-0} = offset{11-0};
626 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
627 // but for now use this class for STRT and STRBT.
628 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
629 IndexMode im, Format f, InstrItinClass itin, string opc,
630 string asm, string cstr, list<dag> pattern>
631 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
633 // AM2 store w/ two operands: (GPR, am2offset)
635 // {13} 1 == Rm, 0 == imm12
639 let Inst{25} = addr{13};
640 let Inst{23} = addr{12};
641 let Inst{19-16} = addr{17-14};
642 let Inst{11-0} = addr{11-0};
645 // addrmode3 instructions
646 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
647 InstrItinClass itin, string opc, string asm, list<dag> pattern>
648 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
649 opc, asm, "", pattern> {
652 let Inst{27-25} = 0b000;
653 let Inst{24} = 1; // P bit
654 let Inst{23} = addr{8}; // U bit
655 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
656 let Inst{21} = 0; // W bit
657 let Inst{20} = op20; // L bit
658 let Inst{19-16} = addr{12-9}; // Rn
659 let Inst{15-12} = Rt; // Rt
660 let Inst{11-8} = addr{7-4}; // imm7_4/zero
662 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
664 let DecoderMethod = "DecodeAddrMode3Instruction";
667 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
668 IndexMode im, Format f, InstrItinClass itin, string opc,
669 string asm, string cstr, list<dag> pattern>
670 : I<oops, iops, AddrMode3, 4, im, f, itin,
671 opc, asm, cstr, pattern> {
673 let Inst{27-25} = 0b000;
674 let Inst{24} = isPre; // P bit
675 let Inst{21} = isPre; // W bit
676 let Inst{20} = op20; // L bit
677 let Inst{15-12} = Rt; // Rt
681 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
682 // but for now use this class for LDRSBT, LDRHT, LDSHT.
683 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
684 IndexMode im, Format f, InstrItinClass itin, string opc,
685 string asm, string cstr, list<dag> pattern>
686 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
687 // {13} 1 == imm8, 0 == Rm
694 let Inst{27-25} = 0b000;
695 let Inst{24} = 0; // P bit
697 let Inst{20} = isLoad; // L bit
698 let Inst{19-16} = addr; // Rn
699 let Inst{15-12} = Rt; // Rt
704 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
705 string opc, string asm, list<dag> pattern>
706 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
707 opc, asm, "", pattern> {
710 let Inst{27-25} = 0b000;
711 let Inst{24} = 1; // P bit
712 let Inst{23} = addr{8}; // U bit
713 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
714 let Inst{21} = 0; // W bit
715 let Inst{20} = 0; // L bit
716 let Inst{19-16} = addr{12-9}; // Rn
717 let Inst{15-12} = Rt; // Rt
718 let Inst{11-8} = addr{7-4}; // imm7_4/zero
720 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
721 let DecoderMethod = "DecodeAddrMode3Instruction";
724 // addrmode4 instructions
725 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
726 string asm, string cstr, list<dag> pattern>
727 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
732 let Inst{27-25} = 0b100;
733 let Inst{22} = 0; // S bit
734 let Inst{19-16} = Rn;
735 let Inst{15-0} = regs;
738 // Unsigned multiply, multiply-accumulate instructions.
739 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
740 string opc, string asm, list<dag> pattern>
741 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
742 opc, asm, "", pattern> {
743 let Inst{7-4} = 0b1001;
744 let Inst{20} = 0; // S bit
745 let Inst{27-21} = opcod;
747 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
748 string opc, string asm, list<dag> pattern>
749 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
750 opc, asm, "", pattern> {
751 let Inst{7-4} = 0b1001;
752 let Inst{27-21} = opcod;
755 // Most significant word multiply
756 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
757 InstrItinClass itin, string opc, string asm, list<dag> pattern>
758 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
759 opc, asm, "", pattern> {
763 let Inst{7-4} = opc7_4;
765 let Inst{27-21} = opcod;
766 let Inst{19-16} = Rd;
770 // MSW multiple w/ Ra operand
771 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
772 InstrItinClass itin, string opc, string asm, list<dag> pattern>
773 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
775 let Inst{15-12} = Ra;
778 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
779 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
780 InstrItinClass itin, string opc, string asm, list<dag> pattern>
781 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
782 opc, asm, "", pattern> {
788 let Inst{27-21} = opcod;
789 let Inst{6-5} = bit6_5;
793 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
794 InstrItinClass itin, string opc, string asm, list<dag> pattern>
795 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
797 let Inst{19-16} = Rd;
800 // AMulxyI with Ra operand
801 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
802 InstrItinClass itin, string opc, string asm, list<dag> pattern>
803 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
805 let Inst{15-12} = Ra;
808 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
809 InstrItinClass itin, string opc, string asm, list<dag> pattern>
810 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
813 let Inst{19-16} = RdHi;
814 let Inst{15-12} = RdLo;
817 // Extend instructions.
818 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
819 string opc, string asm, list<dag> pattern>
820 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
821 opc, asm, "", pattern> {
822 // All AExtI instructions have Rd and Rm register operands.
825 let Inst{15-12} = Rd;
827 let Inst{7-4} = 0b0111;
828 let Inst{9-8} = 0b00;
829 let Inst{27-20} = opcod;
832 // Misc Arithmetic instructions.
833 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
834 InstrItinClass itin, string opc, string asm, list<dag> pattern>
835 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
836 opc, asm, "", pattern> {
839 let Inst{27-20} = opcod;
840 let Inst{19-16} = 0b1111;
841 let Inst{15-12} = Rd;
842 let Inst{11-8} = 0b1111;
843 let Inst{7-4} = opc7_4;
848 def PKHLSLAsmOperand : ImmAsmOperand {
849 let Name = "PKHLSLImm";
850 let ParserMethod = "parsePKHLSLImm";
852 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
853 let PrintMethod = "printPKHLSLShiftImm";
854 let ParserMatchClass = PKHLSLAsmOperand;
856 def PKHASRAsmOperand : AsmOperandClass {
857 let Name = "PKHASRImm";
858 let ParserMethod = "parsePKHASRImm";
860 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
861 let PrintMethod = "printPKHASRShiftImm";
862 let ParserMatchClass = PKHASRAsmOperand;
865 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
866 string opc, string asm, list<dag> pattern>
867 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
868 opc, asm, "", pattern> {
873 let Inst{27-20} = opcod;
874 let Inst{19-16} = Rn;
875 let Inst{15-12} = Rd;
878 let Inst{5-4} = 0b01;
882 //===----------------------------------------------------------------------===//
884 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
885 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
886 list<Predicate> Predicates = [IsARM];
888 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
889 list<Predicate> Predicates = [IsARM, HasV5T];
891 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
892 list<Predicate> Predicates = [IsARM, HasV5TE];
894 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
895 list<Predicate> Predicates = [IsARM, HasV6];
898 //===----------------------------------------------------------------------===//
899 // Thumb Instruction Format Definitions.
902 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
903 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
904 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
905 let OutOperandList = oops;
906 let InOperandList = iops;
908 let Pattern = pattern;
909 list<Predicate> Predicates = [IsThumb];
912 // TI - Thumb instruction.
913 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
914 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
916 // Two-address instructions
917 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
919 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
922 // tBL, tBX 32-bit instructions
923 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
924 dag oops, dag iops, InstrItinClass itin, string asm,
926 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
928 let Inst{31-27} = opcod1;
929 let Inst{15-14} = opcod2;
930 let Inst{12} = opcod3;
933 // BR_JT instructions
934 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
936 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
939 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
940 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
941 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
942 let OutOperandList = oops;
943 let InOperandList = iops;
945 let Pattern = pattern;
946 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
949 class T1I<dag oops, dag iops, InstrItinClass itin,
950 string asm, list<dag> pattern>
951 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
952 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
953 string asm, list<dag> pattern>
954 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
956 // Two-address instructions
957 class T1It<dag oops, dag iops, InstrItinClass itin,
958 string asm, string cstr, list<dag> pattern>
959 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
962 // Thumb1 instruction that can either be predicated or set CPSR.
963 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
965 string opc, string asm, string cstr, list<dag> pattern>
966 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
967 let OutOperandList = !con(oops, (outs s_cc_out:$s));
968 let InOperandList = !con(iops, (ins pred:$p));
969 let AsmString = !strconcat(opc, "${s}${p}", asm);
970 let Pattern = pattern;
971 let thumbArithFlagSetting = 1;
972 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
973 let DecoderNamespace = "ThumbSBit";
976 class T1sI<dag oops, dag iops, InstrItinClass itin,
977 string opc, string asm, list<dag> pattern>
978 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
980 // Two-address instructions
981 class T1sIt<dag oops, dag iops, InstrItinClass itin,
982 string opc, string asm, list<dag> pattern>
983 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
984 "$Rn = $Rdn", pattern>;
986 // Thumb1 instruction that can be predicated.
987 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
989 string opc, string asm, string cstr, list<dag> pattern>
990 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
991 let OutOperandList = oops;
992 let InOperandList = !con(iops, (ins pred:$p));
993 let AsmString = !strconcat(opc, "${p}", asm);
994 let Pattern = pattern;
995 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
998 class T1pI<dag oops, dag iops, InstrItinClass itin,
999 string opc, string asm, list<dag> pattern>
1000 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1002 // Two-address instructions
1003 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1004 string opc, string asm, list<dag> pattern>
1005 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1006 "$Rn = $Rdn", pattern>;
1008 class T1pIs<dag oops, dag iops,
1009 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1010 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1012 class Encoding16 : Encoding {
1013 let Inst{31-16} = 0x0000;
1016 // A6.2 16-bit Thumb instruction encoding
1017 class T1Encoding<bits<6> opcode> : Encoding16 {
1018 let Inst{15-10} = opcode;
1021 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1022 class T1General<bits<5> opcode> : Encoding16 {
1023 let Inst{15-14} = 0b00;
1024 let Inst{13-9} = opcode;
1027 // A6.2.2 Data-processing encoding.
1028 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1029 let Inst{15-10} = 0b010000;
1030 let Inst{9-6} = opcode;
1033 // A6.2.3 Special data instructions and branch and exchange encoding.
1034 class T1Special<bits<4> opcode> : Encoding16 {
1035 let Inst{15-10} = 0b010001;
1036 let Inst{9-6} = opcode;
1039 // A6.2.4 Load/store single data item encoding.
1040 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1041 let Inst{15-12} = opA;
1042 let Inst{11-9} = opB;
1044 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1046 class T1BranchCond<bits<4> opcode> : Encoding16 {
1047 let Inst{15-12} = opcode;
1050 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1051 // following bits are used for "opA" (see A6.2.4):
1053 // 0b0110 => Immediate, 4 bytes
1054 // 0b1000 => Immediate, 2 bytes
1055 // 0b0111 => Immediate, 1 byte
1056 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1057 InstrItinClass itin, string opc, string asm,
1059 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1060 T1LoadStore<0b0101, opcode> {
1063 let Inst{8-6} = addr{5-3}; // Rm
1064 let Inst{5-3} = addr{2-0}; // Rn
1067 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1068 InstrItinClass itin, string opc, string asm,
1070 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1071 T1LoadStore<opA, {opB,?,?}> {
1074 let Inst{10-6} = addr{7-3}; // imm5
1075 let Inst{5-3} = addr{2-0}; // Rn
1079 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1080 class T1Misc<bits<7> opcode> : Encoding16 {
1081 let Inst{15-12} = 0b1011;
1082 let Inst{11-5} = opcode;
1085 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1086 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1087 InstrItinClass itin,
1088 string opc, string asm, string cstr, list<dag> pattern>
1089 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1090 let OutOperandList = oops;
1091 let InOperandList = !con(iops, (ins pred:$p));
1092 let AsmString = !strconcat(opc, "${p}", asm);
1093 let Pattern = pattern;
1094 list<Predicate> Predicates = [IsThumb2];
1095 let DecoderNamespace = "Thumb2";
1098 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1099 // input operand since by default it's a zero register. It will become an
1100 // implicit def once it's "flipped".
1102 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1104 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1105 InstrItinClass itin,
1106 string opc, string asm, string cstr, list<dag> pattern>
1107 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1108 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1111 let OutOperandList = oops;
1112 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1113 let AsmString = !strconcat(opc, "${s}${p}", asm);
1114 let Pattern = pattern;
1115 list<Predicate> Predicates = [IsThumb2];
1116 let DecoderNamespace = "Thumb2";
1120 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1121 InstrItinClass itin,
1122 string asm, string cstr, list<dag> pattern>
1123 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1124 let OutOperandList = oops;
1125 let InOperandList = iops;
1126 let AsmString = asm;
1127 let Pattern = pattern;
1128 list<Predicate> Predicates = [IsThumb2];
1129 let DecoderNamespace = "Thumb2";
1132 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1133 InstrItinClass itin,
1134 string asm, string cstr, list<dag> pattern>
1135 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1136 let OutOperandList = oops;
1137 let InOperandList = iops;
1138 let AsmString = asm;
1139 let Pattern = pattern;
1140 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1141 let DecoderNamespace = "Thumb";
1144 class T2I<dag oops, dag iops, InstrItinClass itin,
1145 string opc, string asm, list<dag> pattern>
1146 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1147 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1148 string opc, string asm, list<dag> pattern>
1149 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1150 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1151 string opc, string asm, list<dag> pattern>
1152 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1153 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1154 string opc, string asm, list<dag> pattern>
1155 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1156 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1157 string opc, string asm, list<dag> pattern>
1158 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1159 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1160 string opc, string asm, string cstr, list<dag> pattern>
1161 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1166 let Inst{31-25} = 0b1110100;
1168 let Inst{23} = addr{8};
1171 let Inst{20} = isLoad;
1172 let Inst{19-16} = addr{12-9};
1173 let Inst{15-12} = Rt{3-0};
1174 let Inst{11-8} = Rt2{3-0};
1175 let Inst{7-0} = addr{7-0};
1177 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1178 InstrItinClass itin, string opc, string asm, string cstr,
1180 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1186 let Inst{31-25} = 0b1110100;
1188 let Inst{23} = imm{8};
1191 let Inst{20} = isLoad;
1192 let Inst{19-16} = addr;
1193 let Inst{15-12} = Rt{3-0};
1194 let Inst{11-8} = Rt2{3-0};
1195 let Inst{7-0} = imm{7-0};
1198 class T2sI<dag oops, dag iops, InstrItinClass itin,
1199 string opc, string asm, list<dag> pattern>
1200 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1202 class T2XI<dag oops, dag iops, InstrItinClass itin,
1203 string asm, list<dag> pattern>
1204 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1205 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1206 string asm, list<dag> pattern>
1207 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1209 // Move to/from coprocessor instructions
1210 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1211 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1212 let Inst{31-28} = opc;
1215 // Two-address instructions
1216 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1217 string asm, string cstr, list<dag> pattern>
1218 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1220 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1221 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1223 AddrMode am, IndexMode im, InstrItinClass itin,
1224 string opc, string asm, string cstr, list<dag> pattern>
1225 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1226 let OutOperandList = oops;
1227 let InOperandList = !con(iops, (ins pred:$p));
1228 let AsmString = !strconcat(opc, "${p}", asm);
1229 let Pattern = pattern;
1230 list<Predicate> Predicates = [IsThumb2];
1231 let DecoderNamespace = "Thumb2";
1235 let Inst{31-27} = 0b11111;
1236 let Inst{26-25} = 0b00;
1237 let Inst{24} = signed;
1239 let Inst{22-21} = opcod;
1240 let Inst{20} = load;
1241 let Inst{19-16} = addr{12-9};
1242 let Inst{15-12} = Rt{3-0};
1244 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1245 let Inst{10} = pre; // The P bit.
1246 let Inst{9} = addr{8}; // Sign bit
1247 let Inst{8} = 1; // The W bit.
1248 let Inst{7-0} = addr{7-0};
1250 let DecoderMethod = "DecodeT2LdStPre";
1253 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1254 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1256 AddrMode am, IndexMode im, InstrItinClass itin,
1257 string opc, string asm, string cstr, list<dag> pattern>
1258 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1259 let OutOperandList = oops;
1260 let InOperandList = !con(iops, (ins pred:$p));
1261 let AsmString = !strconcat(opc, "${p}", asm);
1262 let Pattern = pattern;
1263 list<Predicate> Predicates = [IsThumb2];
1264 let DecoderNamespace = "Thumb2";
1269 let Inst{31-27} = 0b11111;
1270 let Inst{26-25} = 0b00;
1271 let Inst{24} = signed;
1273 let Inst{22-21} = opcod;
1274 let Inst{20} = load;
1275 let Inst{19-16} = Rn;
1276 let Inst{15-12} = Rt{3-0};
1278 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1279 let Inst{10} = pre; // The P bit.
1280 let Inst{9} = offset{8}; // Sign bit
1281 let Inst{8} = 1; // The W bit.
1282 let Inst{7-0} = offset{7-0};
1284 let DecoderMethod = "DecodeT2LdStPre";
1287 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1288 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1289 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1292 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1293 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1294 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1297 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1298 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1299 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1302 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1303 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1304 list<Predicate> Predicates = [IsThumb2];
1307 //===----------------------------------------------------------------------===//
1309 //===----------------------------------------------------------------------===//
1310 // ARM VFP Instruction templates.
1313 // Almost all VFP instructions are predicable.
1314 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1315 IndexMode im, Format f, InstrItinClass itin,
1316 string opc, string asm, string cstr, list<dag> pattern>
1317 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1319 let Inst{31-28} = p;
1320 let OutOperandList = oops;
1321 let InOperandList = !con(iops, (ins pred:$p));
1322 let AsmString = !strconcat(opc, "${p}", asm);
1323 let Pattern = pattern;
1324 let PostEncoderMethod = "VFPThumb2PostEncoder";
1325 let DecoderNamespace = "VFP";
1326 list<Predicate> Predicates = [HasVFP2];
1330 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1331 IndexMode im, Format f, InstrItinClass itin,
1332 string asm, string cstr, list<dag> pattern>
1333 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1335 let Inst{31-28} = p;
1336 let OutOperandList = oops;
1337 let InOperandList = iops;
1338 let AsmString = asm;
1339 let Pattern = pattern;
1340 let PostEncoderMethod = "VFPThumb2PostEncoder";
1341 let DecoderNamespace = "VFP";
1342 list<Predicate> Predicates = [HasVFP2];
1345 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1346 string opc, string asm, list<dag> pattern>
1347 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1348 opc, asm, "", pattern> {
1349 let PostEncoderMethod = "VFPThumb2PostEncoder";
1352 // ARM VFP addrmode5 loads and stores
1353 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1354 InstrItinClass itin,
1355 string opc, string asm, list<dag> pattern>
1356 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1357 VFPLdStFrm, itin, opc, asm, "", pattern> {
1358 // Instruction operands.
1362 // Encode instruction operands.
1363 let Inst{23} = addr{8}; // U (add = (U == '1'))
1364 let Inst{22} = Dd{4};
1365 let Inst{19-16} = addr{12-9}; // Rn
1366 let Inst{15-12} = Dd{3-0};
1367 let Inst{7-0} = addr{7-0}; // imm8
1369 // TODO: Mark the instructions with the appropriate subtarget info.
1370 let Inst{27-24} = opcod1;
1371 let Inst{21-20} = opcod2;
1372 let Inst{11-9} = 0b101;
1373 let Inst{8} = 1; // Double precision
1375 // Loads & stores operate on both NEON and VFP pipelines.
1376 let D = VFPNeonDomain;
1379 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1380 InstrItinClass itin,
1381 string opc, string asm, list<dag> pattern>
1382 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1383 VFPLdStFrm, itin, opc, asm, "", pattern> {
1384 // Instruction operands.
1388 // Encode instruction operands.
1389 let Inst{23} = addr{8}; // U (add = (U == '1'))
1390 let Inst{22} = Sd{0};
1391 let Inst{19-16} = addr{12-9}; // Rn
1392 let Inst{15-12} = Sd{4-1};
1393 let Inst{7-0} = addr{7-0}; // imm8
1395 // TODO: Mark the instructions with the appropriate subtarget info.
1396 let Inst{27-24} = opcod1;
1397 let Inst{21-20} = opcod2;
1398 let Inst{11-9} = 0b101;
1399 let Inst{8} = 0; // Single precision
1401 // Loads & stores operate on both NEON and VFP pipelines.
1402 let D = VFPNeonDomain;
1405 // VFP Load / store multiple pseudo instructions.
1406 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1408 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1410 let OutOperandList = oops;
1411 let InOperandList = !con(iops, (ins pred:$p));
1412 let Pattern = pattern;
1413 list<Predicate> Predicates = [HasVFP2];
1416 // Load / store multiple
1417 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1418 string asm, string cstr, list<dag> pattern>
1419 : VFPXI<oops, iops, AddrMode4, 4, im,
1420 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1421 // Instruction operands.
1425 // Encode instruction operands.
1426 let Inst{19-16} = Rn;
1427 let Inst{22} = regs{12};
1428 let Inst{15-12} = regs{11-8};
1429 let Inst{7-0} = regs{7-0};
1431 // TODO: Mark the instructions with the appropriate subtarget info.
1432 let Inst{27-25} = 0b110;
1433 let Inst{11-9} = 0b101;
1434 let Inst{8} = 1; // Double precision
1437 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1438 string asm, string cstr, list<dag> pattern>
1439 : VFPXI<oops, iops, AddrMode4, 4, im,
1440 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1441 // Instruction operands.
1445 // Encode instruction operands.
1446 let Inst{19-16} = Rn;
1447 let Inst{22} = regs{8};
1448 let Inst{15-12} = regs{12-9};
1449 let Inst{7-0} = regs{7-0};
1451 // TODO: Mark the instructions with the appropriate subtarget info.
1452 let Inst{27-25} = 0b110;
1453 let Inst{11-9} = 0b101;
1454 let Inst{8} = 0; // Single precision
1457 // Double precision, unary
1458 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1459 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1460 string asm, list<dag> pattern>
1461 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1462 // Instruction operands.
1466 // Encode instruction operands.
1467 let Inst{3-0} = Dm{3-0};
1468 let Inst{5} = Dm{4};
1469 let Inst{15-12} = Dd{3-0};
1470 let Inst{22} = Dd{4};
1472 let Inst{27-23} = opcod1;
1473 let Inst{21-20} = opcod2;
1474 let Inst{19-16} = opcod3;
1475 let Inst{11-9} = 0b101;
1476 let Inst{8} = 1; // Double precision
1477 let Inst{7-6} = opcod4;
1478 let Inst{4} = opcod5;
1481 // Double precision, binary
1482 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1483 dag iops, InstrItinClass itin, string opc, string asm,
1485 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1486 // Instruction operands.
1491 // Encode instruction operands.
1492 let Inst{3-0} = Dm{3-0};
1493 let Inst{5} = Dm{4};
1494 let Inst{19-16} = Dn{3-0};
1495 let Inst{7} = Dn{4};
1496 let Inst{15-12} = Dd{3-0};
1497 let Inst{22} = Dd{4};
1499 let Inst{27-23} = opcod1;
1500 let Inst{21-20} = opcod2;
1501 let Inst{11-9} = 0b101;
1502 let Inst{8} = 1; // Double precision
1507 // Single precision, unary
1508 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1509 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1510 string asm, list<dag> pattern>
1511 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1512 // Instruction operands.
1516 // Encode instruction operands.
1517 let Inst{3-0} = Sm{4-1};
1518 let Inst{5} = Sm{0};
1519 let Inst{15-12} = Sd{4-1};
1520 let Inst{22} = Sd{0};
1522 let Inst{27-23} = opcod1;
1523 let Inst{21-20} = opcod2;
1524 let Inst{19-16} = opcod3;
1525 let Inst{11-9} = 0b101;
1526 let Inst{8} = 0; // Single precision
1527 let Inst{7-6} = opcod4;
1528 let Inst{4} = opcod5;
1531 // Single precision unary, if no NEON. Same as ASuI except not available if
1533 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1534 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1535 string asm, list<dag> pattern>
1536 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1538 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1541 // Single precision, binary
1542 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1543 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1544 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1545 // Instruction operands.
1550 // Encode instruction operands.
1551 let Inst{3-0} = Sm{4-1};
1552 let Inst{5} = Sm{0};
1553 let Inst{19-16} = Sn{4-1};
1554 let Inst{7} = Sn{0};
1555 let Inst{15-12} = Sd{4-1};
1556 let Inst{22} = Sd{0};
1558 let Inst{27-23} = opcod1;
1559 let Inst{21-20} = opcod2;
1560 let Inst{11-9} = 0b101;
1561 let Inst{8} = 0; // Single precision
1566 // Single precision binary, if no NEON. Same as ASbI except not available if
1568 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1569 dag iops, InstrItinClass itin, string opc, string asm,
1571 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1572 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1574 // Instruction operands.
1579 // Encode instruction operands.
1580 let Inst{3-0} = Sm{4-1};
1581 let Inst{5} = Sm{0};
1582 let Inst{19-16} = Sn{4-1};
1583 let Inst{7} = Sn{0};
1584 let Inst{15-12} = Sd{4-1};
1585 let Inst{22} = Sd{0};
1588 // VFP conversion instructions
1589 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1590 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1592 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1593 let Inst{27-23} = opcod1;
1594 let Inst{21-20} = opcod2;
1595 let Inst{19-16} = opcod3;
1596 let Inst{11-8} = opcod4;
1601 // VFP conversion between floating-point and fixed-point
1602 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1603 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1605 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1607 // size (fixed-point number): sx == 0 ? 16 : 32
1608 let Inst{7} = op5; // sx
1609 let Inst{5} = fbits{0};
1610 let Inst{3-0} = fbits{4-1};
1613 // VFP conversion instructions, if no NEON
1614 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1615 dag oops, dag iops, InstrItinClass itin,
1616 string opc, string asm, list<dag> pattern>
1617 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1619 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1622 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1623 InstrItinClass itin,
1624 string opc, string asm, list<dag> pattern>
1625 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1626 let Inst{27-20} = opcod1;
1627 let Inst{11-8} = opcod2;
1631 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1632 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1633 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1635 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1636 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1637 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1639 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1640 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1641 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1643 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1644 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1645 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1647 //===----------------------------------------------------------------------===//
1649 //===----------------------------------------------------------------------===//
1650 // ARM NEON Instruction templates.
1653 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1654 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1656 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1657 let OutOperandList = oops;
1658 let InOperandList = !con(iops, (ins pred:$p));
1659 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1660 let Pattern = pattern;
1661 list<Predicate> Predicates = [HasNEON];
1662 let DecoderNamespace = "NEON";
1665 // Same as NeonI except it does not have a "data type" specifier.
1666 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1667 InstrItinClass itin, string opc, string asm, string cstr,
1669 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1670 let OutOperandList = oops;
1671 let InOperandList = !con(iops, (ins pred:$p));
1672 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1673 let Pattern = pattern;
1674 list<Predicate> Predicates = [HasNEON];
1675 let DecoderNamespace = "NEON";
1678 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1679 dag oops, dag iops, InstrItinClass itin,
1680 string opc, string dt, string asm, string cstr, list<dag> pattern>
1681 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1683 let Inst{31-24} = 0b11110100;
1684 let Inst{23} = op23;
1685 let Inst{21-20} = op21_20;
1686 let Inst{11-8} = op11_8;
1687 let Inst{7-4} = op7_4;
1689 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1690 let DecoderNamespace = "NEONLoadStore";
1696 let Inst{22} = Vd{4};
1697 let Inst{15-12} = Vd{3-0};
1698 let Inst{19-16} = Rn{3-0};
1699 let Inst{3-0} = Rm{3-0};
1702 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1703 dag oops, dag iops, InstrItinClass itin,
1704 string opc, string dt, string asm, string cstr, list<dag> pattern>
1705 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1706 dt, asm, cstr, pattern> {
1710 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1711 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1713 let OutOperandList = oops;
1714 let InOperandList = !con(iops, (ins pred:$p));
1715 list<Predicate> Predicates = [HasNEON];
1718 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1720 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1722 let OutOperandList = oops;
1723 let InOperandList = !con(iops, (ins pred:$p));
1724 let Pattern = pattern;
1725 list<Predicate> Predicates = [HasNEON];
1728 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1729 string opc, string dt, string asm, string cstr, list<dag> pattern>
1730 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1732 let Inst{31-25} = 0b1111001;
1733 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1734 let DecoderNamespace = "NEONData";
1737 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1738 string opc, string asm, string cstr, list<dag> pattern>
1739 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1741 let Inst{31-25} = 0b1111001;
1742 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1743 let DecoderNamespace = "NEONData";
1746 // NEON "one register and a modified immediate" format.
1747 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1749 dag oops, dag iops, InstrItinClass itin,
1750 string opc, string dt, string asm, string cstr,
1752 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1753 let Inst{23} = op23;
1754 let Inst{21-19} = op21_19;
1755 let Inst{11-8} = op11_8;
1761 // Instruction operands.
1765 let Inst{15-12} = Vd{3-0};
1766 let Inst{22} = Vd{4};
1767 let Inst{24} = SIMM{7};
1768 let Inst{18-16} = SIMM{6-4};
1769 let Inst{3-0} = SIMM{3-0};
1770 let DecoderMethod = "DecodeNEONModImmInstruction";
1773 // NEON 2 vector register format.
1774 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1775 bits<5> op11_7, bit op6, bit op4,
1776 dag oops, dag iops, InstrItinClass itin,
1777 string opc, string dt, string asm, string cstr, list<dag> pattern>
1778 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1779 let Inst{24-23} = op24_23;
1780 let Inst{21-20} = op21_20;
1781 let Inst{19-18} = op19_18;
1782 let Inst{17-16} = op17_16;
1783 let Inst{11-7} = op11_7;
1787 // Instruction operands.
1791 let Inst{15-12} = Vd{3-0};
1792 let Inst{22} = Vd{4};
1793 let Inst{3-0} = Vm{3-0};
1794 let Inst{5} = Vm{4};
1797 // Same as N2V except it doesn't have a datatype suffix.
1798 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1799 bits<5> op11_7, bit op6, bit op4,
1800 dag oops, dag iops, InstrItinClass itin,
1801 string opc, string asm, string cstr, list<dag> pattern>
1802 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1803 let Inst{24-23} = op24_23;
1804 let Inst{21-20} = op21_20;
1805 let Inst{19-18} = op19_18;
1806 let Inst{17-16} = op17_16;
1807 let Inst{11-7} = op11_7;
1811 // Instruction operands.
1815 let Inst{15-12} = Vd{3-0};
1816 let Inst{22} = Vd{4};
1817 let Inst{3-0} = Vm{3-0};
1818 let Inst{5} = Vm{4};
1821 // NEON 2 vector register with immediate.
1822 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1823 dag oops, dag iops, Format f, InstrItinClass itin,
1824 string opc, string dt, string asm, string cstr, list<dag> pattern>
1825 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1826 let Inst{24} = op24;
1827 let Inst{23} = op23;
1828 let Inst{11-8} = op11_8;
1833 // Instruction operands.
1838 let Inst{15-12} = Vd{3-0};
1839 let Inst{22} = Vd{4};
1840 let Inst{3-0} = Vm{3-0};
1841 let Inst{5} = Vm{4};
1842 let Inst{21-16} = SIMM{5-0};
1845 // NEON 3 vector register format.
1847 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1848 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1849 string opc, string dt, string asm, string cstr,
1851 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1852 let Inst{24} = op24;
1853 let Inst{23} = op23;
1854 let Inst{21-20} = op21_20;
1855 let Inst{11-8} = op11_8;
1860 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1861 dag oops, dag iops, Format f, InstrItinClass itin,
1862 string opc, string dt, string asm, string cstr, list<dag> pattern>
1863 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1864 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1866 // Instruction operands.
1871 let Inst{15-12} = Vd{3-0};
1872 let Inst{22} = Vd{4};
1873 let Inst{19-16} = Vn{3-0};
1874 let Inst{7} = Vn{4};
1875 let Inst{3-0} = Vm{3-0};
1876 let Inst{5} = Vm{4};
1879 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1880 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1881 string opc, string dt, string asm, string cstr,
1883 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1884 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1886 // Instruction operands.
1892 let Inst{15-12} = Vd{3-0};
1893 let Inst{22} = Vd{4};
1894 let Inst{19-16} = Vn{3-0};
1895 let Inst{7} = Vn{4};
1896 let Inst{3-0} = Vm{3-0};
1900 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1901 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1902 string opc, string dt, string asm, string cstr,
1904 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1905 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1907 // Instruction operands.
1913 let Inst{15-12} = Vd{3-0};
1914 let Inst{22} = Vd{4};
1915 let Inst{19-16} = Vn{3-0};
1916 let Inst{7} = Vn{4};
1917 let Inst{2-0} = Vm{2-0};
1918 let Inst{5} = lane{1};
1919 let Inst{3} = lane{0};
1922 // Same as N3V except it doesn't have a data type suffix.
1923 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1925 dag oops, dag iops, Format f, InstrItinClass itin,
1926 string opc, string asm, string cstr, list<dag> pattern>
1927 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1928 let Inst{24} = op24;
1929 let Inst{23} = op23;
1930 let Inst{21-20} = op21_20;
1931 let Inst{11-8} = op11_8;
1935 // Instruction operands.
1940 let Inst{15-12} = Vd{3-0};
1941 let Inst{22} = Vd{4};
1942 let Inst{19-16} = Vn{3-0};
1943 let Inst{7} = Vn{4};
1944 let Inst{3-0} = Vm{3-0};
1945 let Inst{5} = Vm{4};
1948 // NEON VMOVs between scalar and core registers.
1949 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1950 dag oops, dag iops, Format f, InstrItinClass itin,
1951 string opc, string dt, string asm, list<dag> pattern>
1952 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1954 let Inst{27-20} = opcod1;
1955 let Inst{11-8} = opcod2;
1956 let Inst{6-5} = opcod3;
1958 // A8.6.303, A8.6.328, A8.6.329
1959 let Inst{3-0} = 0b0000;
1961 let OutOperandList = oops;
1962 let InOperandList = !con(iops, (ins pred:$p));
1963 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1964 let Pattern = pattern;
1965 list<Predicate> Predicates = [HasNEON];
1967 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1968 let DecoderNamespace = "NEONDup";
1975 let Inst{31-28} = p{3-0};
1977 let Inst{19-16} = V{3-0};
1978 let Inst{15-12} = R{3-0};
1980 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1981 dag oops, dag iops, InstrItinClass itin,
1982 string opc, string dt, string asm, list<dag> pattern>
1983 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1984 opc, dt, asm, pattern>;
1985 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1986 dag oops, dag iops, InstrItinClass itin,
1987 string opc, string dt, string asm, list<dag> pattern>
1988 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1989 opc, dt, asm, pattern>;
1990 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1991 dag oops, dag iops, InstrItinClass itin,
1992 string opc, string dt, string asm, list<dag> pattern>
1993 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1994 opc, dt, asm, pattern>;
1996 // Vector Duplicate Lane (from scalar to all elements)
1997 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1998 InstrItinClass itin, string opc, string dt, string asm,
2000 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2001 let Inst{24-23} = 0b11;
2002 let Inst{21-20} = 0b11;
2003 let Inst{19-16} = op19_16;
2004 let Inst{11-7} = 0b11000;
2011 let Inst{22} = Vd{4};
2012 let Inst{15-12} = Vd{3-0};
2013 let Inst{5} = Vm{4};
2014 let Inst{3-0} = Vm{3-0};
2017 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2018 // for single-precision FP.
2019 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2020 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2023 // VFP/NEON Instruction aliases for type suffices.
2024 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
2025 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2027 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2028 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2029 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2030 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2031 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2034 multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> {
2035 let Predicates = [HasNEON] in {
2036 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2037 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2038 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2039 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2043 // The same alias classes using AsmPseudo instead, for the more complex
2044 // stuff in NEON that InstAlias can't quite handle.
2045 // Note that we can't use anonymous defm references here like we can
2046 // above, as we care about the ultimate instruction enum names generated, unlike
2047 // for instalias defs.
2048 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2049 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2051 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2052 def : TokenAlias<".s8", ".i8">;
2053 def : TokenAlias<".u8", ".i8">;
2054 def : TokenAlias<".s16", ".i16">;
2055 def : TokenAlias<".u16", ".i16">;
2056 def : TokenAlias<".s32", ".i32">;
2057 def : TokenAlias<".u32", ".i32">;
2058 def : TokenAlias<".s64", ".i64">;
2059 def : TokenAlias<".u64", ".i64">;
2061 def : TokenAlias<".i8", ".8">;
2062 def : TokenAlias<".i16", ".16">;
2063 def : TokenAlias<".i32", ".32">;
2064 def : TokenAlias<".i64", ".64">;
2066 def : TokenAlias<".p8", ".8">;
2067 def : TokenAlias<".p16", ".16">;
2069 def : TokenAlias<".f32", ".32">;
2070 def : TokenAlias<".f64", ".64">;
2071 def : TokenAlias<".f", ".f32">;
2072 def : TokenAlias<".d", ".f64">;