1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def BrFrm : Format<3>;
25 def BrMiscFrm : Format<4>;
27 def DPFrm : Format<5>;
28 def DPSoRegFrm : Format<6>;
30 def LdFrm : Format<7>;
31 def StFrm : Format<8>;
32 def LdMiscFrm : Format<9>;
33 def StMiscFrm : Format<10>;
34 def LdMulFrm : Format<11>;
35 def StMulFrm : Format<12>;
37 def ArithMisc : Format<13>;
38 def ThumbFrm : Format<14>;
39 def VFPFrm : Format<15>;
41 // Misc flag for data processing instructions that indicates whether
42 // the instruction has a Rn register operand.
43 class UnaryDP { bit isUnaryDataProc = 1; }
45 //===----------------------------------------------------------------------===//
47 // ARM Instruction templates.
50 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
51 Format f, string cstr>
55 let Namespace = "ARM";
59 bits<4> AddrModeBits = AM.Value;
62 bits<3> SizeFlag = SZ.Value;
65 bits<2> IndexModeBits = IM.Value;
68 bits<5> Form = F.Value;
71 // Attributes specific to ARM instructions...
73 bit isUnaryDataProc = 0;
75 let Constraints = cstr;
78 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
79 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
80 let OutOperandList = oops;
81 let InOperandList = iops;
83 let Pattern = pattern;
86 // Almost all ARM instructions are predicable.
87 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
88 IndexMode im, Format f, string opc, string asm, string cstr,
90 : InstARM<am, sz, im, f, cstr> {
91 let OutOperandList = oops;
92 let InOperandList = !con(iops, (ops pred:$p));
93 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
94 let Pattern = pattern;
95 list<Predicate> Predicates = [IsARM];
98 // Same as I except it can optionally modify CPSR. Note it's modeled as
99 // an input operand since by default it's a zero register. It will
100 // become an implicit def once it's "flipped".
101 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
102 IndexMode im, Format f, string opc, string asm, string cstr,
104 : InstARM<am, sz, im, f, cstr> {
105 let OutOperandList = oops;
106 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
107 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
108 let Pattern = pattern;
109 list<Predicate> Predicates = [IsARM];
113 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
114 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
115 : InstARM<am, sz, im, f, cstr> {
116 let OutOperandList = oops;
117 let InOperandList = iops;
119 let Pattern = pattern;
120 list<Predicate> Predicates = [IsARM];
123 class AI<dag oops, dag iops, Format f, string opc,
124 string asm, list<dag> pattern>
125 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
127 class AsI<dag oops, dag iops, Format f, string opc,
128 string asm, list<dag> pattern>
129 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
131 class AXI<dag oops, dag iops, Format f, string asm,
133 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
136 // Ctrl flow instructions
137 class ABI<bits<4> opcod, dag oops, dag iops, string opc,
138 string asm, list<dag> pattern>
139 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
141 let Inst{27-24} = opcod;
143 class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
144 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
146 let Inst{27-24} = opcod;
148 class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
149 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
152 // BR_JT instructions
154 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
155 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
157 let Inst{20} = 0; // S Bit
158 let Inst{24-21} = opcod;
159 let Inst{27-26} = {0,0};
162 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
163 : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm,
165 let Inst{20} = 0; // S bit
166 let Inst{24-21} = opcod;
167 let Inst{27-26} = {0,0};
170 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
171 : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm,
173 let Inst{20} = 1; // L bit
174 let Inst{21} = 0; // W bit
175 let Inst{22} = 0; // B bit
176 let Inst{24} = 1; // P bit
177 let Inst{27-26} = {0,1};
181 // addrmode1 instructions
182 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
183 string asm, list<dag> pattern>
184 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
186 let Inst{24-21} = opcod;
187 let Inst{27-26} = {0,0};
189 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
190 string asm, list<dag> pattern>
191 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
193 let Inst{24-21} = opcod;
194 let Inst{27-26} = {0,0};
196 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
198 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
200 let Inst{24-21} = opcod;
201 let Inst{27-26} = {0,0};
203 class AI1x2<dag oops, dag iops, Format f, string opc,
204 string asm, list<dag> pattern>
205 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
209 // addrmode2 loads and stores
210 class AI2<dag oops, dag iops, Format f, string opc,
211 string asm, list<dag> pattern>
212 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
214 let Inst{27-26} = {0,1};
218 class AI2ldw<dag oops, dag iops, Format f, string opc,
219 string asm, list<dag> pattern>
220 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
222 let Inst{20} = 1; // L bit
223 let Inst{21} = 0; // W bit
224 let Inst{22} = 0; // B bit
225 let Inst{24} = 1; // P bit
226 let Inst{27-26} = {0,1};
228 class AXI2ldw<dag oops, dag iops, Format f, string asm,
230 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
232 let Inst{20} = 1; // L bit
233 let Inst{21} = 0; // W bit
234 let Inst{22} = 0; // B bit
235 let Inst{24} = 1; // P bit
236 let Inst{27-26} = {0,1};
238 class AI2ldb<dag oops, dag iops, Format f, string opc,
239 string asm, list<dag> pattern>
240 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
242 let Inst{20} = 1; // L bit
243 let Inst{21} = 0; // W bit
244 let Inst{22} = 1; // B bit
245 let Inst{24} = 1; // P bit
246 let Inst{27-26} = {0,1};
248 class AXI2ldb<dag oops, dag iops, Format f, string asm,
250 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
252 let Inst{20} = 1; // L bit
253 let Inst{21} = 0; // W bit
254 let Inst{22} = 1; // B bit
255 let Inst{24} = 1; // P bit
256 let Inst{27-26} = {0,1};
260 class AI2stw<dag oops, dag iops, Format f, string opc,
261 string asm, list<dag> pattern>
262 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
264 let Inst{20} = 0; // L bit
265 let Inst{21} = 0; // W bit
266 let Inst{22} = 0; // B bit
267 let Inst{24} = 1; // P bit
268 let Inst{27-26} = {0,1};
270 class AXI2stw<dag oops, dag iops, Format f, string asm,
272 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
274 let Inst{20} = 0; // L bit
275 let Inst{21} = 0; // W bit
276 let Inst{22} = 0; // B bit
277 let Inst{24} = 1; // P bit
278 let Inst{27-26} = {0,1};
280 class AI2stb<dag oops, dag iops, Format f, string opc,
281 string asm, list<dag> pattern>
282 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
284 let Inst{20} = 0; // L bit
285 let Inst{21} = 0; // W bit
286 let Inst{22} = 1; // B bit
287 let Inst{24} = 1; // P bit
288 let Inst{27-26} = {0,1};
290 class AXI2stb<dag oops, dag iops, Format f, string asm,
292 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
294 let Inst{20} = 0; // L bit
295 let Inst{21} = 0; // W bit
296 let Inst{22} = 1; // B bit
297 let Inst{24} = 1; // P bit
298 let Inst{27-26} = {0,1};
302 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
303 string asm, string cstr, list<dag> pattern>
304 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
305 asm, cstr, pattern> {
306 let Inst{20} = 1; // L bit
307 let Inst{21} = 1; // W bit
308 let Inst{22} = 0; // B bit
309 let Inst{24} = 1; // P bit
310 let Inst{27-26} = {0,1};
312 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
313 string asm, string cstr, list<dag> pattern>
314 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
315 asm, cstr, pattern> {
316 let Inst{20} = 1; // L bit
317 let Inst{21} = 1; // W bit
318 let Inst{22} = 1; // B bit
319 let Inst{24} = 1; // P bit
320 let Inst{27-26} = {0,1};
323 // Pre-indexed stores
324 class AI2stwpr<dag oops, dag iops, Format f, string opc,
325 string asm, string cstr, list<dag> pattern>
326 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
327 asm, cstr, pattern> {
328 let Inst{20} = 0; // L bit
329 let Inst{21} = 1; // W bit
330 let Inst{22} = 0; // B bit
331 let Inst{24} = 1; // P bit
332 let Inst{27-26} = {0,1};
334 class AI2stbpr<dag oops, dag iops, Format f, string opc,
335 string asm, string cstr, list<dag> pattern>
336 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
337 asm, cstr, pattern> {
338 let Inst{20} = 0; // L bit
339 let Inst{21} = 1; // W bit
340 let Inst{22} = 1; // B bit
341 let Inst{24} = 1; // P bit
342 let Inst{27-26} = {0,1};
345 // Post-indexed loads
346 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
347 string asm, string cstr, list<dag> pattern>
348 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
350 let Inst{20} = 1; // L bit
351 let Inst{21} = 0; // W bit
352 let Inst{22} = 0; // B bit
353 let Inst{24} = 0; // P bit
354 let Inst{27-26} = {0,1};
356 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
357 string asm, string cstr, list<dag> pattern>
358 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
360 let Inst{20} = 1; // L bit
361 let Inst{21} = 0; // W bit
362 let Inst{22} = 1; // B bit
363 let Inst{24} = 0; // P bit
364 let Inst{27-26} = {0,1};
367 // Post-indexed stores
368 class AI2stwpo<dag oops, dag iops, Format f, string opc,
369 string asm, string cstr, list<dag> pattern>
370 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
372 let Inst{20} = 0; // L bit
373 let Inst{21} = 0; // W bit
374 let Inst{22} = 0; // B bit
375 let Inst{24} = 0; // P bit
376 let Inst{27-26} = {0,1};
378 class AI2stbpo<dag oops, dag iops, Format f, string opc,
379 string asm, string cstr, list<dag> pattern>
380 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
382 let Inst{20} = 0; // L bit
383 let Inst{21} = 0; // W bit
384 let Inst{22} = 1; // B bit
385 let Inst{24} = 0; // P bit
386 let Inst{27-26} = {0,1};
389 // addrmode3 instructions
390 class AI3<dag oops, dag iops, Format f, string opc,
391 string asm, list<dag> pattern>
392 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
394 class AXI3<dag oops, dag iops, Format f, string asm,
396 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
400 class AI3ldh<dag oops, dag iops, Format f, string opc,
401 string asm, list<dag> pattern>
402 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
405 let Inst{5} = 1; // H bit
406 let Inst{6} = 0; // S bit
408 let Inst{20} = 1; // L bit
409 let Inst{21} = 0; // W bit
410 let Inst{24} = 1; // P bit
412 class AXI3ldh<dag oops, dag iops, Format f, string asm,
414 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
417 let Inst{5} = 1; // H bit
418 let Inst{6} = 0; // S bit
420 let Inst{20} = 1; // L bit
421 let Inst{21} = 0; // W bit
422 let Inst{24} = 1; // P bit
424 class AI3ldsh<dag oops, dag iops, Format f, string opc,
425 string asm, list<dag> pattern>
426 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
429 let Inst{5} = 1; // H bit
430 let Inst{6} = 1; // S bit
432 let Inst{20} = 1; // L bit
433 let Inst{21} = 0; // W bit
434 let Inst{24} = 1; // P bit
436 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
438 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
441 let Inst{5} = 1; // H bit
442 let Inst{6} = 1; // S bit
444 let Inst{20} = 1; // L bit
445 let Inst{21} = 0; // W bit
446 let Inst{24} = 1; // P bit
448 class AI3ldsb<dag oops, dag iops, Format f, string opc,
449 string asm, list<dag> pattern>
450 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
453 let Inst{5} = 0; // H bit
454 let Inst{6} = 1; // S bit
456 let Inst{20} = 1; // L bit
457 let Inst{21} = 0; // W bit
458 let Inst{24} = 1; // P bit
460 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
462 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
465 let Inst{5} = 0; // H bit
466 let Inst{6} = 1; // S bit
468 let Inst{20} = 1; // L bit
469 let Inst{21} = 0; // W bit
470 let Inst{24} = 1; // P bit
472 class AI3ldd<dag oops, dag iops, Format f, string opc,
473 string asm, list<dag> pattern>
474 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
477 let Inst{5} = 0; // H bit
478 let Inst{6} = 1; // S bit
480 let Inst{20} = 0; // L bit
481 let Inst{21} = 0; // W bit
482 let Inst{24} = 1; // P bit
486 class AI3sth<dag oops, dag iops, Format f, string opc,
487 string asm, list<dag> pattern>
488 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
491 let Inst{5} = 1; // H bit
492 let Inst{6} = 0; // S bit
494 let Inst{20} = 0; // L bit
495 let Inst{21} = 0; // W bit
496 let Inst{24} = 1; // P bit
498 class AXI3sth<dag oops, dag iops, Format f, string asm,
500 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
503 let Inst{5} = 1; // H bit
504 let Inst{6} = 0; // S bit
506 let Inst{20} = 0; // L bit
507 let Inst{21} = 0; // W bit
508 let Inst{24} = 1; // P bit
510 class AI3std<dag oops, dag iops, Format f, string opc,
511 string asm, list<dag> pattern>
512 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
515 let Inst{5} = 1; // H bit
516 let Inst{6} = 1; // S bit
518 let Inst{20} = 0; // L bit
519 let Inst{21} = 0; // W bit
520 let Inst{24} = 1; // P bit
524 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
525 string asm, string cstr, list<dag> pattern>
526 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
527 asm, cstr, pattern> {
529 let Inst{5} = 1; // H bit
530 let Inst{6} = 0; // S bit
532 let Inst{20} = 1; // L bit
533 let Inst{21} = 1; // W bit
534 let Inst{24} = 1; // P bit
536 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
537 string asm, string cstr, list<dag> pattern>
538 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
539 asm, cstr, pattern> {
541 let Inst{5} = 1; // H bit
542 let Inst{6} = 1; // S bit
544 let Inst{20} = 1; // L bit
545 let Inst{21} = 1; // W bit
546 let Inst{24} = 1; // P bit
548 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
549 string asm, string cstr, list<dag> pattern>
550 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
551 asm, cstr, pattern> {
553 let Inst{5} = 0; // H bit
554 let Inst{6} = 1; // S bit
556 let Inst{20} = 1; // L bit
557 let Inst{21} = 1; // W bit
558 let Inst{24} = 1; // P bit
561 // Pre-indexed stores
562 class AI3sthpr<dag oops, dag iops, Format f, string opc,
563 string asm, string cstr, list<dag> pattern>
564 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
565 asm, cstr, pattern> {
567 let Inst{5} = 1; // H bit
568 let Inst{6} = 0; // S bit
570 let Inst{20} = 0; // L bit
571 let Inst{21} = 1; // W bit
572 let Inst{24} = 1; // P bit
575 // Post-indexed loads
576 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
577 string asm, string cstr, list<dag> pattern>
578 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
581 let Inst{5} = 1; // H bit
582 let Inst{6} = 0; // S bit
584 let Inst{20} = 1; // L bit
585 let Inst{21} = 1; // W bit
586 let Inst{24} = 0; // P bit
588 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
589 string asm, string cstr, list<dag> pattern>
590 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
593 let Inst{5} = 1; // H bit
594 let Inst{6} = 1; // S bit
596 let Inst{20} = 1; // L bit
597 let Inst{21} = 1; // W bit
598 let Inst{24} = 0; // P bit
600 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
601 string asm, string cstr, list<dag> pattern>
602 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
605 let Inst{5} = 0; // H bit
606 let Inst{6} = 1; // S bit
608 let Inst{20} = 1; // L bit
609 let Inst{21} = 1; // W bit
610 let Inst{24} = 0; // P bit
613 // Post-indexed stores
614 class AI3sthpo<dag oops, dag iops, Format f, string opc,
615 string asm, string cstr, list<dag> pattern>
616 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
619 let Inst{5} = 1; // H bit
620 let Inst{6} = 0; // S bit
622 let Inst{20} = 0; // L bit
623 let Inst{21} = 1; // W bit
624 let Inst{24} = 0; // P bit
628 // addrmode4 instructions
629 class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
630 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
632 let Inst{20} = 1; // L bit
633 let Inst{22} = 0; // S bit
634 let Inst{27-25} = 0b100;
636 class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
637 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
639 let Inst{20} = 0; // L bit
640 let Inst{22} = 0; // S bit
641 let Inst{27-25} = 0b100;
644 // Unsigned multiply, multiply-accumulate instructions.
645 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
646 string asm, list<dag> pattern>
647 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
649 let Inst{7-4} = 0b1001;
650 let Inst{20} = 0; // S bit
651 let Inst{27-21} = opcod;
653 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
654 string asm, list<dag> pattern>
655 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
657 let Inst{7-4} = 0b1001;
658 let Inst{27-21} = opcod;
661 // Most significant word multiply
662 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
663 string asm, list<dag> pattern>
664 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
666 let Inst{7-4} = 0b1001;
668 let Inst{27-21} = opcod;
671 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
672 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
673 string asm, list<dag> pattern>
674 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
679 let Inst{27-21} = opcod;
682 //===----------------------------------------------------------------------===//
684 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
685 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
686 list<Predicate> Predicates = [IsARM];
688 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
689 list<Predicate> Predicates = [IsARM, HasV5TE];
691 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
692 list<Predicate> Predicates = [IsARM, HasV6];
695 //===----------------------------------------------------------------------===//
697 // Thumb Instruction Format Definitions.
701 // TI - Thumb instruction.
703 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
704 string asm, string cstr, list<dag> pattern>
705 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
706 let OutOperandList = outs;
707 let InOperandList = ins;
709 let Pattern = pattern;
710 list<Predicate> Predicates = [IsThumb];
713 class TI<dag outs, dag ins, string asm, list<dag> pattern>
714 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
715 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
716 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
717 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
718 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
719 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
720 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
721 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
722 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
724 // Two-address instructions
725 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
726 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
728 // BL, BLX(1) are translated by assembler into two instructions
729 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
730 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
732 // BR_JT instructions
733 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
734 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
737 //===----------------------------------------------------------------------===//
740 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
741 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
742 list<Predicate> Predicates = [IsThumb];
745 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
746 list<Predicate> Predicates = [IsThumb, HasV5T];