1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : AsmOperandClass {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let ParserMatchClass = MSRMaskOperand;
195 // Shift Right Immediate - A shift right immediate is encoded differently from
196 // other shift immediates. The imm6 field is encoded like so:
199 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
200 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
201 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
202 // 64 64 - <imm> is encoded in imm6<5:0>
203 def shr_imm8 : Operand<i32> {
204 let EncoderMethod = "getShiftRight8Imm";
205 let DecoderMethod = "DecodeShiftRight8Imm";
207 def shr_imm16 : Operand<i32> {
208 let EncoderMethod = "getShiftRight16Imm";
209 let DecoderMethod = "DecodeShiftRight16Imm";
211 def shr_imm32 : Operand<i32> {
212 let EncoderMethod = "getShiftRight32Imm";
213 let DecoderMethod = "DecodeShiftRight32Imm";
215 def shr_imm64 : Operand<i32> {
216 let EncoderMethod = "getShiftRight64Imm";
217 let DecoderMethod = "DecodeShiftRight64Imm";
220 //===----------------------------------------------------------------------===//
221 // ARM Instruction templates.
224 class InstTemplate<AddrMode am, int sz, IndexMode im,
225 Format f, Domain d, string cstr, InstrItinClass itin>
227 let Namespace = "ARM";
232 bits<2> IndexModeBits = IM.Value;
234 bits<6> Form = F.Value;
236 bit isUnaryDataProc = 0;
237 bit canXformTo16Bit = 0;
239 // If this is a pseudo instruction, mark it isCodeGenOnly.
240 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
242 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
243 let TSFlags{4-0} = AM.Value;
244 let TSFlags{6-5} = IndexModeBits;
245 let TSFlags{12-7} = Form;
246 let TSFlags{13} = isUnaryDataProc;
247 let TSFlags{14} = canXformTo16Bit;
248 let TSFlags{17-15} = D.Value;
250 let Constraints = cstr;
251 let Itinerary = itin;
258 class InstARM<AddrMode am, int sz, IndexMode im,
259 Format f, Domain d, string cstr, InstrItinClass itin>
260 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
261 let DecoderNamespace = "ARM";
264 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
265 // on by adding flavors to specific instructions.
266 class InstThumb<AddrMode am, int sz, IndexMode im,
267 Format f, Domain d, string cstr, InstrItinClass itin>
268 : InstTemplate<am, sz, im, f, d, cstr, itin> {
269 let DecoderNamespace = "Thumb";
272 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
273 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
274 GenericDomain, "", itin> {
275 let OutOperandList = oops;
276 let InOperandList = iops;
277 let Pattern = pattern;
278 let isCodeGenOnly = 1;
282 // PseudoInst that's ARM-mode only.
283 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
285 : PseudoInst<oops, iops, itin, pattern> {
287 list<Predicate> Predicates = [IsARM];
290 // PseudoInst that's Thumb-mode only.
291 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
293 : PseudoInst<oops, iops, itin, pattern> {
295 list<Predicate> Predicates = [IsThumb];
298 // PseudoInst that's Thumb2-mode only.
299 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
301 : PseudoInst<oops, iops, itin, pattern> {
303 list<Predicate> Predicates = [IsThumb2];
306 class ARMPseudoExpand<dag oops, dag iops, int sz,
307 InstrItinClass itin, list<dag> pattern,
309 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
310 PseudoInstExpansion<Result>;
312 class tPseudoExpand<dag oops, dag iops, int sz,
313 InstrItinClass itin, list<dag> pattern,
315 : tPseudoInst<oops, iops, sz, itin, pattern>,
316 PseudoInstExpansion<Result>;
318 class t2PseudoExpand<dag oops, dag iops, int sz,
319 InstrItinClass itin, list<dag> pattern,
321 : t2PseudoInst<oops, iops, sz, itin, pattern>,
322 PseudoInstExpansion<Result>;
324 // Almost all ARM instructions are predicable.
325 class I<dag oops, dag iops, AddrMode am, int sz,
326 IndexMode im, Format f, InstrItinClass itin,
327 string opc, string asm, string cstr,
329 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
332 let OutOperandList = oops;
333 let InOperandList = !con(iops, (ins pred:$p));
334 let AsmString = !strconcat(opc, "${p}", asm);
335 let Pattern = pattern;
336 list<Predicate> Predicates = [IsARM];
339 // A few are not predicable
340 class InoP<dag oops, dag iops, AddrMode am, int sz,
341 IndexMode im, Format f, InstrItinClass itin,
342 string opc, string asm, string cstr,
344 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
345 let OutOperandList = oops;
346 let InOperandList = iops;
347 let AsmString = !strconcat(opc, asm);
348 let Pattern = pattern;
349 let isPredicable = 0;
350 list<Predicate> Predicates = [IsARM];
353 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
354 // operand since by default it's a zero register. It will become an implicit def
355 // once it's "flipped".
356 class sI<dag oops, dag iops, AddrMode am, int sz,
357 IndexMode im, Format f, InstrItinClass itin,
358 string opc, string asm, string cstr,
360 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
361 bits<4> p; // Predicate operand
362 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
366 let OutOperandList = oops;
367 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
368 let AsmString = !strconcat(opc, "${s}${p}", asm);
369 let Pattern = pattern;
370 list<Predicate> Predicates = [IsARM];
374 class XI<dag oops, dag iops, AddrMode am, int sz,
375 IndexMode im, Format f, InstrItinClass itin,
376 string asm, string cstr, list<dag> pattern>
377 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
378 let OutOperandList = oops;
379 let InOperandList = iops;
381 let Pattern = pattern;
382 list<Predicate> Predicates = [IsARM];
385 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
386 string opc, string asm, list<dag> pattern>
387 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
388 opc, asm, "", pattern>;
389 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
390 string opc, string asm, list<dag> pattern>
391 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
392 opc, asm, "", pattern>;
393 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
394 string asm, list<dag> pattern>
395 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
397 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
398 string opc, string asm, list<dag> pattern>
399 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
400 opc, asm, "", pattern>;
402 // Ctrl flow instructions
403 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
404 string opc, string asm, list<dag> pattern>
405 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
406 opc, asm, "", pattern> {
407 let Inst{27-24} = opcod;
409 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
410 string asm, list<dag> pattern>
411 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
413 let Inst{27-24} = opcod;
416 // BR_JT instructions
417 class JTI<dag oops, dag iops, InstrItinClass itin,
418 string asm, list<dag> pattern>
419 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
422 // Atomic load/store instructions
423 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
424 string opc, string asm, list<dag> pattern>
425 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
426 opc, asm, "", pattern> {
429 let Inst{27-23} = 0b00011;
430 let Inst{22-21} = opcod;
432 let Inst{19-16} = addr;
433 let Inst{15-12} = Rt;
434 let Inst{11-0} = 0b111110011111;
436 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
437 string opc, string asm, list<dag> pattern>
438 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
439 opc, asm, "", pattern> {
443 let Inst{27-23} = 0b00011;
444 let Inst{22-21} = opcod;
446 let Inst{19-16} = addr;
447 let Inst{15-12} = Rd;
448 let Inst{11-4} = 0b11111001;
451 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
452 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
456 let Inst{27-23} = 0b00010;
458 let Inst{21-20} = 0b00;
459 let Inst{19-16} = addr;
460 let Inst{15-12} = Rt;
461 let Inst{11-4} = 0b00001001;
465 // addrmode1 instructions
466 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
467 string opc, string asm, list<dag> pattern>
468 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
469 opc, asm, "", pattern> {
470 let Inst{24-21} = opcod;
471 let Inst{27-26} = 0b00;
473 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
474 string opc, string asm, list<dag> pattern>
475 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
476 opc, asm, "", pattern> {
477 let Inst{24-21} = opcod;
478 let Inst{27-26} = 0b00;
480 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
481 string asm, list<dag> pattern>
482 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
484 let Inst{24-21} = opcod;
485 let Inst{27-26} = 0b00;
490 // LDR/LDRB/STR/STRB/...
491 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
492 Format f, InstrItinClass itin, string opc, string asm,
494 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
496 let Inst{27-25} = op;
497 let Inst{24} = 1; // 24 == P
499 let Inst{22} = isByte;
500 let Inst{21} = 0; // 21 == W
503 // Indexed load/stores
504 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
505 IndexMode im, Format f, InstrItinClass itin, string opc,
506 string asm, string cstr, list<dag> pattern>
507 : I<oops, iops, AddrMode2, 4, im, f, itin,
508 opc, asm, cstr, pattern> {
510 let Inst{27-26} = 0b01;
511 let Inst{24} = isPre; // P bit
512 let Inst{22} = isByte; // B bit
513 let Inst{21} = isPre; // W bit
514 let Inst{20} = isLd; // L bit
515 let Inst{15-12} = Rt;
517 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
518 IndexMode im, Format f, InstrItinClass itin, string opc,
519 string asm, string cstr, list<dag> pattern>
520 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
522 // AM2 store w/ two operands: (GPR, am2offset)
528 let Inst{23} = offset{12};
529 let Inst{19-16} = Rn;
530 let Inst{11-5} = offset{11-5};
532 let Inst{3-0} = offset{3-0};
535 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
536 IndexMode im, Format f, InstrItinClass itin, string opc,
537 string asm, string cstr, list<dag> pattern>
538 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
540 // AM2 store w/ two operands: (GPR, am2offset)
546 let Inst{23} = offset{12};
547 let Inst{19-16} = Rn;
548 let Inst{11-0} = offset{11-0};
552 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
553 // but for now use this class for STRT and STRBT.
554 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
555 IndexMode im, Format f, InstrItinClass itin, string opc,
556 string asm, string cstr, list<dag> pattern>
557 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
559 // AM2 store w/ two operands: (GPR, am2offset)
561 // {13} 1 == Rm, 0 == imm12
565 let Inst{25} = addr{13};
566 let Inst{23} = addr{12};
567 let Inst{19-16} = addr{17-14};
568 let Inst{11-0} = addr{11-0};
571 // addrmode3 instructions
572 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
573 InstrItinClass itin, string opc, string asm, list<dag> pattern>
574 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
575 opc, asm, "", pattern> {
578 let Inst{27-25} = 0b000;
579 let Inst{24} = 1; // P bit
580 let Inst{23} = addr{8}; // U bit
581 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
582 let Inst{21} = 0; // W bit
583 let Inst{20} = op20; // L bit
584 let Inst{19-16} = addr{12-9}; // Rn
585 let Inst{15-12} = Rt; // Rt
586 let Inst{11-8} = addr{7-4}; // imm7_4/zero
588 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
590 let DecoderMethod = "DecodeAddrMode3Instruction";
593 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
594 IndexMode im, Format f, InstrItinClass itin, string opc,
595 string asm, string cstr, list<dag> pattern>
596 : I<oops, iops, AddrMode3, 4, im, f, itin,
597 opc, asm, cstr, pattern> {
599 let Inst{27-25} = 0b000;
600 let Inst{24} = isPre; // P bit
601 let Inst{21} = isPre; // W bit
602 let Inst{20} = op20; // L bit
603 let Inst{15-12} = Rt; // Rt
607 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
608 // but for now use this class for LDRSBT, LDRHT, LDSHT.
609 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
610 IndexMode im, Format f, InstrItinClass itin, string opc,
611 string asm, string cstr, list<dag> pattern>
612 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
613 // {13} 1 == imm8, 0 == Rm
620 let Inst{27-25} = 0b000;
621 let Inst{24} = 0; // P bit
623 let Inst{20} = isLoad; // L bit
624 let Inst{19-16} = addr; // Rn
625 let Inst{15-12} = Rt; // Rt
629 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
630 IndexMode im, Format f, InstrItinClass itin, string opc,
631 string asm, string cstr, list<dag> pattern>
632 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
634 // AM3 store w/ two operands: (GPR, am3offset)
638 let Inst{27-25} = 0b000;
639 let Inst{23} = offset{8};
640 let Inst{22} = offset{9};
641 let Inst{19-16} = Rn;
642 let Inst{15-12} = Rt; // Rt
643 let Inst{11-8} = offset{7-4}; // imm7_4/zero
645 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
649 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
650 string opc, string asm, list<dag> pattern>
651 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
652 opc, asm, "", pattern> {
655 let Inst{27-25} = 0b000;
656 let Inst{24} = 1; // P bit
657 let Inst{23} = addr{8}; // U bit
658 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
659 let Inst{21} = 0; // W bit
660 let Inst{20} = 0; // L bit
661 let Inst{19-16} = addr{12-9}; // Rn
662 let Inst{15-12} = Rt; // Rt
663 let Inst{11-8} = addr{7-4}; // imm7_4/zero
665 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
668 // Pre-indexed stores
669 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
670 string opc, string asm, string cstr, list<dag> pattern>
671 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
672 opc, asm, cstr, pattern> {
674 let Inst{5} = 1; // H bit
675 let Inst{6} = 0; // S bit
677 let Inst{20} = 0; // L bit
678 let Inst{21} = 1; // W bit
679 let Inst{24} = 1; // P bit
680 let Inst{27-25} = 0b000;
682 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
683 string opc, string asm, string cstr, list<dag> pattern>
684 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
685 opc, asm, cstr, pattern> {
687 let Inst{5} = 1; // H bit
688 let Inst{6} = 1; // S bit
690 let Inst{20} = 0; // L bit
691 let Inst{21} = 1; // W bit
692 let Inst{24} = 1; // P bit
693 let Inst{27-25} = 0b000;
696 // Post-indexed stores
697 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
698 string opc, string asm, string cstr, list<dag> pattern>
699 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
700 opc, asm, cstr, pattern> {
702 let Inst{5} = 1; // H bit
703 let Inst{6} = 1; // S bit
705 let Inst{20} = 0; // L bit
706 let Inst{21} = 0; // W bit
707 let Inst{24} = 0; // P bit
708 let Inst{27-25} = 0b000;
711 // addrmode4 instructions
712 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
713 string asm, string cstr, list<dag> pattern>
714 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
719 let Inst{27-25} = 0b100;
720 let Inst{22} = 0; // S bit
721 let Inst{19-16} = Rn;
722 let Inst{15-0} = regs;
725 // Unsigned multiply, multiply-accumulate instructions.
726 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
727 string opc, string asm, list<dag> pattern>
728 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
729 opc, asm, "", pattern> {
730 let Inst{7-4} = 0b1001;
731 let Inst{20} = 0; // S bit
732 let Inst{27-21} = opcod;
734 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
735 string opc, string asm, list<dag> pattern>
736 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
737 opc, asm, "", pattern> {
738 let Inst{7-4} = 0b1001;
739 let Inst{27-21} = opcod;
742 // Most significant word multiply
743 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
744 InstrItinClass itin, string opc, string asm, list<dag> pattern>
745 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
746 opc, asm, "", pattern> {
750 let Inst{7-4} = opc7_4;
752 let Inst{27-21} = opcod;
753 let Inst{19-16} = Rd;
757 // MSW multiple w/ Ra operand
758 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
759 InstrItinClass itin, string opc, string asm, list<dag> pattern>
760 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
762 let Inst{15-12} = Ra;
765 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
766 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
767 InstrItinClass itin, string opc, string asm, list<dag> pattern>
768 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
769 opc, asm, "", pattern> {
775 let Inst{27-21} = opcod;
776 let Inst{6-5} = bit6_5;
780 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
781 InstrItinClass itin, string opc, string asm, list<dag> pattern>
782 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
784 let Inst{19-16} = Rd;
787 // AMulxyI with Ra operand
788 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
789 InstrItinClass itin, string opc, string asm, list<dag> pattern>
790 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
792 let Inst{15-12} = Ra;
795 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
796 InstrItinClass itin, string opc, string asm, list<dag> pattern>
797 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
800 let Inst{19-16} = RdHi;
801 let Inst{15-12} = RdLo;
804 // Extend instructions.
805 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
806 string opc, string asm, list<dag> pattern>
807 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
808 opc, asm, "", pattern> {
809 // All AExtI instructions have Rd and Rm register operands.
812 let Inst{15-12} = Rd;
814 let Inst{7-4} = 0b0111;
815 let Inst{9-8} = 0b00;
816 let Inst{27-20} = opcod;
819 // Misc Arithmetic instructions.
820 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
821 InstrItinClass itin, string opc, string asm, list<dag> pattern>
822 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
823 opc, asm, "", pattern> {
826 let Inst{27-20} = opcod;
827 let Inst{19-16} = 0b1111;
828 let Inst{15-12} = Rd;
829 let Inst{11-8} = 0b1111;
830 let Inst{7-4} = opc7_4;
835 def PKHLSLAsmOperand : AsmOperandClass {
836 let Name = "PKHLSLImm";
837 let ParserMethod = "parsePKHLSLImm";
839 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
840 let PrintMethod = "printPKHLSLShiftImm";
841 let ParserMatchClass = PKHLSLAsmOperand;
843 def PKHASRAsmOperand : AsmOperandClass {
844 let Name = "PKHASRImm";
845 let ParserMethod = "parsePKHASRImm";
847 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
848 let PrintMethod = "printPKHASRShiftImm";
849 let ParserMatchClass = PKHASRAsmOperand;
852 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
853 string opc, string asm, list<dag> pattern>
854 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
855 opc, asm, "", pattern> {
860 let Inst{27-20} = opcod;
861 let Inst{19-16} = Rn;
862 let Inst{15-12} = Rd;
865 let Inst{5-4} = 0b01;
869 //===----------------------------------------------------------------------===//
871 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
872 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
873 list<Predicate> Predicates = [IsARM];
875 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
876 list<Predicate> Predicates = [IsARM, HasV5T];
878 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
879 list<Predicate> Predicates = [IsARM, HasV5TE];
881 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
882 list<Predicate> Predicates = [IsARM, HasV6];
885 //===----------------------------------------------------------------------===//
886 // Thumb Instruction Format Definitions.
889 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
890 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
891 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
892 let OutOperandList = oops;
893 let InOperandList = iops;
895 let Pattern = pattern;
896 list<Predicate> Predicates = [IsThumb];
899 // TI - Thumb instruction.
900 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
901 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
903 // Two-address instructions
904 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
906 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
909 // tBL, tBX 32-bit instructions
910 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
911 dag oops, dag iops, InstrItinClass itin, string asm,
913 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
915 let Inst{31-27} = opcod1;
916 let Inst{15-14} = opcod2;
917 let Inst{12} = opcod3;
920 // BR_JT instructions
921 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
923 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
926 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
927 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
928 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
929 let OutOperandList = oops;
930 let InOperandList = iops;
932 let Pattern = pattern;
933 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
936 class T1I<dag oops, dag iops, InstrItinClass itin,
937 string asm, list<dag> pattern>
938 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
939 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
940 string asm, list<dag> pattern>
941 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
943 // Two-address instructions
944 class T1It<dag oops, dag iops, InstrItinClass itin,
945 string asm, string cstr, list<dag> pattern>
946 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
949 // Thumb1 instruction that can either be predicated or set CPSR.
950 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
952 string opc, string asm, string cstr, list<dag> pattern>
953 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
954 let OutOperandList = !con(oops, (outs s_cc_out:$s));
955 let InOperandList = !con(iops, (ins pred:$p));
956 let AsmString = !strconcat(opc, "${s}${p}", asm);
957 let Pattern = pattern;
958 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
961 class T1sI<dag oops, dag iops, InstrItinClass itin,
962 string opc, string asm, list<dag> pattern>
963 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
965 // Two-address instructions
966 class T1sIt<dag oops, dag iops, InstrItinClass itin,
967 string opc, string asm, list<dag> pattern>
968 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
969 "$Rn = $Rdn", pattern>;
971 // Thumb1 instruction that can be predicated.
972 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
974 string opc, string asm, string cstr, list<dag> pattern>
975 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
976 let OutOperandList = oops;
977 let InOperandList = !con(iops, (ins pred:$p));
978 let AsmString = !strconcat(opc, "${p}", asm);
979 let Pattern = pattern;
980 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
983 class T1pI<dag oops, dag iops, InstrItinClass itin,
984 string opc, string asm, list<dag> pattern>
985 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
987 // Two-address instructions
988 class T1pIt<dag oops, dag iops, InstrItinClass itin,
989 string opc, string asm, list<dag> pattern>
990 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
991 "$Rn = $Rdn", pattern>;
993 class T1pIs<dag oops, dag iops,
994 InstrItinClass itin, string opc, string asm, list<dag> pattern>
995 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
997 class Encoding16 : Encoding {
998 let Inst{31-16} = 0x0000;
1001 // A6.2 16-bit Thumb instruction encoding
1002 class T1Encoding<bits<6> opcode> : Encoding16 {
1003 let Inst{15-10} = opcode;
1006 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1007 class T1General<bits<5> opcode> : Encoding16 {
1008 let Inst{15-14} = 0b00;
1009 let Inst{13-9} = opcode;
1012 // A6.2.2 Data-processing encoding.
1013 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1014 let Inst{15-10} = 0b010000;
1015 let Inst{9-6} = opcode;
1018 // A6.2.3 Special data instructions and branch and exchange encoding.
1019 class T1Special<bits<4> opcode> : Encoding16 {
1020 let Inst{15-10} = 0b010001;
1021 let Inst{9-6} = opcode;
1024 // A6.2.4 Load/store single data item encoding.
1025 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1026 let Inst{15-12} = opA;
1027 let Inst{11-9} = opB;
1029 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1031 class T1BranchCond<bits<4> opcode> : Encoding16 {
1032 let Inst{15-12} = opcode;
1035 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1036 // following bits are used for "opA" (see A6.2.4):
1038 // 0b0110 => Immediate, 4 bytes
1039 // 0b1000 => Immediate, 2 bytes
1040 // 0b0111 => Immediate, 1 byte
1041 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1042 InstrItinClass itin, string opc, string asm,
1044 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1045 T1LoadStore<0b0101, opcode> {
1048 let Inst{8-6} = addr{5-3}; // Rm
1049 let Inst{5-3} = addr{2-0}; // Rn
1052 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1053 InstrItinClass itin, string opc, string asm,
1055 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1056 T1LoadStore<opA, {opB,?,?}> {
1059 let Inst{10-6} = addr{7-3}; // imm5
1060 let Inst{5-3} = addr{2-0}; // Rn
1064 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1065 class T1Misc<bits<7> opcode> : Encoding16 {
1066 let Inst{15-12} = 0b1011;
1067 let Inst{11-5} = opcode;
1070 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1071 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1072 InstrItinClass itin,
1073 string opc, string asm, string cstr, list<dag> pattern>
1074 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1075 let OutOperandList = oops;
1076 let InOperandList = !con(iops, (ins pred:$p));
1077 let AsmString = !strconcat(opc, "${p}", asm);
1078 let Pattern = pattern;
1079 list<Predicate> Predicates = [IsThumb2];
1080 let DecoderNamespace = "Thumb2";
1083 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1084 // input operand since by default it's a zero register. It will become an
1085 // implicit def once it's "flipped".
1087 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1089 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1090 InstrItinClass itin,
1091 string opc, string asm, string cstr, list<dag> pattern>
1092 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1093 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1096 let OutOperandList = oops;
1097 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1098 let AsmString = !strconcat(opc, "${s}${p}", asm);
1099 let Pattern = pattern;
1100 list<Predicate> Predicates = [IsThumb2];
1101 let DecoderNamespace = "Thumb2";
1105 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1106 InstrItinClass itin,
1107 string asm, string cstr, list<dag> pattern>
1108 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1109 let OutOperandList = oops;
1110 let InOperandList = iops;
1111 let AsmString = asm;
1112 let Pattern = pattern;
1113 list<Predicate> Predicates = [IsThumb2];
1114 let DecoderNamespace = "Thumb2";
1117 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1118 InstrItinClass itin,
1119 string asm, string cstr, list<dag> pattern>
1120 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1121 let OutOperandList = oops;
1122 let InOperandList = iops;
1123 let AsmString = asm;
1124 let Pattern = pattern;
1125 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1126 let DecoderNamespace = "Thumb";
1129 class T2I<dag oops, dag iops, InstrItinClass itin,
1130 string opc, string asm, list<dag> pattern>
1131 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1132 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1133 string opc, string asm, list<dag> pattern>
1134 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1135 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1136 string opc, string asm, list<dag> pattern>
1137 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1138 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1139 string opc, string asm, list<dag> pattern>
1140 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1141 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1142 string opc, string asm, list<dag> pattern>
1143 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1144 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1145 string opc, string asm, list<dag> pattern>
1146 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "",
1151 let Inst{31-25} = 0b1110100;
1153 let Inst{23} = addr{8};
1156 let Inst{20} = isLoad;
1157 let Inst{19-16} = addr{12-9};
1158 let Inst{15-12} = Rt{3-0};
1159 let Inst{11-8} = Rt2{3-0};
1160 let Inst{7-0} = addr{7-0};
1163 class T2Ii8s4Tied<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1164 string opc, string asm, list<dag> pattern>
1165 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "$base = $wb",
1171 let Inst{31-25} = 0b1110100;
1173 let Inst{23} = imm{8};
1176 let Inst{20} = isLoad;
1177 let Inst{19-16} = base{3-0};
1178 let Inst{15-12} = Rt{3-0};
1179 let Inst{11-8} = Rt2{3-0};
1180 let Inst{7-0} = imm{7-0};
1184 class T2sI<dag oops, dag iops, InstrItinClass itin,
1185 string opc, string asm, list<dag> pattern>
1186 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1188 class T2XI<dag oops, dag iops, InstrItinClass itin,
1189 string asm, list<dag> pattern>
1190 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1191 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1192 string asm, list<dag> pattern>
1193 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1195 // Move to/from coprocessor instructions
1196 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1197 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1198 let Inst{31-28} = opc;
1201 // Two-address instructions
1202 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1203 string asm, string cstr, list<dag> pattern>
1204 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1206 // T2Iidxldst - Thumb2 indexed load / store instructions.
1207 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1209 AddrMode am, IndexMode im, InstrItinClass itin,
1210 string opc, string asm, string cstr, list<dag> pattern>
1211 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1212 let OutOperandList = oops;
1213 let InOperandList = !con(iops, (ins pred:$p));
1214 let AsmString = !strconcat(opc, "${p}", asm);
1215 let Pattern = pattern;
1216 list<Predicate> Predicates = [IsThumb2];
1217 let DecoderNamespace = "Thumb2";
1218 let Inst{31-27} = 0b11111;
1219 let Inst{26-25} = 0b00;
1220 let Inst{24} = signed;
1222 let Inst{22-21} = opcod;
1223 let Inst{20} = load;
1225 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1226 let Inst{10} = pre; // The P bit.
1227 let Inst{8} = 1; // The W bit.
1230 let Inst{7-0} = addr{7-0};
1231 let Inst{9} = addr{8}; // Sign bit
1235 let Inst{15-12} = Rt{3-0};
1236 let Inst{19-16} = Rn{3-0};
1239 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1240 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1241 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1244 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1245 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1246 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1249 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1250 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1251 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1254 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1255 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1256 list<Predicate> Predicates = [IsThumb2];
1259 //===----------------------------------------------------------------------===//
1261 //===----------------------------------------------------------------------===//
1262 // ARM VFP Instruction templates.
1265 // Almost all VFP instructions are predicable.
1266 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1267 IndexMode im, Format f, InstrItinClass itin,
1268 string opc, string asm, string cstr, list<dag> pattern>
1269 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1271 let Inst{31-28} = p;
1272 let OutOperandList = oops;
1273 let InOperandList = !con(iops, (ins pred:$p));
1274 let AsmString = !strconcat(opc, "${p}", asm);
1275 let Pattern = pattern;
1276 let PostEncoderMethod = "VFPThumb2PostEncoder";
1277 let DecoderNamespace = "VFP";
1278 list<Predicate> Predicates = [HasVFP2];
1282 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1283 IndexMode im, Format f, InstrItinClass itin,
1284 string asm, string cstr, list<dag> pattern>
1285 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1287 let Inst{31-28} = p;
1288 let OutOperandList = oops;
1289 let InOperandList = iops;
1290 let AsmString = asm;
1291 let Pattern = pattern;
1292 let PostEncoderMethod = "VFPThumb2PostEncoder";
1293 let DecoderNamespace = "VFP";
1294 list<Predicate> Predicates = [HasVFP2];
1297 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1298 string opc, string asm, list<dag> pattern>
1299 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1300 opc, asm, "", pattern> {
1301 let PostEncoderMethod = "VFPThumb2PostEncoder";
1304 // ARM VFP addrmode5 loads and stores
1305 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1306 InstrItinClass itin,
1307 string opc, string asm, list<dag> pattern>
1308 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1309 VFPLdStFrm, itin, opc, asm, "", pattern> {
1310 // Instruction operands.
1314 // Encode instruction operands.
1315 let Inst{23} = addr{8}; // U (add = (U == '1'))
1316 let Inst{22} = Dd{4};
1317 let Inst{19-16} = addr{12-9}; // Rn
1318 let Inst{15-12} = Dd{3-0};
1319 let Inst{7-0} = addr{7-0}; // imm8
1321 // TODO: Mark the instructions with the appropriate subtarget info.
1322 let Inst{27-24} = opcod1;
1323 let Inst{21-20} = opcod2;
1324 let Inst{11-9} = 0b101;
1325 let Inst{8} = 1; // Double precision
1327 // Loads & stores operate on both NEON and VFP pipelines.
1328 let D = VFPNeonDomain;
1331 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1332 InstrItinClass itin,
1333 string opc, string asm, list<dag> pattern>
1334 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1335 VFPLdStFrm, itin, opc, asm, "", pattern> {
1336 // Instruction operands.
1340 // Encode instruction operands.
1341 let Inst{23} = addr{8}; // U (add = (U == '1'))
1342 let Inst{22} = Sd{0};
1343 let Inst{19-16} = addr{12-9}; // Rn
1344 let Inst{15-12} = Sd{4-1};
1345 let Inst{7-0} = addr{7-0}; // imm8
1347 // TODO: Mark the instructions with the appropriate subtarget info.
1348 let Inst{27-24} = opcod1;
1349 let Inst{21-20} = opcod2;
1350 let Inst{11-9} = 0b101;
1351 let Inst{8} = 0; // Single precision
1353 // Loads & stores operate on both NEON and VFP pipelines.
1354 let D = VFPNeonDomain;
1357 // VFP Load / store multiple pseudo instructions.
1358 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1360 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1362 let OutOperandList = oops;
1363 let InOperandList = !con(iops, (ins pred:$p));
1364 let Pattern = pattern;
1365 list<Predicate> Predicates = [HasVFP2];
1368 // Load / store multiple
1369 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1370 string asm, string cstr, list<dag> pattern>
1371 : VFPXI<oops, iops, AddrMode4, 4, im,
1372 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1373 // Instruction operands.
1377 // Encode instruction operands.
1378 let Inst{19-16} = Rn;
1379 let Inst{22} = regs{12};
1380 let Inst{15-12} = regs{11-8};
1381 let Inst{7-0} = regs{7-0};
1383 // TODO: Mark the instructions with the appropriate subtarget info.
1384 let Inst{27-25} = 0b110;
1385 let Inst{11-9} = 0b101;
1386 let Inst{8} = 1; // Double precision
1389 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1390 string asm, string cstr, list<dag> pattern>
1391 : VFPXI<oops, iops, AddrMode4, 4, im,
1392 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1393 // Instruction operands.
1397 // Encode instruction operands.
1398 let Inst{19-16} = Rn;
1399 let Inst{22} = regs{8};
1400 let Inst{15-12} = regs{12-9};
1401 let Inst{7-0} = regs{7-0};
1403 // TODO: Mark the instructions with the appropriate subtarget info.
1404 let Inst{27-25} = 0b110;
1405 let Inst{11-9} = 0b101;
1406 let Inst{8} = 0; // Single precision
1409 // Double precision, unary
1410 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1411 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1412 string asm, list<dag> pattern>
1413 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1414 // Instruction operands.
1418 // Encode instruction operands.
1419 let Inst{3-0} = Dm{3-0};
1420 let Inst{5} = Dm{4};
1421 let Inst{15-12} = Dd{3-0};
1422 let Inst{22} = Dd{4};
1424 let Inst{27-23} = opcod1;
1425 let Inst{21-20} = opcod2;
1426 let Inst{19-16} = opcod3;
1427 let Inst{11-9} = 0b101;
1428 let Inst{8} = 1; // Double precision
1429 let Inst{7-6} = opcod4;
1430 let Inst{4} = opcod5;
1433 // Double precision, binary
1434 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1435 dag iops, InstrItinClass itin, string opc, string asm,
1437 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1438 // Instruction operands.
1443 // Encode instruction operands.
1444 let Inst{3-0} = Dm{3-0};
1445 let Inst{5} = Dm{4};
1446 let Inst{19-16} = Dn{3-0};
1447 let Inst{7} = Dn{4};
1448 let Inst{15-12} = Dd{3-0};
1449 let Inst{22} = Dd{4};
1451 let Inst{27-23} = opcod1;
1452 let Inst{21-20} = opcod2;
1453 let Inst{11-9} = 0b101;
1454 let Inst{8} = 1; // Double precision
1459 // Single precision, unary
1460 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1461 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1462 string asm, list<dag> pattern>
1463 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1464 // Instruction operands.
1468 // Encode instruction operands.
1469 let Inst{3-0} = Sm{4-1};
1470 let Inst{5} = Sm{0};
1471 let Inst{15-12} = Sd{4-1};
1472 let Inst{22} = Sd{0};
1474 let Inst{27-23} = opcod1;
1475 let Inst{21-20} = opcod2;
1476 let Inst{19-16} = opcod3;
1477 let Inst{11-9} = 0b101;
1478 let Inst{8} = 0; // Single precision
1479 let Inst{7-6} = opcod4;
1480 let Inst{4} = opcod5;
1483 // Single precision unary, if no NEON. Same as ASuI except not available if
1485 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1486 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1487 string asm, list<dag> pattern>
1488 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1490 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1493 // Single precision, binary
1494 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1495 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1496 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1497 // Instruction operands.
1502 // Encode instruction operands.
1503 let Inst{3-0} = Sm{4-1};
1504 let Inst{5} = Sm{0};
1505 let Inst{19-16} = Sn{4-1};
1506 let Inst{7} = Sn{0};
1507 let Inst{15-12} = Sd{4-1};
1508 let Inst{22} = Sd{0};
1510 let Inst{27-23} = opcod1;
1511 let Inst{21-20} = opcod2;
1512 let Inst{11-9} = 0b101;
1513 let Inst{8} = 0; // Single precision
1518 // Single precision binary, if no NEON. Same as ASbI except not available if
1520 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1521 dag iops, InstrItinClass itin, string opc, string asm,
1523 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1524 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1526 // Instruction operands.
1531 // Encode instruction operands.
1532 let Inst{3-0} = Sm{4-1};
1533 let Inst{5} = Sm{0};
1534 let Inst{19-16} = Sn{4-1};
1535 let Inst{7} = Sn{0};
1536 let Inst{15-12} = Sd{4-1};
1537 let Inst{22} = Sd{0};
1540 // VFP conversion instructions
1541 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1542 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1544 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1545 let Inst{27-23} = opcod1;
1546 let Inst{21-20} = opcod2;
1547 let Inst{19-16} = opcod3;
1548 let Inst{11-8} = opcod4;
1553 // VFP conversion between floating-point and fixed-point
1554 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1555 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1557 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1558 // size (fixed-point number): sx == 0 ? 16 : 32
1559 let Inst{7} = op5; // sx
1562 // VFP conversion instructions, if no NEON
1563 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1564 dag oops, dag iops, InstrItinClass itin,
1565 string opc, string asm, list<dag> pattern>
1566 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1568 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1571 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1572 InstrItinClass itin,
1573 string opc, string asm, list<dag> pattern>
1574 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1575 let Inst{27-20} = opcod1;
1576 let Inst{11-8} = opcod2;
1580 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1581 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1582 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1584 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1585 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1586 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1588 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1589 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1590 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1592 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1593 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1594 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1596 //===----------------------------------------------------------------------===//
1598 //===----------------------------------------------------------------------===//
1599 // ARM NEON Instruction templates.
1602 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1603 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1605 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1606 let OutOperandList = oops;
1607 let InOperandList = !con(iops, (ins pred:$p));
1608 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1609 let Pattern = pattern;
1610 list<Predicate> Predicates = [HasNEON];
1611 let DecoderNamespace = "NEON";
1614 // Same as NeonI except it does not have a "data type" specifier.
1615 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1616 InstrItinClass itin, string opc, string asm, string cstr,
1618 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1619 let OutOperandList = oops;
1620 let InOperandList = !con(iops, (ins pred:$p));
1621 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1622 let Pattern = pattern;
1623 list<Predicate> Predicates = [HasNEON];
1624 let DecoderNamespace = "NEON";
1627 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1628 dag oops, dag iops, InstrItinClass itin,
1629 string opc, string dt, string asm, string cstr, list<dag> pattern>
1630 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1632 let Inst{31-24} = 0b11110100;
1633 let Inst{23} = op23;
1634 let Inst{21-20} = op21_20;
1635 let Inst{11-8} = op11_8;
1636 let Inst{7-4} = op7_4;
1638 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1644 let Inst{22} = Vd{4};
1645 let Inst{15-12} = Vd{3-0};
1646 let Inst{19-16} = Rn{3-0};
1647 let Inst{3-0} = Rm{3-0};
1650 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1651 dag oops, dag iops, InstrItinClass itin,
1652 string opc, string dt, string asm, string cstr, list<dag> pattern>
1653 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1654 dt, asm, cstr, pattern> {
1658 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1659 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1661 let OutOperandList = oops;
1662 let InOperandList = !con(iops, (ins pred:$p));
1663 list<Predicate> Predicates = [HasNEON];
1666 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1668 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1670 let OutOperandList = oops;
1671 let InOperandList = !con(iops, (ins pred:$p));
1672 let Pattern = pattern;
1673 list<Predicate> Predicates = [HasNEON];
1676 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1677 string opc, string dt, string asm, string cstr, list<dag> pattern>
1678 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1680 let Inst{31-25} = 0b1111001;
1681 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1684 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1685 string opc, string asm, string cstr, list<dag> pattern>
1686 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1688 let Inst{31-25} = 0b1111001;
1689 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1692 // NEON "one register and a modified immediate" format.
1693 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1695 dag oops, dag iops, InstrItinClass itin,
1696 string opc, string dt, string asm, string cstr,
1698 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1699 let Inst{23} = op23;
1700 let Inst{21-19} = op21_19;
1701 let Inst{11-8} = op11_8;
1707 // Instruction operands.
1711 let Inst{15-12} = Vd{3-0};
1712 let Inst{22} = Vd{4};
1713 let Inst{24} = SIMM{7};
1714 let Inst{18-16} = SIMM{6-4};
1715 let Inst{3-0} = SIMM{3-0};
1716 let DecoderMethod = "DecodeNEONModImmInstruction";
1719 // NEON 2 vector register format.
1720 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1721 bits<5> op11_7, bit op6, bit op4,
1722 dag oops, dag iops, InstrItinClass itin,
1723 string opc, string dt, string asm, string cstr, list<dag> pattern>
1724 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1725 let Inst{24-23} = op24_23;
1726 let Inst{21-20} = op21_20;
1727 let Inst{19-18} = op19_18;
1728 let Inst{17-16} = op17_16;
1729 let Inst{11-7} = op11_7;
1733 // Instruction operands.
1737 let Inst{15-12} = Vd{3-0};
1738 let Inst{22} = Vd{4};
1739 let Inst{3-0} = Vm{3-0};
1740 let Inst{5} = Vm{4};
1743 // Same as N2V except it doesn't have a datatype suffix.
1744 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1745 bits<5> op11_7, bit op6, bit op4,
1746 dag oops, dag iops, InstrItinClass itin,
1747 string opc, string asm, string cstr, list<dag> pattern>
1748 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1749 let Inst{24-23} = op24_23;
1750 let Inst{21-20} = op21_20;
1751 let Inst{19-18} = op19_18;
1752 let Inst{17-16} = op17_16;
1753 let Inst{11-7} = op11_7;
1757 // Instruction operands.
1761 let Inst{15-12} = Vd{3-0};
1762 let Inst{22} = Vd{4};
1763 let Inst{3-0} = Vm{3-0};
1764 let Inst{5} = Vm{4};
1767 // NEON 2 vector register with immediate.
1768 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1769 dag oops, dag iops, Format f, InstrItinClass itin,
1770 string opc, string dt, string asm, string cstr, list<dag> pattern>
1771 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1772 let Inst{24} = op24;
1773 let Inst{23} = op23;
1774 let Inst{11-8} = op11_8;
1779 // Instruction operands.
1784 let Inst{15-12} = Vd{3-0};
1785 let Inst{22} = Vd{4};
1786 let Inst{3-0} = Vm{3-0};
1787 let Inst{5} = Vm{4};
1788 let Inst{21-16} = SIMM{5-0};
1791 // NEON 3 vector register format.
1793 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1794 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1795 string opc, string dt, string asm, string cstr,
1797 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1798 let Inst{24} = op24;
1799 let Inst{23} = op23;
1800 let Inst{21-20} = op21_20;
1801 let Inst{11-8} = op11_8;
1806 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1807 dag oops, dag iops, Format f, InstrItinClass itin,
1808 string opc, string dt, string asm, string cstr, list<dag> pattern>
1809 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1810 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1812 // Instruction operands.
1817 let Inst{15-12} = Vd{3-0};
1818 let Inst{22} = Vd{4};
1819 let Inst{19-16} = Vn{3-0};
1820 let Inst{7} = Vn{4};
1821 let Inst{3-0} = Vm{3-0};
1822 let Inst{5} = Vm{4};
1825 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1826 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1827 string opc, string dt, string asm, string cstr,
1829 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1830 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1832 // Instruction operands.
1838 let Inst{15-12} = Vd{3-0};
1839 let Inst{22} = Vd{4};
1840 let Inst{19-16} = Vn{3-0};
1841 let Inst{7} = Vn{4};
1842 let Inst{3-0} = Vm{3-0};
1846 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1847 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1848 string opc, string dt, string asm, string cstr,
1850 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1851 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1853 // Instruction operands.
1859 let Inst{15-12} = Vd{3-0};
1860 let Inst{22} = Vd{4};
1861 let Inst{19-16} = Vn{3-0};
1862 let Inst{7} = Vn{4};
1863 let Inst{2-0} = Vm{2-0};
1864 let Inst{5} = lane{1};
1865 let Inst{3} = lane{0};
1868 // Same as N3V except it doesn't have a data type suffix.
1869 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1871 dag oops, dag iops, Format f, InstrItinClass itin,
1872 string opc, string asm, string cstr, list<dag> pattern>
1873 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1874 let Inst{24} = op24;
1875 let Inst{23} = op23;
1876 let Inst{21-20} = op21_20;
1877 let Inst{11-8} = op11_8;
1881 // Instruction operands.
1886 let Inst{15-12} = Vd{3-0};
1887 let Inst{22} = Vd{4};
1888 let Inst{19-16} = Vn{3-0};
1889 let Inst{7} = Vn{4};
1890 let Inst{3-0} = Vm{3-0};
1891 let Inst{5} = Vm{4};
1894 // NEON VMOVs between scalar and core registers.
1895 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1896 dag oops, dag iops, Format f, InstrItinClass itin,
1897 string opc, string dt, string asm, list<dag> pattern>
1898 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1900 let Inst{27-20} = opcod1;
1901 let Inst{11-8} = opcod2;
1902 let Inst{6-5} = opcod3;
1904 // A8.6.303, A8.6.328, A8.6.329
1905 let Inst{3-0} = 0b0000;
1907 let OutOperandList = oops;
1908 let InOperandList = !con(iops, (ins pred:$p));
1909 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1910 let Pattern = pattern;
1911 list<Predicate> Predicates = [HasNEON];
1913 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1920 let Inst{31-28} = p{3-0};
1922 let Inst{19-16} = V{3-0};
1923 let Inst{15-12} = R{3-0};
1925 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1926 dag oops, dag iops, InstrItinClass itin,
1927 string opc, string dt, string asm, list<dag> pattern>
1928 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1929 opc, dt, asm, pattern>;
1930 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1931 dag oops, dag iops, InstrItinClass itin,
1932 string opc, string dt, string asm, list<dag> pattern>
1933 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1934 opc, dt, asm, pattern>;
1935 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1936 dag oops, dag iops, InstrItinClass itin,
1937 string opc, string dt, string asm, list<dag> pattern>
1938 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1939 opc, dt, asm, pattern>;
1941 // Vector Duplicate Lane (from scalar to all elements)
1942 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1943 InstrItinClass itin, string opc, string dt, string asm,
1945 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1946 let Inst{24-23} = 0b11;
1947 let Inst{21-20} = 0b11;
1948 let Inst{19-16} = op19_16;
1949 let Inst{11-7} = 0b11000;
1957 let Inst{22} = Vd{4};
1958 let Inst{15-12} = Vd{3-0};
1959 let Inst{5} = Vm{4};
1960 let Inst{3-0} = Vm{3-0};
1963 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1964 // for single-precision FP.
1965 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1966 list<Predicate> Predicates = [HasNEON,UseNEONForFP];