1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // The instruction has an Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
87 // FIXME: Once the JIT is MC-ized, these can go away.
89 class AddrMode<bits<5> val> {
92 def AddrModeNone : AddrMode<0>;
93 def AddrMode1 : AddrMode<1>;
94 def AddrMode2 : AddrMode<2>;
95 def AddrMode3 : AddrMode<3>;
96 def AddrMode4 : AddrMode<4>;
97 def AddrMode5 : AddrMode<5>;
98 def AddrMode6 : AddrMode<6>;
99 def AddrModeT1_1 : AddrMode<7>;
100 def AddrModeT1_2 : AddrMode<8>;
101 def AddrModeT1_4 : AddrMode<9>;
102 def AddrModeT1_s : AddrMode<10>;
103 def AddrModeT2_i12 : AddrMode<11>;
104 def AddrModeT2_i8 : AddrMode<12>;
105 def AddrModeT2_so : AddrMode<13>;
106 def AddrModeT2_pc : AddrMode<14>;
107 def AddrModeT2_i8s4 : AddrMode<15>;
108 def AddrMode_i12 : AddrMode<16>;
111 class SizeFlagVal<bits<3> val> {
114 def SizeInvalid : SizeFlagVal<0>; // Unset.
115 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
116 def Size8Bytes : SizeFlagVal<2>;
117 def Size4Bytes : SizeFlagVal<3>;
118 def Size2Bytes : SizeFlagVal<4>;
120 // Load / store index mode.
121 class IndexMode<bits<2> val> {
124 def IndexModeNone : IndexMode<0>;
125 def IndexModePre : IndexMode<1>;
126 def IndexModePost : IndexMode<2>;
127 def IndexModeUpd : IndexMode<3>;
129 // Instruction execution domain.
130 class Domain<bits<3> val> {
133 def GenericDomain : Domain<0>;
134 def VFPDomain : Domain<1>; // Instructions in VFP domain only
135 def NeonDomain : Domain<2>; // Instructions in Neon domain only
136 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
139 //===----------------------------------------------------------------------===//
140 // ARM special operands.
143 def CondCodeOperand : AsmOperandClass {
144 let Name = "CondCode";
145 let SuperClasses = [];
148 def CCOutOperand : AsmOperandClass {
150 let SuperClasses = [];
153 def MemBarrierOptOperand : AsmOperandClass {
154 let Name = "MemBarrierOpt";
155 let SuperClasses = [];
156 let ParserMethod = "tryParseMemBarrierOptOperand";
159 def ProcIFlagsOperand : AsmOperandClass {
160 let Name = "ProcIFlags";
161 let SuperClasses = [];
162 let ParserMethod = "tryParseProcIFlagsOperand";
165 def MSRMaskOperand : AsmOperandClass {
166 let Name = "MSRMask";
167 let SuperClasses = [];
168 let ParserMethod = "tryParseMSRMaskOperand";
171 // ARM imod and iflag operands, used only by the CPS instruction.
172 def imod_op : Operand<i32> {
173 let PrintMethod = "printCPSIMod";
176 def iflags_op : Operand<i32> {
177 let PrintMethod = "printCPSIFlag";
178 let ParserMatchClass = ProcIFlagsOperand;
181 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
182 // register whose default is 0 (no register).
183 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
184 (ops (i32 14), (i32 zero_reg))> {
185 let PrintMethod = "printPredicateOperand";
186 let ParserMatchClass = CondCodeOperand;
189 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
190 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
191 let EncoderMethod = "getCCOutOpValue";
192 let PrintMethod = "printSBitModifierOperand";
193 let ParserMatchClass = CCOutOperand;
196 // Same as cc_out except it defaults to setting CPSR.
197 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
198 let EncoderMethod = "getCCOutOpValue";
199 let PrintMethod = "printSBitModifierOperand";
200 let ParserMatchClass = CCOutOperand;
203 // ARM special operands for disassembly only.
205 def setend_op : Operand<i32> {
206 let PrintMethod = "printSetendOperand";
209 def cps_opt : Operand<i32> {
210 let PrintMethod = "printCPSOptionOperand";
213 def msr_mask : Operand<i32> {
214 let PrintMethod = "printMSRMaskOperand";
215 let ParserMatchClass = MSRMaskOperand;
218 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
219 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
220 def neg_zero : Operand<i32> {
221 let PrintMethod = "printNegZeroOperand";
224 // Shift Right Immediate - A shift right immediate is encoded differently from
225 // other shift immediates. The imm6 field is encoded like so:
228 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
229 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
230 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
231 // 64 64 - <imm> is encoded in imm6<5:0>
232 def shr_imm8 : Operand<i32> {
233 let EncoderMethod = "getShiftRight8Imm";
235 def shr_imm16 : Operand<i32> {
236 let EncoderMethod = "getShiftRight16Imm";
238 def shr_imm32 : Operand<i32> {
239 let EncoderMethod = "getShiftRight32Imm";
241 def shr_imm64 : Operand<i32> {
242 let EncoderMethod = "getShiftRight64Imm";
245 //===----------------------------------------------------------------------===//
246 // ARM Instruction templates.
249 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
250 Format f, Domain d, string cstr, InstrItinClass itin>
252 let Namespace = "ARM";
257 bits<2> IndexModeBits = IM.Value;
259 bits<6> Form = F.Value;
261 bit isUnaryDataProc = 0;
262 bit canXformTo16Bit = 0;
264 // If this is a pseudo instruction, mark it isCodeGenOnly.
265 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
267 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
268 let TSFlags{4-0} = AM.Value;
269 let TSFlags{7-5} = SZ.Value;
270 let TSFlags{9-8} = IndexModeBits;
271 let TSFlags{15-10} = Form;
272 let TSFlags{16} = isUnaryDataProc;
273 let TSFlags{17} = canXformTo16Bit;
274 let TSFlags{20-18} = D.Value;
276 let Constraints = cstr;
277 let Itinerary = itin;
284 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
285 Format f, Domain d, string cstr, InstrItinClass itin>
286 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
288 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
289 // on by adding flavors to specific instructions.
290 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
291 Format f, Domain d, string cstr, InstrItinClass itin>
292 : InstTemplate<am, sz, im, f, d, cstr, itin>;
294 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
295 // FIXME: This really should derive from InstTemplate instead, as pseudos
296 // don't need encoding information. TableGen doesn't like that
297 // currently. Need to figure out why and fix it.
298 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
300 let OutOperandList = oops;
301 let InOperandList = iops;
302 let Pattern = pattern;
303 let isCodeGenOnly = 1;
306 // PseudoInst that's ARM-mode only.
307 class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
309 : PseudoInst<oops, iops, itin, pattern> {
311 list<Predicate> Predicates = [IsARM];
314 // PseudoInst that's Thumb-mode only.
315 class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
317 : PseudoInst<oops, iops, itin, pattern> {
319 list<Predicate> Predicates = [IsThumb];
322 // PseudoInst that's Thumb2-mode only.
323 class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
325 : PseudoInst<oops, iops, itin, pattern> {
327 list<Predicate> Predicates = [IsThumb2];
329 // Almost all ARM instructions are predicable.
330 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
331 IndexMode im, Format f, InstrItinClass itin,
332 string opc, string asm, string cstr,
334 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
337 let OutOperandList = oops;
338 let InOperandList = !con(iops, (ins pred:$p));
339 let AsmString = !strconcat(opc, "${p}", asm);
340 let Pattern = pattern;
341 list<Predicate> Predicates = [IsARM];
344 // A few are not predicable
345 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
346 IndexMode im, Format f, InstrItinClass itin,
347 string opc, string asm, string cstr,
349 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
350 let OutOperandList = oops;
351 let InOperandList = iops;
352 let AsmString = !strconcat(opc, asm);
353 let Pattern = pattern;
354 let isPredicable = 0;
355 list<Predicate> Predicates = [IsARM];
358 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
359 // operand since by default it's a zero register. It will become an implicit def
360 // once it's "flipped".
361 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
362 IndexMode im, Format f, InstrItinClass itin,
363 string opc, string asm, string cstr,
365 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
366 bits<4> p; // Predicate operand
367 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
371 let OutOperandList = oops;
372 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
373 let AsmString = !strconcat(opc, "${s}${p}", asm);
374 let Pattern = pattern;
375 list<Predicate> Predicates = [IsARM];
379 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
380 IndexMode im, Format f, InstrItinClass itin,
381 string asm, string cstr, list<dag> pattern>
382 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
383 let OutOperandList = oops;
384 let InOperandList = iops;
386 let Pattern = pattern;
387 list<Predicate> Predicates = [IsARM];
390 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
393 opc, asm, "", pattern>;
394 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
395 string opc, string asm, list<dag> pattern>
396 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
397 opc, asm, "", pattern>;
398 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
399 string asm, list<dag> pattern>
400 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
402 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
405 opc, asm, "", pattern>;
407 // Ctrl flow instructions
408 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
409 string opc, string asm, list<dag> pattern>
410 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
411 opc, asm, "", pattern> {
412 let Inst{27-24} = opcod;
414 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
415 string asm, list<dag> pattern>
416 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
418 let Inst{27-24} = opcod;
421 // BR_JT instructions
422 class JTI<dag oops, dag iops, InstrItinClass itin,
423 string asm, list<dag> pattern>
424 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
427 // Atomic load/store instructions
428 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
429 string opc, string asm, list<dag> pattern>
430 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
431 opc, asm, "", pattern> {
434 let Inst{27-23} = 0b00011;
435 let Inst{22-21} = opcod;
437 let Inst{19-16} = Rn;
438 let Inst{15-12} = Rt;
439 let Inst{11-0} = 0b111110011111;
441 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
442 string opc, string asm, list<dag> pattern>
443 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
444 opc, asm, "", pattern> {
448 let Inst{27-23} = 0b00011;
449 let Inst{22-21} = opcod;
451 let Inst{19-16} = Rn;
452 let Inst{15-12} = Rd;
453 let Inst{11-4} = 0b11111001;
456 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
457 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
461 let Inst{27-23} = 0b00010;
463 let Inst{21-20} = 0b00;
464 let Inst{19-16} = Rn;
465 let Inst{15-12} = Rt;
466 let Inst{11-4} = 0b00001001;
470 // addrmode1 instructions
471 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
472 string opc, string asm, list<dag> pattern>
473 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
474 opc, asm, "", pattern> {
475 let Inst{24-21} = opcod;
476 let Inst{27-26} = 0b00;
478 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
479 string opc, string asm, list<dag> pattern>
480 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
481 opc, asm, "", pattern> {
482 let Inst{24-21} = opcod;
483 let Inst{27-26} = 0b00;
485 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
486 string asm, list<dag> pattern>
487 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
489 let Inst{24-21} = opcod;
490 let Inst{27-26} = 0b00;
495 // LDR/LDRB/STR/STRB/...
496 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
497 Format f, InstrItinClass itin, string opc, string asm,
499 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
501 let Inst{27-25} = op;
502 let Inst{24} = 1; // 24 == P
504 let Inst{22} = isByte;
505 let Inst{21} = 0; // 21 == W
508 // Indexed load/stores
509 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
510 IndexMode im, Format f, InstrItinClass itin, string opc,
511 string asm, string cstr, list<dag> pattern>
512 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
513 opc, asm, cstr, pattern> {
515 let Inst{27-26} = 0b01;
516 let Inst{24} = isPre; // P bit
517 let Inst{22} = isByte; // B bit
518 let Inst{21} = isPre; // W bit
519 let Inst{20} = isLd; // L bit
520 let Inst{15-12} = Rt;
522 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
523 IndexMode im, Format f, InstrItinClass itin, string opc,
524 string asm, string cstr, list<dag> pattern>
525 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
527 // AM2 store w/ two operands: (GPR, am2offset)
528 // {13} 1 == Rm, 0 == imm12
533 let Inst{25} = offset{13};
534 let Inst{23} = offset{12};
535 let Inst{19-16} = Rn;
536 let Inst{11-0} = offset{11-0};
539 // addrmode3 instructions
540 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
541 InstrItinClass itin, string opc, string asm, list<dag> pattern>
542 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
543 opc, asm, "", pattern> {
546 let Inst{27-25} = 0b000;
547 let Inst{24} = 1; // P bit
548 let Inst{23} = addr{8}; // U bit
549 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
550 let Inst{21} = 0; // W bit
551 let Inst{20} = op20; // L bit
552 let Inst{19-16} = addr{12-9}; // Rn
553 let Inst{15-12} = Rt; // Rt
554 let Inst{11-8} = addr{7-4}; // imm7_4/zero
556 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
559 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
560 IndexMode im, Format f, InstrItinClass itin, string opc,
561 string asm, string cstr, list<dag> pattern>
562 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
563 opc, asm, cstr, pattern> {
565 let Inst{27-25} = 0b000;
566 let Inst{24} = isPre; // P bit
567 let Inst{21} = isPre; // W bit
568 let Inst{20} = op20; // L bit
569 let Inst{15-12} = Rt; // Rt
572 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
573 IndexMode im, Format f, InstrItinClass itin, string opc,
574 string asm, string cstr, list<dag> pattern>
575 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
577 // AM3 store w/ two operands: (GPR, am3offset)
581 let Inst{27-25} = 0b000;
582 let Inst{23} = offset{8};
583 let Inst{22} = offset{9};
584 let Inst{19-16} = Rn;
585 let Inst{15-12} = Rt; // Rt
586 let Inst{11-8} = offset{7-4}; // imm7_4/zero
588 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
592 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
595 opc, asm, "", pattern> {
598 let Inst{27-25} = 0b000;
599 let Inst{24} = 1; // P bit
600 let Inst{23} = addr{8}; // U bit
601 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
602 let Inst{21} = 0; // W bit
603 let Inst{20} = 0; // L bit
604 let Inst{19-16} = addr{12-9}; // Rn
605 let Inst{15-12} = Rt; // Rt
606 let Inst{11-8} = addr{7-4}; // imm7_4/zero
608 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
611 // Pre-indexed stores
612 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
613 string opc, string asm, string cstr, list<dag> pattern>
614 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
615 opc, asm, cstr, pattern> {
617 let Inst{5} = 1; // H bit
618 let Inst{6} = 0; // S bit
620 let Inst{20} = 0; // L bit
621 let Inst{21} = 1; // W bit
622 let Inst{24} = 1; // P bit
623 let Inst{27-25} = 0b000;
625 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
626 string opc, string asm, string cstr, list<dag> pattern>
627 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
628 opc, asm, cstr, pattern> {
630 let Inst{5} = 1; // H bit
631 let Inst{6} = 1; // S bit
633 let Inst{20} = 0; // L bit
634 let Inst{21} = 1; // W bit
635 let Inst{24} = 1; // P bit
636 let Inst{27-25} = 0b000;
639 // Post-indexed stores
640 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
641 string opc, string asm, string cstr, list<dag> pattern>
642 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
643 opc, asm, cstr,pattern> {
645 let Inst{5} = 1; // H bit
646 let Inst{6} = 0; // S bit
648 let Inst{20} = 0; // L bit
649 let Inst{21} = 0; // W bit
650 let Inst{24} = 0; // P bit
651 let Inst{27-25} = 0b000;
653 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
654 string opc, string asm, string cstr, list<dag> pattern>
655 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
656 opc, asm, cstr, pattern> {
658 let Inst{5} = 1; // H bit
659 let Inst{6} = 1; // S bit
661 let Inst{20} = 0; // L bit
662 let Inst{21} = 0; // W bit
663 let Inst{24} = 0; // P bit
664 let Inst{27-25} = 0b000;
667 // addrmode4 instructions
668 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
669 string asm, string cstr, list<dag> pattern>
670 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
675 let Inst{27-25} = 0b100;
676 let Inst{22} = 0; // S bit
677 let Inst{19-16} = Rn;
678 let Inst{15-0} = regs;
681 // Unsigned multiply, multiply-accumulate instructions.
682 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
683 string opc, string asm, list<dag> pattern>
684 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
685 opc, asm, "", pattern> {
686 let Inst{7-4} = 0b1001;
687 let Inst{20} = 0; // S bit
688 let Inst{27-21} = opcod;
690 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
691 string opc, string asm, list<dag> pattern>
692 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
693 opc, asm, "", pattern> {
694 let Inst{7-4} = 0b1001;
695 let Inst{27-21} = opcod;
698 // Most significant word multiply
699 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
700 InstrItinClass itin, string opc, string asm, list<dag> pattern>
701 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
702 opc, asm, "", pattern> {
706 let Inst{7-4} = opc7_4;
708 let Inst{27-21} = opcod;
709 let Inst{19-16} = Rd;
713 // MSW multiple w/ Ra operand
714 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
715 InstrItinClass itin, string opc, string asm, list<dag> pattern>
716 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
718 let Inst{15-12} = Ra;
721 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
722 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
723 InstrItinClass itin, string opc, string asm, list<dag> pattern>
724 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
725 opc, asm, "", pattern> {
731 let Inst{27-21} = opcod;
732 let Inst{6-5} = bit6_5;
736 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
737 InstrItinClass itin, string opc, string asm, list<dag> pattern>
738 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
740 let Inst{19-16} = Rd;
743 // AMulxyI with Ra operand
744 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
745 InstrItinClass itin, string opc, string asm, list<dag> pattern>
746 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
748 let Inst{15-12} = Ra;
751 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
752 InstrItinClass itin, string opc, string asm, list<dag> pattern>
753 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
756 let Inst{19-16} = RdHi;
757 let Inst{15-12} = RdLo;
760 // Extend instructions.
761 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
762 string opc, string asm, list<dag> pattern>
763 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
764 opc, asm, "", pattern> {
765 // All AExtI instructions have Rd and Rm register operands.
768 let Inst{15-12} = Rd;
770 let Inst{7-4} = 0b0111;
771 let Inst{9-8} = 0b00;
772 let Inst{27-20} = opcod;
775 // Misc Arithmetic instructions.
776 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
777 InstrItinClass itin, string opc, string asm, list<dag> pattern>
778 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
779 opc, asm, "", pattern> {
782 let Inst{27-20} = opcod;
783 let Inst{19-16} = 0b1111;
784 let Inst{15-12} = Rd;
785 let Inst{11-8} = 0b1111;
786 let Inst{7-4} = opc7_4;
791 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
792 string opc, string asm, list<dag> pattern>
793 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
794 opc, asm, "", pattern> {
799 let Inst{27-20} = opcod;
800 let Inst{19-16} = Rn;
801 let Inst{15-12} = Rd;
802 let Inst{11-7} = sh{7-3};
804 let Inst{5-4} = 0b01;
808 //===----------------------------------------------------------------------===//
810 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
811 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
812 list<Predicate> Predicates = [IsARM];
814 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
815 list<Predicate> Predicates = [IsARM, HasV5TE];
817 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
818 list<Predicate> Predicates = [IsARM, HasV6];
821 //===----------------------------------------------------------------------===//
822 // Thumb Instruction Format Definitions.
825 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
826 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
827 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
828 let OutOperandList = oops;
829 let InOperandList = iops;
831 let Pattern = pattern;
832 list<Predicate> Predicates = [IsThumb];
835 // TI - Thumb instruction.
836 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
837 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
839 // Two-address instructions
840 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
842 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
845 // tBL, tBX 32-bit instructions
846 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
847 dag oops, dag iops, InstrItinClass itin, string asm,
849 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
851 let Inst{31-27} = opcod1;
852 let Inst{15-14} = opcod2;
853 let Inst{12} = opcod3;
856 // Move to/from coprocessor instructions
857 class T1Cop<dag oops, dag iops, string asm, list<dag> pattern>
858 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>,
859 Encoding, Requires<[IsThumb, HasV6]> {
860 let Inst{31-28} = 0b1110;
863 // BR_JT instructions
864 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
866 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
869 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
870 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
871 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
872 let OutOperandList = oops;
873 let InOperandList = iops;
875 let Pattern = pattern;
876 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
879 class T1I<dag oops, dag iops, InstrItinClass itin,
880 string asm, list<dag> pattern>
881 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
882 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
883 string asm, list<dag> pattern>
884 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
886 // Two-address instructions
887 class T1It<dag oops, dag iops, InstrItinClass itin,
888 string asm, string cstr, list<dag> pattern>
889 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
892 // Thumb1 instruction that can either be predicated or set CPSR.
893 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
895 string opc, string asm, string cstr, list<dag> pattern>
896 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
897 let OutOperandList = !con(oops, (outs s_cc_out:$s));
898 let InOperandList = !con(iops, (ins pred:$p));
899 let AsmString = !strconcat(opc, "${s}${p}", asm);
900 let Pattern = pattern;
901 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
904 class T1sI<dag oops, dag iops, InstrItinClass itin,
905 string opc, string asm, list<dag> pattern>
906 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
908 // Two-address instructions
909 class T1sIt<dag oops, dag iops, InstrItinClass itin,
910 string opc, string asm, list<dag> pattern>
911 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
912 "$Rn = $Rdn", pattern>;
914 // Thumb1 instruction that can be predicated.
915 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
917 string opc, string asm, string cstr, list<dag> pattern>
918 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
919 let OutOperandList = oops;
920 let InOperandList = !con(iops, (ins pred:$p));
921 let AsmString = !strconcat(opc, "${p}", asm);
922 let Pattern = pattern;
923 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
926 class T1pI<dag oops, dag iops, InstrItinClass itin,
927 string opc, string asm, list<dag> pattern>
928 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
930 // Two-address instructions
931 class T1pIt<dag oops, dag iops, InstrItinClass itin,
932 string opc, string asm, list<dag> pattern>
933 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
934 "$Rn = $Rdn", pattern>;
936 class T1pIs<dag oops, dag iops,
937 InstrItinClass itin, string opc, string asm, list<dag> pattern>
938 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
940 class Encoding16 : Encoding {
941 let Inst{31-16} = 0x0000;
944 // A6.2 16-bit Thumb instruction encoding
945 class T1Encoding<bits<6> opcode> : Encoding16 {
946 let Inst{15-10} = opcode;
949 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
950 class T1General<bits<5> opcode> : Encoding16 {
951 let Inst{15-14} = 0b00;
952 let Inst{13-9} = opcode;
955 // A6.2.2 Data-processing encoding.
956 class T1DataProcessing<bits<4> opcode> : Encoding16 {
957 let Inst{15-10} = 0b010000;
958 let Inst{9-6} = opcode;
961 // A6.2.3 Special data instructions and branch and exchange encoding.
962 class T1Special<bits<4> opcode> : Encoding16 {
963 let Inst{15-10} = 0b010001;
964 let Inst{9-6} = opcode;
967 // A6.2.4 Load/store single data item encoding.
968 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
969 let Inst{15-12} = opA;
970 let Inst{11-9} = opB;
972 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
974 // Helper classes to encode Thumb1 loads and stores. For immediates, the
975 // following bits are used for "opA" (see A6.2.4):
977 // 0b0110 => Immediate, 4 bytes
978 // 0b1000 => Immediate, 2 bytes
979 // 0b0111 => Immediate, 1 byte
980 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
981 InstrItinClass itin, string opc, string asm,
983 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
984 T1LoadStore<0b0101, opcode> {
987 let Inst{8-6} = addr{5-3}; // Rm
988 let Inst{5-3} = addr{2-0}; // Rn
991 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
992 InstrItinClass itin, string opc, string asm,
994 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
995 T1LoadStore<opA, {opB,?,?}> {
998 let Inst{10-6} = addr{7-3}; // imm5
999 let Inst{5-3} = addr{2-0}; // Rn
1003 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1004 class T1Misc<bits<7> opcode> : Encoding16 {
1005 let Inst{15-12} = 0b1011;
1006 let Inst{11-5} = opcode;
1009 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1010 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1011 InstrItinClass itin,
1012 string opc, string asm, string cstr, list<dag> pattern>
1013 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1014 let OutOperandList = oops;
1015 let InOperandList = !con(iops, (ins pred:$p));
1016 let AsmString = !strconcat(opc, "${p}", asm);
1017 let Pattern = pattern;
1018 list<Predicate> Predicates = [IsThumb2];
1021 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1022 // input operand since by default it's a zero register. It will become an
1023 // implicit def once it's "flipped".
1025 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1027 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1028 InstrItinClass itin,
1029 string opc, string asm, string cstr, list<dag> pattern>
1030 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1031 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1034 let OutOperandList = oops;
1035 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1036 let AsmString = !strconcat(opc, "${s}${p}", asm);
1037 let Pattern = pattern;
1038 list<Predicate> Predicates = [IsThumb2];
1042 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1043 InstrItinClass itin,
1044 string asm, string cstr, list<dag> pattern>
1045 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1046 let OutOperandList = oops;
1047 let InOperandList = iops;
1048 let AsmString = asm;
1049 let Pattern = pattern;
1050 list<Predicate> Predicates = [IsThumb2];
1053 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1054 InstrItinClass itin,
1055 string asm, string cstr, list<dag> pattern>
1056 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1057 let OutOperandList = oops;
1058 let InOperandList = iops;
1059 let AsmString = asm;
1060 let Pattern = pattern;
1061 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1064 class T2I<dag oops, dag iops, InstrItinClass itin,
1065 string opc, string asm, list<dag> pattern>
1066 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1067 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1068 string opc, string asm, list<dag> pattern>
1069 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1070 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1071 string opc, string asm, list<dag> pattern>
1072 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1073 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1074 string opc, string asm, list<dag> pattern>
1075 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1076 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1077 string opc, string asm, list<dag> pattern>
1078 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1079 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1080 string opc, string asm, list<dag> pattern>
1081 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1086 let Inst{31-25} = 0b1110100;
1088 let Inst{23} = addr{8};
1091 let Inst{20} = isLoad;
1092 let Inst{19-16} = addr{12-9};
1093 let Inst{15-12} = Rt{3-0};
1094 let Inst{11-8} = Rt2{3-0};
1095 let Inst{7-0} = addr{7-0};
1098 class T2sI<dag oops, dag iops, InstrItinClass itin,
1099 string opc, string asm, list<dag> pattern>
1100 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1102 class T2XI<dag oops, dag iops, InstrItinClass itin,
1103 string asm, list<dag> pattern>
1104 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1105 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1106 string asm, list<dag> pattern>
1107 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1109 // Move to/from coprocessor instructions
1110 class T2Cop<dag oops, dag iops, string asm, list<dag> pattern>
1111 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> {
1112 let Inst{31-28} = 0b1111;
1115 // Two-address instructions
1116 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1117 string asm, string cstr, list<dag> pattern>
1118 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1120 // T2Iidxldst - Thumb2 indexed load / store instructions.
1121 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1123 AddrMode am, IndexMode im, InstrItinClass itin,
1124 string opc, string asm, string cstr, list<dag> pattern>
1125 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1126 let OutOperandList = oops;
1127 let InOperandList = !con(iops, (ins pred:$p));
1128 let AsmString = !strconcat(opc, "${p}", asm);
1129 let Pattern = pattern;
1130 list<Predicate> Predicates = [IsThumb2];
1131 let Inst{31-27} = 0b11111;
1132 let Inst{26-25} = 0b00;
1133 let Inst{24} = signed;
1135 let Inst{22-21} = opcod;
1136 let Inst{20} = load;
1138 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1139 let Inst{10} = pre; // The P bit.
1140 let Inst{8} = 1; // The W bit.
1143 let Inst{7-0} = addr{7-0};
1144 let Inst{9} = addr{8}; // Sign bit
1148 let Inst{15-12} = Rt{3-0};
1149 let Inst{19-16} = Rn{3-0};
1152 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1153 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1154 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1157 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1158 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1159 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1162 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1163 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1164 list<Predicate> Predicates = [IsThumb2];
1167 //===----------------------------------------------------------------------===//
1169 //===----------------------------------------------------------------------===//
1170 // ARM VFP Instruction templates.
1173 // Almost all VFP instructions are predicable.
1174 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1175 IndexMode im, Format f, InstrItinClass itin,
1176 string opc, string asm, string cstr, list<dag> pattern>
1177 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1179 let Inst{31-28} = p;
1180 let OutOperandList = oops;
1181 let InOperandList = !con(iops, (ins pred:$p));
1182 let AsmString = !strconcat(opc, "${p}", asm);
1183 let Pattern = pattern;
1184 let PostEncoderMethod = "VFPThumb2PostEncoder";
1185 list<Predicate> Predicates = [HasVFP2];
1189 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1190 IndexMode im, Format f, InstrItinClass itin,
1191 string asm, string cstr, list<dag> pattern>
1192 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1194 let Inst{31-28} = p;
1195 let OutOperandList = oops;
1196 let InOperandList = iops;
1197 let AsmString = asm;
1198 let Pattern = pattern;
1199 let PostEncoderMethod = "VFPThumb2PostEncoder";
1200 list<Predicate> Predicates = [HasVFP2];
1203 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1204 string opc, string asm, list<dag> pattern>
1205 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1206 opc, asm, "", pattern> {
1207 let PostEncoderMethod = "VFPThumb2PostEncoder";
1210 // ARM VFP addrmode5 loads and stores
1211 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1212 InstrItinClass itin,
1213 string opc, string asm, list<dag> pattern>
1214 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1215 VFPLdStFrm, itin, opc, asm, "", pattern> {
1216 // Instruction operands.
1220 // Encode instruction operands.
1221 let Inst{23} = addr{8}; // U (add = (U == '1'))
1222 let Inst{22} = Dd{4};
1223 let Inst{19-16} = addr{12-9}; // Rn
1224 let Inst{15-12} = Dd{3-0};
1225 let Inst{7-0} = addr{7-0}; // imm8
1227 // TODO: Mark the instructions with the appropriate subtarget info.
1228 let Inst{27-24} = opcod1;
1229 let Inst{21-20} = opcod2;
1230 let Inst{11-9} = 0b101;
1231 let Inst{8} = 1; // Double precision
1233 // Loads & stores operate on both NEON and VFP pipelines.
1234 let D = VFPNeonDomain;
1237 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1238 InstrItinClass itin,
1239 string opc, string asm, list<dag> pattern>
1240 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1241 VFPLdStFrm, itin, opc, asm, "", pattern> {
1242 // Instruction operands.
1246 // Encode instruction operands.
1247 let Inst{23} = addr{8}; // U (add = (U == '1'))
1248 let Inst{22} = Sd{0};
1249 let Inst{19-16} = addr{12-9}; // Rn
1250 let Inst{15-12} = Sd{4-1};
1251 let Inst{7-0} = addr{7-0}; // imm8
1253 // TODO: Mark the instructions with the appropriate subtarget info.
1254 let Inst{27-24} = opcod1;
1255 let Inst{21-20} = opcod2;
1256 let Inst{11-9} = 0b101;
1257 let Inst{8} = 0; // Single precision
1259 // Loads & stores operate on both NEON and VFP pipelines.
1260 let D = VFPNeonDomain;
1263 // VFP Load / store multiple pseudo instructions.
1264 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1266 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1268 let OutOperandList = oops;
1269 let InOperandList = !con(iops, (ins pred:$p));
1270 let Pattern = pattern;
1271 list<Predicate> Predicates = [HasVFP2];
1274 // Load / store multiple
1275 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1276 string asm, string cstr, list<dag> pattern>
1277 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1278 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1279 // Instruction operands.
1283 // Encode instruction operands.
1284 let Inst{19-16} = Rn;
1285 let Inst{22} = regs{12};
1286 let Inst{15-12} = regs{11-8};
1287 let Inst{7-0} = regs{7-0};
1289 // TODO: Mark the instructions with the appropriate subtarget info.
1290 let Inst{27-25} = 0b110;
1291 let Inst{11-9} = 0b101;
1292 let Inst{8} = 1; // Double precision
1295 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1296 string asm, string cstr, list<dag> pattern>
1297 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1298 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1299 // Instruction operands.
1303 // Encode instruction operands.
1304 let Inst{19-16} = Rn;
1305 let Inst{22} = regs{8};
1306 let Inst{15-12} = regs{12-9};
1307 let Inst{7-0} = regs{7-0};
1309 // TODO: Mark the instructions with the appropriate subtarget info.
1310 let Inst{27-25} = 0b110;
1311 let Inst{11-9} = 0b101;
1312 let Inst{8} = 0; // Single precision
1315 // Double precision, unary
1316 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1317 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1318 string asm, list<dag> pattern>
1319 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1320 // Instruction operands.
1324 // Encode instruction operands.
1325 let Inst{3-0} = Dm{3-0};
1326 let Inst{5} = Dm{4};
1327 let Inst{15-12} = Dd{3-0};
1328 let Inst{22} = Dd{4};
1330 let Inst{27-23} = opcod1;
1331 let Inst{21-20} = opcod2;
1332 let Inst{19-16} = opcod3;
1333 let Inst{11-9} = 0b101;
1334 let Inst{8} = 1; // Double precision
1335 let Inst{7-6} = opcod4;
1336 let Inst{4} = opcod5;
1339 // Double precision, binary
1340 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1341 dag iops, InstrItinClass itin, string opc, string asm,
1343 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1344 // Instruction operands.
1349 // Encode instruction operands.
1350 let Inst{3-0} = Dm{3-0};
1351 let Inst{5} = Dm{4};
1352 let Inst{19-16} = Dn{3-0};
1353 let Inst{7} = Dn{4};
1354 let Inst{15-12} = Dd{3-0};
1355 let Inst{22} = Dd{4};
1357 let Inst{27-23} = opcod1;
1358 let Inst{21-20} = opcod2;
1359 let Inst{11-9} = 0b101;
1360 let Inst{8} = 1; // Double precision
1365 // Single precision, unary
1366 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1367 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1368 string asm, list<dag> pattern>
1369 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1370 // Instruction operands.
1374 // Encode instruction operands.
1375 let Inst{3-0} = Sm{4-1};
1376 let Inst{5} = Sm{0};
1377 let Inst{15-12} = Sd{4-1};
1378 let Inst{22} = Sd{0};
1380 let Inst{27-23} = opcod1;
1381 let Inst{21-20} = opcod2;
1382 let Inst{19-16} = opcod3;
1383 let Inst{11-9} = 0b101;
1384 let Inst{8} = 0; // Single precision
1385 let Inst{7-6} = opcod4;
1386 let Inst{4} = opcod5;
1389 // Single precision unary, if no NEON. Same as ASuI except not available if
1391 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1392 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1393 string asm, list<dag> pattern>
1394 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1396 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1399 // Single precision, binary
1400 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1401 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1402 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1403 // Instruction operands.
1408 // Encode instruction operands.
1409 let Inst{3-0} = Sm{4-1};
1410 let Inst{5} = Sm{0};
1411 let Inst{19-16} = Sn{4-1};
1412 let Inst{7} = Sn{0};
1413 let Inst{15-12} = Sd{4-1};
1414 let Inst{22} = Sd{0};
1416 let Inst{27-23} = opcod1;
1417 let Inst{21-20} = opcod2;
1418 let Inst{11-9} = 0b101;
1419 let Inst{8} = 0; // Single precision
1424 // Single precision binary, if no NEON. Same as ASbI except not available if
1426 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1427 dag iops, InstrItinClass itin, string opc, string asm,
1429 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1430 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1432 // Instruction operands.
1437 // Encode instruction operands.
1438 let Inst{3-0} = Sm{4-1};
1439 let Inst{5} = Sm{0};
1440 let Inst{19-16} = Sn{4-1};
1441 let Inst{7} = Sn{0};
1442 let Inst{15-12} = Sd{4-1};
1443 let Inst{22} = Sd{0};
1446 // VFP conversion instructions
1447 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1448 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1450 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1451 let Inst{27-23} = opcod1;
1452 let Inst{21-20} = opcod2;
1453 let Inst{19-16} = opcod3;
1454 let Inst{11-8} = opcod4;
1459 // VFP conversion between floating-point and fixed-point
1460 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1461 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1463 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1464 // size (fixed-point number): sx == 0 ? 16 : 32
1465 let Inst{7} = op5; // sx
1468 // VFP conversion instructions, if no NEON
1469 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1470 dag oops, dag iops, InstrItinClass itin,
1471 string opc, string asm, list<dag> pattern>
1472 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1474 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1477 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1478 InstrItinClass itin,
1479 string opc, string asm, list<dag> pattern>
1480 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1481 let Inst{27-20} = opcod1;
1482 let Inst{11-8} = opcod2;
1486 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1487 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1488 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1490 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1491 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1492 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1494 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1495 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1496 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1498 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1499 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1500 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1502 //===----------------------------------------------------------------------===//
1504 //===----------------------------------------------------------------------===//
1505 // ARM NEON Instruction templates.
1508 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1509 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1511 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1512 let OutOperandList = oops;
1513 let InOperandList = !con(iops, (ins pred:$p));
1514 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1515 let Pattern = pattern;
1516 list<Predicate> Predicates = [HasNEON];
1519 // Same as NeonI except it does not have a "data type" specifier.
1520 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1521 InstrItinClass itin, string opc, string asm, string cstr,
1523 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1524 let OutOperandList = oops;
1525 let InOperandList = !con(iops, (ins pred:$p));
1526 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1527 let Pattern = pattern;
1528 list<Predicate> Predicates = [HasNEON];
1531 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1532 dag oops, dag iops, InstrItinClass itin,
1533 string opc, string dt, string asm, string cstr, list<dag> pattern>
1534 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1536 let Inst{31-24} = 0b11110100;
1537 let Inst{23} = op23;
1538 let Inst{21-20} = op21_20;
1539 let Inst{11-8} = op11_8;
1540 let Inst{7-4} = op7_4;
1542 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1548 let Inst{22} = Vd{4};
1549 let Inst{15-12} = Vd{3-0};
1550 let Inst{19-16} = Rn{3-0};
1551 let Inst{3-0} = Rm{3-0};
1554 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1555 dag oops, dag iops, InstrItinClass itin,
1556 string opc, string dt, string asm, string cstr, list<dag> pattern>
1557 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1558 dt, asm, cstr, pattern> {
1562 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1563 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1565 let OutOperandList = oops;
1566 let InOperandList = !con(iops, (ins pred:$p));
1567 list<Predicate> Predicates = [HasNEON];
1570 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1572 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1574 let OutOperandList = oops;
1575 let InOperandList = !con(iops, (ins pred:$p));
1576 let Pattern = pattern;
1577 list<Predicate> Predicates = [HasNEON];
1580 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1581 string opc, string dt, string asm, string cstr, list<dag> pattern>
1582 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1584 let Inst{31-25} = 0b1111001;
1585 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1588 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1589 string opc, string asm, string cstr, list<dag> pattern>
1590 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1592 let Inst{31-25} = 0b1111001;
1593 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1596 // NEON "one register and a modified immediate" format.
1597 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1599 dag oops, dag iops, InstrItinClass itin,
1600 string opc, string dt, string asm, string cstr,
1602 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1603 let Inst{23} = op23;
1604 let Inst{21-19} = op21_19;
1605 let Inst{11-8} = op11_8;
1611 // Instruction operands.
1615 let Inst{15-12} = Vd{3-0};
1616 let Inst{22} = Vd{4};
1617 let Inst{24} = SIMM{7};
1618 let Inst{18-16} = SIMM{6-4};
1619 let Inst{3-0} = SIMM{3-0};
1622 // NEON 2 vector register format.
1623 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1624 bits<5> op11_7, bit op6, bit op4,
1625 dag oops, dag iops, InstrItinClass itin,
1626 string opc, string dt, string asm, string cstr, list<dag> pattern>
1627 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1628 let Inst{24-23} = op24_23;
1629 let Inst{21-20} = op21_20;
1630 let Inst{19-18} = op19_18;
1631 let Inst{17-16} = op17_16;
1632 let Inst{11-7} = op11_7;
1636 // Instruction operands.
1640 let Inst{15-12} = Vd{3-0};
1641 let Inst{22} = Vd{4};
1642 let Inst{3-0} = Vm{3-0};
1643 let Inst{5} = Vm{4};
1646 // Same as N2V except it doesn't have a datatype suffix.
1647 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1648 bits<5> op11_7, bit op6, bit op4,
1649 dag oops, dag iops, InstrItinClass itin,
1650 string opc, string asm, string cstr, list<dag> pattern>
1651 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1652 let Inst{24-23} = op24_23;
1653 let Inst{21-20} = op21_20;
1654 let Inst{19-18} = op19_18;
1655 let Inst{17-16} = op17_16;
1656 let Inst{11-7} = op11_7;
1660 // Instruction operands.
1664 let Inst{15-12} = Vd{3-0};
1665 let Inst{22} = Vd{4};
1666 let Inst{3-0} = Vm{3-0};
1667 let Inst{5} = Vm{4};
1670 // NEON 2 vector register with immediate.
1671 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1672 dag oops, dag iops, Format f, InstrItinClass itin,
1673 string opc, string dt, string asm, string cstr, list<dag> pattern>
1674 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1675 let Inst{24} = op24;
1676 let Inst{23} = op23;
1677 let Inst{11-8} = op11_8;
1682 // Instruction operands.
1687 let Inst{15-12} = Vd{3-0};
1688 let Inst{22} = Vd{4};
1689 let Inst{3-0} = Vm{3-0};
1690 let Inst{5} = Vm{4};
1691 let Inst{21-16} = SIMM{5-0};
1694 // NEON 3 vector register format.
1695 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1696 dag oops, dag iops, Format f, InstrItinClass itin,
1697 string opc, string dt, string asm, string cstr, list<dag> pattern>
1698 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1699 let Inst{24} = op24;
1700 let Inst{23} = op23;
1701 let Inst{21-20} = op21_20;
1702 let Inst{11-8} = op11_8;
1706 // Instruction operands.
1711 let Inst{15-12} = Vd{3-0};
1712 let Inst{22} = Vd{4};
1713 let Inst{19-16} = Vn{3-0};
1714 let Inst{7} = Vn{4};
1715 let Inst{3-0} = Vm{3-0};
1716 let Inst{5} = Vm{4};
1719 // Same as N3V except it doesn't have a data type suffix.
1720 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1722 dag oops, dag iops, Format f, InstrItinClass itin,
1723 string opc, string asm, string cstr, list<dag> pattern>
1724 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1725 let Inst{24} = op24;
1726 let Inst{23} = op23;
1727 let Inst{21-20} = op21_20;
1728 let Inst{11-8} = op11_8;
1732 // Instruction operands.
1737 let Inst{15-12} = Vd{3-0};
1738 let Inst{22} = Vd{4};
1739 let Inst{19-16} = Vn{3-0};
1740 let Inst{7} = Vn{4};
1741 let Inst{3-0} = Vm{3-0};
1742 let Inst{5} = Vm{4};
1745 // NEON VMOVs between scalar and core registers.
1746 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1747 dag oops, dag iops, Format f, InstrItinClass itin,
1748 string opc, string dt, string asm, list<dag> pattern>
1749 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1751 let Inst{27-20} = opcod1;
1752 let Inst{11-8} = opcod2;
1753 let Inst{6-5} = opcod3;
1756 let OutOperandList = oops;
1757 let InOperandList = !con(iops, (ins pred:$p));
1758 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1759 let Pattern = pattern;
1760 list<Predicate> Predicates = [HasNEON];
1762 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1769 let Inst{31-28} = p{3-0};
1771 let Inst{19-16} = V{3-0};
1772 let Inst{15-12} = R{3-0};
1774 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1775 dag oops, dag iops, InstrItinClass itin,
1776 string opc, string dt, string asm, list<dag> pattern>
1777 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1778 opc, dt, asm, pattern>;
1779 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1780 dag oops, dag iops, InstrItinClass itin,
1781 string opc, string dt, string asm, list<dag> pattern>
1782 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1783 opc, dt, asm, pattern>;
1784 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1785 dag oops, dag iops, InstrItinClass itin,
1786 string opc, string dt, string asm, list<dag> pattern>
1787 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1788 opc, dt, asm, pattern>;
1790 // Vector Duplicate Lane (from scalar to all elements)
1791 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1792 InstrItinClass itin, string opc, string dt, string asm,
1794 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1795 let Inst{24-23} = 0b11;
1796 let Inst{21-20} = 0b11;
1797 let Inst{19-16} = op19_16;
1798 let Inst{11-7} = 0b11000;
1806 let Inst{22} = Vd{4};
1807 let Inst{15-12} = Vd{3-0};
1808 let Inst{5} = Vm{4};
1809 let Inst{3-0} = Vm{3-0};
1812 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1813 // for single-precision FP.
1814 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1815 list<Predicate> Predicates = [HasNEON,UseNEONForFP];