1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPRdIm : Format<9>;
32 def DPRdReg : Format<10>;
33 def DPRdSoReg : Format<11>;
34 def DPRdMisc : Format<12>;
35 def DPRnIm : Format<13>;
36 def DPRnReg : Format<14>;
37 def DPRnSoReg : Format<15>;
38 def DPRIm : Format<16>;
39 def DPRReg : Format<17>;
40 def DPRSoReg : Format<18>;
41 def DPRImS : Format<19>;
42 def DPRRegS : Format<20>;
43 def DPRSoRegS : Format<21>;
45 def LdFrm : Format<22>;
46 def StFrm : Format<23>;
48 def ArithMisc : Format<24>;
49 def ThumbFrm : Format<25>;
50 def VFPFrm : Format<26>;
53 //===----------------------------------------------------------------------===//
55 // ARM Instruction templates.
58 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
59 Format f, string cstr>
63 let Namespace = "ARM";
65 bits<4> Opcode = opcod;
67 bits<4> AddrModeBits = AM.Value;
70 bits<3> SizeFlag = SZ.Value;
73 bits<2> IndexModeBits = IM.Value;
76 bits<5> Form = F.Value;
78 let Constraints = cstr;
81 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
82 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
83 let OutOperandList = oops;
84 let InOperandList = iops;
86 let Pattern = pattern;
89 // Almost all ARM instructions are predicable.
90 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
91 IndexMode im, Format f, string opc, string asm, string cstr,
93 : InstARM<opcod, am, sz, im, f, cstr> {
94 let OutOperandList = oops;
95 let InOperandList = !con(iops, (ops pred:$p));
96 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
97 let Pattern = pattern;
98 list<Predicate> Predicates = [IsARM];
101 // Same as I except it can optionally modify CPSR. Note it's modeled as
102 // an input operand since by default it's a zero register. It will
103 // become an implicit def once it's "flipped".
104 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
105 IndexMode im, Format f, string opc, string asm, string cstr,
107 : InstARM<opcod, am, sz, im, f, cstr> {
108 let OutOperandList = oops;
109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
111 let Pattern = pattern;
112 list<Predicate> Predicates = [IsARM];
116 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
117 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
118 : InstARM<opcod, am, sz, im, f, cstr> {
119 let OutOperandList = oops;
120 let InOperandList = iops;
122 let Pattern = pattern;
123 list<Predicate> Predicates = [IsARM];
126 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
127 string asm, list<dag> pattern>
128 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
130 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
131 string asm, list<dag> pattern>
132 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
134 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
136 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
139 // Ctrl flow instructions
140 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
141 string asm, list<dag> pattern>
142 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
144 let Inst{27-24} = opcod;
146 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
148 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
150 let Inst{27-24} = opcod;
153 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
155 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
157 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
159 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
161 let Inst{27-24} = opcod;
163 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
164 string asm, list<dag> pattern>
165 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
167 let Inst{27-24} = opcod;
170 // BR_JT instructions
172 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
173 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
175 let Inst{20} = 0; // S Bit
176 let Inst{24-21} = opcod;
177 let Inst{27-26} = {0,0};
180 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
181 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
183 let Inst{20} = 0; // S bit
184 let Inst{24-21} = opcod;
185 let Inst{27-26} = {0,0};
188 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
189 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
191 let Inst{20} = 1; // L bit
192 let Inst{21} = 0; // W bit
193 let Inst{22} = 0; // B bit
194 let Inst{24} = 1; // P bit
195 let Inst{27-26} = {0,1};
199 // addrmode1 instructions
200 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
201 string asm, list<dag> pattern>
202 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
204 let Inst{24-21} = opcod;
205 let Inst{27-26} = {0,0};
207 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
208 string asm, list<dag> pattern>
209 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
211 let Inst{24-21} = opcod;
212 let Inst{27-26} = {0,0};
214 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
216 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
218 let Inst{24-21} = opcod;
219 let Inst{27-26} = {0,0};
221 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
222 string asm, list<dag> pattern>
223 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
227 // addrmode2 loads and stores
228 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
229 string asm, list<dag> pattern>
230 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
232 let Inst{27-26} = {0,1};
234 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
236 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
240 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
241 string asm, list<dag> pattern>
242 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
243 let Inst{20} = 1; // L bit
244 let Inst{21} = 0; // W bit
245 let Inst{22} = 0; // B bit
246 let Inst{24} = 1; // P bit
248 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
250 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
252 let Inst{20} = 1; // L bit
253 let Inst{21} = 0; // W bit
254 let Inst{22} = 0; // B bit
255 let Inst{24} = 1; // P bit
257 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
258 string asm, list<dag> pattern>
259 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
260 let Inst{20} = 1; // L bit
261 let Inst{21} = 0; // W bit
262 let Inst{22} = 1; // B bit
263 let Inst{24} = 1; // P bit
265 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
267 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
269 let Inst{20} = 1; // L bit
270 let Inst{21} = 0; // W bit
271 let Inst{22} = 1; // B bit
272 let Inst{24} = 1; // P bit
276 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
277 string asm, list<dag> pattern>
278 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
279 let Inst{20} = 0; // L bit
280 let Inst{21} = 0; // W bit
281 let Inst{22} = 0; // B bit
282 let Inst{24} = 1; // P bit
284 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
286 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
288 let Inst{20} = 0; // L bit
289 let Inst{21} = 0; // W bit
290 let Inst{22} = 0; // B bit
291 let Inst{24} = 1; // P bit
293 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
294 string asm, list<dag> pattern>
295 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
296 let Inst{20} = 0; // L bit
297 let Inst{21} = 0; // W bit
298 let Inst{22} = 1; // B bit
299 let Inst{24} = 1; // P bit
301 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
303 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
305 let Inst{20} = 0; // L bit
306 let Inst{21} = 0; // W bit
307 let Inst{22} = 1; // B bit
308 let Inst{24} = 1; // P bit
312 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
313 string asm, string cstr, list<dag> pattern>
314 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
315 asm, cstr, pattern> {
316 let Inst{20} = 1; // L bit
317 let Inst{21} = 1; // W bit
318 let Inst{22} = 0; // B bit
319 let Inst{24} = 1; // P bit
321 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
322 string asm, string cstr, list<dag> pattern>
323 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
324 asm, cstr, pattern> {
325 let Inst{20} = 1; // L bit
326 let Inst{21} = 1; // W bit
327 let Inst{22} = 1; // B bit
328 let Inst{24} = 1; // P bit
331 // Pre-indexed stores
332 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
333 string asm, string cstr, list<dag> pattern>
334 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
335 asm, cstr, pattern> {
336 let Inst{20} = 0; // L bit
337 let Inst{21} = 1; // W bit
338 let Inst{22} = 0; // B bit
339 let Inst{24} = 1; // P bit
341 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
342 string asm, string cstr, list<dag> pattern>
343 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
344 asm, cstr, pattern> {
345 let Inst{20} = 0; // L bit
346 let Inst{21} = 1; // W bit
347 let Inst{22} = 1; // B bit
348 let Inst{24} = 1; // P bit
351 // Post-indexed loads
352 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
353 string asm, string cstr, list<dag> pattern>
354 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
356 let Inst{20} = 1; // L bit
357 let Inst{21} = 0; // W bit
358 let Inst{22} = 0; // B bit
359 let Inst{24} = 0; // P bit
361 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
362 string asm, string cstr, list<dag> pattern>
363 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
365 let Inst{20} = 1; // L bit
366 let Inst{21} = 0; // W bit
367 let Inst{22} = 1; // B bit
368 let Inst{24} = 0; // P bit
371 // Post-indexed stores
372 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
373 string asm, string cstr, list<dag> pattern>
374 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
376 let Inst{20} = 0; // L bit
377 let Inst{21} = 0; // W bit
378 let Inst{22} = 0; // B bit
379 let Inst{24} = 0; // P bit
381 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
382 string asm, string cstr, list<dag> pattern>
383 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
385 let Inst{20} = 0; // L bit
386 let Inst{21} = 0; // W bit
387 let Inst{22} = 1; // B bit
388 let Inst{24} = 0; // P bit
391 // addrmode3 instructions
392 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
393 string asm, list<dag> pattern>
394 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
396 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
398 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
402 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
403 string asm, list<dag> pattern>
404 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
407 let Inst{5} = 1; // H bit
408 let Inst{6} = 0; // S bit
410 let Inst{20} = 1; // L bit
411 let Inst{21} = 0; // W bit
412 let Inst{24} = 1; // P bit
414 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
416 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
419 let Inst{5} = 1; // H bit
420 let Inst{6} = 0; // S bit
422 let Inst{20} = 1; // L bit
423 let Inst{21} = 0; // W bit
424 let Inst{24} = 1; // P bit
426 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
427 string asm, list<dag> pattern>
428 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
431 let Inst{5} = 1; // H bit
432 let Inst{6} = 1; // S bit
434 let Inst{20} = 1; // L bit
435 let Inst{21} = 0; // W bit
436 let Inst{24} = 1; // P bit
438 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
440 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
443 let Inst{5} = 1; // H bit
444 let Inst{6} = 1; // S bit
446 let Inst{20} = 1; // L bit
447 let Inst{21} = 0; // W bit
448 let Inst{24} = 1; // P bit
450 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
451 string asm, list<dag> pattern>
452 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
455 let Inst{5} = 0; // H bit
456 let Inst{6} = 1; // S bit
458 let Inst{20} = 1; // L bit
459 let Inst{21} = 0; // W bit
460 let Inst{24} = 1; // P bit
462 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
464 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
467 let Inst{5} = 0; // H bit
468 let Inst{6} = 1; // S bit
470 let Inst{20} = 1; // L bit
471 let Inst{21} = 0; // W bit
472 let Inst{24} = 1; // P bit
474 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
475 string asm, list<dag> pattern>
476 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
479 let Inst{5} = 0; // H bit
480 let Inst{6} = 1; // S bit
482 let Inst{20} = 0; // L bit
483 let Inst{21} = 0; // W bit
484 let Inst{24} = 1; // P bit
488 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
489 string asm, list<dag> pattern>
490 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
493 let Inst{5} = 1; // H bit
494 let Inst{6} = 0; // S bit
496 let Inst{20} = 0; // L bit
497 let Inst{21} = 0; // W bit
498 let Inst{24} = 1; // P bit
500 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
502 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
505 let Inst{5} = 1; // H bit
506 let Inst{6} = 0; // S bit
508 let Inst{20} = 0; // L bit
509 let Inst{21} = 0; // W bit
510 let Inst{24} = 1; // P bit
512 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
513 string asm, list<dag> pattern>
514 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
517 let Inst{5} = 1; // H bit
518 let Inst{6} = 1; // S bit
520 let Inst{20} = 0; // L bit
521 let Inst{21} = 0; // W bit
522 let Inst{24} = 1; // P bit
526 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
527 string asm, string cstr, list<dag> pattern>
528 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
529 asm, cstr, pattern> {
531 let Inst{5} = 1; // H bit
532 let Inst{6} = 0; // S bit
534 let Inst{20} = 1; // L bit
535 let Inst{21} = 1; // W bit
536 let Inst{24} = 1; // P bit
538 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
539 string asm, string cstr, list<dag> pattern>
540 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
541 asm, cstr, pattern> {
543 let Inst{5} = 1; // H bit
544 let Inst{6} = 1; // S bit
546 let Inst{20} = 1; // L bit
547 let Inst{21} = 1; // W bit
548 let Inst{24} = 1; // P bit
550 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
551 string asm, string cstr, list<dag> pattern>
552 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
553 asm, cstr, pattern> {
555 let Inst{5} = 0; // H bit
556 let Inst{6} = 1; // S bit
558 let Inst{20} = 1; // L bit
559 let Inst{21} = 1; // W bit
560 let Inst{24} = 1; // P bit
563 // Pre-indexed stores
564 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
565 string asm, string cstr, list<dag> pattern>
566 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
567 asm, cstr, pattern> {
569 let Inst{5} = 1; // H bit
570 let Inst{6} = 0; // S bit
572 let Inst{20} = 0; // L bit
573 let Inst{21} = 1; // W bit
574 let Inst{24} = 1; // P bit
577 // Post-indexed loads
578 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
579 string asm, string cstr, list<dag> pattern>
580 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
583 let Inst{5} = 1; // H bit
584 let Inst{6} = 0; // S bit
586 let Inst{20} = 1; // L bit
587 let Inst{21} = 1; // W bit
588 let Inst{24} = 0; // P bit
590 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
591 string asm, string cstr, list<dag> pattern>
592 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
595 let Inst{5} = 1; // H bit
596 let Inst{6} = 1; // S bit
598 let Inst{20} = 1; // L bit
599 let Inst{21} = 1; // W bit
600 let Inst{24} = 0; // P bit
602 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
603 string asm, string cstr, list<dag> pattern>
604 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
607 let Inst{5} = 0; // H bit
608 let Inst{6} = 1; // S bit
610 let Inst{20} = 1; // L bit
611 let Inst{21} = 1; // W bit
612 let Inst{24} = 0; // P bit
615 // Post-indexed stores
616 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
617 string asm, string cstr, list<dag> pattern>
618 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
621 let Inst{5} = 1; // H bit
622 let Inst{6} = 0; // S bit
624 let Inst{20} = 0; // L bit
625 let Inst{21} = 1; // W bit
626 let Inst{24} = 0; // P bit
630 // addrmode4 instructions
631 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
632 string asm, list<dag> pattern>
633 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
635 let Inst{25-27} = {0,0,1};
637 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
639 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
641 let Inst{20} = 1; // L bit
642 let Inst{22} = 0; // S bit
643 let Inst{27-25} = 0b100;
645 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
647 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
649 let Inst{20} = 1; // L bit
650 let Inst{22} = 1; // S bit
651 let Inst{27-25} = 0b100;
653 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
655 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
657 let Inst{20} = 0; // L bit
658 let Inst{22} = 0; // S bit
659 let Inst{27-25} = 0b100;
663 //===----------------------------------------------------------------------===//
665 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
666 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
667 list<Predicate> Predicates = [IsARM];
669 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
670 list<Predicate> Predicates = [IsARM, HasV5TE];
672 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
673 list<Predicate> Predicates = [IsARM, HasV6];
676 //===----------------------------------------------------------------------===//
678 // Thumb Instruction Format Definitions.
682 // TI - Thumb instruction.
684 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
685 string asm, string cstr, list<dag> pattern>
686 // FIXME: Set all opcodes to 0 for now.
687 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
688 let OutOperandList = outs;
689 let InOperandList = ins;
691 let Pattern = pattern;
692 list<Predicate> Predicates = [IsThumb];
695 class TI<dag outs, dag ins, string asm, list<dag> pattern>
696 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
697 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
698 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
699 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
700 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
701 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
702 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
703 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
704 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
706 // Two-address instructions
707 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
708 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
710 // BL, BLX(1) are translated by assembler into two instructions
711 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
712 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
714 // BR_JT instructions
715 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
716 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
719 //===----------------------------------------------------------------------===//
722 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
723 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
724 list<Predicate> Predicates = [IsThumb];
727 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
728 list<Predicate> Predicates = [IsThumb, HasV5T];