1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 string EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 string EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // If this is a pseudo instruction, mark it isCodeGenOnly.
208 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
210 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
211 let TSFlags{4-0} = AM.Value;
212 let TSFlags{7-5} = SZ.Value;
213 let TSFlags{9-8} = IndexModeBits;
214 let TSFlags{15-10} = Form;
215 let TSFlags{16} = isUnaryDataProc;
216 let TSFlags{17} = canXformTo16Bit;
217 let TSFlags{19-18} = D.Value;
219 let Constraints = cstr;
220 let Itinerary = itin;
227 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
228 Format f, Domain d, string cstr, InstrItinClass itin>
229 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
231 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
232 // on by adding flavors to specific instructions.
233 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
234 Format f, Domain d, string cstr, InstrItinClass itin>
235 : InstTemplate<am, sz, im, f, d, cstr, itin>;
237 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
238 string asm, list<dag> pattern>
239 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
241 let OutOperandList = oops;
242 let InOperandList = iops;
244 let Pattern = pattern;
247 // Almost all ARM instructions are predicable.
248 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
249 IndexMode im, Format f, InstrItinClass itin,
250 string opc, string asm, string cstr,
252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
255 let OutOperandList = oops;
256 let InOperandList = !con(iops, (ins pred:$p));
257 let AsmString = !strconcat(opc, "${p}", asm);
258 let Pattern = pattern;
259 list<Predicate> Predicates = [IsARM];
262 // A few are not predicable
263 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
264 IndexMode im, Format f, InstrItinClass itin,
265 string opc, string asm, string cstr,
267 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
268 let OutOperandList = oops;
269 let InOperandList = iops;
270 let AsmString = !strconcat(opc, asm);
271 let Pattern = pattern;
272 let isPredicable = 0;
273 list<Predicate> Predicates = [IsARM];
276 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
277 // operand since by default it's a zero register. It will become an implicit def
278 // once it's "flipped".
279 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
280 IndexMode im, Format f, InstrItinClass itin,
281 string opc, string asm, string cstr,
283 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
284 bits<4> p; // Predicate operand
285 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
289 let OutOperandList = oops;
290 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
291 let AsmString = !strconcat(opc, "${s}${p}", asm);
292 let Pattern = pattern;
293 list<Predicate> Predicates = [IsARM];
297 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
298 IndexMode im, Format f, InstrItinClass itin,
299 string asm, string cstr, list<dag> pattern>
300 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
301 let OutOperandList = oops;
302 let InOperandList = iops;
304 let Pattern = pattern;
305 list<Predicate> Predicates = [IsARM];
308 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
311 opc, asm, "", pattern>;
312 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
313 string opc, string asm, list<dag> pattern>
314 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
315 opc, asm, "", pattern>;
316 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
317 string asm, list<dag> pattern>
318 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
320 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
323 opc, asm, "", pattern>;
325 // Ctrl flow instructions
326 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
329 opc, asm, "", pattern> {
330 let Inst{27-24} = opcod;
332 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
333 string asm, list<dag> pattern>
334 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
336 let Inst{27-24} = opcod;
338 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
339 string asm, list<dag> pattern>
340 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
343 // BR_JT instructions
344 class JTI<dag oops, dag iops, InstrItinClass itin,
345 string asm, list<dag> pattern>
346 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
349 // Atomic load/store instructions
350 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
353 opc, asm, "", pattern> {
356 let Inst{27-23} = 0b00011;
357 let Inst{22-21} = opcod;
359 let Inst{19-16} = Rn;
360 let Inst{15-12} = Rt;
361 let Inst{11-0} = 0b111110011111;
363 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
366 opc, asm, "", pattern> {
370 let Inst{27-23} = 0b00011;
371 let Inst{22-21} = opcod;
373 let Inst{19-16} = Rn;
374 let Inst{15-12} = Rd;
375 let Inst{11-4} = 0b11111001;
378 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
379 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
383 let Inst{27-23} = 0b00010;
385 let Inst{21-20} = 0b00;
386 let Inst{19-16} = Rn;
387 let Inst{15-12} = Rt;
388 let Inst{11-4} = 0b00001001;
392 // addrmode1 instructions
393 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
396 opc, asm, "", pattern> {
397 let Inst{24-21} = opcod;
398 let Inst{27-26} = 0b00;
400 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
403 opc, asm, "", pattern> {
404 let Inst{24-21} = opcod;
405 let Inst{27-26} = 0b00;
407 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
408 string asm, list<dag> pattern>
409 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
411 let Inst{24-21} = opcod;
412 let Inst{27-26} = 0b00;
414 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
417 opc, asm, "", pattern>;
420 // addrmode2 loads and stores
421 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
422 string opc, string asm, list<dag> pattern>
423 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
424 opc, asm, "", pattern> {
425 let Inst{27-26} = 0b01;
431 class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am,
432 Format f, InstrItinClass itin, string opc, string asm,
434 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
436 let Inst{27-25} = op;
437 let Inst{24} = 1; // 24 == P
439 let Inst{22} = opc22;
440 let Inst{21} = 0; // 21 == W
443 // LDRH/LDRSB/LDRSH/LDRD
444 class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
445 Format f, InstrItinClass itin, string opc, string asm,
447 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
449 let Inst{27-25} = 0b000;
450 let Inst{24} = 1; // 24 == P
452 let Inst{22} = opc22;
453 let Inst{21} = 0; // 21 == W
454 let Inst{20} = opc20;
462 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
463 string opc, string asm, list<dag> pattern>
464 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
465 opc, asm, "", pattern> {
466 let Inst{20} = 1; // L bit
467 let Inst{21} = 0; // W bit
468 let Inst{22} = 0; // B bit
469 let Inst{24} = 1; // P bit
470 let Inst{27-26} = 0b01;
472 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
473 string asm, list<dag> pattern>
474 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
476 let Inst{20} = 1; // L bit
477 let Inst{21} = 0; // W bit
478 let Inst{22} = 0; // B bit
479 let Inst{24} = 1; // P bit
480 let Inst{27-26} = 0b01;
482 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
483 string opc, string asm, list<dag> pattern>
484 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
485 opc, asm, "", pattern> {
486 let Inst{20} = 1; // L bit
487 let Inst{21} = 0; // W bit
488 let Inst{22} = 1; // B bit
489 let Inst{24} = 1; // P bit
490 let Inst{27-26} = 0b01;
492 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
493 string asm, list<dag> pattern>
494 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
496 let Inst{20} = 1; // L bit
497 let Inst{21} = 0; // W bit
498 let Inst{22} = 1; // B bit
499 let Inst{24} = 1; // P bit
500 let Inst{27-26} = 0b01;
504 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
505 string opc, string asm, list<dag> pattern>
506 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
507 opc, asm, "", pattern> {
508 let Inst{20} = 0; // L bit
509 let Inst{21} = 0; // W bit
510 let Inst{22} = 0; // B bit
511 let Inst{24} = 1; // P bit
512 let Inst{27-26} = 0b01;
514 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
515 string asm, list<dag> pattern>
516 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
518 let Inst{20} = 0; // L bit
519 let Inst{21} = 0; // W bit
520 let Inst{22} = 0; // B bit
521 let Inst{24} = 1; // P bit
522 let Inst{27-26} = 0b01;
524 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
527 opc, asm, "", pattern> {
528 let Inst{20} = 0; // L bit
529 let Inst{21} = 0; // W bit
530 let Inst{22} = 1; // B bit
531 let Inst{24} = 1; // P bit
532 let Inst{27-26} = 0b01;
534 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
535 string asm, list<dag> pattern>
536 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
538 let Inst{20} = 0; // L bit
539 let Inst{21} = 0; // W bit
540 let Inst{22} = 1; // B bit
541 let Inst{24} = 1; // P bit
542 let Inst{27-26} = 0b01;
546 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
547 string opc, string asm, string cstr, list<dag> pattern>
548 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
549 opc, asm, cstr, pattern> {
550 let Inst{20} = 1; // L bit
551 let Inst{21} = 1; // W bit
552 let Inst{22} = 0; // B bit
553 let Inst{24} = 1; // P bit
554 let Inst{27-26} = 0b01;
556 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
557 string opc, string asm, string cstr, list<dag> pattern>
558 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
559 opc, asm, cstr, pattern> {
560 let Inst{20} = 1; // L bit
561 let Inst{21} = 1; // W bit
562 let Inst{22} = 1; // B bit
563 let Inst{24} = 1; // P bit
564 let Inst{27-26} = 0b01;
567 // Pre-indexed stores
568 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
569 string opc, string asm, string cstr, list<dag> pattern>
570 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
571 opc, asm, cstr, pattern> {
572 let Inst{20} = 0; // L bit
573 let Inst{21} = 1; // W bit
574 let Inst{22} = 0; // B bit
575 let Inst{24} = 1; // P bit
576 let Inst{27-26} = 0b01;
578 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
579 string opc, string asm, string cstr, list<dag> pattern>
580 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
581 opc, asm, cstr, pattern> {
582 let Inst{20} = 0; // L bit
583 let Inst{21} = 1; // W bit
584 let Inst{22} = 1; // B bit
585 let Inst{24} = 1; // P bit
586 let Inst{27-26} = 0b01;
589 // Post-indexed loads
590 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
591 string opc, string asm, string cstr, list<dag> pattern>
592 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
593 opc, asm, cstr,pattern> {
594 let Inst{20} = 1; // L bit
595 let Inst{21} = 0; // W bit
596 let Inst{22} = 0; // B bit
597 let Inst{24} = 0; // P bit
598 let Inst{27-26} = 0b01;
600 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
601 string opc, string asm, string cstr, list<dag> pattern>
602 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
603 opc, asm, cstr,pattern> {
604 let Inst{20} = 1; // L bit
605 let Inst{21} = 0; // W bit
606 let Inst{22} = 1; // B bit
607 let Inst{24} = 0; // P bit
608 let Inst{27-26} = 0b01;
611 // Post-indexed stores
612 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
613 string opc, string asm, string cstr, list<dag> pattern>
614 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
615 opc, asm, cstr,pattern> {
616 let Inst{20} = 0; // L bit
617 let Inst{21} = 0; // W bit
618 let Inst{22} = 0; // B bit
619 let Inst{24} = 0; // P bit
620 let Inst{27-26} = 0b01;
622 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
623 string opc, string asm, string cstr, list<dag> pattern>
624 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
625 opc, asm, cstr,pattern> {
626 let Inst{20} = 0; // L bit
627 let Inst{21} = 0; // W bit
628 let Inst{22} = 1; // B bit
629 let Inst{24} = 0; // P bit
630 let Inst{27-26} = 0b01;
633 // addrmode3 instructions
634 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
635 string opc, string asm, list<dag> pattern>
636 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
637 opc, asm, "", pattern>;
638 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
639 string asm, list<dag> pattern>
640 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
644 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
645 string opc, string asm, list<dag> pattern>
646 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
647 opc, asm, "", pattern> {
649 let Inst{5} = 1; // H bit
650 let Inst{6} = 0; // S bit
652 let Inst{20} = 1; // L bit
653 let Inst{21} = 0; // W bit
654 let Inst{24} = 1; // P bit
655 let Inst{27-25} = 0b000;
657 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
658 string asm, list<dag> pattern>
659 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
662 let Inst{5} = 1; // H bit
663 let Inst{6} = 0; // S bit
665 let Inst{20} = 1; // L bit
666 let Inst{21} = 0; // W bit
667 let Inst{24} = 1; // P bit
669 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
670 string opc, string asm, list<dag> pattern>
671 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
672 opc, asm, "", pattern> {
675 let Inst{27-25} = 0b000;
676 let Inst{24} = 1; // P bit
677 let Inst{23} = addr{8}; // U bit
678 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
679 let Inst{21} = 0; // W bit
680 let Inst{20} = 1; // L bit
681 let Inst{19-16} = addr{12-9}; // Rn
682 let Inst{15-12} = Rt; // Rt
683 let Inst{11-8} = addr{7-4}; // imm7_4/zero
684 let Inst{7-4} = 0b1111;
685 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
687 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
688 string asm, list<dag> pattern>
689 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
692 let Inst{5} = 1; // H bit
693 let Inst{6} = 1; // S bit
695 let Inst{20} = 1; // L bit
696 let Inst{21} = 0; // W bit
697 let Inst{24} = 1; // P bit
699 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
700 string opc, string asm, list<dag> pattern>
701 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
702 opc, asm, "", pattern> {
704 let Inst{5} = 0; // H bit
705 let Inst{6} = 1; // S bit
707 let Inst{20} = 1; // L bit
708 let Inst{21} = 0; // W bit
709 let Inst{24} = 1; // P bit
710 let Inst{27-25} = 0b000;
712 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
713 string asm, list<dag> pattern>
714 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
717 let Inst{5} = 0; // H bit
718 let Inst{6} = 1; // S bit
720 let Inst{20} = 1; // L bit
721 let Inst{21} = 0; // W bit
722 let Inst{24} = 1; // P bit
724 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
725 string opc, string asm, list<dag> pattern>
726 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
727 opc, asm, "", pattern> {
729 let Inst{5} = 0; // H bit
730 let Inst{6} = 1; // S bit
732 let Inst{20} = 0; // L bit
733 let Inst{21} = 0; // W bit
734 let Inst{24} = 1; // P bit
735 let Inst{27-25} = 0b000;
739 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
740 string opc, string asm, list<dag> pattern>
741 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
742 opc, asm, "", pattern> {
745 let Inst{27-25} = 0b000;
746 let Inst{24} = 1; // P bit
747 let Inst{23} = addr{8}; // U bit
748 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
749 let Inst{21} = 0; // W bit
750 let Inst{20} = 0; // L bit
751 let Inst{19-16} = addr{12-9}; // Rn
752 let Inst{15-12} = Rt; // Rt
753 let Inst{11-8} = addr{7-4}; // imm7_4/zero
754 let Inst{7-4} = 0b1011;
755 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
757 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
758 string asm, list<dag> pattern>
759 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
762 let Inst{5} = 1; // H bit
763 let Inst{6} = 0; // S bit
765 let Inst{20} = 0; // L bit
766 let Inst{21} = 0; // W bit
767 let Inst{24} = 1; // P bit
769 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
770 string opc, string asm, list<dag> pattern>
771 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
772 opc, asm, "", pattern> {
774 let Inst{5} = 1; // H bit
775 let Inst{6} = 1; // S bit
777 let Inst{20} = 0; // L bit
778 let Inst{21} = 0; // W bit
779 let Inst{24} = 1; // P bit
780 let Inst{27-25} = 0b000;
784 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
785 string opc, string asm, string cstr, list<dag> pattern>
786 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
787 opc, asm, cstr, pattern> {
789 let Inst{5} = 1; // H bit
790 let Inst{6} = 0; // S bit
792 let Inst{20} = 1; // L bit
793 let Inst{21} = 1; // W bit
794 let Inst{24} = 1; // P bit
795 let Inst{27-25} = 0b000;
797 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
798 string opc, string asm, string cstr, list<dag> pattern>
799 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
800 opc, asm, cstr, pattern> {
803 let Inst{27-25} = 0b000;
804 let Inst{24} = 1; // P bit
805 let Inst{23} = addr{8}; // U bit
806 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
807 let Inst{21} = 1; // W bit
808 let Inst{20} = 1; // L bit
809 let Inst{19-16} = addr{12-9}; // Rn
810 let Inst{15-12} = Rt; // Rt
811 let Inst{11-8} = addr{7-4}; // imm7_4/zero
812 let Inst{7-4} = 0b1111;
813 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
815 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
816 string opc, string asm, string cstr, list<dag> pattern>
817 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
818 opc, asm, cstr, pattern> {
820 let Inst{5} = 0; // H bit
821 let Inst{6} = 1; // S bit
823 let Inst{20} = 1; // L bit
824 let Inst{21} = 1; // W bit
825 let Inst{24} = 1; // P bit
826 let Inst{27-25} = 0b000;
828 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
829 string opc, string asm, string cstr, list<dag> pattern>
830 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
831 opc, asm, cstr, pattern> {
833 let Inst{5} = 0; // H bit
834 let Inst{6} = 1; // S bit
836 let Inst{20} = 0; // L bit
837 let Inst{21} = 1; // W bit
838 let Inst{24} = 1; // P bit
839 let Inst{27-25} = 0b000;
843 // Pre-indexed stores
844 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
845 string opc, string asm, string cstr, list<dag> pattern>
846 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
847 opc, asm, cstr, pattern> {
849 let Inst{5} = 1; // H bit
850 let Inst{6} = 0; // S bit
852 let Inst{20} = 0; // L bit
853 let Inst{21} = 1; // W bit
854 let Inst{24} = 1; // P bit
855 let Inst{27-25} = 0b000;
857 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
858 string opc, string asm, string cstr, list<dag> pattern>
859 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
860 opc, asm, cstr, pattern> {
862 let Inst{5} = 1; // H bit
863 let Inst{6} = 1; // S bit
865 let Inst{20} = 0; // L bit
866 let Inst{21} = 1; // W bit
867 let Inst{24} = 1; // P bit
868 let Inst{27-25} = 0b000;
871 // Post-indexed loads
872 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
873 string opc, string asm, string cstr, list<dag> pattern>
874 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
875 opc, asm, cstr,pattern> {
877 let Inst{5} = 1; // H bit
878 let Inst{6} = 0; // S bit
880 let Inst{20} = 1; // L bit
881 let Inst{21} = 0; // W bit
882 let Inst{24} = 0; // P bit
883 let Inst{27-25} = 0b000;
885 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
886 string opc, string asm, string cstr, list<dag> pattern>
887 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
888 opc, asm, cstr,pattern> {
892 let Inst{27-25} = 0b000;
893 let Inst{24} = 0; // P bit
894 let Inst{23} = offset{8}; // U bit
895 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
896 let Inst{21} = 0; // W bit
897 let Inst{20} = 1; // L bit
898 let Inst{19-16} = Rn; // Rn
899 let Inst{15-12} = Rt; // Rt
900 let Inst{11-8} = offset{7-4}; // imm7_4/zero
901 let Inst{7-4} = 0b1111;
902 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
904 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
905 string opc, string asm, string cstr, list<dag> pattern>
906 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
907 opc, asm, cstr,pattern> {
909 let Inst{5} = 0; // H bit
910 let Inst{6} = 1; // S bit
912 let Inst{20} = 1; // L bit
913 let Inst{21} = 0; // W bit
914 let Inst{24} = 0; // P bit
915 let Inst{27-25} = 0b000;
917 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
918 string opc, string asm, string cstr, list<dag> pattern>
919 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
920 opc, asm, cstr, pattern> {
922 let Inst{5} = 0; // H bit
923 let Inst{6} = 1; // S bit
925 let Inst{20} = 0; // L bit
926 let Inst{21} = 0; // W bit
927 let Inst{24} = 0; // P bit
928 let Inst{27-25} = 0b000;
931 // Post-indexed stores
932 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
933 string opc, string asm, string cstr, list<dag> pattern>
934 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
935 opc, asm, cstr,pattern> {
937 let Inst{5} = 1; // H bit
938 let Inst{6} = 0; // S bit
940 let Inst{20} = 0; // L bit
941 let Inst{21} = 0; // W bit
942 let Inst{24} = 0; // P bit
943 let Inst{27-25} = 0b000;
945 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
946 string opc, string asm, string cstr, list<dag> pattern>
947 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
948 opc, asm, cstr, pattern> {
950 let Inst{5} = 1; // H bit
951 let Inst{6} = 1; // S bit
953 let Inst{20} = 0; // L bit
954 let Inst{21} = 0; // W bit
955 let Inst{24} = 0; // P bit
956 let Inst{27-25} = 0b000;
959 // addrmode4 instructions
960 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
961 string asm, string cstr, list<dag> pattern>
962 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
963 asm, cstr, pattern> {
969 let Inst{27-25} = 0b100;
970 let Inst{24-23} = amode;
971 let Inst{22} = 0; // S bit
972 let Inst{20} = 1; // L bit
973 let Inst{19-16} = Rn;
974 let Inst{15-0} = dsts;
976 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
977 string asm, string cstr, list<dag> pattern>
978 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
979 asm, cstr, pattern> {
985 let Inst{27-25} = 0b100;
986 let Inst{24-23} = amode;
987 let Inst{22} = 0; // S bit
988 let Inst{20} = 0; // L bit
989 let Inst{19-16} = Rn;
990 let Inst{15-0} = srcs;
993 // Unsigned multiply, multiply-accumulate instructions.
994 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
995 string opc, string asm, list<dag> pattern>
996 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
997 opc, asm, "", pattern> {
998 let Inst{7-4} = 0b1001;
999 let Inst{20} = 0; // S bit
1000 let Inst{27-21} = opcod;
1002 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
1003 string opc, string asm, list<dag> pattern>
1004 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
1005 opc, asm, "", pattern> {
1006 let Inst{7-4} = 0b1001;
1007 let Inst{27-21} = opcod;
1010 // Most significant word multiply
1011 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
1012 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1013 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
1014 opc, asm, "", pattern> {
1018 let Inst{7-4} = opc7_4;
1020 let Inst{27-21} = opcod;
1021 let Inst{19-16} = Rd;
1022 let Inst{11-8} = Rm;
1025 // MSW multiple w/ Ra operand
1026 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
1027 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1028 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
1030 let Inst{15-12} = Ra;
1033 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
1034 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1035 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1036 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
1037 opc, asm, "", pattern> {
1043 let Inst{27-21} = opcod;
1044 let Inst{6-5} = bit6_5;
1045 let Inst{11-8} = Rm;
1048 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1049 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1050 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1052 let Inst{19-16} = Rd;
1055 // AMulxyI with Ra operand
1056 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1057 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1058 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1060 let Inst{15-12} = Ra;
1063 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1064 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1065 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1068 let Inst{19-16} = RdHi;
1069 let Inst{15-12} = RdLo;
1072 // Extend instructions.
1073 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
1074 string opc, string asm, list<dag> pattern>
1075 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
1076 opc, asm, "", pattern> {
1077 // All AExtI instructions have Rd and Rm register operands.
1080 let Inst{15-12} = Rd;
1082 let Inst{7-4} = 0b0111;
1083 let Inst{9-8} = 0b00;
1084 let Inst{27-20} = opcod;
1087 // Misc Arithmetic instructions.
1088 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
1089 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1090 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1091 opc, asm, "", pattern> {
1094 let Inst{27-20} = opcod;
1095 let Inst{19-16} = 0b1111;
1096 let Inst{15-12} = Rd;
1097 let Inst{11-8} = 0b1111;
1098 let Inst{7-4} = opc7_4;
1103 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
1104 string opc, string asm, list<dag> pattern>
1105 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1106 opc, asm, "", pattern> {
1111 let Inst{27-20} = opcod;
1112 let Inst{19-16} = Rn;
1113 let Inst{15-12} = Rd;
1114 let Inst{11-7} = sh{7-3};
1116 let Inst{5-4} = 0b01;
1120 //===----------------------------------------------------------------------===//
1122 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
1123 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
1124 list<Predicate> Predicates = [IsARM];
1126 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
1127 list<Predicate> Predicates = [IsARM, HasV5TE];
1129 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1130 list<Predicate> Predicates = [IsARM, HasV6];
1133 //===----------------------------------------------------------------------===//
1135 // Thumb Instruction Format Definitions.
1138 // TI - Thumb instruction.
1140 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1141 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1142 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1143 let OutOperandList = oops;
1144 let InOperandList = iops;
1145 let AsmString = asm;
1146 let Pattern = pattern;
1147 list<Predicate> Predicates = [IsThumb];
1150 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1151 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1153 // Two-address instructions
1154 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1156 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
1159 // tBL, tBX 32-bit instructions
1160 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1161 dag oops, dag iops, InstrItinClass itin, string asm,
1163 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
1165 let Inst{31-27} = opcod1;
1166 let Inst{15-14} = opcod2;
1167 let Inst{12} = opcod3;
1170 // BR_JT instructions
1171 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1173 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1176 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1177 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1178 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1179 let OutOperandList = oops;
1180 let InOperandList = iops;
1181 let AsmString = asm;
1182 let Pattern = pattern;
1183 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1186 class T1I<dag oops, dag iops, InstrItinClass itin,
1187 string asm, list<dag> pattern>
1188 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1189 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1190 string asm, list<dag> pattern>
1191 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1192 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1193 string asm, list<dag> pattern>
1194 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1196 // Two-address instructions
1197 class T1It<dag oops, dag iops, InstrItinClass itin,
1198 string asm, string cstr, list<dag> pattern>
1199 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1200 asm, cstr, pattern>;
1202 // Thumb1 instruction that can either be predicated or set CPSR.
1203 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1204 InstrItinClass itin,
1205 string opc, string asm, string cstr, list<dag> pattern>
1206 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1207 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1208 let InOperandList = !con(iops, (ins pred:$p));
1209 let AsmString = !strconcat(opc, "${s}${p}", asm);
1210 let Pattern = pattern;
1211 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1214 class T1sI<dag oops, dag iops, InstrItinClass itin,
1215 string opc, string asm, list<dag> pattern>
1216 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1218 // Two-address instructions
1219 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1220 string opc, string asm, list<dag> pattern>
1221 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1222 "$lhs = $dst", pattern>;
1224 // Thumb1 instruction that can be predicated.
1225 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1226 InstrItinClass itin,
1227 string opc, string asm, string cstr, list<dag> pattern>
1228 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1229 let OutOperandList = oops;
1230 let InOperandList = !con(iops, (ins pred:$p));
1231 let AsmString = !strconcat(opc, "${p}", asm);
1232 let Pattern = pattern;
1233 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1236 class T1pI<dag oops, dag iops, InstrItinClass itin,
1237 string opc, string asm, list<dag> pattern>
1238 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1240 // Two-address instructions
1241 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1242 string opc, string asm, list<dag> pattern>
1243 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1244 "$lhs = $dst", pattern>;
1246 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1247 string opc, string asm, list<dag> pattern>
1248 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1249 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1250 string opc, string asm, list<dag> pattern>
1251 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1252 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1253 string opc, string asm, list<dag> pattern>
1254 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1255 class T1pIs<dag oops, dag iops,
1256 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1257 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1259 class Encoding16 : Encoding {
1260 let Inst{31-16} = 0x0000;
1263 // A6.2 16-bit Thumb instruction encoding
1264 class T1Encoding<bits<6> opcode> : Encoding16 {
1265 let Inst{15-10} = opcode;
1268 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1269 class T1General<bits<5> opcode> : Encoding16 {
1270 let Inst{15-14} = 0b00;
1271 let Inst{13-9} = opcode;
1274 // A6.2.2 Data-processing encoding.
1275 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1276 let Inst{15-10} = 0b010000;
1277 let Inst{9-6} = opcode;
1280 // A6.2.3 Special data instructions and branch and exchange encoding.
1281 class T1Special<bits<4> opcode> : Encoding16 {
1282 let Inst{15-10} = 0b010001;
1283 let Inst{9-6} = opcode;
1286 // A6.2.4 Load/store single data item encoding.
1287 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1288 let Inst{15-12} = opA;
1289 let Inst{11-9} = opB;
1291 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1292 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1293 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1294 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1295 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1297 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1298 class T1Misc<bits<7> opcode> : Encoding16 {
1299 let Inst{15-12} = 0b1011;
1300 let Inst{11-5} = opcode;
1303 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1304 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1305 InstrItinClass itin,
1306 string opc, string asm, string cstr, list<dag> pattern>
1307 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1308 let OutOperandList = oops;
1309 let InOperandList = !con(iops, (ins pred:$p));
1310 let AsmString = !strconcat(opc, "${p}", asm);
1311 let Pattern = pattern;
1312 list<Predicate> Predicates = [IsThumb2];
1315 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1316 // input operand since by default it's a zero register. It will become an
1317 // implicit def once it's "flipped".
1319 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1321 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1322 InstrItinClass itin,
1323 string opc, string asm, string cstr, list<dag> pattern>
1324 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1325 let OutOperandList = oops;
1326 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1327 let AsmString = !strconcat(opc, "${s}${p}", asm);
1328 let Pattern = pattern;
1329 list<Predicate> Predicates = [IsThumb2];
1333 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1334 InstrItinClass itin,
1335 string asm, string cstr, list<dag> pattern>
1336 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1337 let OutOperandList = oops;
1338 let InOperandList = iops;
1339 let AsmString = asm;
1340 let Pattern = pattern;
1341 list<Predicate> Predicates = [IsThumb2];
1344 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1345 InstrItinClass itin,
1346 string asm, string cstr, list<dag> pattern>
1347 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1348 let OutOperandList = oops;
1349 let InOperandList = iops;
1350 let AsmString = asm;
1351 let Pattern = pattern;
1352 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1355 class T2I<dag oops, dag iops, InstrItinClass itin,
1356 string opc, string asm, list<dag> pattern>
1357 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1358 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1359 string opc, string asm, list<dag> pattern>
1360 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1361 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1362 string opc, string asm, list<dag> pattern>
1363 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1364 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1365 string opc, string asm, list<dag> pattern>
1366 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1367 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1368 string opc, string asm, list<dag> pattern>
1369 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1370 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1371 string opc, string asm, list<dag> pattern>
1372 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1374 let Inst{31-27} = 0b11101;
1375 let Inst{26-25} = 0b00;
1377 let Inst{23} = ?; // The U bit.
1380 let Inst{20} = load;
1383 class T2sI<dag oops, dag iops, InstrItinClass itin,
1384 string opc, string asm, list<dag> pattern>
1385 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1387 class T2XI<dag oops, dag iops, InstrItinClass itin,
1388 string asm, list<dag> pattern>
1389 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1390 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1391 string asm, list<dag> pattern>
1392 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1394 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1395 string opc, string asm, list<dag> pattern>
1396 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1398 // Two-address instructions
1399 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1400 string asm, string cstr, list<dag> pattern>
1401 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1403 // T2Iidxldst - Thumb2 indexed load / store instructions.
1404 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1406 AddrMode am, IndexMode im, InstrItinClass itin,
1407 string opc, string asm, string cstr, list<dag> pattern>
1408 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1409 let OutOperandList = oops;
1410 let InOperandList = !con(iops, (ins pred:$p));
1411 let AsmString = !strconcat(opc, "${p}", asm);
1412 let Pattern = pattern;
1413 list<Predicate> Predicates = [IsThumb2];
1414 let Inst{31-27} = 0b11111;
1415 let Inst{26-25} = 0b00;
1416 let Inst{24} = signed;
1418 let Inst{22-21} = opcod;
1419 let Inst{20} = load;
1421 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1422 let Inst{10} = pre; // The P bit.
1423 let Inst{8} = 1; // The W bit.
1426 // Helper class for disassembly only
1427 // A6.3.16 & A6.3.17
1428 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1429 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1430 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1431 : T2I<oops, iops, itin, opc, asm, pattern> {
1432 let Inst{31-27} = 0b11111;
1433 let Inst{26-24} = 0b011;
1434 let Inst{23} = long;
1435 let Inst{22-20} = op22_20;
1436 let Inst{7-4} = op7_4;
1439 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1440 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1441 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1444 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1445 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1446 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1449 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1450 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1451 list<Predicate> Predicates = [IsThumb2];
1454 //===----------------------------------------------------------------------===//
1456 //===----------------------------------------------------------------------===//
1457 // ARM VFP Instruction templates.
1460 // Almost all VFP instructions are predicable.
1461 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1462 IndexMode im, Format f, InstrItinClass itin,
1463 string opc, string asm, string cstr, list<dag> pattern>
1464 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1466 let Inst{31-28} = p;
1467 let OutOperandList = oops;
1468 let InOperandList = !con(iops, (ins pred:$p));
1469 let AsmString = !strconcat(opc, "${p}", asm);
1470 let Pattern = pattern;
1471 list<Predicate> Predicates = [HasVFP2];
1475 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1476 IndexMode im, Format f, InstrItinClass itin,
1477 string asm, string cstr, list<dag> pattern>
1478 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1479 let OutOperandList = oops;
1480 let InOperandList = iops;
1481 let AsmString = asm;
1482 let Pattern = pattern;
1483 list<Predicate> Predicates = [HasVFP2];
1486 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1487 string opc, string asm, list<dag> pattern>
1488 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1489 opc, asm, "", pattern>;
1491 // ARM VFP addrmode5 loads and stores
1492 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1493 InstrItinClass itin,
1494 string opc, string asm, list<dag> pattern>
1495 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1496 VFPLdStFrm, itin, opc, asm, "", pattern> {
1497 // Instruction operands.
1501 // Encode instruction operands.
1502 let Inst{23} = addr{8}; // U (add = (U == '1'))
1503 let Inst{22} = Dd{4};
1504 let Inst{19-16} = addr{12-9}; // Rn
1505 let Inst{15-12} = Dd{3-0};
1506 let Inst{7-0} = addr{7-0}; // imm8
1508 // TODO: Mark the instructions with the appropriate subtarget info.
1509 let Inst{27-24} = opcod1;
1510 let Inst{21-20} = opcod2;
1511 let Inst{11-9} = 0b101;
1512 let Inst{8} = 1; // Double precision
1514 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1515 let D = VFPNeonDomain;
1518 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1519 InstrItinClass itin,
1520 string opc, string asm, list<dag> pattern>
1521 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1522 VFPLdStFrm, itin, opc, asm, "", pattern> {
1523 // Instruction operands.
1527 // Encode instruction operands.
1528 let Inst{23} = addr{8}; // U (add = (U == '1'))
1529 let Inst{22} = Sd{0};
1530 let Inst{19-16} = addr{12-9}; // Rn
1531 let Inst{15-12} = Sd{4-1};
1532 let Inst{7-0} = addr{7-0}; // imm8
1534 // TODO: Mark the instructions with the appropriate subtarget info.
1535 let Inst{27-24} = opcod1;
1536 let Inst{21-20} = opcod2;
1537 let Inst{11-9} = 0b101;
1538 let Inst{8} = 0; // Single precision
1541 // VFP Load / store multiple pseudo instructions.
1542 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1544 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1546 let OutOperandList = oops;
1547 let InOperandList = !con(iops, (ins pred:$p));
1548 let Pattern = pattern;
1549 list<Predicate> Predicates = [HasVFP2];
1552 // Load / store multiple
1553 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1554 string asm, string cstr, list<dag> pattern>
1555 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1556 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1557 // TODO: Mark the instructions with the appropriate subtarget info.
1558 let Inst{27-25} = 0b110;
1559 let Inst{11-9} = 0b101;
1560 let Inst{8} = 1; // Double precision
1562 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1563 let D = VFPNeonDomain;
1566 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1567 string asm, string cstr, list<dag> pattern>
1568 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1569 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1570 // TODO: Mark the instructions with the appropriate subtarget info.
1571 let Inst{27-25} = 0b110;
1572 let Inst{11-9} = 0b101;
1573 let Inst{8} = 0; // Single precision
1576 // Double precision, unary
1577 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1578 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1579 string asm, list<dag> pattern>
1580 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1581 // Instruction operands.
1585 // Encode instruction operands.
1586 let Inst{3-0} = Dm{3-0};
1587 let Inst{5} = Dm{4};
1588 let Inst{15-12} = Dd{3-0};
1589 let Inst{22} = Dd{4};
1591 let Inst{27-23} = opcod1;
1592 let Inst{21-20} = opcod2;
1593 let Inst{19-16} = opcod3;
1594 let Inst{11-9} = 0b101;
1595 let Inst{8} = 1; // Double precision
1596 let Inst{7-6} = opcod4;
1597 let Inst{4} = opcod5;
1600 // Double precision, binary
1601 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1602 dag iops, InstrItinClass itin, string opc, string asm,
1604 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1605 // Instruction operands.
1610 // Encode instruction operands.
1611 let Inst{3-0} = Dm{3-0};
1612 let Inst{5} = Dm{4};
1613 let Inst{19-16} = Dn{3-0};
1614 let Inst{7} = Dn{4};
1615 let Inst{15-12} = Dd{3-0};
1616 let Inst{22} = Dd{4};
1618 let Inst{27-23} = opcod1;
1619 let Inst{21-20} = opcod2;
1620 let Inst{11-9} = 0b101;
1621 let Inst{8} = 1; // Double precision
1626 // Double precision, binary, VML[AS] (for additional predicate)
1627 class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1628 dag iops, InstrItinClass itin, string opc, string asm,
1630 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1631 // Instruction operands.
1636 // Encode instruction operands.
1637 let Inst{19-16} = Dn{3-0};
1638 let Inst{7} = Dn{4};
1639 let Inst{15-12} = Dd{3-0};
1640 let Inst{22} = Dd{4};
1641 let Inst{3-0} = Dm{3-0};
1642 let Inst{5} = Dm{4};
1644 let Inst{27-23} = opcod1;
1645 let Inst{21-20} = opcod2;
1646 let Inst{11-9} = 0b101;
1647 let Inst{8} = 1; // Double precision
1650 list<Predicate> Predicates = [HasVFP2, UseVMLx];
1653 // Single precision, unary
1654 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1655 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1656 string asm, list<dag> pattern>
1657 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1658 // Instruction operands.
1662 // Encode instruction operands.
1663 let Inst{3-0} = Sm{4-1};
1664 let Inst{5} = Sm{0};
1665 let Inst{15-12} = Sd{4-1};
1666 let Inst{22} = Sd{0};
1668 let Inst{27-23} = opcod1;
1669 let Inst{21-20} = opcod2;
1670 let Inst{19-16} = opcod3;
1671 let Inst{11-9} = 0b101;
1672 let Inst{8} = 0; // Single precision
1673 let Inst{7-6} = opcod4;
1674 let Inst{4} = opcod5;
1677 // Single precision unary, if no NEON
1678 // Same as ASuI except not available if NEON is enabled
1679 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1680 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1681 string asm, list<dag> pattern>
1682 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1684 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1687 // Single precision, binary
1688 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1689 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1690 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1691 // Instruction operands.
1696 // Encode instruction operands.
1697 let Inst{3-0} = Sm{4-1};
1698 let Inst{5} = Sm{0};
1699 let Inst{19-16} = Sn{4-1};
1700 let Inst{7} = Sn{0};
1701 let Inst{15-12} = Sd{4-1};
1702 let Inst{22} = Sd{0};
1704 let Inst{27-23} = opcod1;
1705 let Inst{21-20} = opcod2;
1706 let Inst{11-9} = 0b101;
1707 let Inst{8} = 0; // Single precision
1712 // Single precision binary, if no NEON
1713 // Same as ASbI except not available if NEON is enabled
1714 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1715 dag iops, InstrItinClass itin, string opc, string asm,
1717 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1718 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1720 // Instruction operands.
1725 // Encode instruction operands.
1726 let Inst{3-0} = Sm{4-1};
1727 let Inst{5} = Sm{0};
1728 let Inst{19-16} = Sn{4-1};
1729 let Inst{7} = Sn{0};
1730 let Inst{15-12} = Sd{4-1};
1731 let Inst{22} = Sd{0};
1734 // VFP conversion instructions
1735 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1736 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1738 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1739 let Inst{27-23} = opcod1;
1740 let Inst{21-20} = opcod2;
1741 let Inst{19-16} = opcod3;
1742 let Inst{11-8} = opcod4;
1747 // VFP conversion between floating-point and fixed-point
1748 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1749 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1751 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1752 // size (fixed-point number): sx == 0 ? 16 : 32
1753 let Inst{7} = op5; // sx
1756 // VFP conversion instructions, if no NEON
1757 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1758 dag oops, dag iops, InstrItinClass itin,
1759 string opc, string asm, list<dag> pattern>
1760 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1762 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1765 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1766 InstrItinClass itin,
1767 string opc, string asm, list<dag> pattern>
1768 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1769 let Inst{27-20} = opcod1;
1770 let Inst{11-8} = opcod2;
1774 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1775 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1776 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1778 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1779 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1780 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1782 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1783 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1784 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1786 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1787 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1788 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1790 //===----------------------------------------------------------------------===//
1792 //===----------------------------------------------------------------------===//
1793 // ARM NEON Instruction templates.
1796 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1797 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1799 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1800 let OutOperandList = oops;
1801 let InOperandList = !con(iops, (ins pred:$p));
1802 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1803 let Pattern = pattern;
1804 list<Predicate> Predicates = [HasNEON];
1807 // Same as NeonI except it does not have a "data type" specifier.
1808 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1809 InstrItinClass itin, string opc, string asm, string cstr,
1811 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1812 let OutOperandList = oops;
1813 let InOperandList = !con(iops, (ins pred:$p));
1814 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1815 let Pattern = pattern;
1816 list<Predicate> Predicates = [HasNEON];
1819 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1820 dag oops, dag iops, InstrItinClass itin,
1821 string opc, string dt, string asm, string cstr, list<dag> pattern>
1822 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1824 let Inst{31-24} = 0b11110100;
1825 let Inst{23} = op23;
1826 let Inst{21-20} = op21_20;
1827 let Inst{11-8} = op11_8;
1828 let Inst{7-4} = op7_4;
1830 string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1836 let Inst{22} = Vd{4};
1837 let Inst{15-12} = Vd{3-0};
1838 let Inst{19-16} = Rn{3-0};
1839 let Inst{3-0} = Rm{3-0};
1842 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1843 dag oops, dag iops, InstrItinClass itin,
1844 string opc, string dt, string asm, string cstr, list<dag> pattern>
1845 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1846 dt, asm, cstr, pattern> {
1850 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1851 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1853 let OutOperandList = oops;
1854 let InOperandList = !con(iops, (ins pred:$p));
1855 list<Predicate> Predicates = [HasNEON];
1858 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1860 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1862 let OutOperandList = oops;
1863 let InOperandList = !con(iops, (ins pred:$p));
1864 let Pattern = pattern;
1865 list<Predicate> Predicates = [HasNEON];
1868 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1869 string opc, string dt, string asm, string cstr, list<dag> pattern>
1870 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1872 let Inst{31-25} = 0b1111001;
1873 string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1876 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1877 string opc, string asm, string cstr, list<dag> pattern>
1878 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1880 let Inst{31-25} = 0b1111001;
1883 // NEON "one register and a modified immediate" format.
1884 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1886 dag oops, dag iops, InstrItinClass itin,
1887 string opc, string dt, string asm, string cstr,
1889 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1890 let Inst{23} = op23;
1891 let Inst{21-19} = op21_19;
1892 let Inst{11-8} = op11_8;
1898 // Instruction operands.
1902 let Inst{15-12} = Vd{3-0};
1903 let Inst{22} = Vd{4};
1904 let Inst{24} = SIMM{7};
1905 let Inst{18-16} = SIMM{6-4};
1906 let Inst{3-0} = SIMM{3-0};
1909 // NEON 2 vector register format.
1910 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1911 bits<5> op11_7, bit op6, bit op4,
1912 dag oops, dag iops, InstrItinClass itin,
1913 string opc, string dt, string asm, string cstr, list<dag> pattern>
1914 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1915 let Inst{24-23} = op24_23;
1916 let Inst{21-20} = op21_20;
1917 let Inst{19-18} = op19_18;
1918 let Inst{17-16} = op17_16;
1919 let Inst{11-7} = op11_7;
1923 // Instruction operands.
1927 let Inst{15-12} = Vd{3-0};
1928 let Inst{22} = Vd{4};
1929 let Inst{3-0} = Vm{3-0};
1930 let Inst{5} = Vm{4};
1933 // Same as N2V except it doesn't have a datatype suffix.
1934 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1935 bits<5> op11_7, bit op6, bit op4,
1936 dag oops, dag iops, InstrItinClass itin,
1937 string opc, string asm, string cstr, list<dag> pattern>
1938 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1939 let Inst{24-23} = op24_23;
1940 let Inst{21-20} = op21_20;
1941 let Inst{19-18} = op19_18;
1942 let Inst{17-16} = op17_16;
1943 let Inst{11-7} = op11_7;
1947 // Instruction operands.
1951 let Inst{15-12} = Vd{3-0};
1952 let Inst{22} = Vd{4};
1953 let Inst{3-0} = Vm{3-0};
1954 let Inst{5} = Vm{4};
1957 // NEON 2 vector register with immediate.
1958 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1959 dag oops, dag iops, Format f, InstrItinClass itin,
1960 string opc, string dt, string asm, string cstr, list<dag> pattern>
1961 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1962 let Inst{24} = op24;
1963 let Inst{23} = op23;
1964 let Inst{11-8} = op11_8;
1969 // Instruction operands.
1974 let Inst{15-12} = Vd{3-0};
1975 let Inst{22} = Vd{4};
1976 let Inst{3-0} = Vm{3-0};
1977 let Inst{5} = Vm{4};
1978 let Inst{21-16} = SIMM{5-0};
1981 // NEON 3 vector register format.
1982 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1983 dag oops, dag iops, Format f, InstrItinClass itin,
1984 string opc, string dt, string asm, string cstr, list<dag> pattern>
1985 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1986 let Inst{24} = op24;
1987 let Inst{23} = op23;
1988 let Inst{21-20} = op21_20;
1989 let Inst{11-8} = op11_8;
1993 // Instruction operands.
1998 let Inst{15-12} = Vd{3-0};
1999 let Inst{22} = Vd{4};
2000 let Inst{19-16} = Vn{3-0};
2001 let Inst{7} = Vn{4};
2002 let Inst{3-0} = Vm{3-0};
2003 let Inst{5} = Vm{4};
2006 // Same as N3V except it doesn't have a data type suffix.
2007 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2009 dag oops, dag iops, Format f, InstrItinClass itin,
2010 string opc, string asm, string cstr, list<dag> pattern>
2011 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
2012 let Inst{24} = op24;
2013 let Inst{23} = op23;
2014 let Inst{21-20} = op21_20;
2015 let Inst{11-8} = op11_8;
2019 // Instruction operands.
2024 let Inst{15-12} = Vd{3-0};
2025 let Inst{22} = Vd{4};
2026 let Inst{19-16} = Vn{3-0};
2027 let Inst{7} = Vn{4};
2028 let Inst{3-0} = Vm{3-0};
2029 let Inst{5} = Vm{4};
2032 // NEON VMOVs between scalar and core registers.
2033 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2034 dag oops, dag iops, Format f, InstrItinClass itin,
2035 string opc, string dt, string asm, list<dag> pattern>
2036 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
2038 let Inst{27-20} = opcod1;
2039 let Inst{11-8} = opcod2;
2040 let Inst{6-5} = opcod3;
2043 let OutOperandList = oops;
2044 let InOperandList = !con(iops, (ins pred:$p));
2045 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
2046 let Pattern = pattern;
2047 list<Predicate> Predicates = [HasNEON];
2054 let Inst{31-28} = p{3-0};
2056 let Inst{19-16} = V{3-0};
2057 let Inst{15-12} = R{3-0};
2059 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2060 dag oops, dag iops, InstrItinClass itin,
2061 string opc, string dt, string asm, list<dag> pattern>
2062 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
2063 opc, dt, asm, pattern>;
2064 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2065 dag oops, dag iops, InstrItinClass itin,
2066 string opc, string dt, string asm, list<dag> pattern>
2067 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
2068 opc, dt, asm, pattern>;
2069 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2070 dag oops, dag iops, InstrItinClass itin,
2071 string opc, string dt, string asm, list<dag> pattern>
2072 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
2073 opc, dt, asm, pattern>;
2075 // Vector Duplicate Lane (from scalar to all elements)
2076 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2077 InstrItinClass itin, string opc, string dt, string asm,
2079 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2080 let Inst{24-23} = 0b11;
2081 let Inst{21-20} = 0b11;
2082 let Inst{19-16} = op19_16;
2083 let Inst{11-7} = 0b11000;
2091 let Inst{22} = Vd{4};
2092 let Inst{15-12} = Vd{3-0};
2093 let Inst{5} = Vm{4};
2094 let Inst{3-0} = Vm{3-0};
2097 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2098 // for single-precision FP.
2099 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2100 list<Predicate> Predicates = [HasNEON,UseNEONForFP];