1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def BrFrm : Format<3>;
25 def BrMiscFrm : Format<4>;
27 def DPFrm : Format<5>;
28 def DPSoRegFrm : Format<6>;
30 def LdFrm : Format<7>;
31 def StFrm : Format<8>;
32 def LdMiscFrm : Format<9>;
33 def StMiscFrm : Format<10>;
34 def LdMulFrm : Format<11>;
35 def StMulFrm : Format<12>;
37 def ArithMiscFrm : Format<13>;
38 def ExtFrm : Format<14>;
40 def VFPUnaryFrm : Format<15>;
41 def VFPBinaryFrm : Format<16>;
42 def VFPConv1Frm : Format<17>;
43 def VFPConv2Frm : Format<18>;
44 def VFPConv3Frm : Format<19>;
45 def VFPLdStFrm : Format<20>;
46 def VFPLdStMulFrm : Format<21>;
47 def VFPMiscFrm : Format<22>;
49 def ThumbFrm : Format<23>;
51 // Misc flag for data processing instructions that indicates whether
52 // the instruction has a Rn register operand.
53 class UnaryDP { bit isUnaryDataProc = 1; }
55 //===----------------------------------------------------------------------===//
57 // ARM Instruction templates.
60 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
61 Format f, string cstr>
65 let Namespace = "ARM";
69 bits<4> AddrModeBits = AM.Value;
72 bits<3> SizeFlag = SZ.Value;
75 bits<2> IndexModeBits = IM.Value;
78 bits<5> Form = F.Value;
81 // Attributes specific to ARM instructions...
83 bit isUnaryDataProc = 0;
85 let Constraints = cstr;
88 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
89 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
90 let OutOperandList = oops;
91 let InOperandList = iops;
93 let Pattern = pattern;
96 // Almost all ARM instructions are predicable.
97 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
98 IndexMode im, Format f, string opc, string asm, string cstr,
100 : InstARM<am, sz, im, f, cstr> {
101 let OutOperandList = oops;
102 let InOperandList = !con(iops, (ops pred:$p));
103 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
104 let Pattern = pattern;
105 list<Predicate> Predicates = [IsARM];
108 // Same as I except it can optionally modify CPSR. Note it's modeled as
109 // an input operand since by default it's a zero register. It will
110 // become an implicit def once it's "flipped".
111 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
112 IndexMode im, Format f, string opc, string asm, string cstr,
114 : InstARM<am, sz, im, f, cstr> {
115 let OutOperandList = oops;
116 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
117 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
118 let Pattern = pattern;
119 list<Predicate> Predicates = [IsARM];
123 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
124 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
125 : InstARM<am, sz, im, f, cstr> {
126 let OutOperandList = oops;
127 let InOperandList = iops;
129 let Pattern = pattern;
130 list<Predicate> Predicates = [IsARM];
133 class AI<dag oops, dag iops, Format f, string opc,
134 string asm, list<dag> pattern>
135 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
137 class AsI<dag oops, dag iops, Format f, string opc,
138 string asm, list<dag> pattern>
139 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
141 class AXI<dag oops, dag iops, Format f, string asm,
143 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
146 // Ctrl flow instructions
147 class ABI<bits<4> opcod, dag oops, dag iops, string opc,
148 string asm, list<dag> pattern>
149 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
151 let Inst{27-24} = opcod;
153 class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
154 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
156 let Inst{27-24} = opcod;
158 class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
159 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
162 // BR_JT instructions
163 class JTI<dag oops, dag iops, string asm, list<dag> pattern>
164 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
167 // addrmode1 instructions
168 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
169 string asm, list<dag> pattern>
170 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
172 let Inst{24-21} = opcod;
173 let Inst{27-26} = {0,0};
175 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
176 string asm, list<dag> pattern>
177 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
179 let Inst{24-21} = opcod;
180 let Inst{27-26} = {0,0};
182 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
184 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
186 let Inst{24-21} = opcod;
187 let Inst{27-26} = {0,0};
189 class AI1x2<dag oops, dag iops, Format f, string opc,
190 string asm, list<dag> pattern>
191 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
195 // addrmode2 loads and stores
196 class AI2<dag oops, dag iops, Format f, string opc,
197 string asm, list<dag> pattern>
198 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
200 let Inst{27-26} = {0,1};
204 class AI2ldw<dag oops, dag iops, Format f, string opc,
205 string asm, list<dag> pattern>
206 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
208 let Inst{20} = 1; // L bit
209 let Inst{21} = 0; // W bit
210 let Inst{22} = 0; // B bit
211 let Inst{24} = 1; // P bit
212 let Inst{27-26} = {0,1};
214 class AXI2ldw<dag oops, dag iops, Format f, string asm,
216 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
218 let Inst{20} = 1; // L bit
219 let Inst{21} = 0; // W bit
220 let Inst{22} = 0; // B bit
221 let Inst{24} = 1; // P bit
222 let Inst{27-26} = {0,1};
224 class AI2ldb<dag oops, dag iops, Format f, string opc,
225 string asm, list<dag> pattern>
226 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
228 let Inst{20} = 1; // L bit
229 let Inst{21} = 0; // W bit
230 let Inst{22} = 1; // B bit
231 let Inst{24} = 1; // P bit
232 let Inst{27-26} = {0,1};
234 class AXI2ldb<dag oops, dag iops, Format f, string asm,
236 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
238 let Inst{20} = 1; // L bit
239 let Inst{21} = 0; // W bit
240 let Inst{22} = 1; // B bit
241 let Inst{24} = 1; // P bit
242 let Inst{27-26} = {0,1};
246 class AI2stw<dag oops, dag iops, Format f, string opc,
247 string asm, list<dag> pattern>
248 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
250 let Inst{20} = 0; // L bit
251 let Inst{21} = 0; // W bit
252 let Inst{22} = 0; // B bit
253 let Inst{24} = 1; // P bit
254 let Inst{27-26} = {0,1};
256 class AXI2stw<dag oops, dag iops, Format f, string asm,
258 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
260 let Inst{20} = 0; // L bit
261 let Inst{21} = 0; // W bit
262 let Inst{22} = 0; // B bit
263 let Inst{24} = 1; // P bit
264 let Inst{27-26} = {0,1};
266 class AI2stb<dag oops, dag iops, Format f, string opc,
267 string asm, list<dag> pattern>
268 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
270 let Inst{20} = 0; // L bit
271 let Inst{21} = 0; // W bit
272 let Inst{22} = 1; // B bit
273 let Inst{24} = 1; // P bit
274 let Inst{27-26} = {0,1};
276 class AXI2stb<dag oops, dag iops, Format f, string asm,
278 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
280 let Inst{20} = 0; // L bit
281 let Inst{21} = 0; // W bit
282 let Inst{22} = 1; // B bit
283 let Inst{24} = 1; // P bit
284 let Inst{27-26} = {0,1};
288 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
289 string asm, string cstr, list<dag> pattern>
290 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
291 asm, cstr, pattern> {
292 let Inst{20} = 1; // L bit
293 let Inst{21} = 1; // W bit
294 let Inst{22} = 0; // B bit
295 let Inst{24} = 1; // P bit
296 let Inst{27-26} = {0,1};
298 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
299 string asm, string cstr, list<dag> pattern>
300 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
301 asm, cstr, pattern> {
302 let Inst{20} = 1; // L bit
303 let Inst{21} = 1; // W bit
304 let Inst{22} = 1; // B bit
305 let Inst{24} = 1; // P bit
306 let Inst{27-26} = {0,1};
309 // Pre-indexed stores
310 class AI2stwpr<dag oops, dag iops, Format f, string opc,
311 string asm, string cstr, list<dag> pattern>
312 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
313 asm, cstr, pattern> {
314 let Inst{20} = 0; // L bit
315 let Inst{21} = 1; // W bit
316 let Inst{22} = 0; // B bit
317 let Inst{24} = 1; // P bit
318 let Inst{27-26} = {0,1};
320 class AI2stbpr<dag oops, dag iops, Format f, string opc,
321 string asm, string cstr, list<dag> pattern>
322 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
323 asm, cstr, pattern> {
324 let Inst{20} = 0; // L bit
325 let Inst{21} = 1; // W bit
326 let Inst{22} = 1; // B bit
327 let Inst{24} = 1; // P bit
328 let Inst{27-26} = {0,1};
331 // Post-indexed loads
332 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
333 string asm, string cstr, list<dag> pattern>
334 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
336 let Inst{20} = 1; // L bit
337 let Inst{21} = 0; // W bit
338 let Inst{22} = 0; // B bit
339 let Inst{24} = 0; // P bit
340 let Inst{27-26} = {0,1};
342 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
343 string asm, string cstr, list<dag> pattern>
344 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
346 let Inst{20} = 1; // L bit
347 let Inst{21} = 0; // W bit
348 let Inst{22} = 1; // B bit
349 let Inst{24} = 0; // P bit
350 let Inst{27-26} = {0,1};
353 // Post-indexed stores
354 class AI2stwpo<dag oops, dag iops, Format f, string opc,
355 string asm, string cstr, list<dag> pattern>
356 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
358 let Inst{20} = 0; // L bit
359 let Inst{21} = 0; // W bit
360 let Inst{22} = 0; // B bit
361 let Inst{24} = 0; // P bit
362 let Inst{27-26} = {0,1};
364 class AI2stbpo<dag oops, dag iops, Format f, string opc,
365 string asm, string cstr, list<dag> pattern>
366 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
368 let Inst{20} = 0; // L bit
369 let Inst{21} = 0; // W bit
370 let Inst{22} = 1; // B bit
371 let Inst{24} = 0; // P bit
372 let Inst{27-26} = {0,1};
375 // addrmode3 instructions
376 class AI3<dag oops, dag iops, Format f, string opc,
377 string asm, list<dag> pattern>
378 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
380 class AXI3<dag oops, dag iops, Format f, string asm,
382 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
386 class AI3ldh<dag oops, dag iops, Format f, string opc,
387 string asm, list<dag> pattern>
388 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
391 let Inst{5} = 1; // H bit
392 let Inst{6} = 0; // S bit
394 let Inst{20} = 1; // L bit
395 let Inst{21} = 0; // W bit
396 let Inst{24} = 1; // P bit
398 class AXI3ldh<dag oops, dag iops, Format f, string asm,
400 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
403 let Inst{5} = 1; // H bit
404 let Inst{6} = 0; // S bit
406 let Inst{20} = 1; // L bit
407 let Inst{21} = 0; // W bit
408 let Inst{24} = 1; // P bit
410 class AI3ldsh<dag oops, dag iops, Format f, string opc,
411 string asm, list<dag> pattern>
412 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
415 let Inst{5} = 1; // H bit
416 let Inst{6} = 1; // S bit
418 let Inst{20} = 1; // L bit
419 let Inst{21} = 0; // W bit
420 let Inst{24} = 1; // P bit
422 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
424 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
427 let Inst{5} = 1; // H bit
428 let Inst{6} = 1; // S bit
430 let Inst{20} = 1; // L bit
431 let Inst{21} = 0; // W bit
432 let Inst{24} = 1; // P bit
434 class AI3ldsb<dag oops, dag iops, Format f, string opc,
435 string asm, list<dag> pattern>
436 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
439 let Inst{5} = 0; // H bit
440 let Inst{6} = 1; // S bit
442 let Inst{20} = 1; // L bit
443 let Inst{21} = 0; // W bit
444 let Inst{24} = 1; // P bit
446 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
448 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
451 let Inst{5} = 0; // H bit
452 let Inst{6} = 1; // S bit
454 let Inst{20} = 1; // L bit
455 let Inst{21} = 0; // W bit
456 let Inst{24} = 1; // P bit
458 class AI3ldd<dag oops, dag iops, Format f, string opc,
459 string asm, list<dag> pattern>
460 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
463 let Inst{5} = 0; // H bit
464 let Inst{6} = 1; // S bit
466 let Inst{20} = 0; // L bit
467 let Inst{21} = 0; // W bit
468 let Inst{24} = 1; // P bit
472 class AI3sth<dag oops, dag iops, Format f, string opc,
473 string asm, list<dag> pattern>
474 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
477 let Inst{5} = 1; // H bit
478 let Inst{6} = 0; // S bit
480 let Inst{20} = 0; // L bit
481 let Inst{21} = 0; // W bit
482 let Inst{24} = 1; // P bit
484 class AXI3sth<dag oops, dag iops, Format f, string asm,
486 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
489 let Inst{5} = 1; // H bit
490 let Inst{6} = 0; // S bit
492 let Inst{20} = 0; // L bit
493 let Inst{21} = 0; // W bit
494 let Inst{24} = 1; // P bit
496 class AI3std<dag oops, dag iops, Format f, string opc,
497 string asm, list<dag> pattern>
498 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
501 let Inst{5} = 1; // H bit
502 let Inst{6} = 1; // S bit
504 let Inst{20} = 0; // L bit
505 let Inst{21} = 0; // W bit
506 let Inst{24} = 1; // P bit
510 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
511 string asm, string cstr, list<dag> pattern>
512 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
513 asm, cstr, pattern> {
515 let Inst{5} = 1; // H bit
516 let Inst{6} = 0; // S bit
518 let Inst{20} = 1; // L bit
519 let Inst{21} = 1; // W bit
520 let Inst{24} = 1; // P bit
522 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
523 string asm, string cstr, list<dag> pattern>
524 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
525 asm, cstr, pattern> {
527 let Inst{5} = 1; // H bit
528 let Inst{6} = 1; // S bit
530 let Inst{20} = 1; // L bit
531 let Inst{21} = 1; // W bit
532 let Inst{24} = 1; // P bit
534 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
535 string asm, string cstr, list<dag> pattern>
536 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
537 asm, cstr, pattern> {
539 let Inst{5} = 0; // H bit
540 let Inst{6} = 1; // S bit
542 let Inst{20} = 1; // L bit
543 let Inst{21} = 1; // W bit
544 let Inst{24} = 1; // P bit
547 // Pre-indexed stores
548 class AI3sthpr<dag oops, dag iops, Format f, string opc,
549 string asm, string cstr, list<dag> pattern>
550 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
551 asm, cstr, pattern> {
553 let Inst{5} = 1; // H bit
554 let Inst{6} = 0; // S bit
556 let Inst{20} = 0; // L bit
557 let Inst{21} = 1; // W bit
558 let Inst{24} = 1; // P bit
561 // Post-indexed loads
562 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
563 string asm, string cstr, list<dag> pattern>
564 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
567 let Inst{5} = 1; // H bit
568 let Inst{6} = 0; // S bit
570 let Inst{20} = 1; // L bit
571 let Inst{21} = 1; // W bit
572 let Inst{24} = 0; // P bit
574 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
575 string asm, string cstr, list<dag> pattern>
576 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
579 let Inst{5} = 1; // H bit
580 let Inst{6} = 1; // S bit
582 let Inst{20} = 1; // L bit
583 let Inst{21} = 1; // W bit
584 let Inst{24} = 0; // P bit
586 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
587 string asm, string cstr, list<dag> pattern>
588 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
591 let Inst{5} = 0; // H bit
592 let Inst{6} = 1; // S bit
594 let Inst{20} = 1; // L bit
595 let Inst{21} = 1; // W bit
596 let Inst{24} = 0; // P bit
599 // Post-indexed stores
600 class AI3sthpo<dag oops, dag iops, Format f, string opc,
601 string asm, string cstr, list<dag> pattern>
602 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
605 let Inst{5} = 1; // H bit
606 let Inst{6} = 0; // S bit
608 let Inst{20} = 0; // L bit
609 let Inst{21} = 1; // W bit
610 let Inst{24} = 0; // P bit
614 // addrmode4 instructions
615 class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
616 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
618 let Inst{20} = 1; // L bit
619 let Inst{22} = 0; // S bit
620 let Inst{27-25} = 0b100;
622 class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
623 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
625 let Inst{20} = 0; // L bit
626 let Inst{22} = 0; // S bit
627 let Inst{27-25} = 0b100;
630 // Unsigned multiply, multiply-accumulate instructions.
631 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
632 string asm, list<dag> pattern>
633 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
635 let Inst{7-4} = 0b1001;
636 let Inst{20} = 0; // S bit
637 let Inst{27-21} = opcod;
639 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
640 string asm, list<dag> pattern>
641 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
643 let Inst{7-4} = 0b1001;
644 let Inst{27-21} = opcod;
647 // Most significant word multiply
648 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
649 string asm, list<dag> pattern>
650 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
652 let Inst{7-4} = 0b1001;
654 let Inst{27-21} = opcod;
657 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
658 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
659 string asm, list<dag> pattern>
660 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
665 let Inst{27-21} = opcod;
668 // Extend instructions.
669 class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
670 string asm, list<dag> pattern>
671 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
673 let Inst{7-4} = 0b0111;
674 let Inst{27-20} = opcod;
677 // Misc Arithmetic instructions.
678 class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc,
679 string asm, list<dag> pattern>
680 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc,
682 let Inst{27-20} = opcod;
685 //===----------------------------------------------------------------------===//
687 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
688 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
689 list<Predicate> Predicates = [IsARM];
691 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
692 list<Predicate> Predicates = [IsARM, HasV5TE];
694 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
695 list<Predicate> Predicates = [IsARM, HasV6];
698 //===----------------------------------------------------------------------===//
700 // Thumb Instruction Format Definitions.
704 // TI - Thumb instruction.
706 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
707 string asm, string cstr, list<dag> pattern>
708 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
709 let OutOperandList = outs;
710 let InOperandList = ins;
712 let Pattern = pattern;
713 list<Predicate> Predicates = [IsThumb];
716 class TI<dag outs, dag ins, string asm, list<dag> pattern>
717 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
718 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
719 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
720 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
721 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
722 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
723 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
724 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
725 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
727 // Two-address instructions
728 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
729 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
731 // BL, BLX(1) are translated by assembler into two instructions
732 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
733 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
735 // BR_JT instructions
736 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
737 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
740 //===----------------------------------------------------------------------===//
742 //===----------------------------------------------------------------------===//
743 // ARM VFP Instruction templates.
746 // ARM VFP addrmode5 loads and stores
747 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
748 string opc, string asm, list<dag> pattern>
749 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
750 VFPLdStFrm, opc, asm, "", pattern> {
751 // TODO: Mark the instructions with the appropriate subtarget info.
752 let Inst{27-24} = opcod1;
753 let Inst{21-20} = opcod2;
754 let Inst{11-8} = 0b1011;
757 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
758 string opc, string asm, list<dag> pattern>
759 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
760 VFPLdStFrm, opc, asm, "", pattern> {
761 // TODO: Mark the instructions with the appropriate subtarget info.
762 let Inst{27-24} = opcod1;
763 let Inst{21-20} = opcod2;
764 let Inst{11-8} = 0b1010;
767 // Load / store multiple
768 class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
769 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
770 VFPLdStMulFrm, asm, "", pattern> {
771 // TODO: Mark the instructions with the appropriate subtarget info.
772 let Inst{27-25} = 0b110;
773 let Inst{11-8} = 0b1011;
776 class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
777 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
778 VFPLdStMulFrm, asm, "", pattern> {
779 // TODO: Mark the instructions with the appropriate subtarget info.
780 let Inst{27-25} = 0b110;
781 let Inst{11-8} = 0b1010;
785 // Double precision, unary
786 class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
787 string opc, string asm, list<dag> pattern>
788 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
789 let Inst{27-20} = opcod1;
790 let Inst{19-16} = opcod2;
791 let Inst{11-8} = 0b1011;
792 let Inst{7-4} = opcod3;
795 // Double precision, binary
796 class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
797 string asm, list<dag> pattern>
798 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
799 let Inst{27-20} = opcod;
800 let Inst{11-8} = 0b1011;
803 // Single precision, unary
804 class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
805 string opc, string asm, list<dag> pattern>
806 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
807 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
808 let Inst{27-20} = opcod1;
809 let Inst{19-16} = opcod2;
810 let Inst{11-8} = 0b1010;
811 let Inst{7-4} = opcod3;
814 // Single precision, binary
815 class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
816 string asm, list<dag> pattern>
817 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
818 // Bit 22 (D bit) can be changed during instruction encoding.
819 let Inst{27-20} = opcod;
820 let Inst{11-8} = 0b1010;
823 class AVConv1I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
824 string asm, list<dag> pattern>
825 : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
826 let Inst{27-20} = opcod1;
827 let Inst{11-8} = opcod2;
831 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
832 string asm, list<dag> pattern>
833 : AI<oops, iops, VFPConv2Frm, opc, asm, pattern> {
834 let Inst{27-20} = opcod1;
835 let Inst{11-8} = opcod2;
839 class AVConv3I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
840 dag oops, dag iops, string opc, string asm, list<dag> pattern>
841 : AI<oops, iops, VFPConv3Frm, opc, asm, pattern> {
842 let Inst{27-20} = opcod1;
843 let Inst{19-16} = opcod2;
844 let Inst{11-8} = opcod3;
848 //===----------------------------------------------------------------------===//
851 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
852 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
853 list<Predicate> Predicates = [IsThumb];
856 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
857 list<Predicate> Predicates = [IsThumb, HasV5T];