1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
23 class ARMConstantPoolValue;
27 // ARM Specific DAG Nodes
29 // Start the numbering where the builting ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
32 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
33 // TargetExternalSymbol, and TargetGlobalAddress.
34 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
36 CALL, // Function call.
37 CALL_NOLINK, // Function call with branch not branch-and-link.
38 tCALL, // Thumb function call.
39 BRCOND, // Conditional branch.
40 BR_JT, // Jumptable branch.
41 RET_FLAG, // Return with a flag operand.
43 PIC_ADD, // Add with a PC operand and a PIC label.
45 CMP, // ARM compare instructions.
46 CMPFP, // ARM VFP compare instruction, sets FPSCR.
47 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
48 FMSTAT, // ARM fmstat instruction.
49 CMOV, // ARM conditional move instructions.
50 CNEG, // ARM conditional negate instructions.
52 FTOSI, // FP to sint within a FP register.
53 FTOUI, // FP to uint within a FP register.
54 SITOF, // sint to FP within a FP register.
55 UITOF, // uint to FP within a FP register.
57 MULHILOU, // Lo,Hi = umul LHS, RHS.
58 MULHILOS, // Lo,Hi = smul LHS, RHS.
60 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
61 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
62 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
64 FMRRD, // double to two gprs.
65 FMDRR // Two gprs to double.
69 //===----------------------------------------------------------------------===//
70 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
72 class ARMTargetLowering : public TargetLowering {
73 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
75 ARMTargetLowering(TargetMachine &TM);
77 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
78 virtual const char *getTargetNodeName(unsigned Opcode) const;
80 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
81 MachineBasicBlock *MBB);
83 /// isLegalAddressImmediate - Return true if the integer value can be used
84 /// as the offset of the target addressing mode for load / store of the
86 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
88 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
89 /// the offset of the target addressing mode.
90 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
92 /// isLegalAddressScale - Return true if the integer value can be used as
93 /// the scale of the target addressing mode for load / store of the given
95 virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const;
97 /// isLegalAddressScaleAndImm - Return true if S works for
98 /// IsLegalAddressScale and V works for isLegalAddressImmediate _and_
99 /// both can be applied simultaneously to the same instruction.
100 virtual bool isLegalAddressScaleAndImm(int64_t S, int64_t V,
101 const Type *Ty) const;
103 /// isLegalAddressScaleAndImm - Return true if S works for
104 /// IsLegalAddressScale and GV works for isLegalAddressImmediate _and_
105 /// both can be applied simultaneously to the same instruction.
106 virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV,
107 const Type *Ty) const;
109 /// getPreIndexedAddressParts - returns true by value, base pointer and
110 /// offset pointer and addressing mode by reference if the node's address
111 /// can be legally represented as pre-indexed load / store address.
112 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
114 ISD::MemIndexedMode &AM,
117 /// getPostIndexedAddressParts - returns true by value, base pointer and
118 /// offset pointer and addressing mode by reference if this node can be
119 /// combined with a load / store to form a post-indexed load / store.
120 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
121 SDOperand &Base, SDOperand &Offset,
122 ISD::MemIndexedMode &AM,
125 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
129 unsigned Depth) const;
130 ConstraintType getConstraintType(const std::string &Constraint) const;
131 std::pair<unsigned, const TargetRegisterClass*>
132 getRegForInlineAsmConstraint(const std::string &Constraint,
133 MVT::ValueType VT) const;
134 std::vector<unsigned>
135 getRegClassForInlineAsmConstraint(const std::string &Constraint,
136 MVT::ValueType VT) const;
138 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
139 /// make the right decision when generating code for different targets.
140 const ARMSubtarget *Subtarget;
142 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
144 unsigned ARMPCLabelIndex;
146 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
147 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
148 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
149 SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
153 #endif // ARMISELLOWERING_H