1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
69 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
70 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
72 ADDC, // Add with carry
73 ADDE, // Add using carry
74 SUBC, // Sub with carry
75 SUBE, // Sub using carry
77 VMOVRRD, // double to two gprs.
78 VMOVDRR, // Two gprs to double.
80 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
81 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
82 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
84 TC_RETURN, // Tail call return pseudo.
88 DYN_ALLOC, // Dynamic allocation on the stack.
90 MEMBARRIER_MCR, // Memory barrier (MCR)
94 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
96 VCEQ, // Vector compare equal.
97 VCEQZ, // Vector compare equal to zero.
98 VCGE, // Vector compare greater than or equal.
99 VCGEZ, // Vector compare greater than or equal to zero.
100 VCLEZ, // Vector compare less than or equal to zero.
101 VCGEU, // Vector compare unsigned greater than or equal.
102 VCGT, // Vector compare greater than.
103 VCGTZ, // Vector compare greater than zero.
104 VCLTZ, // Vector compare less than zero.
105 VCGTU, // Vector compare unsigned greater than.
106 VTST, // Vector test bits.
108 // Vector shift by immediate:
110 VSHRs, // ...right (signed)
111 VSHRu, // ...right (unsigned)
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
131 // Vector shift and insert:
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
140 // Vector move immediate and move negated immediate:
144 // Vector move f32 immediate:
153 VREV64, // reverse elements within 64-bit doublewords
154 VREV32, // reverse elements within 32-bit words
155 VREV16, // reverse elements within 16-bit halfwords
156 VZIP, // zip (interleave)
157 VUZP, // unzip (deinterleave)
159 VTBL1, // 1-register shuffle with mask
160 VTBL2, // 2-register shuffle with mask
162 // Vector multiply long:
164 VMULLu, // ...unsigned
166 UMLAL, // 64bit Unsigned Accumulate Multiply
167 SMLAL, // 64bit Signed Accumulate Multiply
169 // Operands of the standard BUILD_VECTOR node are not legalized, which
170 // is fine if BUILD_VECTORs are always lowered to shuffles or other
171 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
172 // operands need to be legalized. Define an ARM-specific version of
173 // BUILD_VECTOR for this purpose.
176 // Floating-point max and min:
185 // Vector OR with immediate
187 // Vector AND with NOT of immediate
190 // Vector bitwise select
193 // Vector load N-element structure to all lanes:
194 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
198 // NEON loads with post-increment base updates:
210 // NEON stores with post-increment base updates:
221 /// Define some predicates that are used for node matching.
223 bool isBitFieldInvertedMask(unsigned v);
226 //===--------------------------------------------------------------------===//
227 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
229 class ARMTargetLowering : public TargetLowering {
231 explicit ARMTargetLowering(const TargetMachine &TM,
232 const ARMSubtarget &STI);
234 unsigned getJumpTableEncoding() const override;
235 bool useSoftFloat() const override;
237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
239 /// ReplaceNodeResults - Replace the results of node with an illegal result
240 /// type with new values built out of custom code.
242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
243 SelectionDAG &DAG) const override;
245 const char *getTargetNodeName(unsigned Opcode) const override;
247 bool isSelectSupported(SelectSupportKind Kind) const override {
248 // ARM does not support scalar condition selects on vectors.
249 return (Kind != ScalarCondVectorVal);
252 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
253 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
254 EVT VT) const override;
257 EmitInstrWithCustomInserter(MachineInstr *MI,
258 MachineBasicBlock *MBB) const override;
260 void AdjustInstrPostInstrSelection(MachineInstr *MI,
261 SDNode *Node) const override;
263 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
264 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
266 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
268 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
269 /// unaligned memory accesses of the specified type. Returns whether it
270 /// is "fast" by reference in the second argument.
271 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
273 bool *Fast) const override;
275 EVT getOptimalMemOpType(uint64_t Size,
276 unsigned DstAlign, unsigned SrcAlign,
277 bool IsMemset, bool ZeroMemset,
279 MachineFunction &MF) const override;
281 using TargetLowering::isZExtFree;
282 bool isZExtFree(SDValue Val, EVT VT2) const override;
284 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
286 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
289 /// isLegalAddressingMode - Return true if the addressing mode represented
290 /// by AM is legal for this target, for a load/store of the specified type.
291 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
292 Type *Ty, unsigned AS) const override;
293 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
295 /// isLegalICmpImmediate - Return true if the specified immediate is legal
296 /// icmp immediate, that is the target has icmp instructions which can
297 /// compare a register against the immediate without having to materialize
298 /// the immediate into a register.
299 bool isLegalICmpImmediate(int64_t Imm) const override;
301 /// isLegalAddImmediate - Return true if the specified immediate is legal
302 /// add immediate, that is the target has add instructions which can
303 /// add a register and the immediate without having to materialize
304 /// the immediate into a register.
305 bool isLegalAddImmediate(int64_t Imm) const override;
307 /// getPreIndexedAddressParts - returns true by value, base pointer and
308 /// offset pointer and addressing mode by reference if the node's address
309 /// can be legally represented as pre-indexed load / store address.
310 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
311 ISD::MemIndexedMode &AM,
312 SelectionDAG &DAG) const override;
314 /// getPostIndexedAddressParts - returns true by value, base pointer and
315 /// offset pointer and addressing mode by reference if this node can be
316 /// combined with a load / store to form a post-indexed load / store.
317 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
318 SDValue &Offset, ISD::MemIndexedMode &AM,
319 SelectionDAG &DAG) const override;
321 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
323 const SelectionDAG &DAG,
324 unsigned Depth) const override;
327 bool ExpandInlineAsm(CallInst *CI) const override;
329 ConstraintType getConstraintType(StringRef Constraint) const override;
331 /// Examine constraint string and operand type and determine a weight value.
332 /// The operand object must already have been set up with the operand type.
333 ConstraintWeight getSingleConstraintMatchWeight(
334 AsmOperandInfo &info, const char *constraint) const override;
336 std::pair<unsigned, const TargetRegisterClass *>
337 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
338 StringRef Constraint, MVT VT) const override;
340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
341 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
342 /// true it means one of the asm constraint of the inline asm instruction
343 /// being processed is 'm'.
344 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
345 std::vector<SDValue> &Ops,
346 SelectionDAG &DAG) const override;
349 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
350 if (ConstraintCode == "Q")
351 return InlineAsm::Constraint_Q;
352 else if (ConstraintCode.size() == 2) {
353 if (ConstraintCode[0] == 'U') {
354 switch(ConstraintCode[1]) {
358 return InlineAsm::Constraint_Um;
360 return InlineAsm::Constraint_Un;
362 return InlineAsm::Constraint_Uq;
364 return InlineAsm::Constraint_Us;
366 return InlineAsm::Constraint_Ut;
368 return InlineAsm::Constraint_Uv;
370 return InlineAsm::Constraint_Uy;
374 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
377 const ARMSubtarget* getSubtarget() const {
381 /// getRegClassFor - Return the register class that should be used for the
382 /// specified value type.
383 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
385 /// Returns true if a cast between SrcAS and DestAS is a noop.
386 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
387 // Addrspacecasts are always noops.
391 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
392 unsigned &PrefAlign) const override;
394 /// createFastISel - This method returns a target specific FastISel object,
395 /// or null if the target does not support "fast" ISel.
396 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
397 const TargetLibraryInfo *libInfo) const override;
399 Sched::Preference getSchedulingPreference(SDNode *N) const override;
402 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
403 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
405 /// isFPImmLegal - Returns true if the target can instruction select the
406 /// specified FP immediate natively. If false, the legalizer will
407 /// materialize the FP immediate as a load from a constant pool.
408 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
410 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
412 unsigned Intrinsic) const override;
414 /// \brief Returns true if it is beneficial to convert a load of a constant
415 /// to just the constant itself.
416 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
417 Type *Ty) const override;
419 /// \brief Returns true if an argument of type Ty needs to be passed in a
420 /// contiguous block of registers in calling convention CallConv.
421 bool functionArgumentNeedsConsecutiveRegisters(
422 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
424 bool hasLoadLinkedStoreConditional() const override;
425 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
426 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
427 AtomicOrdering Ord) const override;
428 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
429 Value *Addr, AtomicOrdering Ord) const override;
431 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
432 bool IsStore, bool IsLoad) const override;
433 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
434 bool IsStore, bool IsLoad) const override;
436 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
438 bool lowerInterleavedLoad(LoadInst *LI,
439 ArrayRef<ShuffleVectorInst *> Shuffles,
440 ArrayRef<unsigned> Indices,
441 unsigned Factor) const override;
442 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
443 unsigned Factor) const override;
445 bool shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
446 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
447 TargetLoweringBase::AtomicRMWExpansionKind
448 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
450 bool useLoadStackGuardNode() const override;
452 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
453 unsigned &Cost) const override;
456 std::pair<const TargetRegisterClass *, uint8_t>
457 findRepresentativeClass(const TargetRegisterInfo *TRI,
458 MVT VT) const override;
461 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
462 /// make the right decision when generating code for different targets.
463 const ARMSubtarget *Subtarget;
465 const TargetRegisterInfo *RegInfo;
467 const InstrItineraryData *Itins;
469 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
471 unsigned ARMPCLabelIndex;
473 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
474 void addDRTypeForNEON(MVT VT);
475 void addQRTypeForNEON(MVT VT);
476 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
478 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
479 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
480 SDValue Chain, SDValue &Arg,
481 RegsToPassVector &RegsToPass,
482 CCValAssign &VA, CCValAssign &NextVA,
484 SmallVectorImpl<SDValue> &MemOpChains,
485 ISD::ArgFlagsTy Flags) const;
486 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
487 SDValue &Root, SelectionDAG &DAG,
490 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
491 bool isVarArg) const;
492 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
493 bool isVarArg) const;
494 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
495 SDLoc dl, SelectionDAG &DAG,
496 const CCValAssign &VA,
497 ISD::ArgFlagsTy Flags) const;
498 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
502 const ARMSubtarget *Subtarget) const;
503 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
509 SelectionDAG &DAG) const;
510 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
512 TLSModel::Model model) const;
513 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
520 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
521 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
525 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
526 const ARMSubtarget *ST) const;
527 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
528 const ARMSubtarget *ST) const;
529 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
531 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
532 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
533 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
537 unsigned getRegisterByName(const char* RegName, EVT VT,
538 SelectionDAG &DAG) const override;
540 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
541 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
542 /// expanded to FMAs when this method returns true, otherwise fmuladd is
543 /// expanded to fmul + fadd.
545 /// ARM supports both fused and unfused multiply-add operations; we already
546 /// lower a pair of fmul and fadd to the latter so it's not clear that there
547 /// would be a gain or that the gain would be worthwhile enough to risk
548 /// correctness bugs.
549 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
551 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
554 CallingConv::ID CallConv, bool isVarArg,
555 const SmallVectorImpl<ISD::InputArg> &Ins,
556 SDLoc dl, SelectionDAG &DAG,
557 SmallVectorImpl<SDValue> &InVals,
558 bool isThisReturn, SDValue ThisVal) const;
561 LowerFormalArguments(SDValue Chain,
562 CallingConv::ID CallConv, bool isVarArg,
563 const SmallVectorImpl<ISD::InputArg> &Ins,
564 SDLoc dl, SelectionDAG &DAG,
565 SmallVectorImpl<SDValue> &InVals) const override;
567 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
568 SDLoc dl, SDValue &Chain,
569 const Value *OrigArg,
570 unsigned InRegsParamRecordIdx,
572 unsigned ArgSize) const;
574 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
575 SDLoc dl, SDValue &Chain,
577 unsigned TotalArgRegsSaveSize,
578 bool ForceMutable = false) const;
581 LowerCall(TargetLowering::CallLoweringInfo &CLI,
582 SmallVectorImpl<SDValue> &InVals) const override;
584 /// HandleByVal - Target-specific cleanup for ByVal support.
585 void HandleByVal(CCState *, unsigned &, unsigned) const override;
587 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
588 /// for tail call optimization. Targets which want to do tail call
589 /// optimization should implement this function.
590 bool IsEligibleForTailCallOptimization(SDValue Callee,
591 CallingConv::ID CalleeCC,
593 bool isCalleeStructRet,
594 bool isCallerStructRet,
595 const SmallVectorImpl<ISD::OutputArg> &Outs,
596 const SmallVectorImpl<SDValue> &OutVals,
597 const SmallVectorImpl<ISD::InputArg> &Ins,
598 SelectionDAG& DAG) const;
600 bool CanLowerReturn(CallingConv::ID CallConv,
601 MachineFunction &MF, bool isVarArg,
602 const SmallVectorImpl<ISD::OutputArg> &Outs,
603 LLVMContext &Context) const override;
606 LowerReturn(SDValue Chain,
607 CallingConv::ID CallConv, bool isVarArg,
608 const SmallVectorImpl<ISD::OutputArg> &Outs,
609 const SmallVectorImpl<SDValue> &OutVals,
610 SDLoc dl, SelectionDAG &DAG) const override;
612 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
614 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
616 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
617 SDValue ARMcc, SDValue CCR, SDValue Cmp,
618 SelectionDAG &DAG) const;
619 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
620 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
621 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
622 SelectionDAG &DAG, SDLoc dl) const;
623 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
625 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
627 void SetupEntryBlockForSjLj(MachineInstr *MI,
628 MachineBasicBlock *MBB,
629 MachineBasicBlock *DispatchBB, int FI) const;
631 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
633 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
635 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
636 MachineBasicBlock *MBB) const;
638 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
639 MachineBasicBlock *MBB) const;
642 enum NEONModImmType {
649 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
650 const TargetLibraryInfo *libInfo);
654 #endif // ARMISELLOWERING_H