1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 FTOSI, // FP to sint within a FP register.
69 FTOUI, // FP to uint within a FP register.
70 SITOF, // sint to FP within a FP register.
71 UITOF, // uint to FP within a FP register.
73 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
74 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
75 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
77 ADDC, // Add with carry
78 ADDE, // Add using carry
79 SUBC, // Sub with carry
80 SUBE, // Sub using carry
82 VMOVRRD, // double to two gprs.
83 VMOVDRR, // Two gprs to double.
85 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
86 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
88 TC_RETURN, // Tail call return pseudo.
92 DYN_ALLOC, // Dynamic allocation on the stack.
94 MEMBARRIER_MCR, // Memory barrier (MCR)
98 VCEQ, // Vector compare equal.
99 VCEQZ, // Vector compare equal to zero.
100 VCGE, // Vector compare greater than or equal.
101 VCGEZ, // Vector compare greater than or equal to zero.
102 VCLEZ, // Vector compare less than or equal to zero.
103 VCGEU, // Vector compare unsigned greater than or equal.
104 VCGT, // Vector compare greater than.
105 VCGTZ, // Vector compare greater than zero.
106 VCLTZ, // Vector compare less than zero.
107 VCGTU, // Vector compare unsigned greater than.
108 VTST, // Vector test bits.
110 // Vector shift by immediate:
112 VSHRs, // ...right (signed)
113 VSHRu, // ...right (unsigned)
115 // Vector rounding shift by immediate:
116 VRSHRs, // ...right (signed)
117 VRSHRu, // ...right (unsigned)
118 VRSHRN, // ...right narrow
120 // Vector saturating shift by immediate:
121 VQSHLs, // ...left (signed)
122 VQSHLu, // ...left (unsigned)
123 VQSHLsu, // ...left (signed to unsigned)
124 VQSHRNs, // ...right narrow (signed)
125 VQSHRNu, // ...right narrow (unsigned)
126 VQSHRNsu, // ...right narrow (signed to unsigned)
128 // Vector saturating rounding shift by immediate:
129 VQRSHRNs, // ...right narrow (signed)
130 VQRSHRNu, // ...right narrow (unsigned)
131 VQRSHRNsu, // ...right narrow (signed to unsigned)
133 // Vector shift and insert:
137 // Vector get lane (VMOV scalar to ARM core register)
138 // (These are used for 8- and 16-bit element types only.)
139 VGETLANEu, // zero-extend vector extract element
140 VGETLANEs, // sign-extend vector extract element
142 // Vector move immediate and move negated immediate:
146 // Vector move f32 immediate:
155 VREV64, // reverse elements within 64-bit doublewords
156 VREV32, // reverse elements within 32-bit words
157 VREV16, // reverse elements within 16-bit halfwords
158 VZIP, // zip (interleave)
159 VUZP, // unzip (deinterleave)
161 VTBL1, // 1-register shuffle with mask
162 VTBL2, // 2-register shuffle with mask
164 // Vector multiply long:
166 VMULLu, // ...unsigned
168 UMLAL, // 64bit Unsigned Accumulate Multiply
169 SMLAL, // 64bit Signed Accumulate Multiply
171 // Operands of the standard BUILD_VECTOR node are not legalized, which
172 // is fine if BUILD_VECTORs are always lowered to shuffles or other
173 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
174 // operands need to be legalized. Define an ARM-specific version of
175 // BUILD_VECTOR for this purpose.
178 // Floating-point max and min:
187 // Vector OR with immediate
189 // Vector AND with NOT of immediate
192 // Vector bitwise select
195 // Vector load N-element structure to all lanes:
196 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
200 // NEON loads with post-increment base updates:
212 // NEON stores with post-increment base updates:
223 /// Define some predicates that are used for node matching.
225 bool isBitFieldInvertedMask(unsigned v);
228 //===--------------------------------------------------------------------===//
229 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
231 class ARMTargetLowering : public TargetLowering {
233 explicit ARMTargetLowering(TargetMachine &TM);
235 unsigned getJumpTableEncoding() const override;
237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
239 /// ReplaceNodeResults - Replace the results of node with an illegal result
240 /// type with new values built out of custom code.
242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
243 SelectionDAG &DAG) const override;
245 const char *getTargetNodeName(unsigned Opcode) const override;
247 bool isSelectSupported(SelectSupportKind Kind) const override {
248 // ARM does not support scalar condition selects on vectors.
249 return (Kind != ScalarCondVectorVal);
252 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
253 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
256 EmitInstrWithCustomInserter(MachineInstr *MI,
257 MachineBasicBlock *MBB) const override;
259 void AdjustInstrPostInstrSelection(MachineInstr *MI,
260 SDNode *Node) const override;
262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
263 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
265 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
267 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
268 /// unaligned memory accesses of the specified type. Returns whether it
269 /// is "fast" by reference in the second argument.
270 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
271 bool *Fast) const override;
273 EVT getOptimalMemOpType(uint64_t Size,
274 unsigned DstAlign, unsigned SrcAlign,
275 bool IsMemset, bool ZeroMemset,
277 MachineFunction &MF) const override;
279 using TargetLowering::isZExtFree;
280 bool isZExtFree(SDValue Val, EVT VT2) const override;
282 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
285 /// isLegalAddressingMode - Return true if the addressing mode represented
286 /// by AM is legal for this target, for a load/store of the specified type.
287 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
288 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
290 /// isLegalICmpImmediate - Return true if the specified immediate is legal
291 /// icmp immediate, that is the target has icmp instructions which can
292 /// compare a register against the immediate without having to materialize
293 /// the immediate into a register.
294 bool isLegalICmpImmediate(int64_t Imm) const override;
296 /// isLegalAddImmediate - Return true if the specified immediate is legal
297 /// add immediate, that is the target has add instructions which can
298 /// add a register and the immediate without having to materialize
299 /// the immediate into a register.
300 bool isLegalAddImmediate(int64_t Imm) const override;
302 /// getPreIndexedAddressParts - returns true by value, base pointer and
303 /// offset pointer and addressing mode by reference if the node's address
304 /// can be legally represented as pre-indexed load / store address.
305 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
306 ISD::MemIndexedMode &AM,
307 SelectionDAG &DAG) const override;
309 /// getPostIndexedAddressParts - returns true by value, base pointer and
310 /// offset pointer and addressing mode by reference if this node can be
311 /// combined with a load / store to form a post-indexed load / store.
312 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
313 SDValue &Offset, ISD::MemIndexedMode &AM,
314 SelectionDAG &DAG) const override;
316 void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero,
318 const SelectionDAG &DAG,
319 unsigned Depth) const override;
322 bool ExpandInlineAsm(CallInst *CI) const override;
325 getConstraintType(const std::string &Constraint) const override;
327 /// Examine constraint string and operand type and determine a weight value.
328 /// The operand object must already have been set up with the operand type.
329 ConstraintWeight getSingleConstraintMatchWeight(
330 AsmOperandInfo &info, const char *constraint) const override;
332 std::pair<unsigned, const TargetRegisterClass*>
333 getRegForInlineAsmConstraint(const std::string &Constraint,
334 MVT VT) const override;
336 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
337 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
338 /// true it means one of the asm constraint of the inline asm instruction
339 /// being processed is 'm'.
340 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
341 std::vector<SDValue> &Ops,
342 SelectionDAG &DAG) const override;
344 const ARMSubtarget* getSubtarget() const {
348 /// getRegClassFor - Return the register class that should be used for the
349 /// specified value type.
350 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
352 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
353 /// be used for loads / stores from the global.
354 unsigned getMaximalGlobalOffset() const override;
356 /// Returns true if a cast between SrcAS and DestAS is a noop.
357 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
358 // Addrspacecasts are always noops.
362 /// createFastISel - This method returns a target specific FastISel object,
363 /// or null if the target does not support "fast" ISel.
364 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
365 const TargetLibraryInfo *libInfo) const override;
367 Sched::Preference getSchedulingPreference(SDNode *N) const override;
370 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
371 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
373 /// isFPImmLegal - Returns true if the target can instruction select the
374 /// specified FP immediate natively. If false, the legalizer will
375 /// materialize the FP immediate as a load from a constant pool.
376 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
378 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
380 unsigned Intrinsic) const override;
382 /// \brief Returns true if it is beneficial to convert a load of a constant
383 /// to just the constant itself.
384 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
385 Type *Ty) const override;
387 /// \brief Returns true if an argument of type Ty needs to be passed in a
388 /// contiguous block of registers in calling convention CallConv.
389 bool functionArgumentNeedsConsecutiveRegisters(
390 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
392 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
393 AtomicOrdering Ord) const override;
394 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
395 Value *Addr, AtomicOrdering Ord) const override;
397 bool shouldExpandAtomicInIR(Instruction *Inst) const override;
400 std::pair<const TargetRegisterClass*, uint8_t>
401 findRepresentativeClass(MVT VT) const override;
404 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
405 /// make the right decision when generating code for different targets.
406 const ARMSubtarget *Subtarget;
408 const TargetRegisterInfo *RegInfo;
410 const InstrItineraryData *Itins;
412 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
414 unsigned ARMPCLabelIndex;
416 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
417 void addDRTypeForNEON(MVT VT);
418 void addQRTypeForNEON(MVT VT);
420 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
421 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
422 SDValue Chain, SDValue &Arg,
423 RegsToPassVector &RegsToPass,
424 CCValAssign &VA, CCValAssign &NextVA,
426 SmallVectorImpl<SDValue> &MemOpChains,
427 ISD::ArgFlagsTy Flags) const;
428 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
429 SDValue &Root, SelectionDAG &DAG,
432 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
433 bool isVarArg) const;
434 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
435 bool isVarArg) const;
436 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
437 SDLoc dl, SelectionDAG &DAG,
438 const CCValAssign &VA,
439 ISD::ArgFlagsTy Flags) const;
440 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
441 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
442 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
443 const ARMSubtarget *Subtarget) const;
444 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
446 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
448 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
449 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
450 SelectionDAG &DAG) const;
451 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
453 TLSModel::Model model) const;
454 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
456 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
457 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
463 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
466 const ARMSubtarget *ST) const;
467 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
468 const ARMSubtarget *ST) const;
469 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
470 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
472 unsigned getRegisterByName(const char* RegName) const;
474 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
475 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
476 /// expanded to FMAs when this method returns true, otherwise fmuladd is
477 /// expanded to fmul + fadd.
479 /// ARM supports both fused and unfused multiply-add operations; we already
480 /// lower a pair of fmul and fadd to the latter so it's not clear that there
481 /// would be a gain or that the gain would be worthwhile enough to risk
482 /// correctness bugs.
483 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
485 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
488 CallingConv::ID CallConv, bool isVarArg,
489 const SmallVectorImpl<ISD::InputArg> &Ins,
490 SDLoc dl, SelectionDAG &DAG,
491 SmallVectorImpl<SDValue> &InVals,
492 bool isThisReturn, SDValue ThisVal) const;
495 LowerFormalArguments(SDValue Chain,
496 CallingConv::ID CallConv, bool isVarArg,
497 const SmallVectorImpl<ISD::InputArg> &Ins,
498 SDLoc dl, SelectionDAG &DAG,
499 SmallVectorImpl<SDValue> &InVals) const override;
501 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
502 SDLoc dl, SDValue &Chain,
503 const Value *OrigArg,
504 unsigned InRegsParamRecordIdx,
505 unsigned OffsetFromOrigArg,
509 unsigned ByValStoreOffset,
510 unsigned TotalArgRegsSaveSize) const;
512 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
513 SDLoc dl, SDValue &Chain,
515 unsigned TotalArgRegsSaveSize,
516 bool ForceMutable = false) const;
518 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
519 unsigned InRegsParamRecordIdx,
521 unsigned &ArgRegsSize,
522 unsigned &ArgRegsSaveSize) const;
525 LowerCall(TargetLowering::CallLoweringInfo &CLI,
526 SmallVectorImpl<SDValue> &InVals) const override;
528 /// HandleByVal - Target-specific cleanup for ByVal support.
529 void HandleByVal(CCState *, unsigned &, unsigned) const override;
531 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
532 /// for tail call optimization. Targets which want to do tail call
533 /// optimization should implement this function.
534 bool IsEligibleForTailCallOptimization(SDValue Callee,
535 CallingConv::ID CalleeCC,
537 bool isCalleeStructRet,
538 bool isCallerStructRet,
539 const SmallVectorImpl<ISD::OutputArg> &Outs,
540 const SmallVectorImpl<SDValue> &OutVals,
541 const SmallVectorImpl<ISD::InputArg> &Ins,
542 SelectionDAG& DAG) const;
544 bool CanLowerReturn(CallingConv::ID CallConv,
545 MachineFunction &MF, bool isVarArg,
546 const SmallVectorImpl<ISD::OutputArg> &Outs,
547 LLVMContext &Context) const override;
550 LowerReturn(SDValue Chain,
551 CallingConv::ID CallConv, bool isVarArg,
552 const SmallVectorImpl<ISD::OutputArg> &Outs,
553 const SmallVectorImpl<SDValue> &OutVals,
554 SDLoc dl, SelectionDAG &DAG) const override;
556 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
558 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
560 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
561 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
562 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
563 SelectionDAG &DAG, SDLoc dl) const;
564 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
566 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
568 void SetupEntryBlockForSjLj(MachineInstr *MI,
569 MachineBasicBlock *MBB,
570 MachineBasicBlock *DispatchBB, int FI) const;
572 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
573 MachineBasicBlock *MBB) const;
575 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
577 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
578 MachineBasicBlock *MBB) const;
581 enum NEONModImmType {
588 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
589 const TargetLibraryInfo *libInfo);
593 #endif // ARMISELLOWERING_H