1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/VectorExtras.h"
36 #include "llvm/Support/MathExtras.h"
39 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM), ARMPCLabelIndex(0) {
41 Subtarget = &TM.getSubtarget<ARMSubtarget>();
43 if (Subtarget->isTargetDarwin()) {
45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
48 // Uses VFP for Thumb libfuncs if available.
49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
50 // Single-precision floating-point arithmetic.
51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
56 // Double-precision floating-point arithmetic.
57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
62 // Single-precision comparisons.
63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
81 // Double-precision comparisons.
82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
100 // Floating-point to integer conversions.
101 // i64 conversions are done via library routines even when generating VFP
102 // instructions, so use the same ones.
103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
108 // Conversions between floating types.
109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
112 // Integer to floating-point conversions.
113 // i64 conversions are done via library routines even when generating VFP
114 // instructions, so use the same ones.
115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
116 // __floatunsidf vs. __floatunssidfvfp.
117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
129 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
131 computeRegisterProperties();
133 // ARM does not have f32 extending load.
134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
136 // ARM does not have i1 sign extending load.
137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
139 // ARM supports all 4 flavors of integer indexed load / store.
140 for (unsigned im = (unsigned)ISD::PRE_INC;
141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
142 setIndexedLoadAction(im, MVT::i1, Legal);
143 setIndexedLoadAction(im, MVT::i8, Legal);
144 setIndexedLoadAction(im, MVT::i16, Legal);
145 setIndexedLoadAction(im, MVT::i32, Legal);
146 setIndexedStoreAction(im, MVT::i1, Legal);
147 setIndexedStoreAction(im, MVT::i8, Legal);
148 setIndexedStoreAction(im, MVT::i16, Legal);
149 setIndexedStoreAction(im, MVT::i32, Legal);
152 // i64 operation support.
153 if (Subtarget->isThumb()) {
154 setOperationAction(ISD::MUL, MVT::i64, Expand);
155 setOperationAction(ISD::MULHU, MVT::i32, Expand);
156 setOperationAction(ISD::MULHS, MVT::i32, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i64, Expand);
161 setOperationAction(ISD::MULHU, MVT::i32, Expand);
162 if (!Subtarget->hasV6Ops())
163 setOperationAction(ISD::MULHS, MVT::i32, Expand);
165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
168 setOperationAction(ISD::SRL, MVT::i64, Custom);
169 setOperationAction(ISD::SRA, MVT::i64, Custom);
171 // ARM does not have ROTL.
172 setOperationAction(ISD::ROTL, MVT::i32, Expand);
173 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
174 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
176 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
178 // Only ARMv6 has BSWAP.
179 if (!Subtarget->hasV6Ops())
180 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
182 // These are expanded into libcalls.
183 setOperationAction(ISD::SDIV, MVT::i32, Expand);
184 setOperationAction(ISD::UDIV, MVT::i32, Expand);
185 setOperationAction(ISD::SREM, MVT::i32, Expand);
186 setOperationAction(ISD::UREM, MVT::i32, Expand);
187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
190 // Support label based line numbers.
191 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
194 setOperationAction(ISD::RET, MVT::Other, Custom);
195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
200 // Use the default implementation.
201 setOperationAction(ISD::VASTART , MVT::Other, Custom);
202 setOperationAction(ISD::VAARG , MVT::Other, Expand);
203 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
204 setOperationAction(ISD::VAEND , MVT::Other, Expand);
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
208 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
210 if (!Subtarget->hasV6Ops()) {
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
216 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
217 // Turn f64->i64 into FMRRD iff target supports vfp2.
218 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
220 // We want to custom lower some of our intrinsics.
221 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
223 setOperationAction(ISD::SETCC , MVT::i32, Expand);
224 setOperationAction(ISD::SETCC , MVT::f32, Expand);
225 setOperationAction(ISD::SETCC , MVT::f64, Expand);
226 setOperationAction(ISD::SELECT , MVT::i32, Expand);
227 setOperationAction(ISD::SELECT , MVT::f32, Expand);
228 setOperationAction(ISD::SELECT , MVT::f64, Expand);
229 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
230 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
231 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
233 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
234 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
235 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
236 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
237 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
239 // We don't support sin/cos/fmod/copysign/pow
240 setOperationAction(ISD::FSIN , MVT::f64, Expand);
241 setOperationAction(ISD::FSIN , MVT::f32, Expand);
242 setOperationAction(ISD::FCOS , MVT::f32, Expand);
243 setOperationAction(ISD::FCOS , MVT::f64, Expand);
244 setOperationAction(ISD::FREM , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f32, Expand);
246 setOperationAction(ISD::FLOG , MVT::f64, Expand);
247 setOperationAction(ISD::FLOG , MVT::f32, Expand);
248 setOperationAction(ISD::FLOG2 , MVT::f64, Expand);
249 setOperationAction(ISD::FLOG2 , MVT::f32, Expand);
250 setOperationAction(ISD::FLOG10 , MVT::f64, Expand);
251 setOperationAction(ISD::FLOG10 , MVT::f32, Expand);
252 setOperationAction(ISD::FEXP , MVT::f64, Expand);
253 setOperationAction(ISD::FEXP , MVT::f32, Expand);
254 setOperationAction(ISD::FEXP2 , MVT::f64, Expand);
255 setOperationAction(ISD::FEXP2 , MVT::f32, Expand);
256 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
258 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
260 setOperationAction(ISD::FPOW , MVT::f64, Expand);
261 setOperationAction(ISD::FPOW , MVT::f32, Expand);
263 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
264 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
265 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
266 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
267 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
271 // We have target-specific dag combine patterns for the following nodes:
272 // ARMISD::FMRRD - No need to call setTargetDAGCombine
274 setStackPointerRegisterToSaveRestore(ARM::SP);
275 setSchedulingPreference(SchedulingForRegPressure);
276 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
277 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
279 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
283 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
286 case ARMISD::Wrapper: return "ARMISD::Wrapper";
287 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
288 case ARMISD::CALL: return "ARMISD::CALL";
289 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
290 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
291 case ARMISD::tCALL: return "ARMISD::tCALL";
292 case ARMISD::BRCOND: return "ARMISD::BRCOND";
293 case ARMISD::BR_JT: return "ARMISD::BR_JT";
294 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
295 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
296 case ARMISD::CMP: return "ARMISD::CMP";
297 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
298 case ARMISD::CMPFP: return "ARMISD::CMPFP";
299 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
300 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
301 case ARMISD::CMOV: return "ARMISD::CMOV";
302 case ARMISD::CNEG: return "ARMISD::CNEG";
304 case ARMISD::FTOSI: return "ARMISD::FTOSI";
305 case ARMISD::FTOUI: return "ARMISD::FTOUI";
306 case ARMISD::SITOF: return "ARMISD::SITOF";
307 case ARMISD::UITOF: return "ARMISD::UITOF";
309 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
310 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
311 case ARMISD::RRX: return "ARMISD::RRX";
313 case ARMISD::FMRRD: return "ARMISD::FMRRD";
314 case ARMISD::FMDRR: return "ARMISD::FMDRR";
316 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
320 //===----------------------------------------------------------------------===//
322 //===----------------------------------------------------------------------===//
325 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
326 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
328 default: assert(0 && "Unknown condition code!");
329 case ISD::SETNE: return ARMCC::NE;
330 case ISD::SETEQ: return ARMCC::EQ;
331 case ISD::SETGT: return ARMCC::GT;
332 case ISD::SETGE: return ARMCC::GE;
333 case ISD::SETLT: return ARMCC::LT;
334 case ISD::SETLE: return ARMCC::LE;
335 case ISD::SETUGT: return ARMCC::HI;
336 case ISD::SETUGE: return ARMCC::HS;
337 case ISD::SETULT: return ARMCC::LO;
338 case ISD::SETULE: return ARMCC::LS;
342 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
343 /// returns true if the operands should be inverted to form the proper
345 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
346 ARMCC::CondCodes &CondCode2) {
348 CondCode2 = ARMCC::AL;
350 default: assert(0 && "Unknown FP condition!");
352 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
354 case ISD::SETOGT: CondCode = ARMCC::GT; break;
356 case ISD::SETOGE: CondCode = ARMCC::GE; break;
357 case ISD::SETOLT: CondCode = ARMCC::MI; break;
358 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
359 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
360 case ISD::SETO: CondCode = ARMCC::VC; break;
361 case ISD::SETUO: CondCode = ARMCC::VS; break;
362 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
363 case ISD::SETUGT: CondCode = ARMCC::HI; break;
364 case ISD::SETUGE: CondCode = ARMCC::PL; break;
366 case ISD::SETULT: CondCode = ARMCC::LT; break;
368 case ISD::SETULE: CondCode = ARMCC::LE; break;
370 case ISD::SETUNE: CondCode = ARMCC::NE; break;
376 HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
377 unsigned StackOffset, unsigned &NeededGPRs,
378 unsigned &NeededStackSize, unsigned &GPRPad,
379 unsigned &StackPad, ISD::ArgFlagsTy Flags) {
384 unsigned align = Flags.getOrigAlign();
385 GPRPad = NumGPRs % ((align + 3)/4);
386 StackPad = StackOffset % align;
387 unsigned firstGPR = NumGPRs + GPRPad;
388 switch (ObjectVT.getSimpleVT()) {
389 default: assert(0 && "Unhandled argument type!");
401 else if (firstGPR == 3) {
409 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
410 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
412 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
413 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
414 MVT RetVT = TheCall->getRetValType(0);
415 SDValue Chain = TheCall->getChain();
416 unsigned CallConv = TheCall->getCallingConv();
417 assert((CallConv == CallingConv::C ||
418 CallConv == CallingConv::Fast) && "unknown calling convention");
419 SDValue Callee = TheCall->getCallee();
420 unsigned NumOps = TheCall->getNumArgs();
421 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
422 unsigned NumGPRs = 0; // GPRs used for parameter passing.
424 // Count how many bytes are to be pushed on the stack.
425 unsigned NumBytes = 0;
427 // Add up all the space actually used.
428 for (unsigned i = 0; i < NumOps; ++i) {
433 MVT ObjectVT = TheCall->getArg(i).getValueType();
434 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
435 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
436 GPRPad, StackPad, Flags);
437 NumBytes += ObjSize + StackPad;
438 NumGPRs += ObjGPRs + GPRPad;
441 // Adjust the stack pointer for the new arguments...
442 // These operations are automatically eliminated by the prolog/epilog pass
443 Chain = DAG.getCALLSEQ_START(Chain,
444 DAG.getConstant(NumBytes, MVT::i32));
446 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
448 static const unsigned GPRArgRegs[] = {
449 ARM::R0, ARM::R1, ARM::R2, ARM::R3
453 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
454 std::vector<SDValue> MemOpChains;
455 for (unsigned i = 0; i != NumOps; ++i) {
456 SDValue Arg = TheCall->getArg(i);
457 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
458 MVT ArgVT = Arg.getValueType();
464 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
465 ObjSize, GPRPad, StackPad, Flags);
467 ArgOffset += StackPad;
469 switch (ArgVT.getSimpleVT()) {
470 default: assert(0 && "Unexpected ValueType for argument!");
472 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
475 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
476 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
479 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
480 DAG.getConstant(0, getPointerTy()));
481 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
482 DAG.getConstant(1, getPointerTy()));
483 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
485 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
487 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
488 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
489 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
494 SDValue Cvt = DAG.getNode(ARMISD::FMRRD,
495 DAG.getVTList(MVT::i32, MVT::i32),
497 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
499 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
502 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
503 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
504 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
511 assert(ObjSize != 0);
512 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
513 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
514 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
518 ArgOffset += ObjSize;
521 if (!MemOpChains.empty())
522 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
523 &MemOpChains[0], MemOpChains.size());
525 // Build a sequence of copy-to-reg nodes chained together with token chain
526 // and flag operands which copy the outgoing args into the appropriate regs.
528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
529 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
531 InFlag = Chain.getValue(1);
534 // If the callee is a GlobalAddress/Symbol node (quite common, every direct
535 // call is) turn it into a TargetGlobalAddress/TargetSymbol node so that
536 // legalize doesn't hack it.
537 bool isDirect = false;
538 bool isARMFunc = false;
539 bool isLocalARMFunc = false;
540 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
541 GlobalValue *GV = G->getGlobal();
543 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
544 GV->hasLinkOnceLinkage());
545 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
546 getTargetMachine().getRelocationModel() != Reloc::Static;
547 isARMFunc = !Subtarget->isThumb() || isStub;
548 // ARM call to a local ARM function is predicable.
549 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
550 // tBX takes a register source operand.
551 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
552 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
554 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
555 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
556 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
557 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
558 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
560 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
561 } else if (SymbolSDNode *S = dyn_cast<SymbolSDNode>(Callee)) {
563 bool isStub = Subtarget->isTargetDarwin() &&
564 getTargetMachine().getRelocationModel() != Reloc::Static;
565 isARMFunc = !Subtarget->isThumb() || isStub;
566 // tBX takes a register source operand.
567 const char *Sym = S->getSymbol();
568 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
569 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
571 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
572 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
573 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
574 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
575 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
577 Callee = DAG.getTargetSymbol(Sym, getPointerTy(), S->getLinkage());
580 // FIXME: handle tail calls differently.
582 if (Subtarget->isThumb()) {
583 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
584 CallOpc = ARMISD::CALL_NOLINK;
586 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
588 CallOpc = (isDirect || Subtarget->hasV5TOps())
589 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
590 : ARMISD::CALL_NOLINK;
592 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
593 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
594 Chain = DAG.getCopyToReg(Chain, ARM::LR,
595 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
596 InFlag = Chain.getValue(1);
599 std::vector<SDValue> Ops;
600 Ops.push_back(Chain);
601 Ops.push_back(Callee);
603 // Add argument registers to the end of the list so that they are known live
605 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
606 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
607 RegsToPass[i].second.getValueType()));
609 if (InFlag.getNode())
610 Ops.push_back(InFlag);
611 // Returns a chain and a flag for retval copy to use.
612 Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
613 &Ops[0], Ops.size());
614 InFlag = Chain.getValue(1);
616 Chain = DAG.getCALLSEQ_END(Chain,
617 DAG.getConstant(NumBytes, MVT::i32),
618 DAG.getConstant(0, MVT::i32),
620 if (RetVT != MVT::Other)
621 InFlag = Chain.getValue(1);
623 std::vector<SDValue> ResultVals;
625 // If the call has results, copy the values out of the ret val registers.
626 switch (RetVT.getSimpleVT()) {
627 default: assert(0 && "Unexpected ret value!");
631 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
632 ResultVals.push_back(Chain.getValue(0));
633 if (TheCall->getNumRetVals() > 1 &&
634 TheCall->getRetValType(1) == MVT::i32) {
635 // Returns a i64 value.
636 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
637 Chain.getValue(2)).getValue(1);
638 ResultVals.push_back(Chain.getValue(0));
642 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
643 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
647 SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
648 SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
649 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
654 if (ResultVals.empty())
657 ResultVals.push_back(Chain);
658 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
659 return Res.getValue(Op.getResNo());
662 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
664 SDValue Chain = Op.getOperand(0);
665 switch(Op.getNumOperands()) {
667 assert(0 && "Do not know how to return this many arguments!");
670 SDValue LR = DAG.getRegister(ARM::LR, MVT::i32);
671 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
674 Op = Op.getOperand(1);
675 if (Op.getValueType() == MVT::f32) {
676 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
677 } else if (Op.getValueType() == MVT::f64) {
678 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
680 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
681 SDValue Sign = DAG.getConstant(0, MVT::i32);
682 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
683 Op.getValue(1), Sign);
685 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue());
686 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
687 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
690 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue());
691 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
692 // If we haven't noted the R0+R1 are live out, do so now.
693 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
694 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
698 case 9: // i128 -> 4 regs
699 Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue());
700 Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
701 Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
702 Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
703 // If we haven't noted the R0+R1 are live out, do so now.
704 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
705 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
706 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
707 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2);
708 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3);
714 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
715 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
718 // ConstantPool, JumpTable, GlobalAddress, and Symbol are lowered as their
719 // target countpart wrapped in the ARMISD::Wrapper node. Suppose N is one of the
720 // above mentioned nodes. It has to be wrapped because otherwise Select(N)
721 // returns N. So the raw TargetGlobalAddress nodes, etc. can only be used to
722 // form addressing mode. These wrapped nodes will be selected into MOVi.
723 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
724 MVT PtrVT = Op.getValueType();
725 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
727 if (CP->isMachineConstantPoolEntry())
728 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
731 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
733 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
736 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
738 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
740 MVT PtrVT = getPointerTy();
741 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
742 ARMConstantPoolValue *CPV =
743 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
744 PCAdj, "tlsgd", true);
745 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
746 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
747 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
748 SDValue Chain = Argument.getValue(1);
750 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
751 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
753 // call __tls_get_addr.
756 Entry.Node = Argument;
757 Entry.Ty = (const Type *) Type::Int32Ty;
758 Args.push_back(Entry);
759 std::pair<SDValue, SDValue> CallResult =
760 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
761 CallingConv::C, false,
762 DAG.getSymbol("__tls_get_addr", PtrVT), Args, DAG);
763 return CallResult.first;
766 // Lower ISD::GlobalTLSAddress using the "initial exec" or
767 // "local exec" model.
769 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
771 GlobalValue *GV = GA->getGlobal();
773 SDValue Chain = DAG.getEntryNode();
774 MVT PtrVT = getPointerTy();
775 // Get the Thread Pointer
776 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
778 if (GV->isDeclaration()){
779 // initial exec model
780 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
781 ARMConstantPoolValue *CPV =
782 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
783 PCAdj, "gottpoff", true);
784 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
785 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
786 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
787 Chain = Offset.getValue(1);
789 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
790 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
792 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
795 ARMConstantPoolValue *CPV =
796 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
797 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
798 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
799 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
802 // The address of the thread local variable is the add of the thread
803 // pointer with the offset of the variable.
804 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
808 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
809 // TODO: implement the "local dynamic" model
810 assert(Subtarget->isTargetELF() &&
811 "TLS not implemented for non-ELF targets");
812 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
813 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
814 // otherwise use the "Local Exec" TLS Model
815 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
816 return LowerToTLSGeneralDynamicModel(GA, DAG);
818 return LowerToTLSExecModels(GA, DAG);
821 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
823 MVT PtrVT = getPointerTy();
824 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
825 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
826 if (RelocM == Reloc::PIC_) {
827 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
828 ARMConstantPoolValue *CPV =
829 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
830 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
831 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
832 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
833 SDValue Chain = Result.getValue(1);
834 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
835 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
837 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
840 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
841 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
842 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
846 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
847 /// even in non-static mode.
848 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
849 return RelocM != Reloc::Static &&
850 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
851 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
854 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
856 MVT PtrVT = getPointerTy();
857 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
858 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
859 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
861 if (RelocM == Reloc::Static)
862 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
864 unsigned PCAdj = (RelocM != Reloc::PIC_)
865 ? 0 : (Subtarget->isThumb() ? 4 : 8);
866 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
868 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
870 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
872 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
874 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
875 SDValue Chain = Result.getValue(1);
877 if (RelocM == Reloc::PIC_) {
878 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
879 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
882 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
887 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
889 assert(Subtarget->isTargetELF() &&
890 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
891 MVT PtrVT = getPointerTy();
892 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
893 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
895 ARMCP::CPValue, PCAdj);
896 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
897 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
898 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
899 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
900 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
903 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
904 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
905 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
907 default: return SDValue(); // Don't custom lower most intrinsics.
908 case Intrinsic::arm_thread_pointer:
909 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
913 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
914 unsigned VarArgsFrameIndex) {
915 // vastart just stores the address of the VarArgsFrameIndex slot into the
916 // memory location argument.
917 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
918 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
919 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
920 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
923 static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG,
924 unsigned ArgNo, unsigned &NumGPRs,
925 unsigned &ArgOffset) {
926 MachineFunction &MF = DAG.getMachineFunction();
927 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
928 SDValue Root = Op.getOperand(0);
929 MachineRegisterInfo &RegInfo = MF.getRegInfo();
931 static const unsigned GPRArgRegs[] = {
932 ARM::R0, ARM::R1, ARM::R2, ARM::R3
939 ISD::ArgFlagsTy Flags =
940 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags();
941 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
942 ObjSize, GPRPad, StackPad, Flags);
944 ArgOffset += StackPad;
948 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
949 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
950 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
951 if (ObjectVT == MVT::f32)
952 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
953 } else if (ObjGPRs == 2) {
954 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
955 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
956 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
958 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
959 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
960 SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
962 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
963 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
968 MachineFrameInfo *MFI = MF.getFrameInfo();
969 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
970 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
972 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
974 SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
975 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
976 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
979 ArgOffset += ObjSize; // Move on to the next argument.
986 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
987 std::vector<SDValue> ArgValues;
988 SDValue Root = Op.getOperand(0);
989 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
990 unsigned NumGPRs = 0; // GPRs used for parameter passing.
992 unsigned NumArgs = Op.getNode()->getNumValues()-1;
993 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
994 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
995 NumGPRs, ArgOffset));
997 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
999 static const unsigned GPRArgRegs[] = {
1000 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1003 MachineFunction &MF = DAG.getMachineFunction();
1004 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1005 MachineFrameInfo *MFI = MF.getFrameInfo();
1006 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1007 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1008 unsigned VARegSize = (4 - NumGPRs) * 4;
1009 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1010 if (VARegSaveSize) {
1011 // If this function is vararg, store any remaining integer argument regs
1012 // to their spots on the stack so that they may be loaded by deferencing
1013 // the result of va_next.
1014 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1015 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1016 VARegSaveSize - VARegSize);
1017 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1019 SmallVector<SDValue, 4> MemOps;
1020 for (; NumGPRs < 4; ++NumGPRs) {
1021 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1022 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1023 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1024 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1025 MemOps.push_back(Store);
1026 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1027 DAG.getConstant(4, getPointerTy()));
1029 if (!MemOps.empty())
1030 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1031 &MemOps[0], MemOps.size());
1033 // This will point to the next argument passed via stack.
1034 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1037 ArgValues.push_back(Root);
1039 // Return the new list of results.
1040 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1044 /// isFloatingPointZero - Return true if this is +0.0.
1045 static bool isFloatingPointZero(SDValue Op) {
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1047 return CFP->getValueAPF().isPosZero();
1048 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1049 // Maybe this has already been legalized into the constant pool?
1050 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1051 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1052 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1053 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1054 return CFP->getValueAPF().isPosZero();
1060 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1061 return ( isThumb && (C & ~255U) == 0) ||
1062 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1065 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1066 /// the given operands.
1067 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1068 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
1069 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1070 unsigned C = RHSC->getZExtValue();
1071 if (!isLegalCmpImmediate(C, isThumb)) {
1072 // Constant does not fit, try adjusting it by one?
1077 if (isLegalCmpImmediate(C-1, isThumb)) {
1078 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1079 RHS = DAG.getConstant(C-1, MVT::i32);
1084 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1085 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1086 RHS = DAG.getConstant(C-1, MVT::i32);
1091 if (isLegalCmpImmediate(C+1, isThumb)) {
1092 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1093 RHS = DAG.getConstant(C+1, MVT::i32);
1098 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1099 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1100 RHS = DAG.getConstant(C+1, MVT::i32);
1107 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1108 ARMISD::NodeType CompareType;
1111 CompareType = ARMISD::CMP;
1117 // Uses only N and Z Flags
1118 CompareType = ARMISD::CMPNZ;
1121 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1122 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1125 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1126 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) {
1128 if (!isFloatingPointZero(RHS))
1129 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1131 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1132 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1135 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1136 const ARMSubtarget *ST) {
1137 MVT VT = Op.getValueType();
1138 SDValue LHS = Op.getOperand(0);
1139 SDValue RHS = Op.getOperand(1);
1140 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1141 SDValue TrueVal = Op.getOperand(2);
1142 SDValue FalseVal = Op.getOperand(3);
1144 if (LHS.getValueType() == MVT::i32) {
1146 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1147 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1148 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1151 ARMCC::CondCodes CondCode, CondCode2;
1152 if (FPCCToARMCC(CC, CondCode, CondCode2))
1153 std::swap(TrueVal, FalseVal);
1155 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1156 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1157 SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
1158 SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1160 if (CondCode2 != ARMCC::AL) {
1161 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1162 // FIXME: Needs another CMP because flag can have but one use.
1163 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG);
1164 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1169 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1170 const ARMSubtarget *ST) {
1171 SDValue Chain = Op.getOperand(0);
1172 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1173 SDValue LHS = Op.getOperand(2);
1174 SDValue RHS = Op.getOperand(3);
1175 SDValue Dest = Op.getOperand(4);
1177 if (LHS.getValueType() == MVT::i32) {
1179 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1180 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1181 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1184 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1185 ARMCC::CondCodes CondCode, CondCode2;
1186 if (FPCCToARMCC(CC, CondCode, CondCode2))
1187 // Swap the LHS/RHS of the comparison if needed.
1188 std::swap(LHS, RHS);
1190 SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
1191 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1192 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1193 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1194 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1195 SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1196 if (CondCode2 != ARMCC::AL) {
1197 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1198 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1199 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1204 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1205 SDValue Chain = Op.getOperand(0);
1206 SDValue Table = Op.getOperand(1);
1207 SDValue Index = Op.getOperand(2);
1209 MVT PTy = getPointerTy();
1210 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1211 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1212 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1213 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1214 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1215 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1216 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1217 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1218 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
1219 Chain, Addr, NULL, 0);
1220 Chain = Addr.getValue(1);
1222 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1223 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1226 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1228 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1229 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1230 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1233 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1234 MVT VT = Op.getValueType();
1236 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1238 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1239 return DAG.getNode(Opc, VT, Op);
1242 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1243 // Implement fcopysign with a fabs and a conditional fneg.
1244 SDValue Tmp0 = Op.getOperand(0);
1245 SDValue Tmp1 = Op.getOperand(1);
1246 MVT VT = Op.getValueType();
1247 MVT SrcVT = Tmp1.getValueType();
1248 SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1249 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1250 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1251 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1252 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1256 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1258 SDValue Dst, SDValue Src,
1259 SDValue Size, unsigned Align,
1261 const Value *DstSV, uint64_t DstSVOff,
1262 const Value *SrcSV, uint64_t SrcSVOff){
1263 // Do repeated 4-byte loads and stores. To be improved.
1264 // This requires 4-byte alignment.
1265 if ((Align & 3) != 0)
1267 // This requires the copy size to be a constant, preferrably
1268 // within a subtarget-specific limit.
1269 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1272 uint64_t SizeVal = ConstantSize->getZExtValue();
1273 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1276 unsigned BytesLeft = SizeVal & 3;
1277 unsigned NumMemOps = SizeVal >> 2;
1278 unsigned EmittedNumMemOps = 0;
1280 unsigned VTSize = 4;
1282 const unsigned MAX_LOADS_IN_LDM = 6;
1283 SDValue TFOps[MAX_LOADS_IN_LDM];
1284 SDValue Loads[MAX_LOADS_IN_LDM];
1285 uint64_t SrcOff = 0, DstOff = 0;
1287 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1288 // same number of stores. The loads and stores will get combined into
1289 // ldm/stm later on.
1290 while (EmittedNumMemOps < NumMemOps) {
1292 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1293 Loads[i] = DAG.getLoad(VT, Chain,
1294 DAG.getNode(ISD::ADD, MVT::i32, Src,
1295 DAG.getConstant(SrcOff, MVT::i32)),
1296 SrcSV, SrcSVOff + SrcOff);
1297 TFOps[i] = Loads[i].getValue(1);
1300 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1303 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1304 TFOps[i] = DAG.getStore(Chain, Loads[i],
1305 DAG.getNode(ISD::ADD, MVT::i32, Dst,
1306 DAG.getConstant(DstOff, MVT::i32)),
1307 DstSV, DstSVOff + DstOff);
1310 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1312 EmittedNumMemOps += i;
1318 // Issue loads / stores for the trailing (1 - 3) bytes.
1319 unsigned BytesLeftSave = BytesLeft;
1322 if (BytesLeft >= 2) {
1330 Loads[i] = DAG.getLoad(VT, Chain,
1331 DAG.getNode(ISD::ADD, MVT::i32, Src,
1332 DAG.getConstant(SrcOff, MVT::i32)),
1333 SrcSV, SrcSVOff + SrcOff);
1334 TFOps[i] = Loads[i].getValue(1);
1337 BytesLeft -= VTSize;
1339 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1342 BytesLeft = BytesLeftSave;
1344 if (BytesLeft >= 2) {
1352 TFOps[i] = DAG.getStore(Chain, Loads[i],
1353 DAG.getNode(ISD::ADD, MVT::i32, Dst,
1354 DAG.getConstant(DstOff, MVT::i32)),
1355 DstSV, DstSVOff + DstOff);
1358 BytesLeft -= VTSize;
1360 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1363 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1364 // Turn f64->i64 into FMRRD.
1365 assert(N->getValueType(0) == MVT::i64 &&
1366 N->getOperand(0).getValueType() == MVT::f64);
1368 SDValue Op = N->getOperand(0);
1369 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1372 // Merge the pieces into a single i64 value.
1373 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode();
1376 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1377 assert(N->getValueType(0) == MVT::i64 &&
1378 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1379 "Unknown shift to lower!");
1381 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1382 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1383 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1386 // If we are in thumb mode, we don't have RRX.
1387 if (ST->isThumb()) return 0;
1389 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1390 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1391 DAG.getConstant(0, MVT::i32));
1392 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1393 DAG.getConstant(1, MVT::i32));
1395 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1396 // captures the result into a carry flag.
1397 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1398 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1400 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1401 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1403 // Merge the pieces into a single i64 value.
1404 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
1408 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1409 switch (Op.getOpcode()) {
1410 default: assert(0 && "Don't know how to custom lower this!"); abort();
1411 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1412 case ISD::GlobalAddress:
1413 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1414 LowerGlobalAddressELF(Op, DAG);
1415 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1416 case ISD::CALL: return LowerCALL(Op, DAG);
1417 case ISD::RET: return LowerRET(Op, DAG);
1418 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1419 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1420 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1421 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1422 case ISD::SINT_TO_FP:
1423 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1424 case ISD::FP_TO_SINT:
1425 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1426 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1427 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1428 case ISD::RETURNADDR: break;
1429 case ISD::FRAMEADDR: break;
1430 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1431 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1434 // FIXME: Remove these when LegalizeDAGTypes lands.
1435 case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
1437 case ISD::SRA: return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0);
1443 /// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal
1445 SDNode *ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
1446 switch (N->getOpcode()) {
1447 default: assert(0 && "Don't know how to custom expand this!"); abort();
1448 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
1450 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
1455 //===----------------------------------------------------------------------===//
1456 // ARM Scheduler Hooks
1457 //===----------------------------------------------------------------------===//
1460 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1461 MachineBasicBlock *BB) {
1462 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1463 switch (MI->getOpcode()) {
1464 default: assert(false && "Unexpected instr type to insert");
1465 case ARM::tMOVCCr: {
1466 // To "insert" a SELECT_CC instruction, we actually have to insert the
1467 // diamond control-flow pattern. The incoming instruction knows the
1468 // destination vreg to set, the condition code register to branch on, the
1469 // true/false values to select between, and a branch opcode to use.
1470 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1471 MachineFunction::iterator It = BB;
1477 // cmpTY ccX, r1, r2
1479 // fallthrough --> copy0MBB
1480 MachineBasicBlock *thisMBB = BB;
1481 MachineFunction *F = BB->getParent();
1482 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1483 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1484 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1485 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1486 F->insert(It, copy0MBB);
1487 F->insert(It, sinkMBB);
1488 // Update machine-CFG edges by first adding all successors of the current
1489 // block to the new block which will contain the Phi node for the select.
1490 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1491 e = BB->succ_end(); i != e; ++i)
1492 sinkMBB->addSuccessor(*i);
1493 // Next, remove all successors of the current block, and add the true
1494 // and fallthrough blocks as its successors.
1495 while(!BB->succ_empty())
1496 BB->removeSuccessor(BB->succ_begin());
1497 BB->addSuccessor(copy0MBB);
1498 BB->addSuccessor(sinkMBB);
1501 // %FalseValue = ...
1502 // # fallthrough to sinkMBB
1505 // Update machine-CFG edges
1506 BB->addSuccessor(sinkMBB);
1509 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1512 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1513 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1514 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1516 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1522 //===----------------------------------------------------------------------===//
1523 // ARM Optimization Hooks
1524 //===----------------------------------------------------------------------===//
1526 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1527 static SDValue PerformFMRRDCombine(SDNode *N,
1528 TargetLowering::DAGCombinerInfo &DCI) {
1529 // fmrrd(fmdrr x, y) -> x,y
1530 SDValue InDouble = N->getOperand(0);
1531 if (InDouble.getOpcode() == ARMISD::FMDRR)
1532 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1536 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1537 DAGCombinerInfo &DCI) const {
1538 switch (N->getOpcode()) {
1540 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1547 /// isLegalAddressImmediate - Return true if the integer value can be used
1548 /// as the offset of the target addressing mode for load / store of the
1550 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1551 const ARMSubtarget *Subtarget) {
1555 if (Subtarget->isThumb()) {
1560 switch (VT.getSimpleVT()) {
1561 default: return false;
1576 if ((V & (Scale - 1)) != 0)
1579 return V == (V & ((1LL << 5) - 1));
1584 switch (VT.getSimpleVT()) {
1585 default: return false;
1590 return V == (V & ((1LL << 12) - 1));
1593 return V == (V & ((1LL << 8) - 1));
1596 if (!Subtarget->hasVFP2())
1601 return V == (V & ((1LL << 8) - 1));
1605 /// isLegalAddressingMode - Return true if the addressing mode represented
1606 /// by AM is legal for this target, for a load/store of the specified type.
1607 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1608 const Type *Ty) const {
1609 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget))
1612 // Can never fold addr of global into load/store.
1617 case 0: // no scale reg, must be "r+i" or "r", or "i".
1620 if (Subtarget->isThumb())
1624 // ARM doesn't support any R+R*scale+imm addr modes.
1628 int Scale = AM.Scale;
1629 switch (getValueType(Ty).getSimpleVT()) {
1630 default: return false;
1635 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1636 // ldrd / strd are used, then its address mode is same as i16.
1638 if (Scale < 0) Scale = -Scale;
1642 return isPowerOf2_32(Scale & ~1);
1645 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1650 // Note, we allow "void" uses (basically, uses that aren't loads or
1651 // stores), because arm allows folding a scale into many arithmetic
1652 // operations. This should be made more precise and revisited later.
1654 // Allow r << imm, but the imm has to be a multiple of two.
1655 if (AM.Scale & 1) return false;
1656 return isPowerOf2_32(AM.Scale);
1664 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1665 bool isSEXTLoad, SDValue &Base,
1666 SDValue &Offset, bool &isInc,
1667 SelectionDAG &DAG) {
1668 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1671 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1673 Base = Ptr->getOperand(0);
1674 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1675 int RHSC = (int)RHS->getZExtValue();
1676 if (RHSC < 0 && RHSC > -256) {
1678 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1682 isInc = (Ptr->getOpcode() == ISD::ADD);
1683 Offset = Ptr->getOperand(1);
1685 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1687 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1688 int RHSC = (int)RHS->getZExtValue();
1689 if (RHSC < 0 && RHSC > -0x1000) {
1691 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1692 Base = Ptr->getOperand(0);
1697 if (Ptr->getOpcode() == ISD::ADD) {
1699 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1700 if (ShOpcVal != ARM_AM::no_shift) {
1701 Base = Ptr->getOperand(1);
1702 Offset = Ptr->getOperand(0);
1704 Base = Ptr->getOperand(0);
1705 Offset = Ptr->getOperand(1);
1710 isInc = (Ptr->getOpcode() == ISD::ADD);
1711 Base = Ptr->getOperand(0);
1712 Offset = Ptr->getOperand(1);
1716 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1720 /// getPreIndexedAddressParts - returns true by value, base pointer and
1721 /// offset pointer and addressing mode by reference if the node's address
1722 /// can be legally represented as pre-indexed load / store address.
1724 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1726 ISD::MemIndexedMode &AM,
1727 SelectionDAG &DAG) {
1728 if (Subtarget->isThumb())
1733 bool isSEXTLoad = false;
1734 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1735 Ptr = LD->getBasePtr();
1736 VT = LD->getMemoryVT();
1737 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1738 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1739 Ptr = ST->getBasePtr();
1740 VT = ST->getMemoryVT();
1745 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
1748 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1754 /// getPostIndexedAddressParts - returns true by value, base pointer and
1755 /// offset pointer and addressing mode by reference if this node can be
1756 /// combined with a load / store to form a post-indexed load / store.
1757 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1760 ISD::MemIndexedMode &AM,
1761 SelectionDAG &DAG) {
1762 if (Subtarget->isThumb())
1767 bool isSEXTLoad = false;
1768 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1769 VT = LD->getMemoryVT();
1770 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1771 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1772 VT = ST->getMemoryVT();
1777 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1780 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1786 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1790 const SelectionDAG &DAG,
1791 unsigned Depth) const {
1792 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1793 switch (Op.getOpcode()) {
1795 case ARMISD::CMOV: {
1796 // Bits are known zero/one if known on the LHS and RHS.
1797 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1798 if (KnownZero == 0 && KnownOne == 0) return;
1800 APInt KnownZeroRHS, KnownOneRHS;
1801 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1802 KnownZeroRHS, KnownOneRHS, Depth+1);
1803 KnownZero &= KnownZeroRHS;
1804 KnownOne &= KnownOneRHS;
1810 //===----------------------------------------------------------------------===//
1811 // ARM Inline Assembly Support
1812 //===----------------------------------------------------------------------===//
1814 /// getConstraintType - Given a constraint letter, return the type of
1815 /// constraint it is for this target.
1816 ARMTargetLowering::ConstraintType
1817 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1818 if (Constraint.size() == 1) {
1819 switch (Constraint[0]) {
1821 case 'l': return C_RegisterClass;
1822 case 'w': return C_RegisterClass;
1825 return TargetLowering::getConstraintType(Constraint);
1828 std::pair<unsigned, const TargetRegisterClass*>
1829 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1831 if (Constraint.size() == 1) {
1832 // GCC RS6000 Constraint Letters
1833 switch (Constraint[0]) {
1835 // FIXME: in thumb mode, 'l' is only low-regs.
1838 return std::make_pair(0U, ARM::GPRRegisterClass);
1841 return std::make_pair(0U, ARM::SPRRegisterClass);
1843 return std::make_pair(0U, ARM::DPRRegisterClass);
1847 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1850 std::vector<unsigned> ARMTargetLowering::
1851 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1853 if (Constraint.size() != 1)
1854 return std::vector<unsigned>();
1856 switch (Constraint[0]) { // GCC ARM Constraint Letters
1860 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1861 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1862 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1863 ARM::R12, ARM::LR, 0);
1866 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1867 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1868 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1869 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1870 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1871 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1872 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1873 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1875 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1876 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1877 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1878 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1882 return std::vector<unsigned>();