1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/ADT/VectorExtras.h"
34 #include "llvm/Support/MathExtras.h"
37 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
38 : TargetLowering(TM), ARMPCLabelIndex(0) {
39 Subtarget = &TM.getSubtarget<ARMSubtarget>();
41 // Uses VFP for Thumb libfuncs if available.
42 if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) {
43 // Single-precision floating-point arithmetic.
44 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
45 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
46 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
47 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
49 // Double-precision floating-point arithmetic.
50 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
51 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
52 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
53 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
55 // Single-precision comparisons.
56 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
57 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
58 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
59 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
60 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
61 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
62 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
63 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
65 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
66 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
67 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
68 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
69 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
70 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
71 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
72 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
74 // Double-precision comparisons.
75 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
76 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
77 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
78 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
79 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
80 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
81 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
82 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
84 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
85 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
86 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
87 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
88 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
89 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
93 // Floating-point to integer conversions.
94 // i64 conversions are done via library routines even when generating VFP
95 // instructions, so use the same ones.
96 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
97 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
98 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
99 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
101 // Conversions between floating types.
102 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
103 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
105 // Integer to floating-point conversions.
106 // i64 conversions are done via library routines even when generating VFP
107 // instructions, so use the same ones.
108 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
109 // __floatunsidf vs. __floatunssidfvfp.
110 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
111 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
112 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
113 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
116 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
117 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
118 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
119 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
122 // ARM does not have f32 extending load.
123 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
125 // ARM supports all 4 flavors of integer indexed load / store.
126 for (unsigned im = (unsigned)ISD::PRE_INC;
127 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
128 setIndexedLoadAction(im, MVT::i1, Legal);
129 setIndexedLoadAction(im, MVT::i8, Legal);
130 setIndexedLoadAction(im, MVT::i16, Legal);
131 setIndexedLoadAction(im, MVT::i32, Legal);
132 setIndexedStoreAction(im, MVT::i1, Legal);
133 setIndexedStoreAction(im, MVT::i8, Legal);
134 setIndexedStoreAction(im, MVT::i16, Legal);
135 setIndexedStoreAction(im, MVT::i32, Legal);
138 // i64 operation support.
139 if (Subtarget->isThumb()) {
140 setOperationAction(ISD::MUL, MVT::i64, Expand);
141 setOperationAction(ISD::MULHU, MVT::i32, Expand);
142 setOperationAction(ISD::MULHS, MVT::i32, Expand);
144 setOperationAction(ISD::MUL, MVT::i64, Custom);
145 setOperationAction(ISD::MULHU, MVT::i32, Custom);
146 if (!Subtarget->hasV6Ops())
147 setOperationAction(ISD::MULHS, MVT::i32, Custom);
149 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
150 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
151 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
152 setOperationAction(ISD::SRL, MVT::i64, Custom);
153 setOperationAction(ISD::SRA, MVT::i64, Custom);
155 // ARM does not have ROTL.
156 setOperationAction(ISD::ROTL, MVT::i32, Expand);
157 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
158 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
159 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
160 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
162 // Only ARMv6 has BSWAP.
163 if (!Subtarget->hasV6Ops())
164 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
166 // These are expanded into libcalls.
167 setOperationAction(ISD::SDIV, MVT::i32, Expand);
168 setOperationAction(ISD::UDIV, MVT::i32, Expand);
169 setOperationAction(ISD::SREM, MVT::i32, Expand);
170 setOperationAction(ISD::UREM, MVT::i32, Expand);
172 // Support label based line numbers.
173 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
174 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
175 // FIXME - use subtarget debug flags
176 if (!Subtarget->isTargetDarwin())
177 setOperationAction(ISD::LABEL, MVT::Other, Expand);
179 setOperationAction(ISD::RET, MVT::Other, Custom);
180 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
183 // Expand mem operations genericly.
184 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
185 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
186 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
188 // Use the default implementation.
189 setOperationAction(ISD::VASTART , MVT::Other, Expand);
190 setOperationAction(ISD::VAARG , MVT::Other, Expand);
191 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
192 setOperationAction(ISD::VAEND , MVT::Other, Expand);
193 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
194 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
195 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
197 if (!Subtarget->hasV6Ops()) {
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
203 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
204 // Turn f64->i64 into FMRRD iff target supports vfp2.
205 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
207 setOperationAction(ISD::SETCC , MVT::i32, Expand);
208 setOperationAction(ISD::SETCC , MVT::f32, Expand);
209 setOperationAction(ISD::SETCC , MVT::f64, Expand);
210 setOperationAction(ISD::SELECT , MVT::i32, Expand);
211 setOperationAction(ISD::SELECT , MVT::f32, Expand);
212 setOperationAction(ISD::SELECT , MVT::f64, Expand);
213 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
214 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
215 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
217 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
218 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
219 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
220 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
221 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
223 setOperationAction(ISD::VASTART, MVT::Other, Custom);
224 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
225 setOperationAction(ISD::VAEND, MVT::Other, Expand);
226 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
227 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
229 // FP Constants can't be immediates.
230 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
231 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
233 // We don't support sin/cos/fmod/copysign
234 setOperationAction(ISD::FSIN , MVT::f64, Expand);
235 setOperationAction(ISD::FSIN , MVT::f32, Expand);
236 setOperationAction(ISD::FCOS , MVT::f32, Expand);
237 setOperationAction(ISD::FCOS , MVT::f64, Expand);
238 setOperationAction(ISD::FREM , MVT::f64, Expand);
239 setOperationAction(ISD::FREM , MVT::f32, Expand);
240 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
243 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
244 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
245 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
246 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
247 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
249 setStackPointerRegisterToSaveRestore(ARM::SP);
251 setSchedulingPreference(SchedulingForRegPressure);
252 computeRegisterProperties();
256 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
259 case ARMISD::Wrapper: return "ARMISD::Wrapper";
260 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
261 case ARMISD::CALL: return "ARMISD::CALL";
262 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
263 case ARMISD::tCALL: return "ARMISD::tCALL";
264 case ARMISD::BRCOND: return "ARMISD::BRCOND";
265 case ARMISD::BR_JT: return "ARMISD::BR_JT";
266 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
267 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
268 case ARMISD::CMP: return "ARMISD::CMP";
269 case ARMISD::CMPFP: return "ARMISD::CMPFP";
270 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
271 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
272 case ARMISD::CMOV: return "ARMISD::CMOV";
273 case ARMISD::CNEG: return "ARMISD::CNEG";
275 case ARMISD::FTOSI: return "ARMISD::FTOSI";
276 case ARMISD::FTOUI: return "ARMISD::FTOUI";
277 case ARMISD::SITOF: return "ARMISD::SITOF";
278 case ARMISD::UITOF: return "ARMISD::UITOF";
279 case ARMISD::MULHILOU: return "ARMISD::MULHILOU";
280 case ARMISD::MULHILOS: return "ARMISD::MULHILOS";
282 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
283 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
284 case ARMISD::RRX: return "ARMISD::RRX";
286 case ARMISD::FMRRD: return "ARMISD::FMRRD";
287 case ARMISD::FMDRR: return "ARMISD::FMDRR";
291 //===----------------------------------------------------------------------===//
293 //===----------------------------------------------------------------------===//
296 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
297 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
299 default: assert(0 && "Unknown condition code!");
300 case ISD::SETNE: return ARMCC::NE;
301 case ISD::SETEQ: return ARMCC::EQ;
302 case ISD::SETGT: return ARMCC::GT;
303 case ISD::SETGE: return ARMCC::GE;
304 case ISD::SETLT: return ARMCC::LT;
305 case ISD::SETLE: return ARMCC::LE;
306 case ISD::SETUGT: return ARMCC::HI;
307 case ISD::SETUGE: return ARMCC::HS;
308 case ISD::SETULT: return ARMCC::LO;
309 case ISD::SETULE: return ARMCC::LS;
313 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
314 /// returns true if the operands should be inverted to form the proper
316 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
317 ARMCC::CondCodes &CondCode2) {
319 CondCode2 = ARMCC::AL;
321 default: assert(0 && "Unknown FP condition!");
323 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
325 case ISD::SETOGT: CondCode = ARMCC::GT; break;
327 case ISD::SETOGE: CondCode = ARMCC::GE; break;
328 case ISD::SETOLT: CondCode = ARMCC::MI; break;
329 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
330 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
331 case ISD::SETO: CondCode = ARMCC::VC; break;
332 case ISD::SETUO: CondCode = ARMCC::VS; break;
333 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
334 case ISD::SETUGT: CondCode = ARMCC::HI; break;
335 case ISD::SETUGE: CondCode = ARMCC::PL; break;
337 case ISD::SETULT: CondCode = ARMCC::LT; break;
339 case ISD::SETULE: CondCode = ARMCC::LE; break;
341 case ISD::SETUNE: CondCode = ARMCC::NE; break;
347 HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
348 unsigned StackOffset, unsigned &NeededGPRs,
349 unsigned &NeededStackSize, unsigned &GPRPad,
350 unsigned &StackPad, unsigned Flags) {
355 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
356 GPRPad = NumGPRs % ((align + 3)/4);
357 StackPad = StackOffset % align;
358 unsigned firstGPR = NumGPRs + GPRPad;
360 default: assert(0 && "Unhandled argument type!");
372 else if (firstGPR == 3) {
380 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
381 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
383 SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
384 MVT::ValueType RetVT= Op.Val->getValueType(0);
385 SDOperand Chain = Op.getOperand(0);
386 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
387 assert((CallConv == CallingConv::C ||
388 CallConv == CallingConv::Fast) && "unknown calling convention");
389 SDOperand Callee = Op.getOperand(4);
390 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
391 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
392 unsigned NumGPRs = 0; // GPRs used for parameter passing.
394 // Count how many bytes are to be pushed on the stack.
395 unsigned NumBytes = 0;
397 // Add up all the space actually used.
398 for (unsigned i = 0; i < NumOps; ++i) {
403 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
404 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
405 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
406 GPRPad, StackPad, Flags);
407 NumBytes += ObjSize + StackPad;
408 NumGPRs += ObjGPRs + GPRPad;
411 // Adjust the stack pointer for the new arguments...
412 // These operations are automatically eliminated by the prolog/epilog pass
413 Chain = DAG.getCALLSEQ_START(Chain,
414 DAG.getConstant(NumBytes, MVT::i32));
416 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
418 static const unsigned GPRArgRegs[] = {
419 ARM::R0, ARM::R1, ARM::R2, ARM::R3
423 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
424 std::vector<SDOperand> MemOpChains;
425 for (unsigned i = 0; i != NumOps; ++i) {
426 SDOperand Arg = Op.getOperand(5+2*i);
427 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
428 MVT::ValueType ArgVT = Arg.getValueType();
434 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
435 ObjSize, GPRPad, StackPad, Flags);
437 ArgOffset += StackPad;
440 default: assert(0 && "Unexpected ValueType for argument!");
442 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
445 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
446 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
449 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
450 DAG.getConstant(0, getPointerTy()));
451 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
452 DAG.getConstant(1, getPointerTy()));
453 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
455 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
457 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
458 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
459 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
464 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
465 DAG.getVTList(MVT::i32, MVT::i32),
467 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
469 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
472 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
473 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
474 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
481 assert(ObjSize != 0);
482 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
483 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
484 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
488 ArgOffset += ObjSize;
491 if (!MemOpChains.empty())
492 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
493 &MemOpChains[0], MemOpChains.size());
495 // Build a sequence of copy-to-reg nodes chained together with token chain
496 // and flag operands which copy the outgoing args into the appropriate regs.
498 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
499 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
501 InFlag = Chain.getValue(1);
504 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
505 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
506 // node so that legalize doesn't hack it.
507 bool isDirect = false;
508 bool isARMFunc = false;
509 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
510 GlobalValue *GV = G->getGlobal();
512 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
513 GV->hasLinkOnceLinkage());
514 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
515 getTargetMachine().getRelocationModel() != Reloc::Static;
516 isARMFunc = !Subtarget->isThumb() || isStub;
517 // tBX takes a register source operand.
518 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
519 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
521 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
522 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
523 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
524 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
525 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
527 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
528 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
530 bool isStub = Subtarget->isTargetDarwin() &&
531 getTargetMachine().getRelocationModel() != Reloc::Static;
532 isARMFunc = !Subtarget->isThumb() || isStub;
533 // tBX takes a register source operand.
534 const char *Sym = S->getSymbol();
535 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
536 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
538 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
539 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
540 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
541 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
542 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
544 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
547 // FIXME: handle tail calls differently.
549 if (Subtarget->isThumb()) {
550 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
551 CallOpc = ARMISD::CALL_NOLINK;
553 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
555 CallOpc = (isDirect || Subtarget->hasV5TOps())
556 ? ARMISD::CALL : ARMISD::CALL_NOLINK;
558 if (CallOpc == ARMISD::CALL_NOLINK) {
559 // On CALL_NOLINK we must move PC to LR
560 Chain = DAG.getCopyToReg(Chain, ARM::LR,
561 DAG.getRegister(ARM::PC, MVT::i32), InFlag);
562 InFlag = Chain.getValue(1);
565 std::vector<MVT::ValueType> NodeTys;
566 NodeTys.push_back(MVT::Other); // Returns a chain
567 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
569 std::vector<SDOperand> Ops;
570 Ops.push_back(Chain);
571 Ops.push_back(Callee);
573 // Add argument registers to the end of the list so that they are known live
575 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
576 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
577 RegsToPass[i].second.getValueType()));
580 Ops.push_back(InFlag);
581 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
582 InFlag = Chain.getValue(1);
584 SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
585 Chain = DAG.getNode(ISD::CALLSEQ_END,
586 DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
587 ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
588 if (RetVT != MVT::Other)
589 InFlag = Chain.getValue(1);
591 std::vector<SDOperand> ResultVals;
594 // If the call has results, copy the values out of the ret val registers.
596 default: assert(0 && "Unexpected ret value!");
600 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
601 ResultVals.push_back(Chain.getValue(0));
602 if (Op.Val->getValueType(1) == MVT::i32) {
603 // Returns a i64 value.
604 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
605 Chain.getValue(2)).getValue(1);
606 ResultVals.push_back(Chain.getValue(0));
607 NodeTys.push_back(MVT::i32);
609 NodeTys.push_back(MVT::i32);
612 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
613 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
615 NodeTys.push_back(MVT::f32);
618 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
619 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
620 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
621 NodeTys.push_back(MVT::f64);
626 NodeTys.push_back(MVT::Other);
628 if (ResultVals.empty())
631 ResultVals.push_back(Chain);
632 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
634 return Res.getValue(Op.ResNo);
637 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
639 SDOperand Chain = Op.getOperand(0);
640 switch(Op.getNumOperands()) {
642 assert(0 && "Do not know how to return this many arguments!");
645 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
646 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
649 Op = Op.getOperand(1);
650 if (Op.getValueType() == MVT::f32) {
651 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
652 } else if (Op.getValueType() == MVT::f64) {
653 // Recursively legalize f64 -> i64.
654 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
655 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
656 DAG.getConstant(0, MVT::i32));
658 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
659 if (DAG.getMachineFunction().liveout_empty())
660 DAG.getMachineFunction().addLiveOut(ARM::R0);
663 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
664 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
665 // If we haven't noted the R0+R1 are live out, do so now.
666 if (DAG.getMachineFunction().liveout_empty()) {
667 DAG.getMachineFunction().addLiveOut(ARM::R0);
668 DAG.getMachineFunction().addLiveOut(ARM::R1);
673 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
674 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
677 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
678 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
679 // one of the above mentioned nodes. It has to be wrapped because otherwise
680 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
681 // be used to form addressing mode. These wrapped nodes will be selected
683 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
684 MVT::ValueType PtrVT = Op.getValueType();
685 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
687 if (CP->isMachineConstantPoolEntry())
688 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
691 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
693 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
696 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
697 /// even in dynamic-no-pic mode.
698 static bool GVIsIndirectSymbol(GlobalValue *GV) {
699 return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
700 (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
703 SDOperand ARMTargetLowering::LowerGlobalAddress(SDOperand Op,
705 MVT::ValueType PtrVT = getPointerTy();
706 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
707 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
708 bool IsIndirect = Subtarget->isTargetDarwin() && GVIsIndirectSymbol(GV);
710 if (RelocM == Reloc::Static)
711 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
713 unsigned PCAdj = (RelocM != Reloc::PIC_)
714 ? 0 : (Subtarget->isThumb() ? 4 : 8);
715 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
717 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
719 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
721 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
723 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
724 SDOperand Chain = Result.getValue(1);
726 if (RelocM == Reloc::PIC_) {
727 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
728 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
731 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
736 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
737 unsigned VarArgsFrameIndex) {
738 // vastart just stores the address of the VarArgsFrameIndex slot into the
739 // memory location argument.
740 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
741 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
742 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
743 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
747 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
748 unsigned *vRegs, unsigned ArgNo,
749 unsigned &NumGPRs, unsigned &ArgOffset) {
750 MachineFunction &MF = DAG.getMachineFunction();
751 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
752 SDOperand Root = Op.getOperand(0);
753 std::vector<SDOperand> ArgValues;
754 SSARegMap *RegMap = MF.getSSARegMap();
756 static const unsigned GPRArgRegs[] = {
757 ARM::R0, ARM::R1, ARM::R2, ARM::R3
764 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
765 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
766 ObjSize, GPRPad, StackPad, Flags);
768 ArgOffset += StackPad;
772 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
773 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
774 vRegs[NumGPRs] = VReg;
775 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
776 if (ObjectVT == MVT::f32)
777 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
778 } else if (ObjGPRs == 2) {
779 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
780 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
781 vRegs[NumGPRs] = VReg;
782 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
784 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
785 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
786 vRegs[NumGPRs+1] = VReg;
787 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
789 if (ObjectVT == MVT::i64)
790 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
792 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
797 // If the argument is actually used, emit a load from the right stack
799 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
800 MachineFrameInfo *MFI = MF.getFrameInfo();
801 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
802 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
804 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
806 SDOperand ArgValue2 =
807 DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
808 if (ObjectVT == MVT::i64)
809 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
811 ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
814 // Don't emit a dead load.
815 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
818 ArgOffset += ObjSize; // Move on to the next argument.
825 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
826 std::vector<SDOperand> ArgValues;
827 SDOperand Root = Op.getOperand(0);
828 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
829 unsigned NumGPRs = 0; // GPRs used for parameter passing.
832 unsigned NumArgs = Op.Val->getNumValues()-1;
833 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
834 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
835 NumGPRs, ArgOffset));
837 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
839 static const unsigned GPRArgRegs[] = {
840 ARM::R0, ARM::R1, ARM::R2, ARM::R3
843 MachineFunction &MF = DAG.getMachineFunction();
844 SSARegMap *RegMap = MF.getSSARegMap();
845 MachineFrameInfo *MFI = MF.getFrameInfo();
846 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
847 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
848 unsigned VARegSize = (4 - NumGPRs) * 4;
849 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
851 // If this function is vararg, store any remaining integer argument regs
852 // to their spots on the stack so that they may be loaded by deferencing
853 // the result of va_next.
854 AFI->setVarArgsRegSaveSize(VARegSaveSize);
855 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
856 VARegSaveSize - VARegSize);
857 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
859 SmallVector<SDOperand, 4> MemOps;
860 for (; NumGPRs < 4; ++NumGPRs) {
861 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
862 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
863 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
864 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
865 MemOps.push_back(Store);
866 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
867 DAG.getConstant(4, getPointerTy()));
870 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
871 &MemOps[0], MemOps.size());
873 // This will point to the next argument passed via stack.
874 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
877 ArgValues.push_back(Root);
879 // Return the new list of results.
880 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
881 Op.Val->value_end());
882 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
885 /// isFloatingPointZero - Return true if this is +0.0.
886 static bool isFloatingPointZero(SDOperand Op) {
887 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
888 return CFP->isExactlyValue(0.0);
889 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
890 // Maybe this has already been legalized into the constant pool?
891 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
892 SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
893 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
894 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
895 return CFP->isExactlyValue(0.0);
901 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
902 return ( isThumb && (C & ~255U) == 0) ||
903 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
906 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
907 /// the given operands.
908 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
909 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
910 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
911 unsigned C = RHSC->getValue();
912 if (!isLegalCmpImmediate(C, isThumb)) {
913 // Constant does not fit, try adjusting it by one?
918 if (isLegalCmpImmediate(C-1, isThumb)) {
919 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
920 RHS = DAG.getConstant(C-1, MVT::i32);
925 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
926 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
927 RHS = DAG.getConstant(C-1, MVT::i32);
932 if (isLegalCmpImmediate(C+1, isThumb)) {
933 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
934 RHS = DAG.getConstant(C+1, MVT::i32);
939 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
940 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
941 RHS = DAG.getConstant(C+1, MVT::i32);
948 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
949 ARMCC = DAG.getConstant(CondCode, MVT::i32);
950 return DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
953 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
954 static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
956 if (!isFloatingPointZero(RHS))
957 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
959 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
960 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
963 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
964 const ARMSubtarget *ST) {
965 MVT::ValueType VT = Op.getValueType();
966 SDOperand LHS = Op.getOperand(0);
967 SDOperand RHS = Op.getOperand(1);
968 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
969 SDOperand TrueVal = Op.getOperand(2);
970 SDOperand FalseVal = Op.getOperand(3);
972 if (LHS.getValueType() == MVT::i32) {
974 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
975 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
978 ARMCC::CondCodes CondCode, CondCode2;
979 if (FPCCToARMCC(CC, CondCode, CondCode2))
980 std::swap(TrueVal, FalseVal);
982 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
983 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
984 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
986 if (CondCode2 != ARMCC::AL) {
987 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
988 // FIXME: Needs another CMP because flag can have but one use.
989 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
990 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
995 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
996 const ARMSubtarget *ST) {
997 SDOperand Chain = Op.getOperand(0);
998 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
999 SDOperand LHS = Op.getOperand(2);
1000 SDOperand RHS = Op.getOperand(3);
1001 SDOperand Dest = Op.getOperand(4);
1003 if (LHS.getValueType() == MVT::i32) {
1005 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1006 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
1009 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1010 ARMCC::CondCodes CondCode, CondCode2;
1011 if (FPCCToARMCC(CC, CondCode, CondCode2))
1012 // Swap the LHS/RHS of the comparison if needed.
1013 std::swap(LHS, RHS);
1015 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1016 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1017 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1018 SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
1019 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1020 if (CondCode2 != ARMCC::AL) {
1021 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1022 SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
1023 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1028 SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1029 SDOperand Chain = Op.getOperand(0);
1030 SDOperand Table = Op.getOperand(1);
1031 SDOperand Index = Op.getOperand(2);
1033 MVT::ValueType PTy = getPointerTy();
1034 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1035 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1036 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1037 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1038 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1039 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1040 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1041 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1042 Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1043 Chain = Addr.getValue(1);
1045 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1046 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1049 static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1051 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1052 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1053 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1056 static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1057 MVT::ValueType VT = Op.getValueType();
1059 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1061 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1062 return DAG.getNode(Opc, VT, Op);
1065 static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1066 // Implement fcopysign with a fabs and a conditional fneg.
1067 SDOperand Tmp0 = Op.getOperand(0);
1068 SDOperand Tmp1 = Op.getOperand(1);
1069 MVT::ValueType VT = Op.getValueType();
1070 MVT::ValueType SrcVT = Tmp1.getValueType();
1071 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1072 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1073 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1074 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
1077 static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
1078 // Turn f64->i64 into FMRRD.
1079 assert(Op.getValueType() == MVT::i64 &&
1080 Op.getOperand(0).getValueType() == MVT::f64);
1082 Op = Op.getOperand(0);
1083 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1086 // Merge the pieces into a single i64 value.
1087 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
1090 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1091 // FIXME: All this code is target-independent. Create a new target-indep
1092 // MULHILO node and move this code to the legalizer.
1094 assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!");
1096 SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1097 DAG.getConstant(0, MVT::i32));
1098 SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1099 DAG.getConstant(0, MVT::i32));
1101 const TargetLowering &TL = DAG.getTargetLoweringInfo();
1102 unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
1103 unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
1106 // Figure out how to lower this multiply.
1107 if (LHSSB >= 33 && RHSSB >= 33) {
1108 // If the input values are both sign extended, we can emit a mulhs+mul.
1109 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1110 Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
1111 } else if (LHSSB == 32 && RHSSB == 32 &&
1112 TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
1113 TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
1114 // If the inputs are zero extended, use mulhu.
1115 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1116 Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
1118 SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1119 DAG.getConstant(1, MVT::i32));
1120 SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1121 DAG.getConstant(1, MVT::i32));
1123 // Lo,Hi = umul LHS, RHS.
1124 SDOperand Ops[] = { LL, RL };
1125 SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU,
1126 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2);
1128 Hi = UMul64.getValue(1);
1129 RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH);
1130 LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL);
1131 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH);
1132 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH);
1135 // Merge the pieces into a single i64 value.
1136 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1139 static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) {
1140 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1141 return DAG.getNode(ARMISD::MULHILOU,
1142 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1145 static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) {
1146 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1147 return DAG.getNode(ARMISD::MULHILOS,
1148 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1151 static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG,
1152 const ARMSubtarget *ST) {
1153 assert(Op.getValueType() == MVT::i64 &&
1154 (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
1155 "Unknown shift to lower!");
1157 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1158 if (!isa<ConstantSDNode>(Op.getOperand(1)) ||
1159 cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1)
1162 // If we are in thumb mode, we don't have RRX.
1163 if (ST->isThumb()) return SDOperand();
1165 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1166 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1167 DAG.getConstant(0, MVT::i32));
1168 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1169 DAG.getConstant(1, MVT::i32));
1171 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1172 // captures the result into a carry flag.
1173 unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1174 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1176 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1177 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1179 // Merge the pieces into a single i64 value.
1180 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1183 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1184 switch (Op.getOpcode()) {
1185 default: assert(0 && "Don't know how to custom lower this!"); abort();
1186 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1187 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1188 case ISD::CALL: return LowerCALL(Op, DAG);
1189 case ISD::RET: return LowerRET(Op, DAG);
1190 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1191 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1192 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1193 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1194 case ISD::SINT_TO_FP:
1195 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1196 case ISD::FP_TO_SINT:
1197 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1198 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1199 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
1200 case ISD::MUL: return LowerMUL(Op, DAG);
1201 case ISD::MULHU: return LowerMULHU(Op, DAG);
1202 case ISD::MULHS: return LowerMULHS(Op, DAG);
1204 case ISD::SRA: return LowerSRx(Op, DAG, Subtarget);
1205 case ISD::FORMAL_ARGUMENTS:
1206 return LowerFORMAL_ARGUMENTS(Op, DAG);
1207 case ISD::RETURNADDR: break;
1208 case ISD::FRAMEADDR: break;
1213 //===----------------------------------------------------------------------===//
1214 // ARM Scheduler Hooks
1215 //===----------------------------------------------------------------------===//
1218 ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1219 MachineBasicBlock *BB) {
1220 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1221 switch (MI->getOpcode()) {
1222 default: assert(false && "Unexpected instr type to insert");
1223 case ARM::tMOVCCr: {
1224 // To "insert" a SELECT_CC instruction, we actually have to insert the
1225 // diamond control-flow pattern. The incoming instruction knows the
1226 // destination vreg to set, the condition code register to branch on, the
1227 // true/false values to select between, and a branch opcode to use.
1228 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1229 ilist<MachineBasicBlock>::iterator It = BB;
1235 // cmpTY ccX, r1, r2
1237 // fallthrough --> copy0MBB
1238 MachineBasicBlock *thisMBB = BB;
1239 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1240 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1241 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1242 .addImm(MI->getOperand(3).getImm());
1243 MachineFunction *F = BB->getParent();
1244 F->getBasicBlockList().insert(It, copy0MBB);
1245 F->getBasicBlockList().insert(It, sinkMBB);
1246 // Update machine-CFG edges by first adding all successors of the current
1247 // block to the new block which will contain the Phi node for the select.
1248 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1249 e = BB->succ_end(); i != e; ++i)
1250 sinkMBB->addSuccessor(*i);
1251 // Next, remove all successors of the current block, and add the true
1252 // and fallthrough blocks as its successors.
1253 while(!BB->succ_empty())
1254 BB->removeSuccessor(BB->succ_begin());
1255 BB->addSuccessor(copy0MBB);
1256 BB->addSuccessor(sinkMBB);
1259 // %FalseValue = ...
1260 // # fallthrough to sinkMBB
1263 // Update machine-CFG edges
1264 BB->addSuccessor(sinkMBB);
1267 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1270 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1271 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1272 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1274 delete MI; // The pseudo instruction is gone now.
1280 //===----------------------------------------------------------------------===//
1281 // ARM Optimization Hooks
1282 //===----------------------------------------------------------------------===//
1284 /// isLegalAddressExpression - Return true if the binary expression made up of
1285 /// specified opcode, operands, and type can be folded into target addressing
1286 /// mode for load / store of the given type.
1287 bool ARMTargetLowering::isLegalAddressExpression(unsigned Opc, Value *Op0,
1288 Value *Op1, const Type *Ty) const {
1289 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1290 if (Opc == Instruction::Add)
1291 return isLegalAddressImmediate(Op1C->getSExtValue(), Ty);
1292 if (Opc == Instruction::Sub)
1293 return isLegalAddressImmediate(-Op1C->getSExtValue(), Ty);
1298 /// isLegalAddressImmediate - Return true if the integer value can be used
1299 /// as the offset of the target addressing mode for load / store of the
1301 bool ARMTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
1305 MVT::ValueType VT = getValueType(Ty);
1306 if (Subtarget->isThumb()) {
1312 default: return false;
1327 if ((V & (Scale - 1)) != 0)
1330 return V == V & ((1LL << 5) - 1);
1336 default: return false;
1341 return V == V & ((1LL << 12) - 1);
1344 return V == V & ((1LL << 8) - 1);
1347 if (!Subtarget->hasVFP2())
1352 return V == V & ((1LL << 8) - 1);
1356 bool ARMTargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
1360 /// isLegalAddressScale - Return true if the integer value can be used as
1361 /// the scale of the target addressing mode for load / store of the given
1363 bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
1364 if (Subtarget->isThumb())
1367 MVT::ValueType VT = getValueType(Ty);
1369 default: return false;
1378 return isPowerOf2_32(S);
1382 /// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
1383 /// and V works for isLegalAddressImmediate _and_ both can be applied
1384 /// simultaneously to the same instruction.
1385 bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S, int64_t V,
1386 const Type* Ty) const {
1388 return isLegalAddressScale(S, Ty);
1392 /// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
1393 /// and GV works for isLegalAddressImmediate _and_ both can be applied
1394 /// simultaneously to the same instruction.
1395 bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S,
1396 GlobalValue *GV) const {
1400 static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1401 bool isSEXTLoad, SDOperand &Base,
1402 SDOperand &Offset, bool &isInc,
1403 SelectionDAG &DAG) {
1404 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1407 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1409 Base = Ptr->getOperand(0);
1410 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1411 int RHSC = (int)RHS->getValue();
1412 if (RHSC < 0 && RHSC > -256) {
1414 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1418 isInc = (Ptr->getOpcode() == ISD::ADD);
1419 Offset = Ptr->getOperand(1);
1421 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1423 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1424 int RHSC = (int)RHS->getValue();
1425 if (RHSC < 0 && RHSC > -0x1000) {
1427 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1428 Base = Ptr->getOperand(0);
1433 if (Ptr->getOpcode() == ISD::ADD) {
1435 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1436 if (ShOpcVal != ARM_AM::no_shift) {
1437 Base = Ptr->getOperand(1);
1438 Offset = Ptr->getOperand(0);
1440 Base = Ptr->getOperand(0);
1441 Offset = Ptr->getOperand(1);
1446 isInc = (Ptr->getOpcode() == ISD::ADD);
1447 Base = Ptr->getOperand(0);
1448 Offset = Ptr->getOperand(1);
1452 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1456 /// getPreIndexedAddressParts - returns true by value, base pointer and
1457 /// offset pointer and addressing mode by reference if the node's address
1458 /// can be legally represented as pre-indexed load / store address.
1460 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1462 ISD::MemIndexedMode &AM,
1463 SelectionDAG &DAG) {
1464 if (Subtarget->isThumb())
1469 bool isSEXTLoad = false;
1470 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1471 Ptr = LD->getBasePtr();
1472 VT = LD->getLoadedVT();
1473 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1474 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1475 Ptr = ST->getBasePtr();
1476 VT = ST->getStoredVT();
1481 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1484 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1490 /// getPostIndexedAddressParts - returns true by value, base pointer and
1491 /// offset pointer and addressing mode by reference if this node can be
1492 /// combined with a load / store to form a post-indexed load / store.
1493 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1496 ISD::MemIndexedMode &AM,
1497 SelectionDAG &DAG) {
1498 if (Subtarget->isThumb())
1503 bool isSEXTLoad = false;
1504 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1505 VT = LD->getLoadedVT();
1506 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1507 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1508 VT = ST->getStoredVT();
1513 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1516 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1522 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1524 uint64_t &KnownZero,
1526 unsigned Depth) const {
1529 switch (Op.getOpcode()) {
1531 case ARMISD::CMOV: {
1532 // Bits are known zero/one if known on the LHS and RHS.
1533 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1534 if (KnownZero == 0 && KnownOne == 0) return;
1536 uint64_t KnownZeroRHS, KnownOneRHS;
1537 ComputeMaskedBits(Op.getOperand(1), Mask,
1538 KnownZeroRHS, KnownOneRHS, Depth+1);
1539 KnownZero &= KnownZeroRHS;
1540 KnownOne &= KnownOneRHS;
1546 //===----------------------------------------------------------------------===//
1547 // ARM Inline Assembly Support
1548 //===----------------------------------------------------------------------===//
1550 /// getConstraintType - Given a constraint letter, return the type of
1551 /// constraint it is for this target.
1552 ARMTargetLowering::ConstraintType
1553 ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
1554 switch (ConstraintLetter) {
1556 return C_RegisterClass;
1557 default: return TargetLowering::getConstraintType(ConstraintLetter);
1561 std::pair<unsigned, const TargetRegisterClass*>
1562 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1563 MVT::ValueType VT) const {
1564 if (Constraint.size() == 1) {
1565 // GCC RS6000 Constraint Letters
1566 switch (Constraint[0]) {
1568 // FIXME: in thumb mode, 'l' is only low-regs.
1571 return std::make_pair(0U, ARM::GPRRegisterClass);
1575 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1578 std::vector<unsigned> ARMTargetLowering::
1579 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1580 MVT::ValueType VT) const {
1581 if (Constraint.size() != 1)
1582 return std::vector<unsigned>();
1584 switch (Constraint[0]) { // GCC ARM Constraint Letters
1588 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1589 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1590 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1591 ARM::R12, ARM::LR, 0);
1594 return std::vector<unsigned>();