1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/VectorExtras.h"
36 #include "llvm/Support/MathExtras.h"
39 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM), ARMPCLabelIndex(0) {
41 Subtarget = &TM.getSubtarget<ARMSubtarget>();
43 if (Subtarget->isTargetDarwin()) {
45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
48 // Uses VFP for Thumb libfuncs if available.
49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
50 // Single-precision floating-point arithmetic.
51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
56 // Double-precision floating-point arithmetic.
57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
62 // Single-precision comparisons.
63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
81 // Double-precision comparisons.
82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
100 // Floating-point to integer conversions.
101 // i64 conversions are done via library routines even when generating VFP
102 // instructions, so use the same ones.
103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
108 // Conversions between floating types.
109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
112 // Integer to floating-point conversions.
113 // i64 conversions are done via library routines even when generating VFP
114 // instructions, so use the same ones.
115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
116 // __floatunsidf vs. __floatunssidfvfp.
117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
129 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
131 computeRegisterProperties();
133 // ARM does not have f32 extending load.
134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
136 // ARM does not have i1 sign extending load.
137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
139 // ARM supports all 4 flavors of integer indexed load / store.
140 for (unsigned im = (unsigned)ISD::PRE_INC;
141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
142 setIndexedLoadAction(im, MVT::i1, Legal);
143 setIndexedLoadAction(im, MVT::i8, Legal);
144 setIndexedLoadAction(im, MVT::i16, Legal);
145 setIndexedLoadAction(im, MVT::i32, Legal);
146 setIndexedStoreAction(im, MVT::i1, Legal);
147 setIndexedStoreAction(im, MVT::i8, Legal);
148 setIndexedStoreAction(im, MVT::i16, Legal);
149 setIndexedStoreAction(im, MVT::i32, Legal);
152 // i64 operation support.
153 if (Subtarget->isThumb()) {
154 setOperationAction(ISD::MUL, MVT::i64, Expand);
155 setOperationAction(ISD::MULHU, MVT::i32, Expand);
156 setOperationAction(ISD::MULHS, MVT::i32, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i64, Expand);
161 setOperationAction(ISD::MULHU, MVT::i32, Expand);
162 if (!Subtarget->hasV6Ops())
163 setOperationAction(ISD::MULHS, MVT::i32, Expand);
165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
168 setOperationAction(ISD::SRL, MVT::i64, Custom);
169 setOperationAction(ISD::SRA, MVT::i64, Custom);
171 // ARM does not have ROTL.
172 setOperationAction(ISD::ROTL, MVT::i32, Expand);
173 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
174 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
176 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
178 // Only ARMv6 has BSWAP.
179 if (!Subtarget->hasV6Ops())
180 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
182 // These are expanded into libcalls.
183 setOperationAction(ISD::SDIV, MVT::i32, Expand);
184 setOperationAction(ISD::UDIV, MVT::i32, Expand);
185 setOperationAction(ISD::SREM, MVT::i32, Expand);
186 setOperationAction(ISD::UREM, MVT::i32, Expand);
187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
190 // Support label based line numbers.
191 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
194 setOperationAction(ISD::RET, MVT::Other, Custom);
195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
200 // Use the default implementation.
201 setOperationAction(ISD::VASTART , MVT::Other, Custom);
202 setOperationAction(ISD::VAARG , MVT::Other, Expand);
203 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
204 setOperationAction(ISD::VAEND , MVT::Other, Expand);
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
208 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
210 if (!Subtarget->hasV6Ops()) {
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
216 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
217 // Turn f64->i64 into FMRRD iff target supports vfp2.
218 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
220 // We want to custom lower some of our intrinsics.
221 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
223 setOperationAction(ISD::SETCC , MVT::i32, Expand);
224 setOperationAction(ISD::SETCC , MVT::f32, Expand);
225 setOperationAction(ISD::SETCC , MVT::f64, Expand);
226 setOperationAction(ISD::SELECT , MVT::i32, Expand);
227 setOperationAction(ISD::SELECT , MVT::f32, Expand);
228 setOperationAction(ISD::SELECT , MVT::f64, Expand);
229 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
230 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
231 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
233 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
234 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
235 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
236 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
237 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
239 // We don't support sin/cos/fmod/copysign/pow
240 setOperationAction(ISD::FSIN , MVT::f64, Expand);
241 setOperationAction(ISD::FSIN , MVT::f32, Expand);
242 setOperationAction(ISD::FCOS , MVT::f32, Expand);
243 setOperationAction(ISD::FCOS , MVT::f64, Expand);
244 setOperationAction(ISD::FREM , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f32, Expand);
246 setOperationAction(ISD::FLOG , MVT::f64, Expand);
247 setOperationAction(ISD::FLOG , MVT::f32, Expand);
248 setOperationAction(ISD::FLOG2 , MVT::f64, Expand);
249 setOperationAction(ISD::FLOG2 , MVT::f32, Expand);
250 setOperationAction(ISD::FLOG10 , MVT::f64, Expand);
251 setOperationAction(ISD::FLOG10 , MVT::f32, Expand);
252 setOperationAction(ISD::FEXP , MVT::f64, Expand);
253 setOperationAction(ISD::FEXP , MVT::f32, Expand);
254 setOperationAction(ISD::FEXP2 , MVT::f64, Expand);
255 setOperationAction(ISD::FEXP2 , MVT::f32, Expand);
256 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
258 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
260 setOperationAction(ISD::FPOW , MVT::f64, Expand);
261 setOperationAction(ISD::FPOW , MVT::f32, Expand);
263 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
264 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
265 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
266 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
267 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
271 // We have target-specific dag combine patterns for the following nodes:
272 // ARMISD::FMRRD - No need to call setTargetDAGCombine
274 setStackPointerRegisterToSaveRestore(ARM::SP);
275 setSchedulingPreference(SchedulingForRegPressure);
276 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
277 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
279 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
283 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
286 case ARMISD::Wrapper: return "ARMISD::Wrapper";
287 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
288 case ARMISD::CALL: return "ARMISD::CALL";
289 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
290 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
291 case ARMISD::tCALL: return "ARMISD::tCALL";
292 case ARMISD::BRCOND: return "ARMISD::BRCOND";
293 case ARMISD::BR_JT: return "ARMISD::BR_JT";
294 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
295 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
296 case ARMISD::CMP: return "ARMISD::CMP";
297 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
298 case ARMISD::CMPFP: return "ARMISD::CMPFP";
299 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
300 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
301 case ARMISD::CMOV: return "ARMISD::CMOV";
302 case ARMISD::CNEG: return "ARMISD::CNEG";
304 case ARMISD::FTOSI: return "ARMISD::FTOSI";
305 case ARMISD::FTOUI: return "ARMISD::FTOUI";
306 case ARMISD::SITOF: return "ARMISD::SITOF";
307 case ARMISD::UITOF: return "ARMISD::UITOF";
309 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
310 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
311 case ARMISD::RRX: return "ARMISD::RRX";
313 case ARMISD::FMRRD: return "ARMISD::FMRRD";
314 case ARMISD::FMDRR: return "ARMISD::FMDRR";
316 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
320 //===----------------------------------------------------------------------===//
322 //===----------------------------------------------------------------------===//
325 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
326 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
328 default: assert(0 && "Unknown condition code!");
329 case ISD::SETNE: return ARMCC::NE;
330 case ISD::SETEQ: return ARMCC::EQ;
331 case ISD::SETGT: return ARMCC::GT;
332 case ISD::SETGE: return ARMCC::GE;
333 case ISD::SETLT: return ARMCC::LT;
334 case ISD::SETLE: return ARMCC::LE;
335 case ISD::SETUGT: return ARMCC::HI;
336 case ISD::SETUGE: return ARMCC::HS;
337 case ISD::SETULT: return ARMCC::LO;
338 case ISD::SETULE: return ARMCC::LS;
342 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
343 /// returns true if the operands should be inverted to form the proper
345 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
346 ARMCC::CondCodes &CondCode2) {
348 CondCode2 = ARMCC::AL;
350 default: assert(0 && "Unknown FP condition!");
352 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
354 case ISD::SETOGT: CondCode = ARMCC::GT; break;
356 case ISD::SETOGE: CondCode = ARMCC::GE; break;
357 case ISD::SETOLT: CondCode = ARMCC::MI; break;
358 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
359 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
360 case ISD::SETO: CondCode = ARMCC::VC; break;
361 case ISD::SETUO: CondCode = ARMCC::VS; break;
362 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
363 case ISD::SETUGT: CondCode = ARMCC::HI; break;
364 case ISD::SETUGE: CondCode = ARMCC::PL; break;
366 case ISD::SETULT: CondCode = ARMCC::LT; break;
368 case ISD::SETULE: CondCode = ARMCC::LE; break;
370 case ISD::SETUNE: CondCode = ARMCC::NE; break;
376 HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
377 unsigned StackOffset, unsigned &NeededGPRs,
378 unsigned &NeededStackSize, unsigned &GPRPad,
379 unsigned &StackPad, ISD::ArgFlagsTy Flags) {
384 unsigned align = Flags.getOrigAlign();
385 GPRPad = NumGPRs % ((align + 3)/4);
386 StackPad = StackOffset % align;
387 unsigned firstGPR = NumGPRs + GPRPad;
388 switch (ObjectVT.getSimpleVT()) {
389 default: assert(0 && "Unhandled argument type!");
401 else if (firstGPR == 3) {
409 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
410 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
412 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
413 MVT RetVT= Op.getNode()->getValueType(0);
414 SDValue Chain = Op.getOperand(0);
415 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
416 assert((CallConv == CallingConv::C ||
417 CallConv == CallingConv::Fast) && "unknown calling convention");
418 SDValue Callee = Op.getOperand(4);
419 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
420 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
421 unsigned NumGPRs = 0; // GPRs used for parameter passing.
423 // Count how many bytes are to be pushed on the stack.
424 unsigned NumBytes = 0;
426 // Add up all the space actually used.
427 for (unsigned i = 0; i < NumOps; ++i) {
432 MVT ObjectVT = Op.getOperand(5+2*i).getValueType();
433 ISD::ArgFlagsTy Flags =
434 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
435 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
436 GPRPad, StackPad, Flags);
437 NumBytes += ObjSize + StackPad;
438 NumGPRs += ObjGPRs + GPRPad;
441 // Adjust the stack pointer for the new arguments...
442 // These operations are automatically eliminated by the prolog/epilog pass
443 Chain = DAG.getCALLSEQ_START(Chain,
444 DAG.getConstant(NumBytes, MVT::i32));
446 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
448 static const unsigned GPRArgRegs[] = {
449 ARM::R0, ARM::R1, ARM::R2, ARM::R3
453 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
454 std::vector<SDValue> MemOpChains;
455 for (unsigned i = 0; i != NumOps; ++i) {
456 SDValue Arg = Op.getOperand(5+2*i);
457 ISD::ArgFlagsTy Flags =
458 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
459 MVT ArgVT = Arg.getValueType();
465 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
466 ObjSize, GPRPad, StackPad, Flags);
468 ArgOffset += StackPad;
470 switch (ArgVT.getSimpleVT()) {
471 default: assert(0 && "Unexpected ValueType for argument!");
473 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
476 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
477 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
480 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
481 DAG.getConstant(0, getPointerTy()));
482 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
483 DAG.getConstant(1, getPointerTy()));
484 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
486 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
488 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
489 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
490 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
495 SDValue Cvt = DAG.getNode(ARMISD::FMRRD,
496 DAG.getVTList(MVT::i32, MVT::i32),
498 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
500 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
503 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
504 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
505 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
512 assert(ObjSize != 0);
513 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
514 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
515 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
519 ArgOffset += ObjSize;
522 if (!MemOpChains.empty())
523 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
524 &MemOpChains[0], MemOpChains.size());
526 // Build a sequence of copy-to-reg nodes chained together with token chain
527 // and flag operands which copy the outgoing args into the appropriate regs.
529 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
530 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
532 InFlag = Chain.getValue(1);
535 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
536 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
537 // node so that legalize doesn't hack it.
538 bool isDirect = false;
539 bool isARMFunc = false;
540 bool isLocalARMFunc = false;
541 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
542 GlobalValue *GV = G->getGlobal();
544 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
545 GV->hasLinkOnceLinkage());
546 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
547 getTargetMachine().getRelocationModel() != Reloc::Static;
548 isARMFunc = !Subtarget->isThumb() || isStub;
549 // ARM call to a local ARM function is predicable.
550 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
551 // tBX takes a register source operand.
552 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
553 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
555 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
556 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
557 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
558 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
559 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
561 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
562 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
564 bool isStub = Subtarget->isTargetDarwin() &&
565 getTargetMachine().getRelocationModel() != Reloc::Static;
566 isARMFunc = !Subtarget->isThumb() || isStub;
567 // tBX takes a register source operand.
568 const char *Sym = S->getSymbol();
569 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
570 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
572 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
573 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
574 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
575 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
576 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
578 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
581 // FIXME: handle tail calls differently.
583 if (Subtarget->isThumb()) {
584 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
585 CallOpc = ARMISD::CALL_NOLINK;
587 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
589 CallOpc = (isDirect || Subtarget->hasV5TOps())
590 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
591 : ARMISD::CALL_NOLINK;
593 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
594 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
595 Chain = DAG.getCopyToReg(Chain, ARM::LR,
596 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
597 InFlag = Chain.getValue(1);
600 std::vector<SDValue> Ops;
601 Ops.push_back(Chain);
602 Ops.push_back(Callee);
604 // Add argument registers to the end of the list so that they are known live
606 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
607 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
608 RegsToPass[i].second.getValueType()));
610 if (InFlag.getNode())
611 Ops.push_back(InFlag);
612 // Returns a chain and a flag for retval copy to use.
613 Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
614 &Ops[0], Ops.size());
615 InFlag = Chain.getValue(1);
617 Chain = DAG.getCALLSEQ_END(Chain,
618 DAG.getConstant(NumBytes, MVT::i32),
619 DAG.getConstant(0, MVT::i32),
621 if (RetVT != MVT::Other)
622 InFlag = Chain.getValue(1);
624 std::vector<SDValue> ResultVals;
626 // If the call has results, copy the values out of the ret val registers.
627 switch (RetVT.getSimpleVT()) {
628 default: assert(0 && "Unexpected ret value!");
632 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
633 ResultVals.push_back(Chain.getValue(0));
634 if (Op.getNode()->getValueType(1) == MVT::i32) {
635 // Returns a i64 value.
636 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
637 Chain.getValue(2)).getValue(1);
638 ResultVals.push_back(Chain.getValue(0));
642 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
643 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
647 SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
648 SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
649 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
654 if (ResultVals.empty())
657 ResultVals.push_back(Chain);
658 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
659 return Res.getValue(Op.getResNo());
662 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
664 SDValue Chain = Op.getOperand(0);
665 switch(Op.getNumOperands()) {
667 assert(0 && "Do not know how to return this many arguments!");
670 SDValue LR = DAG.getRegister(ARM::LR, MVT::i32);
671 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
674 Op = Op.getOperand(1);
675 if (Op.getValueType() == MVT::f32) {
676 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
677 } else if (Op.getValueType() == MVT::f64) {
678 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
680 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
681 SDValue Sign = DAG.getConstant(0, MVT::i32);
682 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
683 Op.getValue(1), Sign);
685 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue());
686 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
687 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
690 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue());
691 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
692 // If we haven't noted the R0+R1 are live out, do so now.
693 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
694 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
698 case 9: // i128 -> 4 regs
699 Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue());
700 Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
701 Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
702 Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
703 // If we haven't noted the R0+R1 are live out, do so now.
704 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
705 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
706 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
707 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2);
708 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3);
714 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
715 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
718 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
719 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
720 // one of the above mentioned nodes. It has to be wrapped because otherwise
721 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
722 // be used to form addressing mode. These wrapped nodes will be selected
724 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
725 MVT PtrVT = Op.getValueType();
726 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
728 if (CP->isMachineConstantPoolEntry())
729 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
732 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
734 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
737 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
739 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
741 MVT PtrVT = getPointerTy();
742 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
743 ARMConstantPoolValue *CPV =
744 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
745 PCAdj, "tlsgd", true);
746 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
747 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
748 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
749 SDValue Chain = Argument.getValue(1);
751 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
752 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
754 // call __tls_get_addr.
757 Entry.Node = Argument;
758 Entry.Ty = (const Type *) Type::Int32Ty;
759 Args.push_back(Entry);
760 std::pair<SDValue, SDValue> CallResult =
761 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
762 CallingConv::C, false,
763 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
764 return CallResult.first;
767 // Lower ISD::GlobalTLSAddress using the "initial exec" or
768 // "local exec" model.
770 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
772 GlobalValue *GV = GA->getGlobal();
774 SDValue Chain = DAG.getEntryNode();
775 MVT PtrVT = getPointerTy();
776 // Get the Thread Pointer
777 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
779 if (GV->isDeclaration()){
780 // initial exec model
781 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
782 ARMConstantPoolValue *CPV =
783 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
784 PCAdj, "gottpoff", true);
785 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
786 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
787 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
788 Chain = Offset.getValue(1);
790 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
791 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
793 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
796 ARMConstantPoolValue *CPV =
797 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
798 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
799 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
800 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
803 // The address of the thread local variable is the add of the thread
804 // pointer with the offset of the variable.
805 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
809 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
810 // TODO: implement the "local dynamic" model
811 assert(Subtarget->isTargetELF() &&
812 "TLS not implemented for non-ELF targets");
813 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
814 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
815 // otherwise use the "Local Exec" TLS Model
816 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
817 return LowerToTLSGeneralDynamicModel(GA, DAG);
819 return LowerToTLSExecModels(GA, DAG);
822 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
824 MVT PtrVT = getPointerTy();
825 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
826 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
827 if (RelocM == Reloc::PIC_) {
828 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
829 ARMConstantPoolValue *CPV =
830 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
831 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
832 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
833 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
834 SDValue Chain = Result.getValue(1);
835 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
836 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
838 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
841 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
842 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
843 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
847 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
848 /// even in non-static mode.
849 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
850 return RelocM != Reloc::Static &&
851 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
852 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
855 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
857 MVT PtrVT = getPointerTy();
858 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
859 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
860 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
862 if (RelocM == Reloc::Static)
863 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
865 unsigned PCAdj = (RelocM != Reloc::PIC_)
866 ? 0 : (Subtarget->isThumb() ? 4 : 8);
867 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
869 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
871 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
873 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
875 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
876 SDValue Chain = Result.getValue(1);
878 if (RelocM == Reloc::PIC_) {
879 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
880 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
883 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
888 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
890 assert(Subtarget->isTargetELF() &&
891 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
892 MVT PtrVT = getPointerTy();
893 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
894 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
896 ARMCP::CPValue, PCAdj);
897 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
898 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
899 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
900 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
901 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
904 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
905 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
906 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
908 default: return SDValue(); // Don't custom lower most intrinsics.
909 case Intrinsic::arm_thread_pointer:
910 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
914 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
915 unsigned VarArgsFrameIndex) {
916 // vastart just stores the address of the VarArgsFrameIndex slot into the
917 // memory location argument.
918 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
919 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
920 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
921 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
924 static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG,
925 unsigned ArgNo, unsigned &NumGPRs,
926 unsigned &ArgOffset) {
927 MachineFunction &MF = DAG.getMachineFunction();
928 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
929 SDValue Root = Op.getOperand(0);
930 std::vector<SDValue> ArgValues;
931 MachineRegisterInfo &RegInfo = MF.getRegInfo();
933 static const unsigned GPRArgRegs[] = {
934 ARM::R0, ARM::R1, ARM::R2, ARM::R3
941 ISD::ArgFlagsTy Flags =
942 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags();
943 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
944 ObjSize, GPRPad, StackPad, Flags);
946 ArgOffset += StackPad;
950 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
951 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
952 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
953 if (ObjectVT == MVT::f32)
954 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
955 } else if (ObjGPRs == 2) {
956 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
957 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
958 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
960 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
961 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
962 SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
964 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
965 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
970 MachineFrameInfo *MFI = MF.getFrameInfo();
971 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
972 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
974 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
976 SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
977 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
978 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
981 ArgOffset += ObjSize; // Move on to the next argument.
988 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
989 std::vector<SDValue> ArgValues;
990 SDValue Root = Op.getOperand(0);
991 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
992 unsigned NumGPRs = 0; // GPRs used for parameter passing.
994 unsigned NumArgs = Op.getNode()->getNumValues()-1;
995 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
996 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
997 NumGPRs, ArgOffset));
999 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1001 static const unsigned GPRArgRegs[] = {
1002 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1005 MachineFunction &MF = DAG.getMachineFunction();
1006 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1007 MachineFrameInfo *MFI = MF.getFrameInfo();
1008 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1009 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1010 unsigned VARegSize = (4 - NumGPRs) * 4;
1011 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1012 if (VARegSaveSize) {
1013 // If this function is vararg, store any remaining integer argument regs
1014 // to their spots on the stack so that they may be loaded by deferencing
1015 // the result of va_next.
1016 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1017 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1018 VARegSaveSize - VARegSize);
1019 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1021 SmallVector<SDValue, 4> MemOps;
1022 for (; NumGPRs < 4; ++NumGPRs) {
1023 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1024 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1025 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1026 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1027 MemOps.push_back(Store);
1028 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1029 DAG.getConstant(4, getPointerTy()));
1031 if (!MemOps.empty())
1032 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1033 &MemOps[0], MemOps.size());
1035 // This will point to the next argument passed via stack.
1036 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1039 ArgValues.push_back(Root);
1041 // Return the new list of results.
1042 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1046 /// isFloatingPointZero - Return true if this is +0.0.
1047 static bool isFloatingPointZero(SDValue Op) {
1048 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1049 return CFP->getValueAPF().isPosZero();
1050 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1051 // Maybe this has already been legalized into the constant pool?
1052 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1053 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1054 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1055 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1056 return CFP->getValueAPF().isPosZero();
1062 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1063 return ( isThumb && (C & ~255U) == 0) ||
1064 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1067 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1068 /// the given operands.
1069 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1070 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
1071 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1072 unsigned C = RHSC->getValue();
1073 if (!isLegalCmpImmediate(C, isThumb)) {
1074 // Constant does not fit, try adjusting it by one?
1079 if (isLegalCmpImmediate(C-1, isThumb)) {
1080 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1081 RHS = DAG.getConstant(C-1, MVT::i32);
1086 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1087 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1088 RHS = DAG.getConstant(C-1, MVT::i32);
1093 if (isLegalCmpImmediate(C+1, isThumb)) {
1094 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1095 RHS = DAG.getConstant(C+1, MVT::i32);
1100 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1101 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1102 RHS = DAG.getConstant(C+1, MVT::i32);
1109 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1110 ARMISD::NodeType CompareType;
1113 CompareType = ARMISD::CMP;
1119 // Uses only N and Z Flags
1120 CompareType = ARMISD::CMPNZ;
1123 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1124 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1127 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1128 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) {
1130 if (!isFloatingPointZero(RHS))
1131 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1133 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1134 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1137 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1138 const ARMSubtarget *ST) {
1139 MVT VT = Op.getValueType();
1140 SDValue LHS = Op.getOperand(0);
1141 SDValue RHS = Op.getOperand(1);
1142 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1143 SDValue TrueVal = Op.getOperand(2);
1144 SDValue FalseVal = Op.getOperand(3);
1146 if (LHS.getValueType() == MVT::i32) {
1148 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1149 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1150 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1153 ARMCC::CondCodes CondCode, CondCode2;
1154 if (FPCCToARMCC(CC, CondCode, CondCode2))
1155 std::swap(TrueVal, FalseVal);
1157 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1158 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1159 SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
1160 SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1162 if (CondCode2 != ARMCC::AL) {
1163 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1164 // FIXME: Needs another CMP because flag can have but one use.
1165 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG);
1166 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1171 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1172 const ARMSubtarget *ST) {
1173 SDValue Chain = Op.getOperand(0);
1174 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1175 SDValue LHS = Op.getOperand(2);
1176 SDValue RHS = Op.getOperand(3);
1177 SDValue Dest = Op.getOperand(4);
1179 if (LHS.getValueType() == MVT::i32) {
1181 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1182 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1183 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1186 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1187 ARMCC::CondCodes CondCode, CondCode2;
1188 if (FPCCToARMCC(CC, CondCode, CondCode2))
1189 // Swap the LHS/RHS of the comparison if needed.
1190 std::swap(LHS, RHS);
1192 SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
1193 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1194 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1195 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1196 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1197 SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1198 if (CondCode2 != ARMCC::AL) {
1199 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1200 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1201 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1206 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1207 SDValue Chain = Op.getOperand(0);
1208 SDValue Table = Op.getOperand(1);
1209 SDValue Index = Op.getOperand(2);
1211 MVT PTy = getPointerTy();
1212 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1213 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1214 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1215 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1216 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1217 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1218 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1219 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1220 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
1221 Chain, Addr, NULL, 0);
1222 Chain = Addr.getValue(1);
1224 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1225 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1228 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1230 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1231 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1232 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1235 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1236 MVT VT = Op.getValueType();
1238 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1240 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1241 return DAG.getNode(Opc, VT, Op);
1244 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1245 // Implement fcopysign with a fabs and a conditional fneg.
1246 SDValue Tmp0 = Op.getOperand(0);
1247 SDValue Tmp1 = Op.getOperand(1);
1248 MVT VT = Op.getValueType();
1249 MVT SrcVT = Tmp1.getValueType();
1250 SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1251 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1252 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1253 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1254 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1258 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1260 SDValue Dst, SDValue Src,
1261 SDValue Size, unsigned Align,
1263 const Value *DstSV, uint64_t DstSVOff,
1264 const Value *SrcSV, uint64_t SrcSVOff){
1265 // Do repeated 4-byte loads and stores. To be improved.
1266 // This requires 4-byte alignment.
1267 if ((Align & 3) != 0)
1269 // This requires the copy size to be a constant, preferrably
1270 // within a subtarget-specific limit.
1271 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1274 uint64_t SizeVal = ConstantSize->getValue();
1275 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1278 unsigned BytesLeft = SizeVal & 3;
1279 unsigned NumMemOps = SizeVal >> 2;
1280 unsigned EmittedNumMemOps = 0;
1282 unsigned VTSize = 4;
1284 const unsigned MAX_LOADS_IN_LDM = 6;
1285 SDValue TFOps[MAX_LOADS_IN_LDM];
1286 SDValue Loads[MAX_LOADS_IN_LDM];
1287 uint64_t SrcOff = 0, DstOff = 0;
1289 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1290 // same number of stores. The loads and stores will get combined into
1291 // ldm/stm later on.
1292 while (EmittedNumMemOps < NumMemOps) {
1294 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1295 Loads[i] = DAG.getLoad(VT, Chain,
1296 DAG.getNode(ISD::ADD, MVT::i32, Src,
1297 DAG.getConstant(SrcOff, MVT::i32)),
1298 SrcSV, SrcSVOff + SrcOff);
1299 TFOps[i] = Loads[i].getValue(1);
1302 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1305 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1306 TFOps[i] = DAG.getStore(Chain, Loads[i],
1307 DAG.getNode(ISD::ADD, MVT::i32, Dst,
1308 DAG.getConstant(DstOff, MVT::i32)),
1309 DstSV, DstSVOff + DstOff);
1312 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1314 EmittedNumMemOps += i;
1320 // Issue loads / stores for the trailing (1 - 3) bytes.
1321 unsigned BytesLeftSave = BytesLeft;
1324 if (BytesLeft >= 2) {
1332 Loads[i] = DAG.getLoad(VT, Chain,
1333 DAG.getNode(ISD::ADD, MVT::i32, Src,
1334 DAG.getConstant(SrcOff, MVT::i32)),
1335 SrcSV, SrcSVOff + SrcOff);
1336 TFOps[i] = Loads[i].getValue(1);
1339 BytesLeft -= VTSize;
1341 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1344 BytesLeft = BytesLeftSave;
1346 if (BytesLeft >= 2) {
1354 TFOps[i] = DAG.getStore(Chain, Loads[i],
1355 DAG.getNode(ISD::ADD, MVT::i32, Dst,
1356 DAG.getConstant(DstOff, MVT::i32)),
1357 DstSV, DstSVOff + DstOff);
1360 BytesLeft -= VTSize;
1362 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1365 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1366 // Turn f64->i64 into FMRRD.
1367 assert(N->getValueType(0) == MVT::i64 &&
1368 N->getOperand(0).getValueType() == MVT::f64);
1370 SDValue Op = N->getOperand(0);
1371 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1374 // Merge the pieces into a single i64 value.
1375 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode();
1378 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1379 assert(N->getValueType(0) == MVT::i64 &&
1380 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1381 "Unknown shift to lower!");
1383 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1384 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1385 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
1388 // If we are in thumb mode, we don't have RRX.
1389 if (ST->isThumb()) return 0;
1391 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1392 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1393 DAG.getConstant(0, MVT::i32));
1394 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1395 DAG.getConstant(1, MVT::i32));
1397 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1398 // captures the result into a carry flag.
1399 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1400 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1402 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1403 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1405 // Merge the pieces into a single i64 value.
1406 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
1410 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1411 switch (Op.getOpcode()) {
1412 default: assert(0 && "Don't know how to custom lower this!"); abort();
1413 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1414 case ISD::GlobalAddress:
1415 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1416 LowerGlobalAddressELF(Op, DAG);
1417 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1418 case ISD::CALL: return LowerCALL(Op, DAG);
1419 case ISD::RET: return LowerRET(Op, DAG);
1420 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1421 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1422 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1423 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1424 case ISD::SINT_TO_FP:
1425 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1426 case ISD::FP_TO_SINT:
1427 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1428 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1429 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1430 case ISD::RETURNADDR: break;
1431 case ISD::FRAMEADDR: break;
1432 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1433 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1436 // FIXME: Remove these when LegalizeDAGTypes lands.
1437 case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
1439 case ISD::SRA: return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0);
1445 /// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal
1447 SDNode *ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
1448 switch (N->getOpcode()) {
1449 default: assert(0 && "Don't know how to custom expand this!"); abort();
1450 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
1452 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
1457 //===----------------------------------------------------------------------===//
1458 // ARM Scheduler Hooks
1459 //===----------------------------------------------------------------------===//
1462 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1463 MachineBasicBlock *BB) {
1464 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1465 switch (MI->getOpcode()) {
1466 default: assert(false && "Unexpected instr type to insert");
1467 case ARM::tMOVCCr: {
1468 // To "insert" a SELECT_CC instruction, we actually have to insert the
1469 // diamond control-flow pattern. The incoming instruction knows the
1470 // destination vreg to set, the condition code register to branch on, the
1471 // true/false values to select between, and a branch opcode to use.
1472 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1473 MachineFunction::iterator It = BB;
1479 // cmpTY ccX, r1, r2
1481 // fallthrough --> copy0MBB
1482 MachineBasicBlock *thisMBB = BB;
1483 MachineFunction *F = BB->getParent();
1484 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1485 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1486 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1487 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1488 F->insert(It, copy0MBB);
1489 F->insert(It, sinkMBB);
1490 // Update machine-CFG edges by first adding all successors of the current
1491 // block to the new block which will contain the Phi node for the select.
1492 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1493 e = BB->succ_end(); i != e; ++i)
1494 sinkMBB->addSuccessor(*i);
1495 // Next, remove all successors of the current block, and add the true
1496 // and fallthrough blocks as its successors.
1497 while(!BB->succ_empty())
1498 BB->removeSuccessor(BB->succ_begin());
1499 BB->addSuccessor(copy0MBB);
1500 BB->addSuccessor(sinkMBB);
1503 // %FalseValue = ...
1504 // # fallthrough to sinkMBB
1507 // Update machine-CFG edges
1508 BB->addSuccessor(sinkMBB);
1511 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1514 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1515 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1516 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1518 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1524 //===----------------------------------------------------------------------===//
1525 // ARM Optimization Hooks
1526 //===----------------------------------------------------------------------===//
1528 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1529 static SDValue PerformFMRRDCombine(SDNode *N,
1530 TargetLowering::DAGCombinerInfo &DCI) {
1531 // fmrrd(fmdrr x, y) -> x,y
1532 SDValue InDouble = N->getOperand(0);
1533 if (InDouble.getOpcode() == ARMISD::FMDRR)
1534 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1538 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1539 DAGCombinerInfo &DCI) const {
1540 switch (N->getOpcode()) {
1542 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1549 /// isLegalAddressImmediate - Return true if the integer value can be used
1550 /// as the offset of the target addressing mode for load / store of the
1552 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1553 const ARMSubtarget *Subtarget) {
1557 if (Subtarget->isThumb()) {
1562 switch (VT.getSimpleVT()) {
1563 default: return false;
1578 if ((V & (Scale - 1)) != 0)
1581 return V == (V & ((1LL << 5) - 1));
1586 switch (VT.getSimpleVT()) {
1587 default: return false;
1592 return V == (V & ((1LL << 12) - 1));
1595 return V == (V & ((1LL << 8) - 1));
1598 if (!Subtarget->hasVFP2())
1603 return V == (V & ((1LL << 8) - 1));
1607 /// isLegalAddressingMode - Return true if the addressing mode represented
1608 /// by AM is legal for this target, for a load/store of the specified type.
1609 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1610 const Type *Ty) const {
1611 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget))
1614 // Can never fold addr of global into load/store.
1619 case 0: // no scale reg, must be "r+i" or "r", or "i".
1622 if (Subtarget->isThumb())
1626 // ARM doesn't support any R+R*scale+imm addr modes.
1630 int Scale = AM.Scale;
1631 switch (getValueType(Ty).getSimpleVT()) {
1632 default: return false;
1637 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1638 // ldrd / strd are used, then its address mode is same as i16.
1640 if (Scale < 0) Scale = -Scale;
1644 return isPowerOf2_32(Scale & ~1);
1647 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1652 // Note, we allow "void" uses (basically, uses that aren't loads or
1653 // stores), because arm allows folding a scale into many arithmetic
1654 // operations. This should be made more precise and revisited later.
1656 // Allow r << imm, but the imm has to be a multiple of two.
1657 if (AM.Scale & 1) return false;
1658 return isPowerOf2_32(AM.Scale);
1666 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1667 bool isSEXTLoad, SDValue &Base,
1668 SDValue &Offset, bool &isInc,
1669 SelectionDAG &DAG) {
1670 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1673 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1675 Base = Ptr->getOperand(0);
1676 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1677 int RHSC = (int)RHS->getValue();
1678 if (RHSC < 0 && RHSC > -256) {
1680 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1684 isInc = (Ptr->getOpcode() == ISD::ADD);
1685 Offset = Ptr->getOperand(1);
1687 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1689 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1690 int RHSC = (int)RHS->getValue();
1691 if (RHSC < 0 && RHSC > -0x1000) {
1693 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1694 Base = Ptr->getOperand(0);
1699 if (Ptr->getOpcode() == ISD::ADD) {
1701 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1702 if (ShOpcVal != ARM_AM::no_shift) {
1703 Base = Ptr->getOperand(1);
1704 Offset = Ptr->getOperand(0);
1706 Base = Ptr->getOperand(0);
1707 Offset = Ptr->getOperand(1);
1712 isInc = (Ptr->getOpcode() == ISD::ADD);
1713 Base = Ptr->getOperand(0);
1714 Offset = Ptr->getOperand(1);
1718 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1722 /// getPreIndexedAddressParts - returns true by value, base pointer and
1723 /// offset pointer and addressing mode by reference if the node's address
1724 /// can be legally represented as pre-indexed load / store address.
1726 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1728 ISD::MemIndexedMode &AM,
1729 SelectionDAG &DAG) {
1730 if (Subtarget->isThumb())
1735 bool isSEXTLoad = false;
1736 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1737 Ptr = LD->getBasePtr();
1738 VT = LD->getMemoryVT();
1739 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1740 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1741 Ptr = ST->getBasePtr();
1742 VT = ST->getMemoryVT();
1747 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
1750 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1756 /// getPostIndexedAddressParts - returns true by value, base pointer and
1757 /// offset pointer and addressing mode by reference if this node can be
1758 /// combined with a load / store to form a post-indexed load / store.
1759 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1762 ISD::MemIndexedMode &AM,
1763 SelectionDAG &DAG) {
1764 if (Subtarget->isThumb())
1769 bool isSEXTLoad = false;
1770 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1771 VT = LD->getMemoryVT();
1772 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1773 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1774 VT = ST->getMemoryVT();
1779 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1782 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1788 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1792 const SelectionDAG &DAG,
1793 unsigned Depth) const {
1794 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1795 switch (Op.getOpcode()) {
1797 case ARMISD::CMOV: {
1798 // Bits are known zero/one if known on the LHS and RHS.
1799 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1800 if (KnownZero == 0 && KnownOne == 0) return;
1802 APInt KnownZeroRHS, KnownOneRHS;
1803 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1804 KnownZeroRHS, KnownOneRHS, Depth+1);
1805 KnownZero &= KnownZeroRHS;
1806 KnownOne &= KnownOneRHS;
1812 //===----------------------------------------------------------------------===//
1813 // ARM Inline Assembly Support
1814 //===----------------------------------------------------------------------===//
1816 /// getConstraintType - Given a constraint letter, return the type of
1817 /// constraint it is for this target.
1818 ARMTargetLowering::ConstraintType
1819 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1820 if (Constraint.size() == 1) {
1821 switch (Constraint[0]) {
1823 case 'l': return C_RegisterClass;
1824 case 'w': return C_RegisterClass;
1827 return TargetLowering::getConstraintType(Constraint);
1830 std::pair<unsigned, const TargetRegisterClass*>
1831 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1833 if (Constraint.size() == 1) {
1834 // GCC RS6000 Constraint Letters
1835 switch (Constraint[0]) {
1837 // FIXME: in thumb mode, 'l' is only low-regs.
1840 return std::make_pair(0U, ARM::GPRRegisterClass);
1843 return std::make_pair(0U, ARM::SPRRegisterClass);
1845 return std::make_pair(0U, ARM::DPRRegisterClass);
1849 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1852 std::vector<unsigned> ARMTargetLowering::
1853 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1855 if (Constraint.size() != 1)
1856 return std::vector<unsigned>();
1858 switch (Constraint[0]) { // GCC ARM Constraint Letters
1862 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1863 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1864 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1865 ARM::R12, ARM::LR, 0);
1868 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1869 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1870 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1871 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1872 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1873 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1874 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1875 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1877 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1878 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1879 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1880 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1884 return std::vector<unsigned>();