1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
72 cl::desc("Enable code placement pass for ARM"),
75 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
76 CCValAssign::LocInfo &LocInfo,
77 ISD::ArgFlagsTy &ArgFlags,
79 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
80 CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags,
83 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags,
87 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
88 CCValAssign::LocInfo &LocInfo,
89 ISD::ArgFlagsTy &ArgFlags,
92 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
93 EVT PromotedBitwiseVT) {
94 if (VT != PromotedLdStVT) {
95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
104 EVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
109 if (ElemTy != MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
121 if (VT.isInteger()) {
122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 // Promote all bit-wise operations.
128 if (VT.isInteger() && VT != PromotedBitwiseVT) {
129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
133 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
134 PromotedBitwiseVT.getSimpleVT());
135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
137 PromotedBitwiseVT.getSimpleVT());
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
149 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::DPRRegisterClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::QPRRegisterClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
161 return new TargetLoweringObjectFileMachO();
163 return new ARMElfTargetObjectFile();
166 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
167 : TargetLowering(TM, createTLOF(TM)) {
168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 if (Subtarget->isTargetDarwin()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
173 // Single-precision floating-point arithmetic.
174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179 // Double-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185 // Single-precision comparisons.
186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
204 // Double-precision comparisons.
205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
223 // Floating-point to integer conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231 // Conversions between floating types.
232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
235 // Integer to floating-point conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
239 // e.g., __floatunsidf vs. __floatunssidfvfp.
240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, 0);
249 setLibcallName(RTLIB::SRL_I128, 0);
250 setLibcallName(RTLIB::SRA_I128, 0);
252 // Libcalls should use the AAPCS base standard ABI, even if hard float
253 // is in effect, as per the ARM RTABI specification, section 4.1.2.
254 if (Subtarget->isAAPCS_ABI()) {
255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
257 CallingConv::ARM_AAPCS);
261 if (Subtarget->isThumb1Only())
262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
269 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
272 if (Subtarget->hasNEON()) {
273 addDRTypeForNEON(MVT::v2f32);
274 addDRTypeForNEON(MVT::v8i8);
275 addDRTypeForNEON(MVT::v4i16);
276 addDRTypeForNEON(MVT::v2i32);
277 addDRTypeForNEON(MVT::v1i64);
279 addQRTypeForNEON(MVT::v4f32);
280 addQRTypeForNEON(MVT::v2f64);
281 addQRTypeForNEON(MVT::v16i8);
282 addQRTypeForNEON(MVT::v8i16);
283 addQRTypeForNEON(MVT::v4i32);
284 addQRTypeForNEON(MVT::v2i64);
286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
287 // neither Neon nor VFP support any arithmetic operations on it.
288 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
292 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
313 // Neon does not support some operations on v1i64 and v2i64 types.
314 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
315 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
320 setTargetDAGCombine(ISD::SHL);
321 setTargetDAGCombine(ISD::SRL);
322 setTargetDAGCombine(ISD::SRA);
323 setTargetDAGCombine(ISD::SIGN_EXTEND);
324 setTargetDAGCombine(ISD::ZERO_EXTEND);
325 setTargetDAGCombine(ISD::ANY_EXTEND);
326 setTargetDAGCombine(ISD::SELECT_CC);
329 computeRegisterProperties();
331 // ARM does not have f32 extending load.
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
334 // ARM does not have i1 sign extending load.
335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
337 // ARM supports all 4 flavors of integer indexed load / store.
338 if (!Subtarget->isThumb1Only()) {
339 for (unsigned im = (unsigned)ISD::PRE_INC;
340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
341 setIndexedLoadAction(im, MVT::i1, Legal);
342 setIndexedLoadAction(im, MVT::i8, Legal);
343 setIndexedLoadAction(im, MVT::i16, Legal);
344 setIndexedLoadAction(im, MVT::i32, Legal);
345 setIndexedStoreAction(im, MVT::i1, Legal);
346 setIndexedStoreAction(im, MVT::i8, Legal);
347 setIndexedStoreAction(im, MVT::i16, Legal);
348 setIndexedStoreAction(im, MVT::i32, Legal);
352 // i64 operation support.
353 if (Subtarget->isThumb1Only()) {
354 setOperationAction(ISD::MUL, MVT::i64, Expand);
355 setOperationAction(ISD::MULHU, MVT::i32, Expand);
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
360 setOperationAction(ISD::MUL, MVT::i64, Expand);
361 setOperationAction(ISD::MULHU, MVT::i32, Expand);
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::MULHS, MVT::i32, Expand);
365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
368 setOperationAction(ISD::SRL, MVT::i64, Custom);
369 setOperationAction(ISD::SRA, MVT::i64, Custom);
371 // ARM does not have ROTL.
372 setOperationAction(ISD::ROTL, MVT::i32, Expand);
373 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
374 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
376 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 // Only ARMv6 has BSWAP.
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
382 // These are expanded into libcalls.
383 if (!Subtarget->hasDivide()) {
384 // v7M has a hardware divider
385 setOperationAction(ISD::SDIV, MVT::i32, Expand);
386 setOperationAction(ISD::UDIV, MVT::i32, Expand);
388 setOperationAction(ISD::SREM, MVT::i32, Expand);
389 setOperationAction(ISD::UREM, MVT::i32, Expand);
390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // Use the default implementation.
402 setOperationAction(ISD::VASTART, MVT::Other, Custom);
403 setOperationAction(ISD::VAARG, MVT::Other, Expand);
404 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
405 setOperationAction(ISD::VAEND, MVT::Other, Expand);
406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
409 // FIXME: Shouldn't need this, since no register is used, but the legalizer
410 // doesn't yet know how to not do that for SjLj.
411 setExceptionSelectorRegister(ARM::R0);
412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
414 // use the default expansion.
415 bool canHandleAtomics =
416 (Subtarget->hasV7Ops() ||
417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
418 if (canHandleAtomics) {
419 // membarrier needs custom lowering; the rest are legal and handled
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
423 // Set them all for expansion, which will force libcalls.
424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
449 // Since the libcalls include locking, fold in the fences
450 setShouldFoldAtomicFences(true);
452 // 64-bit versions are always libcalls (for now)
453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
463 if (!Subtarget->hasV6Ops()) {
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
471 // iff target supports vfp2.
472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
474 // We want to custom lower some of our intrinsics.
475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
476 if (Subtarget->isTargetDarwin()) {
477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
481 setOperationAction(ISD::SETCC, MVT::i32, Expand);
482 setOperationAction(ISD::SETCC, MVT::f32, Expand);
483 setOperationAction(ISD::SETCC, MVT::f64, Expand);
484 setOperationAction(ISD::SELECT, MVT::i32, Expand);
485 setOperationAction(ISD::SELECT, MVT::f32, Expand);
486 setOperationAction(ISD::SELECT, MVT::f64, Expand);
487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
491 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
492 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
493 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
494 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
495 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
497 // We don't support sin/cos/fmod/copysign/pow
498 setOperationAction(ISD::FSIN, MVT::f64, Expand);
499 setOperationAction(ISD::FSIN, MVT::f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::f64, Expand);
502 setOperationAction(ISD::FREM, MVT::f64, Expand);
503 setOperationAction(ISD::FREM, MVT::f32, Expand);
504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
508 setOperationAction(ISD::FPOW, MVT::f64, Expand);
509 setOperationAction(ISD::FPOW, MVT::f32, Expand);
511 // Various VFP goodness
512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
513 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
514 if (Subtarget->hasVFP2()) {
515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
520 // Special handling for half-precision FP.
521 if (!Subtarget->hasFP16()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
527 // We have target-specific dag combine patterns for the following nodes:
528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
529 setTargetDAGCombine(ISD::ADD);
530 setTargetDAGCombine(ISD::SUB);
531 setTargetDAGCombine(ISD::MUL);
533 setStackPointerRegisterToSaveRestore(ARM::SP);
535 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
536 setSchedulingPreference(Sched::RegPressure);
538 setSchedulingPreference(Sched::Hybrid);
540 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
542 // On ARM arguments smaller than 4 bytes are extended, so all arguments
543 // are at least 4 bytes aligned.
544 setMinStackArgumentAlignment(4);
546 if (EnableARMCodePlacement)
547 benefitFromCodePlacementOpt = true;
550 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
553 case ARMISD::Wrapper: return "ARMISD::Wrapper";
554 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
555 case ARMISD::CALL: return "ARMISD::CALL";
556 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
557 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
558 case ARMISD::tCALL: return "ARMISD::tCALL";
559 case ARMISD::BRCOND: return "ARMISD::BRCOND";
560 case ARMISD::BR_JT: return "ARMISD::BR_JT";
561 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
562 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
563 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
564 case ARMISD::CMP: return "ARMISD::CMP";
565 case ARMISD::CMPZ: return "ARMISD::CMPZ";
566 case ARMISD::CMPFP: return "ARMISD::CMPFP";
567 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
568 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
569 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
570 case ARMISD::CMOV: return "ARMISD::CMOV";
571 case ARMISD::CNEG: return "ARMISD::CNEG";
573 case ARMISD::RBIT: return "ARMISD::RBIT";
575 case ARMISD::FTOSI: return "ARMISD::FTOSI";
576 case ARMISD::FTOUI: return "ARMISD::FTOUI";
577 case ARMISD::SITOF: return "ARMISD::SITOF";
578 case ARMISD::UITOF: return "ARMISD::UITOF";
580 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
581 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
582 case ARMISD::RRX: return "ARMISD::RRX";
584 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
585 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
587 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
588 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
590 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
592 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
594 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
596 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
597 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
599 case ARMISD::VCEQ: return "ARMISD::VCEQ";
600 case ARMISD::VCGE: return "ARMISD::VCGE";
601 case ARMISD::VCGEU: return "ARMISD::VCGEU";
602 case ARMISD::VCGT: return "ARMISD::VCGT";
603 case ARMISD::VCGTU: return "ARMISD::VCGTU";
604 case ARMISD::VTST: return "ARMISD::VTST";
606 case ARMISD::VSHL: return "ARMISD::VSHL";
607 case ARMISD::VSHRs: return "ARMISD::VSHRs";
608 case ARMISD::VSHRu: return "ARMISD::VSHRu";
609 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
610 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
611 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
612 case ARMISD::VSHRN: return "ARMISD::VSHRN";
613 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
614 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
615 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
616 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
617 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
618 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
619 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
620 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
621 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
622 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
623 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
624 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
625 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
626 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
627 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
628 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
629 case ARMISD::VDUP: return "ARMISD::VDUP";
630 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
631 case ARMISD::VEXT: return "ARMISD::VEXT";
632 case ARMISD::VREV64: return "ARMISD::VREV64";
633 case ARMISD::VREV32: return "ARMISD::VREV32";
634 case ARMISD::VREV16: return "ARMISD::VREV16";
635 case ARMISD::VZIP: return "ARMISD::VZIP";
636 case ARMISD::VUZP: return "ARMISD::VUZP";
637 case ARMISD::VTRN: return "ARMISD::VTRN";
638 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
639 case ARMISD::FMAX: return "ARMISD::FMAX";
640 case ARMISD::FMIN: return "ARMISD::FMIN";
644 /// getRegClassFor - Return the register class that should be used for the
645 /// specified value type.
646 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
647 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
648 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
649 // load / store 4 to 8 consecutive D registers.
650 if (Subtarget->hasNEON()) {
651 if (VT == MVT::v4i64)
652 return ARM::QQPRRegisterClass;
653 else if (VT == MVT::v8i64)
654 return ARM::QQQQPRRegisterClass;
656 return TargetLowering::getRegClassFor(VT);
659 /// getFunctionAlignment - Return the Log2 alignment of this function.
660 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
661 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
664 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
665 unsigned NumVals = N->getNumValues();
667 return Sched::RegPressure;
669 for (unsigned i = 0; i != NumVals; ++i) {
670 EVT VT = N->getValueType(i);
671 if (VT.isFloatingPoint() || VT.isVector())
672 return Sched::Latency;
675 if (!N->isMachineOpcode())
676 return Sched::RegPressure;
678 // Load are scheduled for latency even if there instruction itinerary
680 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
681 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
683 return Sched::Latency;
685 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
686 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
687 return Sched::Latency;
688 return Sched::RegPressure;
691 //===----------------------------------------------------------------------===//
693 //===----------------------------------------------------------------------===//
695 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
696 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
698 default: llvm_unreachable("Unknown condition code!");
699 case ISD::SETNE: return ARMCC::NE;
700 case ISD::SETEQ: return ARMCC::EQ;
701 case ISD::SETGT: return ARMCC::GT;
702 case ISD::SETGE: return ARMCC::GE;
703 case ISD::SETLT: return ARMCC::LT;
704 case ISD::SETLE: return ARMCC::LE;
705 case ISD::SETUGT: return ARMCC::HI;
706 case ISD::SETUGE: return ARMCC::HS;
707 case ISD::SETULT: return ARMCC::LO;
708 case ISD::SETULE: return ARMCC::LS;
712 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
713 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
714 ARMCC::CondCodes &CondCode2) {
715 CondCode2 = ARMCC::AL;
717 default: llvm_unreachable("Unknown FP condition!");
719 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
721 case ISD::SETOGT: CondCode = ARMCC::GT; break;
723 case ISD::SETOGE: CondCode = ARMCC::GE; break;
724 case ISD::SETOLT: CondCode = ARMCC::MI; break;
725 case ISD::SETOLE: CondCode = ARMCC::LS; break;
726 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
727 case ISD::SETO: CondCode = ARMCC::VC; break;
728 case ISD::SETUO: CondCode = ARMCC::VS; break;
729 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
730 case ISD::SETUGT: CondCode = ARMCC::HI; break;
731 case ISD::SETUGE: CondCode = ARMCC::PL; break;
733 case ISD::SETULT: CondCode = ARMCC::LT; break;
735 case ISD::SETULE: CondCode = ARMCC::LE; break;
737 case ISD::SETUNE: CondCode = ARMCC::NE; break;
741 //===----------------------------------------------------------------------===//
742 // Calling Convention Implementation
743 //===----------------------------------------------------------------------===//
745 #include "ARMGenCallingConv.inc"
747 // APCS f64 is in register pairs, possibly split to stack
748 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
749 CCValAssign::LocInfo &LocInfo,
750 CCState &State, bool CanFail) {
751 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
753 // Try to get the first register.
754 if (unsigned Reg = State.AllocateReg(RegList, 4))
755 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
757 // For the 2nd half of a v2f64, do not fail.
761 // Put the whole thing on the stack.
762 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
763 State.AllocateStack(8, 4),
768 // Try to get the second register.
769 if (unsigned Reg = State.AllocateReg(RegList, 4))
770 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
772 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
773 State.AllocateStack(4, 4),
778 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
779 CCValAssign::LocInfo &LocInfo,
780 ISD::ArgFlagsTy &ArgFlags,
782 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
784 if (LocVT == MVT::v2f64 &&
785 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
787 return true; // we handled it
790 // AAPCS f64 is in aligned register pairs
791 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
792 CCValAssign::LocInfo &LocInfo,
793 CCState &State, bool CanFail) {
794 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
795 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
797 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
799 // For the 2nd half of a v2f64, do not just fail.
803 // Put the whole thing on the stack.
804 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
805 State.AllocateStack(8, 8),
811 for (i = 0; i < 2; ++i)
812 if (HiRegList[i] == Reg)
815 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
816 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
821 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
822 CCValAssign::LocInfo &LocInfo,
823 ISD::ArgFlagsTy &ArgFlags,
825 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
827 if (LocVT == MVT::v2f64 &&
828 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
830 return true; // we handled it
833 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
834 CCValAssign::LocInfo &LocInfo, CCState &State) {
835 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
836 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
838 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
840 return false; // we didn't handle it
843 for (i = 0; i < 2; ++i)
844 if (HiRegList[i] == Reg)
847 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
848 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
853 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
854 CCValAssign::LocInfo &LocInfo,
855 ISD::ArgFlagsTy &ArgFlags,
857 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
859 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
861 return true; // we handled it
864 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
865 CCValAssign::LocInfo &LocInfo,
866 ISD::ArgFlagsTy &ArgFlags,
868 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
872 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
873 /// given CallingConvention value.
874 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
876 bool isVarArg) const {
879 llvm_unreachable("Unsupported calling convention");
881 case CallingConv::Fast:
882 // Use target triple & subtarget features to do actual dispatch.
883 if (Subtarget->isAAPCS_ABI()) {
884 if (Subtarget->hasVFP2() &&
885 FloatABIType == FloatABI::Hard && !isVarArg)
886 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
888 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
890 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
891 case CallingConv::ARM_AAPCS_VFP:
892 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
893 case CallingConv::ARM_AAPCS:
894 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
895 case CallingConv::ARM_APCS:
896 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
900 /// LowerCallResult - Lower the result values of a call into the
901 /// appropriate copies out of appropriate physical registers.
903 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
904 CallingConv::ID CallConv, bool isVarArg,
905 const SmallVectorImpl<ISD::InputArg> &Ins,
906 DebugLoc dl, SelectionDAG &DAG,
907 SmallVectorImpl<SDValue> &InVals) const {
909 // Assign locations to each value returned by this call.
910 SmallVector<CCValAssign, 16> RVLocs;
911 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
912 RVLocs, *DAG.getContext());
913 CCInfo.AnalyzeCallResult(Ins,
914 CCAssignFnForNode(CallConv, /* Return*/ true,
917 // Copy all of the result registers out of their specified physreg.
918 for (unsigned i = 0; i != RVLocs.size(); ++i) {
919 CCValAssign VA = RVLocs[i];
922 if (VA.needsCustom()) {
923 // Handle f64 or half of a v2f64.
924 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
926 Chain = Lo.getValue(1);
927 InFlag = Lo.getValue(2);
928 VA = RVLocs[++i]; // skip ahead to next loc
929 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
931 Chain = Hi.getValue(1);
932 InFlag = Hi.getValue(2);
933 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
935 if (VA.getLocVT() == MVT::v2f64) {
936 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
937 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
938 DAG.getConstant(0, MVT::i32));
940 VA = RVLocs[++i]; // skip ahead to next loc
941 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
942 Chain = Lo.getValue(1);
943 InFlag = Lo.getValue(2);
944 VA = RVLocs[++i]; // skip ahead to next loc
945 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
946 Chain = Hi.getValue(1);
947 InFlag = Hi.getValue(2);
948 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
949 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
950 DAG.getConstant(1, MVT::i32));
953 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
955 Chain = Val.getValue(1);
956 InFlag = Val.getValue(2);
959 switch (VA.getLocInfo()) {
960 default: llvm_unreachable("Unknown loc info!");
961 case CCValAssign::Full: break;
962 case CCValAssign::BCvt:
963 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
967 InVals.push_back(Val);
973 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
974 /// by "Src" to address "Dst" of size "Size". Alignment information is
975 /// specified by the specific parameter attribute. The copy will be passed as
976 /// a byval function parameter.
977 /// Sometimes what we are copying is the end of a larger object, the part that
978 /// does not fit in registers.
980 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
981 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
983 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
984 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
985 /*isVolatile=*/false, /*AlwaysInline=*/false,
989 /// LowerMemOpCallTo - Store the argument to the stack.
991 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
992 SDValue StackPtr, SDValue Arg,
993 DebugLoc dl, SelectionDAG &DAG,
994 const CCValAssign &VA,
995 ISD::ArgFlagsTy Flags) const {
996 unsigned LocMemOffset = VA.getLocMemOffset();
997 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
998 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
999 if (Flags.isByVal()) {
1000 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1002 return DAG.getStore(Chain, dl, Arg, PtrOff,
1003 PseudoSourceValue::getStack(), LocMemOffset,
1007 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1008 SDValue Chain, SDValue &Arg,
1009 RegsToPassVector &RegsToPass,
1010 CCValAssign &VA, CCValAssign &NextVA,
1012 SmallVector<SDValue, 8> &MemOpChains,
1013 ISD::ArgFlagsTy Flags) const {
1015 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1016 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1017 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1019 if (NextVA.isRegLoc())
1020 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1022 assert(NextVA.isMemLoc());
1023 if (StackPtr.getNode() == 0)
1024 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1026 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1032 /// LowerCall - Lowering a call into a callseq_start <-
1033 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1036 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1037 CallingConv::ID CallConv, bool isVarArg,
1039 const SmallVectorImpl<ISD::OutputArg> &Outs,
1040 const SmallVectorImpl<SDValue> &OutVals,
1041 const SmallVectorImpl<ISD::InputArg> &Ins,
1042 DebugLoc dl, SelectionDAG &DAG,
1043 SmallVectorImpl<SDValue> &InVals) const {
1044 MachineFunction &MF = DAG.getMachineFunction();
1045 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1046 bool IsSibCall = false;
1047 // Temporarily disable tail calls so things don't break.
1048 if (!EnableARMTailCalls)
1051 // Check if it's really possible to do a tail call.
1052 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1053 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1054 Outs, OutVals, Ins, DAG);
1055 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1056 // detected sibcalls.
1063 // Analyze operands of the call, assigning locations to each operand.
1064 SmallVector<CCValAssign, 16> ArgLocs;
1065 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1067 CCInfo.AnalyzeCallOperands(Outs,
1068 CCAssignFnForNode(CallConv, /* Return*/ false,
1071 // Get a count of how many bytes are to be pushed on the stack.
1072 unsigned NumBytes = CCInfo.getNextStackOffset();
1074 // For tail calls, memory operands are available in our caller's stack.
1078 // Adjust the stack pointer for the new arguments...
1079 // These operations are automatically eliminated by the prolog/epilog pass
1081 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1083 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1085 RegsToPassVector RegsToPass;
1086 SmallVector<SDValue, 8> MemOpChains;
1088 // Walk the register/memloc assignments, inserting copies/loads. In the case
1089 // of tail call optimization, arguments are handled later.
1090 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1092 ++i, ++realArgIdx) {
1093 CCValAssign &VA = ArgLocs[i];
1094 SDValue Arg = OutVals[realArgIdx];
1095 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1097 // Promote the value if needed.
1098 switch (VA.getLocInfo()) {
1099 default: llvm_unreachable("Unknown loc info!");
1100 case CCValAssign::Full: break;
1101 case CCValAssign::SExt:
1102 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1104 case CCValAssign::ZExt:
1105 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1107 case CCValAssign::AExt:
1108 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1110 case CCValAssign::BCvt:
1111 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1115 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1116 if (VA.needsCustom()) {
1117 if (VA.getLocVT() == MVT::v2f64) {
1118 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1119 DAG.getConstant(0, MVT::i32));
1120 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1121 DAG.getConstant(1, MVT::i32));
1123 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1124 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1126 VA = ArgLocs[++i]; // skip ahead to next loc
1127 if (VA.isRegLoc()) {
1128 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1129 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1131 assert(VA.isMemLoc());
1133 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1134 dl, DAG, VA, Flags));
1137 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1138 StackPtr, MemOpChains, Flags);
1140 } else if (VA.isRegLoc()) {
1141 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1142 } else if (!IsSibCall) {
1143 assert(VA.isMemLoc());
1145 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1146 dl, DAG, VA, Flags));
1150 if (!MemOpChains.empty())
1151 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1152 &MemOpChains[0], MemOpChains.size());
1154 // Build a sequence of copy-to-reg nodes chained together with token chain
1155 // and flag operands which copy the outgoing args into the appropriate regs.
1157 // Tail call byval lowering might overwrite argument registers so in case of
1158 // tail call optimization the copies to registers are lowered later.
1160 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1161 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1162 RegsToPass[i].second, InFlag);
1163 InFlag = Chain.getValue(1);
1166 // For tail calls lower the arguments to the 'real' stack slot.
1168 // Force all the incoming stack arguments to be loaded from the stack
1169 // before any new outgoing arguments are stored to the stack, because the
1170 // outgoing stack slots may alias the incoming argument stack slots, and
1171 // the alias isn't otherwise explicit. This is slightly more conservative
1172 // than necessary, because it means that each store effectively depends
1173 // on every argument instead of just those arguments it would clobber.
1175 // Do not flag preceeding copytoreg stuff together with the following stuff.
1177 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1178 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1179 RegsToPass[i].second, InFlag);
1180 InFlag = Chain.getValue(1);
1185 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1186 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1187 // node so that legalize doesn't hack it.
1188 bool isDirect = false;
1189 bool isARMFunc = false;
1190 bool isLocalARMFunc = false;
1191 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1193 if (EnableARMLongCalls) {
1194 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1195 && "long-calls with non-static relocation model!");
1196 // Handle a global address or an external symbol. If it's not one of
1197 // those, the target's already in a register, so we don't need to do
1199 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1200 const GlobalValue *GV = G->getGlobal();
1201 // Create a constant pool entry for the callee address
1202 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1203 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1206 // Get the address of the callee into a register
1207 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1208 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1209 Callee = DAG.getLoad(getPointerTy(), dl,
1210 DAG.getEntryNode(), CPAddr,
1211 PseudoSourceValue::getConstantPool(), 0,
1213 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1214 const char *Sym = S->getSymbol();
1216 // Create a constant pool entry for the callee address
1217 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1218 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1219 Sym, ARMPCLabelIndex, 0);
1220 // Get the address of the callee into a register
1221 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1222 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1223 Callee = DAG.getLoad(getPointerTy(), dl,
1224 DAG.getEntryNode(), CPAddr,
1225 PseudoSourceValue::getConstantPool(), 0,
1228 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1229 const GlobalValue *GV = G->getGlobal();
1231 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1232 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1233 getTargetMachine().getRelocationModel() != Reloc::Static;
1234 isARMFunc = !Subtarget->isThumb() || isStub;
1235 // ARM call to a local ARM function is predicable.
1236 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1237 // tBX takes a register source operand.
1238 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1239 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1240 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1243 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1244 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1245 Callee = DAG.getLoad(getPointerTy(), dl,
1246 DAG.getEntryNode(), CPAddr,
1247 PseudoSourceValue::getConstantPool(), 0,
1249 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1250 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1251 getPointerTy(), Callee, PICLabel);
1253 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1254 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1256 bool isStub = Subtarget->isTargetDarwin() &&
1257 getTargetMachine().getRelocationModel() != Reloc::Static;
1258 isARMFunc = !Subtarget->isThumb() || isStub;
1259 // tBX takes a register source operand.
1260 const char *Sym = S->getSymbol();
1261 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1262 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1263 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1264 Sym, ARMPCLabelIndex, 4);
1265 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1266 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1267 Callee = DAG.getLoad(getPointerTy(), dl,
1268 DAG.getEntryNode(), CPAddr,
1269 PseudoSourceValue::getConstantPool(), 0,
1271 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1272 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1273 getPointerTy(), Callee, PICLabel);
1275 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1278 // FIXME: handle tail calls differently.
1280 if (Subtarget->isThumb()) {
1281 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1282 CallOpc = ARMISD::CALL_NOLINK;
1284 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1286 CallOpc = (isDirect || Subtarget->hasV5TOps())
1287 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1288 : ARMISD::CALL_NOLINK;
1291 std::vector<SDValue> Ops;
1292 Ops.push_back(Chain);
1293 Ops.push_back(Callee);
1295 // Add argument registers to the end of the list so that they are known live
1297 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1298 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1299 RegsToPass[i].second.getValueType()));
1301 if (InFlag.getNode())
1302 Ops.push_back(InFlag);
1304 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1306 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1308 // Returns a chain and a flag for retval copy to use.
1309 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1310 InFlag = Chain.getValue(1);
1312 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1313 DAG.getIntPtrConstant(0, true), InFlag);
1315 InFlag = Chain.getValue(1);
1317 // Handle result values, copying them out of physregs into vregs that we
1319 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1323 /// MatchingStackOffset - Return true if the given stack call argument is
1324 /// already available in the same position (relatively) of the caller's
1325 /// incoming argument stack.
1327 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1328 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1329 const ARMInstrInfo *TII) {
1330 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1332 if (Arg.getOpcode() == ISD::CopyFromReg) {
1333 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1334 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1336 MachineInstr *Def = MRI->getVRegDef(VR);
1339 if (!Flags.isByVal()) {
1340 if (!TII->isLoadFromStackSlot(Def, FI))
1345 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1346 if (Flags.isByVal())
1347 // ByVal argument is passed in as a pointer but it's now being
1348 // dereferenced. e.g.
1349 // define @foo(%struct.X* %A) {
1350 // tail call @bar(%struct.X* byval %A)
1353 SDValue Ptr = Ld->getBasePtr();
1354 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1357 FI = FINode->getIndex();
1361 assert(FI != INT_MAX);
1362 if (!MFI->isFixedObjectIndex(FI))
1364 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1367 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1368 /// for tail call optimization. Targets which want to do tail call
1369 /// optimization should implement this function.
1371 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1372 CallingConv::ID CalleeCC,
1374 bool isCalleeStructRet,
1375 bool isCallerStructRet,
1376 const SmallVectorImpl<ISD::OutputArg> &Outs,
1377 const SmallVectorImpl<SDValue> &OutVals,
1378 const SmallVectorImpl<ISD::InputArg> &Ins,
1379 SelectionDAG& DAG) const {
1380 const Function *CallerF = DAG.getMachineFunction().getFunction();
1381 CallingConv::ID CallerCC = CallerF->getCallingConv();
1382 bool CCMatch = CallerCC == CalleeCC;
1384 // Look for obvious safe cases to perform tail call optimization that do not
1385 // require ABI changes. This is what gcc calls sibcall.
1387 // Do not sibcall optimize vararg calls unless the call site is not passing
1389 if (isVarArg && !Outs.empty())
1392 // Also avoid sibcall optimization if either caller or callee uses struct
1393 // return semantics.
1394 if (isCalleeStructRet || isCallerStructRet)
1397 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1398 // emitEpilogue is not ready for them.
1399 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1400 // LR. This means if we need to reload LR, it takes an extra instructions,
1401 // which outweighs the value of the tail call; but here we don't know yet
1402 // whether LR is going to be used. Probably the right approach is to
1403 // generate the tail call here and turn it back into CALL/RET in
1404 // emitEpilogue if LR is used.
1405 if (Subtarget->isThumb1Only())
1408 // For the moment, we can only do this to functions defined in this
1409 // compilation, or to indirect calls. A Thumb B to an ARM function,
1410 // or vice versa, is not easily fixed up in the linker unlike BL.
1411 // (We could do this by loading the address of the callee into a register;
1412 // that is an extra instruction over the direct call and burns a register
1413 // as well, so is not likely to be a win.)
1415 // It might be safe to remove this restriction on non-Darwin.
1417 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1418 // but we need to make sure there are enough registers; the only valid
1419 // registers are the 4 used for parameters. We don't currently do this
1421 if (isa<ExternalSymbolSDNode>(Callee))
1424 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1425 const GlobalValue *GV = G->getGlobal();
1426 if (GV->isDeclaration() || GV->isWeakForLinker())
1430 // If the calling conventions do not match, then we'd better make sure the
1431 // results are returned in the same way as what the caller expects.
1433 SmallVector<CCValAssign, 16> RVLocs1;
1434 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1435 RVLocs1, *DAG.getContext());
1436 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1438 SmallVector<CCValAssign, 16> RVLocs2;
1439 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1440 RVLocs2, *DAG.getContext());
1441 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1443 if (RVLocs1.size() != RVLocs2.size())
1445 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1446 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1448 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1450 if (RVLocs1[i].isRegLoc()) {
1451 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1454 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1460 // If the callee takes no arguments then go on to check the results of the
1462 if (!Outs.empty()) {
1463 // Check if stack adjustment is needed. For now, do not do this if any
1464 // argument is passed on the stack.
1465 SmallVector<CCValAssign, 16> ArgLocs;
1466 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1467 ArgLocs, *DAG.getContext());
1468 CCInfo.AnalyzeCallOperands(Outs,
1469 CCAssignFnForNode(CalleeCC, false, isVarArg));
1470 if (CCInfo.getNextStackOffset()) {
1471 MachineFunction &MF = DAG.getMachineFunction();
1473 // Check if the arguments are already laid out in the right way as
1474 // the caller's fixed stack objects.
1475 MachineFrameInfo *MFI = MF.getFrameInfo();
1476 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1477 const ARMInstrInfo *TII =
1478 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1479 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1481 ++i, ++realArgIdx) {
1482 CCValAssign &VA = ArgLocs[i];
1483 EVT RegVT = VA.getLocVT();
1484 SDValue Arg = OutVals[realArgIdx];
1485 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1486 if (VA.getLocInfo() == CCValAssign::Indirect)
1488 if (VA.needsCustom()) {
1489 // f64 and vector types are split into multiple registers or
1490 // register/stack-slot combinations. The types will not match
1491 // the registers; give up on memory f64 refs until we figure
1492 // out what to do about this.
1495 if (!ArgLocs[++i].isRegLoc())
1497 if (RegVT == MVT::v2f64) {
1498 if (!ArgLocs[++i].isRegLoc())
1500 if (!ArgLocs[++i].isRegLoc())
1503 } else if (!VA.isRegLoc()) {
1504 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1516 ARMTargetLowering::LowerReturn(SDValue Chain,
1517 CallingConv::ID CallConv, bool isVarArg,
1518 const SmallVectorImpl<ISD::OutputArg> &Outs,
1519 const SmallVectorImpl<SDValue> &OutVals,
1520 DebugLoc dl, SelectionDAG &DAG) const {
1522 // CCValAssign - represent the assignment of the return value to a location.
1523 SmallVector<CCValAssign, 16> RVLocs;
1525 // CCState - Info about the registers and stack slots.
1526 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1529 // Analyze outgoing return values.
1530 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1533 // If this is the first return lowered for this function, add
1534 // the regs to the liveout set for the function.
1535 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1536 for (unsigned i = 0; i != RVLocs.size(); ++i)
1537 if (RVLocs[i].isRegLoc())
1538 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1543 // Copy the result values into the output registers.
1544 for (unsigned i = 0, realRVLocIdx = 0;
1546 ++i, ++realRVLocIdx) {
1547 CCValAssign &VA = RVLocs[i];
1548 assert(VA.isRegLoc() && "Can only return in registers!");
1550 SDValue Arg = OutVals[realRVLocIdx];
1552 switch (VA.getLocInfo()) {
1553 default: llvm_unreachable("Unknown loc info!");
1554 case CCValAssign::Full: break;
1555 case CCValAssign::BCvt:
1556 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1560 if (VA.needsCustom()) {
1561 if (VA.getLocVT() == MVT::v2f64) {
1562 // Extract the first half and return it in two registers.
1563 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1564 DAG.getConstant(0, MVT::i32));
1565 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1566 DAG.getVTList(MVT::i32, MVT::i32), Half);
1568 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1569 Flag = Chain.getValue(1);
1570 VA = RVLocs[++i]; // skip ahead to next loc
1571 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1572 HalfGPRs.getValue(1), Flag);
1573 Flag = Chain.getValue(1);
1574 VA = RVLocs[++i]; // skip ahead to next loc
1576 // Extract the 2nd half and fall through to handle it as an f64 value.
1577 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1578 DAG.getConstant(1, MVT::i32));
1580 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1582 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1583 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1584 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1585 Flag = Chain.getValue(1);
1586 VA = RVLocs[++i]; // skip ahead to next loc
1587 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1590 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1592 // Guarantee that all emitted copies are
1593 // stuck together, avoiding something bad.
1594 Flag = Chain.getValue(1);
1599 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1601 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1606 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1607 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1608 // one of the above mentioned nodes. It has to be wrapped because otherwise
1609 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1610 // be used to form addressing mode. These wrapped nodes will be selected
1612 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1613 EVT PtrVT = Op.getValueType();
1614 // FIXME there is no actual debug info here
1615 DebugLoc dl = Op.getDebugLoc();
1616 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1618 if (CP->isMachineConstantPoolEntry())
1619 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1620 CP->getAlignment());
1622 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1623 CP->getAlignment());
1624 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1627 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1628 SelectionDAG &DAG) const {
1629 MachineFunction &MF = DAG.getMachineFunction();
1630 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1631 unsigned ARMPCLabelIndex = 0;
1632 DebugLoc DL = Op.getDebugLoc();
1633 EVT PtrVT = getPointerTy();
1634 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1635 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1637 if (RelocM == Reloc::Static) {
1638 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1640 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1641 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1642 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1643 ARMCP::CPBlockAddress,
1645 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1647 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1648 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1649 PseudoSourceValue::getConstantPool(), 0,
1651 if (RelocM == Reloc::Static)
1653 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1654 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1657 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1659 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1660 SelectionDAG &DAG) const {
1661 DebugLoc dl = GA->getDebugLoc();
1662 EVT PtrVT = getPointerTy();
1663 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1664 MachineFunction &MF = DAG.getMachineFunction();
1665 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1666 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1667 ARMConstantPoolValue *CPV =
1668 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1669 ARMCP::CPValue, PCAdj, "tlsgd", true);
1670 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1671 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1672 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1673 PseudoSourceValue::getConstantPool(), 0,
1675 SDValue Chain = Argument.getValue(1);
1677 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1678 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1680 // call __tls_get_addr.
1683 Entry.Node = Argument;
1684 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1685 Args.push_back(Entry);
1686 // FIXME: is there useful debug info available here?
1687 std::pair<SDValue, SDValue> CallResult =
1688 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1689 false, false, false, false,
1690 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1691 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1692 return CallResult.first;
1695 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1696 // "local exec" model.
1698 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1699 SelectionDAG &DAG) const {
1700 const GlobalValue *GV = GA->getGlobal();
1701 DebugLoc dl = GA->getDebugLoc();
1703 SDValue Chain = DAG.getEntryNode();
1704 EVT PtrVT = getPointerTy();
1705 // Get the Thread Pointer
1706 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1708 if (GV->isDeclaration()) {
1709 MachineFunction &MF = DAG.getMachineFunction();
1710 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1711 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1712 // Initial exec model.
1713 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1714 ARMConstantPoolValue *CPV =
1715 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1716 ARMCP::CPValue, PCAdj, "gottpoff", true);
1717 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1718 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1719 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1720 PseudoSourceValue::getConstantPool(), 0,
1722 Chain = Offset.getValue(1);
1724 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1725 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1727 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1728 PseudoSourceValue::getConstantPool(), 0,
1732 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1733 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1734 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1735 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1736 PseudoSourceValue::getConstantPool(), 0,
1740 // The address of the thread local variable is the add of the thread
1741 // pointer with the offset of the variable.
1742 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1746 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1747 // TODO: implement the "local dynamic" model
1748 assert(Subtarget->isTargetELF() &&
1749 "TLS not implemented for non-ELF targets");
1750 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1751 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1752 // otherwise use the "Local Exec" TLS Model
1753 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1754 return LowerToTLSGeneralDynamicModel(GA, DAG);
1756 return LowerToTLSExecModels(GA, DAG);
1759 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1760 SelectionDAG &DAG) const {
1761 EVT PtrVT = getPointerTy();
1762 DebugLoc dl = Op.getDebugLoc();
1763 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1764 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1765 if (RelocM == Reloc::PIC_) {
1766 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1767 ARMConstantPoolValue *CPV =
1768 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1769 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1770 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1771 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1773 PseudoSourceValue::getConstantPool(), 0,
1775 SDValue Chain = Result.getValue(1);
1776 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1777 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1779 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1780 PseudoSourceValue::getGOT(), 0,
1784 // If we have T2 ops, we can materialize the address directly via movt/movw
1785 // pair. This is always cheaper.
1786 if (Subtarget->useMovt()) {
1787 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1788 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1790 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1791 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1792 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1793 PseudoSourceValue::getConstantPool(), 0,
1799 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1800 SelectionDAG &DAG) const {
1801 MachineFunction &MF = DAG.getMachineFunction();
1802 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1803 unsigned ARMPCLabelIndex = 0;
1804 EVT PtrVT = getPointerTy();
1805 DebugLoc dl = Op.getDebugLoc();
1806 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1807 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1809 if (RelocM == Reloc::Static)
1810 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1812 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1813 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1814 ARMConstantPoolValue *CPV =
1815 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1816 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1818 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1820 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1821 PseudoSourceValue::getConstantPool(), 0,
1823 SDValue Chain = Result.getValue(1);
1825 if (RelocM == Reloc::PIC_) {
1826 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1827 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1830 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1831 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1832 PseudoSourceValue::getGOT(), 0,
1838 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1839 SelectionDAG &DAG) const {
1840 assert(Subtarget->isTargetELF() &&
1841 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1842 MachineFunction &MF = DAG.getMachineFunction();
1843 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1844 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1845 EVT PtrVT = getPointerTy();
1846 DebugLoc dl = Op.getDebugLoc();
1847 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1848 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1849 "_GLOBAL_OFFSET_TABLE_",
1850 ARMPCLabelIndex, PCAdj);
1851 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1852 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1853 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1854 PseudoSourceValue::getConstantPool(), 0,
1856 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1857 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1861 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1862 DebugLoc dl = Op.getDebugLoc();
1863 SDValue Val = DAG.getConstant(0, MVT::i32);
1864 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1865 Op.getOperand(1), Val);
1869 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1870 DebugLoc dl = Op.getDebugLoc();
1871 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1872 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1876 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1877 const ARMSubtarget *Subtarget) const {
1878 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1879 DebugLoc dl = Op.getDebugLoc();
1881 default: return SDValue(); // Don't custom lower most intrinsics.
1882 case Intrinsic::arm_thread_pointer: {
1883 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1884 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1886 case Intrinsic::eh_sjlj_lsda: {
1887 MachineFunction &MF = DAG.getMachineFunction();
1888 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1889 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1890 EVT PtrVT = getPointerTy();
1891 DebugLoc dl = Op.getDebugLoc();
1892 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1894 unsigned PCAdj = (RelocM != Reloc::PIC_)
1895 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1896 ARMConstantPoolValue *CPV =
1897 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1898 ARMCP::CPLSDA, PCAdj);
1899 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1900 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1902 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1903 PseudoSourceValue::getConstantPool(), 0,
1906 if (RelocM == Reloc::PIC_) {
1907 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1908 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1915 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1916 const ARMSubtarget *Subtarget) {
1917 DebugLoc dl = Op.getDebugLoc();
1918 SDValue Op5 = Op.getOperand(5);
1919 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1920 // v6 and v7 can both handle barriers directly, but need handled a bit
1921 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1923 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1924 if (Subtarget->hasV7Ops())
1925 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1926 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1927 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1928 DAG.getConstant(0, MVT::i32));
1929 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1933 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1934 MachineFunction &MF = DAG.getMachineFunction();
1935 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1937 // vastart just stores the address of the VarArgsFrameIndex slot into the
1938 // memory location argument.
1939 DebugLoc dl = Op.getDebugLoc();
1940 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1941 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1942 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1943 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1948 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1949 SelectionDAG &DAG) const {
1950 SDNode *Node = Op.getNode();
1951 DebugLoc dl = Node->getDebugLoc();
1952 EVT VT = Node->getValueType(0);
1953 SDValue Chain = Op.getOperand(0);
1954 SDValue Size = Op.getOperand(1);
1955 SDValue Align = Op.getOperand(2);
1957 // Chain the dynamic stack allocation so that it doesn't modify the stack
1958 // pointer when other instructions are using the stack.
1959 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1961 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1962 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1963 if (AlignVal > StackAlign)
1964 // Do this now since selection pass cannot introduce new target
1965 // independent node.
1966 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1968 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1969 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1970 // do even more horrible hack later.
1971 MachineFunction &MF = DAG.getMachineFunction();
1972 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1973 if (AFI->isThumb1OnlyFunction()) {
1975 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1977 uint32_t Val = C->getZExtValue();
1978 if (Val <= 508 && ((Val & 3) == 0))
1982 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1985 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1986 SDValue Ops1[] = { Chain, Size, Align };
1987 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1988 Chain = Res.getValue(1);
1989 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1990 DAG.getIntPtrConstant(0, true), SDValue());
1991 SDValue Ops2[] = { Res, Chain };
1992 return DAG.getMergeValues(Ops2, 2, dl);
1996 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1997 SDValue &Root, SelectionDAG &DAG,
1998 DebugLoc dl) const {
1999 MachineFunction &MF = DAG.getMachineFunction();
2000 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2002 TargetRegisterClass *RC;
2003 if (AFI->isThumb1OnlyFunction())
2004 RC = ARM::tGPRRegisterClass;
2006 RC = ARM::GPRRegisterClass;
2008 // Transform the arguments stored in physical registers into virtual ones.
2009 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2010 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2013 if (NextVA.isMemLoc()) {
2014 MachineFrameInfo *MFI = MF.getFrameInfo();
2015 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2017 // Create load node to retrieve arguments from the stack.
2018 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2019 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2020 PseudoSourceValue::getFixedStack(FI), 0,
2023 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2024 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2027 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2031 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2032 CallingConv::ID CallConv, bool isVarArg,
2033 const SmallVectorImpl<ISD::InputArg>
2035 DebugLoc dl, SelectionDAG &DAG,
2036 SmallVectorImpl<SDValue> &InVals)
2039 MachineFunction &MF = DAG.getMachineFunction();
2040 MachineFrameInfo *MFI = MF.getFrameInfo();
2042 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2044 // Assign locations to all of the incoming arguments.
2045 SmallVector<CCValAssign, 16> ArgLocs;
2046 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2048 CCInfo.AnalyzeFormalArguments(Ins,
2049 CCAssignFnForNode(CallConv, /* Return*/ false,
2052 SmallVector<SDValue, 16> ArgValues;
2054 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2055 CCValAssign &VA = ArgLocs[i];
2057 // Arguments stored in registers.
2058 if (VA.isRegLoc()) {
2059 EVT RegVT = VA.getLocVT();
2062 if (VA.needsCustom()) {
2063 // f64 and vector types are split up into multiple registers or
2064 // combinations of registers and stack slots.
2065 if (VA.getLocVT() == MVT::v2f64) {
2066 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2068 VA = ArgLocs[++i]; // skip ahead to next loc
2070 if (VA.isMemLoc()) {
2071 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2072 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2073 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2074 PseudoSourceValue::getFixedStack(FI), 0,
2077 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2080 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2081 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2082 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2083 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2084 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2086 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2089 TargetRegisterClass *RC;
2091 if (RegVT == MVT::f32)
2092 RC = ARM::SPRRegisterClass;
2093 else if (RegVT == MVT::f64)
2094 RC = ARM::DPRRegisterClass;
2095 else if (RegVT == MVT::v2f64)
2096 RC = ARM::QPRRegisterClass;
2097 else if (RegVT == MVT::i32)
2098 RC = (AFI->isThumb1OnlyFunction() ?
2099 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2101 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2103 // Transform the arguments in physical registers into virtual ones.
2104 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2105 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2108 // If this is an 8 or 16-bit value, it is really passed promoted
2109 // to 32 bits. Insert an assert[sz]ext to capture this, then
2110 // truncate to the right size.
2111 switch (VA.getLocInfo()) {
2112 default: llvm_unreachable("Unknown loc info!");
2113 case CCValAssign::Full: break;
2114 case CCValAssign::BCvt:
2115 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2117 case CCValAssign::SExt:
2118 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2119 DAG.getValueType(VA.getValVT()));
2120 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2122 case CCValAssign::ZExt:
2123 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2124 DAG.getValueType(VA.getValVT()));
2125 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2129 InVals.push_back(ArgValue);
2131 } else { // VA.isRegLoc()
2134 assert(VA.isMemLoc());
2135 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2137 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2138 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2140 // Create load nodes to retrieve arguments from the stack.
2141 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2142 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2143 PseudoSourceValue::getFixedStack(FI), 0,
2150 static const unsigned GPRArgRegs[] = {
2151 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2154 unsigned NumGPRs = CCInfo.getFirstUnallocated
2155 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2157 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2158 unsigned VARegSize = (4 - NumGPRs) * 4;
2159 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2160 unsigned ArgOffset = CCInfo.getNextStackOffset();
2161 if (VARegSaveSize) {
2162 // If this function is vararg, store any remaining integer argument regs
2163 // to their spots on the stack so that they may be loaded by deferencing
2164 // the result of va_next.
2165 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2166 AFI->setVarArgsFrameIndex(
2167 MFI->CreateFixedObject(VARegSaveSize,
2168 ArgOffset + VARegSaveSize - VARegSize,
2170 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2173 SmallVector<SDValue, 4> MemOps;
2174 for (; NumGPRs < 4; ++NumGPRs) {
2175 TargetRegisterClass *RC;
2176 if (AFI->isThumb1OnlyFunction())
2177 RC = ARM::tGPRRegisterClass;
2179 RC = ARM::GPRRegisterClass;
2181 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2182 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2184 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2185 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2186 0, false, false, 0);
2187 MemOps.push_back(Store);
2188 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2189 DAG.getConstant(4, getPointerTy()));
2191 if (!MemOps.empty())
2192 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2193 &MemOps[0], MemOps.size());
2195 // This will point to the next argument passed via stack.
2196 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2202 /// isFloatingPointZero - Return true if this is +0.0.
2203 static bool isFloatingPointZero(SDValue Op) {
2204 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2205 return CFP->getValueAPF().isPosZero();
2206 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2207 // Maybe this has already been legalized into the constant pool?
2208 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2209 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2210 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2211 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2212 return CFP->getValueAPF().isPosZero();
2218 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2219 /// the given operands.
2221 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2222 SDValue &ARMcc, SelectionDAG &DAG,
2223 DebugLoc dl) const {
2224 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2225 unsigned C = RHSC->getZExtValue();
2226 if (!isLegalICmpImmediate(C)) {
2227 // Constant does not fit, try adjusting it by one?
2232 if (isLegalICmpImmediate(C-1)) {
2233 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2234 RHS = DAG.getConstant(C-1, MVT::i32);
2239 if (C > 0 && isLegalICmpImmediate(C-1)) {
2240 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2241 RHS = DAG.getConstant(C-1, MVT::i32);
2246 if (isLegalICmpImmediate(C+1)) {
2247 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2248 RHS = DAG.getConstant(C+1, MVT::i32);
2253 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2254 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2255 RHS = DAG.getConstant(C+1, MVT::i32);
2262 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2263 ARMISD::NodeType CompareType;
2266 CompareType = ARMISD::CMP;
2271 CompareType = ARMISD::CMPZ;
2274 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2275 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2278 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2280 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2281 DebugLoc dl) const {
2283 if (!isFloatingPointZero(RHS))
2284 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2286 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2287 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2290 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2291 EVT VT = Op.getValueType();
2292 SDValue LHS = Op.getOperand(0);
2293 SDValue RHS = Op.getOperand(1);
2294 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2295 SDValue TrueVal = Op.getOperand(2);
2296 SDValue FalseVal = Op.getOperand(3);
2297 DebugLoc dl = Op.getDebugLoc();
2299 if (LHS.getValueType() == MVT::i32) {
2301 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2302 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2303 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2306 ARMCC::CondCodes CondCode, CondCode2;
2307 FPCCToARMCC(CC, CondCode, CondCode2);
2309 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2310 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2311 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2312 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2314 if (CondCode2 != ARMCC::AL) {
2315 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2316 // FIXME: Needs another CMP because flag can have but one use.
2317 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2318 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2319 Result, TrueVal, ARMcc2, CCR, Cmp2);
2324 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2325 /// to morph to an integer compare sequence.
2326 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2327 const ARMSubtarget *Subtarget) {
2328 SDNode *N = Op.getNode();
2329 if (!N->hasOneUse())
2330 // Otherwise it requires moving the value from fp to integer registers.
2332 if (!N->getNumValues())
2334 EVT VT = Op.getValueType();
2335 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2336 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2337 // vmrs are very slow, e.g. cortex-a8.
2340 if (isFloatingPointZero(Op)) {
2344 return ISD::isNormalLoad(N);
2347 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2348 if (isFloatingPointZero(Op))
2349 return DAG.getConstant(0, MVT::i32);
2351 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2352 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2353 Ld->getChain(), Ld->getBasePtr(),
2354 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2355 Ld->isVolatile(), Ld->isNonTemporal(),
2356 Ld->getAlignment());
2358 llvm_unreachable("Unknown VFP cmp argument!");
2361 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2362 SDValue &RetVal1, SDValue &RetVal2) {
2363 if (isFloatingPointZero(Op)) {
2364 RetVal1 = DAG.getConstant(0, MVT::i32);
2365 RetVal2 = DAG.getConstant(0, MVT::i32);
2369 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2370 SDValue Ptr = Ld->getBasePtr();
2371 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2372 Ld->getChain(), Ptr,
2373 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2374 Ld->isVolatile(), Ld->isNonTemporal(),
2375 Ld->getAlignment());
2377 EVT PtrType = Ptr.getValueType();
2378 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2379 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2380 PtrType, Ptr, DAG.getConstant(4, PtrType));
2381 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2382 Ld->getChain(), NewPtr,
2383 Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
2384 Ld->isVolatile(), Ld->isNonTemporal(),
2389 llvm_unreachable("Unknown VFP cmp argument!");
2392 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2393 /// f32 and even f64 comparisons to integer ones.
2395 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2396 SDValue Chain = Op.getOperand(0);
2397 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2398 SDValue LHS = Op.getOperand(2);
2399 SDValue RHS = Op.getOperand(3);
2400 SDValue Dest = Op.getOperand(4);
2401 DebugLoc dl = Op.getDebugLoc();
2403 bool SeenZero = false;
2404 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2405 canChangeToInt(RHS, SeenZero, Subtarget) &&
2406 // If one of the operand is zero, it's safe to ignore the NaN case since
2407 // we only care about equality comparisons.
2408 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2409 // If unsafe fp math optimization is enabled and there are no othter uses of
2410 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2411 // to an integer comparison.
2412 if (CC == ISD::SETOEQ)
2414 else if (CC == ISD::SETUNE)
2418 if (LHS.getValueType() == MVT::f32) {
2419 LHS = bitcastf32Toi32(LHS, DAG);
2420 RHS = bitcastf32Toi32(RHS, DAG);
2421 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2422 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2423 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2424 Chain, Dest, ARMcc, CCR, Cmp);
2429 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2430 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2431 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2432 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2433 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2434 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2435 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2441 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2442 SDValue Chain = Op.getOperand(0);
2443 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2444 SDValue LHS = Op.getOperand(2);
2445 SDValue RHS = Op.getOperand(3);
2446 SDValue Dest = Op.getOperand(4);
2447 DebugLoc dl = Op.getDebugLoc();
2449 if (LHS.getValueType() == MVT::i32) {
2451 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2452 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2453 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2454 Chain, Dest, ARMcc, CCR, Cmp);
2457 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2460 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2461 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2462 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2463 if (Result.getNode())
2467 ARMCC::CondCodes CondCode, CondCode2;
2468 FPCCToARMCC(CC, CondCode, CondCode2);
2470 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2471 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2472 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2473 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2474 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2475 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2476 if (CondCode2 != ARMCC::AL) {
2477 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2478 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2479 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2484 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2485 SDValue Chain = Op.getOperand(0);
2486 SDValue Table = Op.getOperand(1);
2487 SDValue Index = Op.getOperand(2);
2488 DebugLoc dl = Op.getDebugLoc();
2490 EVT PTy = getPointerTy();
2491 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2492 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2493 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2494 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2495 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2496 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2497 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2498 if (Subtarget->isThumb2()) {
2499 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2500 // which does another jump to the destination. This also makes it easier
2501 // to translate it to TBB / TBH later.
2502 // FIXME: This might not work if the function is extremely large.
2503 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2504 Addr, Op.getOperand(2), JTI, UId);
2506 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2507 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2508 PseudoSourceValue::getJumpTable(), 0,
2510 Chain = Addr.getValue(1);
2511 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2512 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2514 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2515 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2516 Chain = Addr.getValue(1);
2517 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2521 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2522 DebugLoc dl = Op.getDebugLoc();
2525 switch (Op.getOpcode()) {
2527 assert(0 && "Invalid opcode!");
2528 case ISD::FP_TO_SINT:
2529 Opc = ARMISD::FTOSI;
2531 case ISD::FP_TO_UINT:
2532 Opc = ARMISD::FTOUI;
2535 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2536 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2539 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2540 EVT VT = Op.getValueType();
2541 DebugLoc dl = Op.getDebugLoc();
2544 switch (Op.getOpcode()) {
2546 assert(0 && "Invalid opcode!");
2547 case ISD::SINT_TO_FP:
2548 Opc = ARMISD::SITOF;
2550 case ISD::UINT_TO_FP:
2551 Opc = ARMISD::UITOF;
2555 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2556 return DAG.getNode(Opc, dl, VT, Op);
2559 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2560 // Implement fcopysign with a fabs and a conditional fneg.
2561 SDValue Tmp0 = Op.getOperand(0);
2562 SDValue Tmp1 = Op.getOperand(1);
2563 DebugLoc dl = Op.getDebugLoc();
2564 EVT VT = Op.getValueType();
2565 EVT SrcVT = Tmp1.getValueType();
2566 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2567 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2568 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2569 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2570 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2571 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2574 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2575 MachineFunction &MF = DAG.getMachineFunction();
2576 MachineFrameInfo *MFI = MF.getFrameInfo();
2577 MFI->setReturnAddressIsTaken(true);
2579 EVT VT = Op.getValueType();
2580 DebugLoc dl = Op.getDebugLoc();
2581 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2583 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2584 SDValue Offset = DAG.getConstant(4, MVT::i32);
2585 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2586 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2587 NULL, 0, false, false, 0);
2590 // Return LR, which contains the return address. Mark it an implicit live-in.
2591 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2592 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2595 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2596 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2597 MFI->setFrameAddressIsTaken(true);
2599 EVT VT = Op.getValueType();
2600 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2601 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2602 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2603 ? ARM::R7 : ARM::R11;
2604 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2606 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2611 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2612 /// expand a bit convert where either the source or destination type is i64 to
2613 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2614 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2615 /// vectors), since the legalizer won't know what to do with that.
2616 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2618 DebugLoc dl = N->getDebugLoc();
2619 SDValue Op = N->getOperand(0);
2621 // This function is only supposed to be called for i64 types, either as the
2622 // source or destination of the bit convert.
2623 EVT SrcVT = Op.getValueType();
2624 EVT DstVT = N->getValueType(0);
2625 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2626 "ExpandBIT_CONVERT called for non-i64 type");
2628 // Turn i64->f64 into VMOVDRR.
2629 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2630 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2631 DAG.getConstant(0, MVT::i32));
2632 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2633 DAG.getConstant(1, MVT::i32));
2634 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2635 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2638 // Turn f64->i64 into VMOVRRD.
2639 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2640 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2641 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2642 // Merge the pieces into a single i64 value.
2643 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2649 /// getZeroVector - Returns a vector of specified type with all zero elements.
2650 /// Zero vectors are used to represent vector negation and in those cases
2651 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2652 /// not support i64 elements, so sometimes the zero vectors will need to be
2653 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2655 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2656 assert(VT.isVector() && "Expected a vector type");
2657 // The canonical modified immediate encoding of a zero vector is....0!
2658 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2659 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2660 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2661 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2664 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2665 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2666 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2667 SelectionDAG &DAG) const {
2668 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2669 EVT VT = Op.getValueType();
2670 unsigned VTBits = VT.getSizeInBits();
2671 DebugLoc dl = Op.getDebugLoc();
2672 SDValue ShOpLo = Op.getOperand(0);
2673 SDValue ShOpHi = Op.getOperand(1);
2674 SDValue ShAmt = Op.getOperand(2);
2676 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2678 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2680 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2681 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2682 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2683 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2684 DAG.getConstant(VTBits, MVT::i32));
2685 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2686 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2687 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2689 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2690 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2692 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2693 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2696 SDValue Ops[2] = { Lo, Hi };
2697 return DAG.getMergeValues(Ops, 2, dl);
2700 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2701 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2702 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2703 SelectionDAG &DAG) const {
2704 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2705 EVT VT = Op.getValueType();
2706 unsigned VTBits = VT.getSizeInBits();
2707 DebugLoc dl = Op.getDebugLoc();
2708 SDValue ShOpLo = Op.getOperand(0);
2709 SDValue ShOpHi = Op.getOperand(1);
2710 SDValue ShAmt = Op.getOperand(2);
2713 assert(Op.getOpcode() == ISD::SHL_PARTS);
2714 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2715 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2716 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2717 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2718 DAG.getConstant(VTBits, MVT::i32));
2719 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2720 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2722 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2723 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2724 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2726 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2727 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2730 SDValue Ops[2] = { Lo, Hi };
2731 return DAG.getMergeValues(Ops, 2, dl);
2734 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2735 const ARMSubtarget *ST) {
2736 EVT VT = N->getValueType(0);
2737 DebugLoc dl = N->getDebugLoc();
2739 if (!ST->hasV6T2Ops())
2742 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2743 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2746 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2747 const ARMSubtarget *ST) {
2748 EVT VT = N->getValueType(0);
2749 DebugLoc dl = N->getDebugLoc();
2751 // Lower vector shifts on NEON to use VSHL.
2752 if (VT.isVector()) {
2753 assert(ST->hasNEON() && "unexpected vector shift");
2755 // Left shifts translate directly to the vshiftu intrinsic.
2756 if (N->getOpcode() == ISD::SHL)
2757 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2758 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2759 N->getOperand(0), N->getOperand(1));
2761 assert((N->getOpcode() == ISD::SRA ||
2762 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2764 // NEON uses the same intrinsics for both left and right shifts. For
2765 // right shifts, the shift amounts are negative, so negate the vector of
2767 EVT ShiftVT = N->getOperand(1).getValueType();
2768 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2769 getZeroVector(ShiftVT, DAG, dl),
2771 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2772 Intrinsic::arm_neon_vshifts :
2773 Intrinsic::arm_neon_vshiftu);
2774 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2775 DAG.getConstant(vshiftInt, MVT::i32),
2776 N->getOperand(0), NegatedCount);
2779 // We can get here for a node like i32 = ISD::SHL i32, i64
2783 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2784 "Unknown shift to lower!");
2786 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2787 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2788 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2791 // If we are in thumb mode, we don't have RRX.
2792 if (ST->isThumb1Only()) return SDValue();
2794 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2795 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2796 DAG.getConstant(0, MVT::i32));
2797 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2798 DAG.getConstant(1, MVT::i32));
2800 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2801 // captures the result into a carry flag.
2802 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2803 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2805 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2806 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2808 // Merge the pieces into a single i64 value.
2809 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2812 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2813 SDValue TmpOp0, TmpOp1;
2814 bool Invert = false;
2818 SDValue Op0 = Op.getOperand(0);
2819 SDValue Op1 = Op.getOperand(1);
2820 SDValue CC = Op.getOperand(2);
2821 EVT VT = Op.getValueType();
2822 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2823 DebugLoc dl = Op.getDebugLoc();
2825 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2826 switch (SetCCOpcode) {
2827 default: llvm_unreachable("Illegal FP comparison"); break;
2829 case ISD::SETNE: Invert = true; // Fallthrough
2831 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2833 case ISD::SETLT: Swap = true; // Fallthrough
2835 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2837 case ISD::SETLE: Swap = true; // Fallthrough
2839 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2840 case ISD::SETUGE: Swap = true; // Fallthrough
2841 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2842 case ISD::SETUGT: Swap = true; // Fallthrough
2843 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2844 case ISD::SETUEQ: Invert = true; // Fallthrough
2846 // Expand this to (OLT | OGT).
2850 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2851 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2853 case ISD::SETUO: Invert = true; // Fallthrough
2855 // Expand this to (OLT | OGE).
2859 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2860 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2864 // Integer comparisons.
2865 switch (SetCCOpcode) {
2866 default: llvm_unreachable("Illegal integer comparison"); break;
2867 case ISD::SETNE: Invert = true;
2868 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2869 case ISD::SETLT: Swap = true;
2870 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2871 case ISD::SETLE: Swap = true;
2872 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2873 case ISD::SETULT: Swap = true;
2874 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2875 case ISD::SETULE: Swap = true;
2876 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2879 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2880 if (Opc == ARMISD::VCEQ) {
2883 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2885 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2888 // Ignore bitconvert.
2889 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2890 AndOp = AndOp.getOperand(0);
2892 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2894 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2895 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2902 std::swap(Op0, Op1);
2904 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2907 Result = DAG.getNOT(dl, Result, VT);
2912 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2913 /// valid vector constant for a NEON instruction with a "modified immediate"
2914 /// operand (e.g., VMOV). If so, return the encoded value.
2915 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2916 unsigned SplatBitSize, SelectionDAG &DAG,
2917 EVT &VT, bool is128Bits, bool isVMOV) {
2918 unsigned OpCmode, Imm;
2920 // SplatBitSize is set to the smallest size that splats the vector, so a
2921 // zero vector will always have SplatBitSize == 8. However, NEON modified
2922 // immediate instructions others than VMOV do not support the 8-bit encoding
2923 // of a zero vector, and the default encoding of zero is supposed to be the
2928 switch (SplatBitSize) {
2932 // Any 1-byte value is OK. Op=0, Cmode=1110.
2933 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2936 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
2940 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2941 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
2942 if ((SplatBits & ~0xff) == 0) {
2943 // Value = 0x00nn: Op=x, Cmode=100x.
2948 if ((SplatBits & ~0xff00) == 0) {
2949 // Value = 0xnn00: Op=x, Cmode=101x.
2951 Imm = SplatBits >> 8;
2957 // NEON's 32-bit VMOV supports splat values where:
2958 // * only one byte is nonzero, or
2959 // * the least significant byte is 0xff and the second byte is nonzero, or
2960 // * the least significant 2 bytes are 0xff and the third is nonzero.
2961 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
2962 if ((SplatBits & ~0xff) == 0) {
2963 // Value = 0x000000nn: Op=x, Cmode=000x.
2968 if ((SplatBits & ~0xff00) == 0) {
2969 // Value = 0x0000nn00: Op=x, Cmode=001x.
2971 Imm = SplatBits >> 8;
2974 if ((SplatBits & ~0xff0000) == 0) {
2975 // Value = 0x00nn0000: Op=x, Cmode=010x.
2977 Imm = SplatBits >> 16;
2980 if ((SplatBits & ~0xff000000) == 0) {
2981 // Value = 0xnn000000: Op=x, Cmode=011x.
2983 Imm = SplatBits >> 24;
2987 if ((SplatBits & ~0xffff) == 0 &&
2988 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2989 // Value = 0x0000nnff: Op=x, Cmode=1100.
2991 Imm = SplatBits >> 8;
2996 if ((SplatBits & ~0xffffff) == 0 &&
2997 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2998 // Value = 0x00nnffff: Op=x, Cmode=1101.
3000 Imm = SplatBits >> 16;
3001 SplatBits |= 0xffff;
3005 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3006 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3007 // VMOV.I32. A (very) minor optimization would be to replicate the value
3008 // and fall through here to test for a valid 64-bit splat. But, then the
3009 // caller would also need to check and handle the change in size.
3015 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3016 uint64_t BitMask = 0xff;
3018 unsigned ImmMask = 1;
3020 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3021 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3024 } else if ((SplatBits & BitMask) != 0) {
3030 // Op=1, Cmode=1110.
3033 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3038 llvm_unreachable("unexpected size for isNEONModifiedImm");
3042 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3043 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3046 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3047 bool &ReverseVEXT, unsigned &Imm) {
3048 unsigned NumElts = VT.getVectorNumElements();
3049 ReverseVEXT = false;
3052 // If this is a VEXT shuffle, the immediate value is the index of the first
3053 // element. The other shuffle indices must be the successive elements after
3055 unsigned ExpectedElt = Imm;
3056 for (unsigned i = 1; i < NumElts; ++i) {
3057 // Increment the expected index. If it wraps around, it may still be
3058 // a VEXT but the source vectors must be swapped.
3060 if (ExpectedElt == NumElts * 2) {
3065 if (ExpectedElt != static_cast<unsigned>(M[i]))
3069 // Adjust the index value if the source operands will be swapped.
3076 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3077 /// instruction with the specified blocksize. (The order of the elements
3078 /// within each block of the vector is reversed.)
3079 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3080 unsigned BlockSize) {
3081 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3082 "Only possible block sizes for VREV are: 16, 32, 64");
3084 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3088 unsigned NumElts = VT.getVectorNumElements();
3089 unsigned BlockElts = M[0] + 1;
3091 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3094 for (unsigned i = 0; i < NumElts; ++i) {
3095 if ((unsigned) M[i] !=
3096 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3103 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3104 unsigned &WhichResult) {
3105 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3109 unsigned NumElts = VT.getVectorNumElements();
3110 WhichResult = (M[0] == 0 ? 0 : 1);
3111 for (unsigned i = 0; i < NumElts; i += 2) {
3112 if ((unsigned) M[i] != i + WhichResult ||
3113 (unsigned) M[i+1] != i + NumElts + WhichResult)
3119 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3120 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3121 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3122 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3123 unsigned &WhichResult) {
3124 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3128 unsigned NumElts = VT.getVectorNumElements();
3129 WhichResult = (M[0] == 0 ? 0 : 1);
3130 for (unsigned i = 0; i < NumElts; i += 2) {
3131 if ((unsigned) M[i] != i + WhichResult ||
3132 (unsigned) M[i+1] != i + WhichResult)
3138 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3139 unsigned &WhichResult) {
3140 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3144 unsigned NumElts = VT.getVectorNumElements();
3145 WhichResult = (M[0] == 0 ? 0 : 1);
3146 for (unsigned i = 0; i != NumElts; ++i) {
3147 if ((unsigned) M[i] != 2 * i + WhichResult)
3151 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3152 if (VT.is64BitVector() && EltSz == 32)
3158 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3159 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3160 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3161 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3162 unsigned &WhichResult) {
3163 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3167 unsigned Half = VT.getVectorNumElements() / 2;
3168 WhichResult = (M[0] == 0 ? 0 : 1);
3169 for (unsigned j = 0; j != 2; ++j) {
3170 unsigned Idx = WhichResult;
3171 for (unsigned i = 0; i != Half; ++i) {
3172 if ((unsigned) M[i + j * Half] != Idx)
3178 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3179 if (VT.is64BitVector() && EltSz == 32)
3185 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3186 unsigned &WhichResult) {
3187 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3191 unsigned NumElts = VT.getVectorNumElements();
3192 WhichResult = (M[0] == 0 ? 0 : 1);
3193 unsigned Idx = WhichResult * NumElts / 2;
3194 for (unsigned i = 0; i != NumElts; i += 2) {
3195 if ((unsigned) M[i] != Idx ||
3196 (unsigned) M[i+1] != Idx + NumElts)
3201 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3202 if (VT.is64BitVector() && EltSz == 32)
3208 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3209 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3210 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3211 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3212 unsigned &WhichResult) {
3213 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3217 unsigned NumElts = VT.getVectorNumElements();
3218 WhichResult = (M[0] == 0 ? 0 : 1);
3219 unsigned Idx = WhichResult * NumElts / 2;
3220 for (unsigned i = 0; i != NumElts; i += 2) {
3221 if ((unsigned) M[i] != Idx ||
3222 (unsigned) M[i+1] != Idx)
3227 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3228 if (VT.is64BitVector() && EltSz == 32)
3234 // If this is a case we can't handle, return null and let the default
3235 // expansion code take care of it.
3236 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3237 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3238 DebugLoc dl = Op.getDebugLoc();
3239 EVT VT = Op.getValueType();
3241 APInt SplatBits, SplatUndef;
3242 unsigned SplatBitSize;
3244 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3245 if (SplatBitSize <= 64) {
3246 // Check if an immediate VMOV works.
3248 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3249 SplatUndef.getZExtValue(), SplatBitSize,
3250 DAG, VmovVT, VT.is128BitVector(), true);
3251 if (Val.getNode()) {
3252 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3253 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3256 // Try an immediate VMVN.
3257 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3258 ((1LL << SplatBitSize) - 1));
3259 Val = isNEONModifiedImm(NegatedImm,
3260 SplatUndef.getZExtValue(), SplatBitSize,
3261 DAG, VmovVT, VT.is128BitVector(), false);
3262 if (Val.getNode()) {
3263 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3264 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3269 // Scan through the operands to see if only one value is used.
3270 unsigned NumElts = VT.getVectorNumElements();
3271 bool isOnlyLowElement = true;
3272 bool usesOnlyOneValue = true;
3273 bool isConstant = true;
3275 for (unsigned i = 0; i < NumElts; ++i) {
3276 SDValue V = Op.getOperand(i);
3277 if (V.getOpcode() == ISD::UNDEF)
3280 isOnlyLowElement = false;
3281 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3284 if (!Value.getNode())
3286 else if (V != Value)
3287 usesOnlyOneValue = false;
3290 if (!Value.getNode())
3291 return DAG.getUNDEF(VT);
3293 if (isOnlyLowElement)
3294 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3296 // If all elements are constants, fall back to the default expansion, which
3297 // will generate a load from the constant pool.
3301 // Use VDUP for non-constant splats.
3302 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3303 if (usesOnlyOneValue && EltSize <= 32)
3304 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3306 // Vectors with 32- or 64-bit elements can be built by directly assigning
3307 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3308 // will be legalized.
3309 if (EltSize >= 32) {
3310 // Do the expansion with floating-point types, since that is what the VFP
3311 // registers are defined to use, and since i64 is not legal.
3312 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3313 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3314 SmallVector<SDValue, 8> Ops;
3315 for (unsigned i = 0; i < NumElts; ++i)
3316 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3317 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3318 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3324 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3325 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3326 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3327 /// are assumed to be legal.
3329 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3331 if (VT.getVectorNumElements() == 4 &&
3332 (VT.is128BitVector() || VT.is64BitVector())) {
3333 unsigned PFIndexes[4];
3334 for (unsigned i = 0; i != 4; ++i) {
3338 PFIndexes[i] = M[i];
3341 // Compute the index in the perfect shuffle table.
3342 unsigned PFTableIndex =
3343 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3344 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3345 unsigned Cost = (PFEntry >> 30);
3352 unsigned Imm, WhichResult;
3354 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3355 return (EltSize >= 32 ||
3356 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3357 isVREVMask(M, VT, 64) ||
3358 isVREVMask(M, VT, 32) ||
3359 isVREVMask(M, VT, 16) ||
3360 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3361 isVTRNMask(M, VT, WhichResult) ||
3362 isVUZPMask(M, VT, WhichResult) ||
3363 isVZIPMask(M, VT, WhichResult) ||
3364 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3365 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3366 isVZIP_v_undef_Mask(M, VT, WhichResult));
3369 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3370 /// the specified operations to build the shuffle.
3371 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3372 SDValue RHS, SelectionDAG &DAG,
3374 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3375 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3376 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3379 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3388 OP_VUZPL, // VUZP, left result
3389 OP_VUZPR, // VUZP, right result
3390 OP_VZIPL, // VZIP, left result
3391 OP_VZIPR, // VZIP, right result
3392 OP_VTRNL, // VTRN, left result
3393 OP_VTRNR // VTRN, right result
3396 if (OpNum == OP_COPY) {
3397 if (LHSID == (1*9+2)*9+3) return LHS;
3398 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3402 SDValue OpLHS, OpRHS;
3403 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3404 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3405 EVT VT = OpLHS.getValueType();
3408 default: llvm_unreachable("Unknown shuffle opcode!");
3410 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3415 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3416 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3420 return DAG.getNode(ARMISD::VEXT, dl, VT,
3422 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3425 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3426 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3429 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3430 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3433 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3434 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3438 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3439 SDValue V1 = Op.getOperand(0);
3440 SDValue V2 = Op.getOperand(1);
3441 DebugLoc dl = Op.getDebugLoc();
3442 EVT VT = Op.getValueType();
3443 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3444 SmallVector<int, 8> ShuffleMask;
3446 // Convert shuffles that are directly supported on NEON to target-specific
3447 // DAG nodes, instead of keeping them as shuffles and matching them again
3448 // during code selection. This is more efficient and avoids the possibility
3449 // of inconsistencies between legalization and selection.
3450 // FIXME: floating-point vectors should be canonicalized to integer vectors
3451 // of the same time so that they get CSEd properly.
3452 SVN->getMask(ShuffleMask);
3454 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3455 if (EltSize <= 32) {
3456 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3457 int Lane = SVN->getSplatIndex();
3458 // If this is undef splat, generate it via "just" vdup, if possible.
3459 if (Lane == -1) Lane = 0;
3461 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3462 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3464 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3465 DAG.getConstant(Lane, MVT::i32));
3470 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3473 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3474 DAG.getConstant(Imm, MVT::i32));
3477 if (isVREVMask(ShuffleMask, VT, 64))
3478 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3479 if (isVREVMask(ShuffleMask, VT, 32))
3480 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3481 if (isVREVMask(ShuffleMask, VT, 16))
3482 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3484 // Check for Neon shuffles that modify both input vectors in place.
3485 // If both results are used, i.e., if there are two shuffles with the same
3486 // source operands and with masks corresponding to both results of one of
3487 // these operations, DAG memoization will ensure that a single node is
3488 // used for both shuffles.
3489 unsigned WhichResult;
3490 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3491 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3492 V1, V2).getValue(WhichResult);
3493 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3494 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3495 V1, V2).getValue(WhichResult);
3496 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3497 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3498 V1, V2).getValue(WhichResult);
3500 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3501 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3502 V1, V1).getValue(WhichResult);
3503 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3504 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3505 V1, V1).getValue(WhichResult);
3506 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3507 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3508 V1, V1).getValue(WhichResult);
3511 // If the shuffle is not directly supported and it has 4 elements, use
3512 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3513 unsigned NumElts = VT.getVectorNumElements();
3515 unsigned PFIndexes[4];
3516 for (unsigned i = 0; i != 4; ++i) {
3517 if (ShuffleMask[i] < 0)
3520 PFIndexes[i] = ShuffleMask[i];
3523 // Compute the index in the perfect shuffle table.
3524 unsigned PFTableIndex =
3525 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3526 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3527 unsigned Cost = (PFEntry >> 30);
3530 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3533 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3534 if (EltSize >= 32) {
3535 // Do the expansion with floating-point types, since that is what the VFP
3536 // registers are defined to use, and since i64 is not legal.
3537 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3538 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3539 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3540 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3541 SmallVector<SDValue, 8> Ops;
3542 for (unsigned i = 0; i < NumElts; ++i) {
3543 if (ShuffleMask[i] < 0)
3544 Ops.push_back(DAG.getUNDEF(EltVT));
3546 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3547 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3548 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3551 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3552 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3558 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3559 EVT VT = Op.getValueType();
3560 DebugLoc dl = Op.getDebugLoc();
3561 SDValue Vec = Op.getOperand(0);
3562 SDValue Lane = Op.getOperand(1);
3563 assert(VT == MVT::i32 &&
3564 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3565 "unexpected type for custom-lowering vector extract");
3566 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3569 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3570 // The only time a CONCAT_VECTORS operation can have legal types is when
3571 // two 64-bit vectors are concatenated to a 128-bit vector.
3572 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3573 "unexpected CONCAT_VECTORS");
3574 DebugLoc dl = Op.getDebugLoc();
3575 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3576 SDValue Op0 = Op.getOperand(0);
3577 SDValue Op1 = Op.getOperand(1);
3578 if (Op0.getOpcode() != ISD::UNDEF)
3579 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3580 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3581 DAG.getIntPtrConstant(0));
3582 if (Op1.getOpcode() != ISD::UNDEF)
3583 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3584 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3585 DAG.getIntPtrConstant(1));
3586 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3589 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3590 switch (Op.getOpcode()) {
3591 default: llvm_unreachable("Don't know how to custom lower this!");
3592 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3593 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3594 case ISD::GlobalAddress:
3595 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3596 LowerGlobalAddressELF(Op, DAG);
3597 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3598 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3599 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3600 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3601 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3602 case ISD::VASTART: return LowerVASTART(Op, DAG);
3603 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3604 case ISD::SINT_TO_FP:
3605 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3606 case ISD::FP_TO_SINT:
3607 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3608 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3609 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3610 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3611 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3612 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3613 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3614 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3616 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3619 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3620 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3621 case ISD::SRL_PARTS:
3622 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3623 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3624 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3625 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3626 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3627 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3628 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3633 /// ReplaceNodeResults - Replace the results of node with an illegal result
3634 /// type with new values built out of custom code.
3635 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3636 SmallVectorImpl<SDValue>&Results,
3637 SelectionDAG &DAG) const {
3639 switch (N->getOpcode()) {
3641 llvm_unreachable("Don't know how to custom expand this!");
3643 case ISD::BIT_CONVERT:
3644 Res = ExpandBIT_CONVERT(N, DAG);
3648 Res = LowerShift(N, DAG, Subtarget);
3652 Results.push_back(Res);
3655 //===----------------------------------------------------------------------===//
3656 // ARM Scheduler Hooks
3657 //===----------------------------------------------------------------------===//
3660 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3661 MachineBasicBlock *BB,
3662 unsigned Size) const {
3663 unsigned dest = MI->getOperand(0).getReg();
3664 unsigned ptr = MI->getOperand(1).getReg();
3665 unsigned oldval = MI->getOperand(2).getReg();
3666 unsigned newval = MI->getOperand(3).getReg();
3667 unsigned scratch = BB->getParent()->getRegInfo()
3668 .createVirtualRegister(ARM::GPRRegisterClass);
3669 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3670 DebugLoc dl = MI->getDebugLoc();
3671 bool isThumb2 = Subtarget->isThumb2();
3673 unsigned ldrOpc, strOpc;
3675 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3677 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3678 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3681 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3682 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3685 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3686 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3690 MachineFunction *MF = BB->getParent();
3691 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3692 MachineFunction::iterator It = BB;
3693 ++It; // insert the new blocks after the current block
3695 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3696 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3697 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3698 MF->insert(It, loop1MBB);
3699 MF->insert(It, loop2MBB);
3700 MF->insert(It, exitMBB);
3702 // Transfer the remainder of BB and its successor edges to exitMBB.
3703 exitMBB->splice(exitMBB->begin(), BB,
3704 llvm::next(MachineBasicBlock::iterator(MI)),
3706 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3710 // fallthrough --> loop1MBB
3711 BB->addSuccessor(loop1MBB);
3714 // ldrex dest, [ptr]
3718 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3719 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3720 .addReg(dest).addReg(oldval));
3721 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3722 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3723 BB->addSuccessor(loop2MBB);
3724 BB->addSuccessor(exitMBB);
3727 // strex scratch, newval, [ptr]
3731 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3733 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3734 .addReg(scratch).addImm(0));
3735 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3736 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3737 BB->addSuccessor(loop1MBB);
3738 BB->addSuccessor(exitMBB);
3744 MI->eraseFromParent(); // The instruction is gone now.
3750 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3751 unsigned Size, unsigned BinOpcode) const {
3752 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3753 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3755 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3756 MachineFunction *MF = BB->getParent();
3757 MachineFunction::iterator It = BB;
3760 unsigned dest = MI->getOperand(0).getReg();
3761 unsigned ptr = MI->getOperand(1).getReg();
3762 unsigned incr = MI->getOperand(2).getReg();
3763 DebugLoc dl = MI->getDebugLoc();
3765 bool isThumb2 = Subtarget->isThumb2();
3766 unsigned ldrOpc, strOpc;
3768 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3770 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3771 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3774 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3775 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3778 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3779 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3783 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3784 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3785 MF->insert(It, loopMBB);
3786 MF->insert(It, exitMBB);
3788 // Transfer the remainder of BB and its successor edges to exitMBB.
3789 exitMBB->splice(exitMBB->begin(), BB,
3790 llvm::next(MachineBasicBlock::iterator(MI)),
3792 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3794 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3795 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3796 unsigned scratch2 = (!BinOpcode) ? incr :
3797 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3801 // fallthrough --> loopMBB
3802 BB->addSuccessor(loopMBB);
3806 // <binop> scratch2, dest, incr
3807 // strex scratch, scratch2, ptr
3810 // fallthrough --> exitMBB
3812 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3814 // operand order needs to go the other way for NAND
3815 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3816 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3817 addReg(incr).addReg(dest)).addReg(0);
3819 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3820 addReg(dest).addReg(incr)).addReg(0);
3823 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3825 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3826 .addReg(scratch).addImm(0));
3827 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3828 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3830 BB->addSuccessor(loopMBB);
3831 BB->addSuccessor(exitMBB);
3837 MI->eraseFromParent(); // The instruction is gone now.
3843 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
3844 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
3845 E = MBB->succ_end(); I != E; ++I)
3848 llvm_unreachable("Expecting a BB with two successors!");
3852 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3853 MachineBasicBlock *BB) const {
3854 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3855 DebugLoc dl = MI->getDebugLoc();
3856 bool isThumb2 = Subtarget->isThumb2();
3857 switch (MI->getOpcode()) {
3860 llvm_unreachable("Unexpected instr type to insert");
3862 case ARM::ATOMIC_LOAD_ADD_I8:
3863 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3864 case ARM::ATOMIC_LOAD_ADD_I16:
3865 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3866 case ARM::ATOMIC_LOAD_ADD_I32:
3867 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3869 case ARM::ATOMIC_LOAD_AND_I8:
3870 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3871 case ARM::ATOMIC_LOAD_AND_I16:
3872 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3873 case ARM::ATOMIC_LOAD_AND_I32:
3874 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3876 case ARM::ATOMIC_LOAD_OR_I8:
3877 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3878 case ARM::ATOMIC_LOAD_OR_I16:
3879 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3880 case ARM::ATOMIC_LOAD_OR_I32:
3881 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3883 case ARM::ATOMIC_LOAD_XOR_I8:
3884 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3885 case ARM::ATOMIC_LOAD_XOR_I16:
3886 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3887 case ARM::ATOMIC_LOAD_XOR_I32:
3888 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3890 case ARM::ATOMIC_LOAD_NAND_I8:
3891 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3892 case ARM::ATOMIC_LOAD_NAND_I16:
3893 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3894 case ARM::ATOMIC_LOAD_NAND_I32:
3895 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3897 case ARM::ATOMIC_LOAD_SUB_I8:
3898 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3899 case ARM::ATOMIC_LOAD_SUB_I16:
3900 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3901 case ARM::ATOMIC_LOAD_SUB_I32:
3902 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3904 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3905 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3906 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3908 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3909 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3910 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3912 case ARM::tMOVCCr_pseudo: {
3913 // To "insert" a SELECT_CC instruction, we actually have to insert the
3914 // diamond control-flow pattern. The incoming instruction knows the
3915 // destination vreg to set, the condition code register to branch on, the
3916 // true/false values to select between, and a branch opcode to use.
3917 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3918 MachineFunction::iterator It = BB;
3924 // cmpTY ccX, r1, r2
3926 // fallthrough --> copy0MBB
3927 MachineBasicBlock *thisMBB = BB;
3928 MachineFunction *F = BB->getParent();
3929 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3930 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3931 F->insert(It, copy0MBB);
3932 F->insert(It, sinkMBB);
3934 // Transfer the remainder of BB and its successor edges to sinkMBB.
3935 sinkMBB->splice(sinkMBB->begin(), BB,
3936 llvm::next(MachineBasicBlock::iterator(MI)),
3938 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3940 BB->addSuccessor(copy0MBB);
3941 BB->addSuccessor(sinkMBB);
3943 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3944 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3947 // %FalseValue = ...
3948 // # fallthrough to sinkMBB
3951 // Update machine-CFG edges
3952 BB->addSuccessor(sinkMBB);
3955 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3958 BuildMI(*BB, BB->begin(), dl,
3959 TII->get(ARM::PHI), MI->getOperand(0).getReg())
3960 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3961 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3963 MI->eraseFromParent(); // The pseudo instruction is gone now.
3968 case ARM::BCCZi64: {
3969 // Compare both parts that make up the double comparison separately for
3971 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
3973 unsigned LHS1 = MI->getOperand(1).getReg();
3974 unsigned LHS2 = MI->getOperand(2).getReg();
3976 AddDefaultPred(BuildMI(BB, dl,
3977 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3978 .addReg(LHS1).addImm(0));
3979 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3980 .addReg(LHS2).addImm(0)
3981 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
3983 unsigned RHS1 = MI->getOperand(3).getReg();
3984 unsigned RHS2 = MI->getOperand(4).getReg();
3985 AddDefaultPred(BuildMI(BB, dl,
3986 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3987 .addReg(LHS1).addReg(RHS1));
3988 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3989 .addReg(LHS2).addReg(RHS2)
3990 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
3993 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
3994 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
3995 if (MI->getOperand(0).getImm() == ARMCC::NE)
3996 std::swap(destMBB, exitMBB);
3998 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3999 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4000 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4003 MI->eraseFromParent(); // The pseudo instruction is gone now.
4010 case ARM::t2SUBrSPi_:
4011 case ARM::t2SUBrSPi12_:
4012 case ARM::t2SUBrSPs_: {
4013 MachineFunction *MF = BB->getParent();
4014 unsigned DstReg = MI->getOperand(0).getReg();
4015 unsigned SrcReg = MI->getOperand(1).getReg();
4016 bool DstIsDead = MI->getOperand(0).isDead();
4017 bool SrcIsKill = MI->getOperand(1).isKill();
4019 if (SrcReg != ARM::SP) {
4020 // Copy the source to SP from virtual register.
4021 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
4022 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4023 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
4024 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
4025 .addReg(SrcReg, getKillRegState(SrcIsKill));
4029 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
4030 switch (MI->getOpcode()) {
4032 llvm_unreachable("Unexpected pseudo instruction!");
4038 OpOpc = ARM::tADDspr;
4041 OpOpc = ARM::tSUBspi;
4043 case ARM::t2SUBrSPi_:
4044 OpOpc = ARM::t2SUBrSPi;
4045 NeedPred = true; NeedCC = true;
4047 case ARM::t2SUBrSPi12_:
4048 OpOpc = ARM::t2SUBrSPi12;
4051 case ARM::t2SUBrSPs_:
4052 OpOpc = ARM::t2SUBrSPs;
4053 NeedPred = true; NeedCC = true; NeedOp3 = true;
4056 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
4057 if (OpOpc == ARM::tAND)
4058 AddDefaultT1CC(MIB);
4059 MIB.addReg(ARM::SP);
4060 MIB.addOperand(MI->getOperand(2));
4062 MIB.addOperand(MI->getOperand(3));
4064 AddDefaultPred(MIB);
4068 // Copy the result from SP to virtual register.
4069 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
4070 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4071 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
4072 BuildMI(*BB, MI, dl, TII->get(CopyOpc))
4073 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
4075 MI->eraseFromParent(); // The pseudo instruction is gone now.
4081 //===----------------------------------------------------------------------===//
4082 // ARM Optimization Hooks
4083 //===----------------------------------------------------------------------===//
4086 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4087 TargetLowering::DAGCombinerInfo &DCI) {
4088 SelectionDAG &DAG = DCI.DAG;
4089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4090 EVT VT = N->getValueType(0);
4091 unsigned Opc = N->getOpcode();
4092 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4093 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4094 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4095 ISD::CondCode CC = ISD::SETCC_INVALID;
4098 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4100 SDValue CCOp = Slct.getOperand(0);
4101 if (CCOp.getOpcode() == ISD::SETCC)
4102 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4105 bool DoXform = false;
4107 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4110 if (LHS.getOpcode() == ISD::Constant &&
4111 cast<ConstantSDNode>(LHS)->isNullValue()) {
4113 } else if (CC != ISD::SETCC_INVALID &&
4114 RHS.getOpcode() == ISD::Constant &&
4115 cast<ConstantSDNode>(RHS)->isNullValue()) {
4116 std::swap(LHS, RHS);
4117 SDValue Op0 = Slct.getOperand(0);
4118 EVT OpVT = isSlctCC ? Op0.getValueType() :
4119 Op0.getOperand(0).getValueType();
4120 bool isInt = OpVT.isInteger();
4121 CC = ISD::getSetCCInverse(CC, isInt);
4123 if (!TLI.isCondCodeLegal(CC, OpVT))
4124 return SDValue(); // Inverse operator isn't legal.
4131 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4133 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4134 Slct.getOperand(0), Slct.getOperand(1), CC);
4135 SDValue CCOp = Slct.getOperand(0);
4137 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4138 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4139 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4140 CCOp, OtherOp, Result);
4145 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4146 static SDValue PerformADDCombine(SDNode *N,
4147 TargetLowering::DAGCombinerInfo &DCI) {
4148 // added by evan in r37685 with no testcase.
4149 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4151 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4152 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4153 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4154 if (Result.getNode()) return Result;
4156 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4157 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4158 if (Result.getNode()) return Result;
4164 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4165 static SDValue PerformSUBCombine(SDNode *N,
4166 TargetLowering::DAGCombinerInfo &DCI) {
4167 // added by evan in r37685 with no testcase.
4168 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4170 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4171 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4172 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4173 if (Result.getNode()) return Result;
4179 static SDValue PerformMULCombine(SDNode *N,
4180 TargetLowering::DAGCombinerInfo &DCI,
4181 const ARMSubtarget *Subtarget) {
4182 SelectionDAG &DAG = DCI.DAG;
4184 if (Subtarget->isThumb1Only())
4187 if (DAG.getMachineFunction().
4188 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4191 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4194 EVT VT = N->getValueType(0);
4198 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4202 uint64_t MulAmt = C->getZExtValue();
4203 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4204 ShiftAmt = ShiftAmt & (32 - 1);
4205 SDValue V = N->getOperand(0);
4206 DebugLoc DL = N->getDebugLoc();
4209 MulAmt >>= ShiftAmt;
4210 if (isPowerOf2_32(MulAmt - 1)) {
4211 // (mul x, 2^N + 1) => (add (shl x, N), x)
4212 Res = DAG.getNode(ISD::ADD, DL, VT,
4213 V, DAG.getNode(ISD::SHL, DL, VT,
4214 V, DAG.getConstant(Log2_32(MulAmt-1),
4216 } else if (isPowerOf2_32(MulAmt + 1)) {
4217 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4218 Res = DAG.getNode(ISD::SUB, DL, VT,
4219 DAG.getNode(ISD::SHL, DL, VT,
4220 V, DAG.getConstant(Log2_32(MulAmt+1),
4227 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4228 DAG.getConstant(ShiftAmt, MVT::i32));
4230 // Do not add new nodes to DAG combiner worklist.
4231 DCI.CombineTo(N, Res, false);
4235 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4236 /// ARMISD::VMOVRRD.
4237 static SDValue PerformVMOVRRDCombine(SDNode *N,
4238 TargetLowering::DAGCombinerInfo &DCI) {
4239 // fmrrd(fmdrr x, y) -> x,y
4240 SDValue InDouble = N->getOperand(0);
4241 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4242 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4246 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4247 /// ARMISD::VDUPLANE.
4248 static SDValue PerformVDUPLANECombine(SDNode *N,
4249 TargetLowering::DAGCombinerInfo &DCI) {
4250 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4252 SDValue Op = N->getOperand(0);
4253 EVT VT = N->getValueType(0);
4255 // Ignore bit_converts.
4256 while (Op.getOpcode() == ISD::BIT_CONVERT)
4257 Op = Op.getOperand(0);
4258 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4261 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4262 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4263 // The canonical VMOV for a zero vector uses a 32-bit element size.
4264 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4266 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4268 if (EltSize > VT.getVectorElementType().getSizeInBits())
4271 SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4272 return DCI.CombineTo(N, Res, false);
4275 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4276 /// operand of a vector shift operation, where all the elements of the
4277 /// build_vector must have the same constant integer value.
4278 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4279 // Ignore bit_converts.
4280 while (Op.getOpcode() == ISD::BIT_CONVERT)
4281 Op = Op.getOperand(0);
4282 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4283 APInt SplatBits, SplatUndef;
4284 unsigned SplatBitSize;
4286 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4287 HasAnyUndefs, ElementBits) ||
4288 SplatBitSize > ElementBits)
4290 Cnt = SplatBits.getSExtValue();
4294 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4295 /// operand of a vector shift left operation. That value must be in the range:
4296 /// 0 <= Value < ElementBits for a left shift; or
4297 /// 0 <= Value <= ElementBits for a long left shift.
4298 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4299 assert(VT.isVector() && "vector shift count is not a vector type");
4300 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4301 if (! getVShiftImm(Op, ElementBits, Cnt))
4303 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4306 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4307 /// operand of a vector shift right operation. For a shift opcode, the value
4308 /// is positive, but for an intrinsic the value count must be negative. The
4309 /// absolute value must be in the range:
4310 /// 1 <= |Value| <= ElementBits for a right shift; or
4311 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4312 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4314 assert(VT.isVector() && "vector shift count is not a vector type");
4315 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4316 if (! getVShiftImm(Op, ElementBits, Cnt))
4320 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4323 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4324 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4325 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4328 // Don't do anything for most intrinsics.
4331 // Vector shifts: check for immediate versions and lower them.
4332 // Note: This is done during DAG combining instead of DAG legalizing because
4333 // the build_vectors for 64-bit vector element shift counts are generally
4334 // not legal, and it is hard to see their values after they get legalized to
4335 // loads from a constant pool.
4336 case Intrinsic::arm_neon_vshifts:
4337 case Intrinsic::arm_neon_vshiftu:
4338 case Intrinsic::arm_neon_vshiftls:
4339 case Intrinsic::arm_neon_vshiftlu:
4340 case Intrinsic::arm_neon_vshiftn:
4341 case Intrinsic::arm_neon_vrshifts:
4342 case Intrinsic::arm_neon_vrshiftu:
4343 case Intrinsic::arm_neon_vrshiftn:
4344 case Intrinsic::arm_neon_vqshifts:
4345 case Intrinsic::arm_neon_vqshiftu:
4346 case Intrinsic::arm_neon_vqshiftsu:
4347 case Intrinsic::arm_neon_vqshiftns:
4348 case Intrinsic::arm_neon_vqshiftnu:
4349 case Intrinsic::arm_neon_vqshiftnsu:
4350 case Intrinsic::arm_neon_vqrshiftns:
4351 case Intrinsic::arm_neon_vqrshiftnu:
4352 case Intrinsic::arm_neon_vqrshiftnsu: {
4353 EVT VT = N->getOperand(1).getValueType();
4355 unsigned VShiftOpc = 0;
4358 case Intrinsic::arm_neon_vshifts:
4359 case Intrinsic::arm_neon_vshiftu:
4360 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4361 VShiftOpc = ARMISD::VSHL;
4364 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4365 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4366 ARMISD::VSHRs : ARMISD::VSHRu);
4371 case Intrinsic::arm_neon_vshiftls:
4372 case Intrinsic::arm_neon_vshiftlu:
4373 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4375 llvm_unreachable("invalid shift count for vshll intrinsic");
4377 case Intrinsic::arm_neon_vrshifts:
4378 case Intrinsic::arm_neon_vrshiftu:
4379 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4383 case Intrinsic::arm_neon_vqshifts:
4384 case Intrinsic::arm_neon_vqshiftu:
4385 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4389 case Intrinsic::arm_neon_vqshiftsu:
4390 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4392 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4394 case Intrinsic::arm_neon_vshiftn:
4395 case Intrinsic::arm_neon_vrshiftn:
4396 case Intrinsic::arm_neon_vqshiftns:
4397 case Intrinsic::arm_neon_vqshiftnu:
4398 case Intrinsic::arm_neon_vqshiftnsu:
4399 case Intrinsic::arm_neon_vqrshiftns:
4400 case Intrinsic::arm_neon_vqrshiftnu:
4401 case Intrinsic::arm_neon_vqrshiftnsu:
4402 // Narrowing shifts require an immediate right shift.
4403 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4405 llvm_unreachable("invalid shift count for narrowing vector shift "
4409 llvm_unreachable("unhandled vector shift");
4413 case Intrinsic::arm_neon_vshifts:
4414 case Intrinsic::arm_neon_vshiftu:
4415 // Opcode already set above.
4417 case Intrinsic::arm_neon_vshiftls:
4418 case Intrinsic::arm_neon_vshiftlu:
4419 if (Cnt == VT.getVectorElementType().getSizeInBits())
4420 VShiftOpc = ARMISD::VSHLLi;
4422 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4423 ARMISD::VSHLLs : ARMISD::VSHLLu);
4425 case Intrinsic::arm_neon_vshiftn:
4426 VShiftOpc = ARMISD::VSHRN; break;
4427 case Intrinsic::arm_neon_vrshifts:
4428 VShiftOpc = ARMISD::VRSHRs; break;
4429 case Intrinsic::arm_neon_vrshiftu:
4430 VShiftOpc = ARMISD::VRSHRu; break;
4431 case Intrinsic::arm_neon_vrshiftn:
4432 VShiftOpc = ARMISD::VRSHRN; break;
4433 case Intrinsic::arm_neon_vqshifts:
4434 VShiftOpc = ARMISD::VQSHLs; break;
4435 case Intrinsic::arm_neon_vqshiftu:
4436 VShiftOpc = ARMISD::VQSHLu; break;
4437 case Intrinsic::arm_neon_vqshiftsu:
4438 VShiftOpc = ARMISD::VQSHLsu; break;
4439 case Intrinsic::arm_neon_vqshiftns:
4440 VShiftOpc = ARMISD::VQSHRNs; break;
4441 case Intrinsic::arm_neon_vqshiftnu:
4442 VShiftOpc = ARMISD::VQSHRNu; break;
4443 case Intrinsic::arm_neon_vqshiftnsu:
4444 VShiftOpc = ARMISD::VQSHRNsu; break;
4445 case Intrinsic::arm_neon_vqrshiftns:
4446 VShiftOpc = ARMISD::VQRSHRNs; break;
4447 case Intrinsic::arm_neon_vqrshiftnu:
4448 VShiftOpc = ARMISD::VQRSHRNu; break;
4449 case Intrinsic::arm_neon_vqrshiftnsu:
4450 VShiftOpc = ARMISD::VQRSHRNsu; break;
4453 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4454 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4457 case Intrinsic::arm_neon_vshiftins: {
4458 EVT VT = N->getOperand(1).getValueType();
4460 unsigned VShiftOpc = 0;
4462 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4463 VShiftOpc = ARMISD::VSLI;
4464 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4465 VShiftOpc = ARMISD::VSRI;
4467 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4470 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4471 N->getOperand(1), N->getOperand(2),
4472 DAG.getConstant(Cnt, MVT::i32));
4475 case Intrinsic::arm_neon_vqrshifts:
4476 case Intrinsic::arm_neon_vqrshiftu:
4477 // No immediate versions of these to check for.
4484 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4485 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4486 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4487 /// vector element shift counts are generally not legal, and it is hard to see
4488 /// their values after they get legalized to loads from a constant pool.
4489 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4490 const ARMSubtarget *ST) {
4491 EVT VT = N->getValueType(0);
4493 // Nothing to be done for scalar shifts.
4494 if (! VT.isVector())
4497 assert(ST->hasNEON() && "unexpected vector shift");
4500 switch (N->getOpcode()) {
4501 default: llvm_unreachable("unexpected shift opcode");
4504 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4505 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4506 DAG.getConstant(Cnt, MVT::i32));
4511 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4512 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4513 ARMISD::VSHRs : ARMISD::VSHRu);
4514 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4515 DAG.getConstant(Cnt, MVT::i32));
4521 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4522 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4523 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4524 const ARMSubtarget *ST) {
4525 SDValue N0 = N->getOperand(0);
4527 // Check for sign- and zero-extensions of vector extract operations of 8-
4528 // and 16-bit vector elements. NEON supports these directly. They are
4529 // handled during DAG combining because type legalization will promote them
4530 // to 32-bit types and it is messy to recognize the operations after that.
4531 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4532 SDValue Vec = N0.getOperand(0);
4533 SDValue Lane = N0.getOperand(1);
4534 EVT VT = N->getValueType(0);
4535 EVT EltVT = N0.getValueType();
4536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4538 if (VT == MVT::i32 &&
4539 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4540 TLI.isTypeLegal(Vec.getValueType())) {
4543 switch (N->getOpcode()) {
4544 default: llvm_unreachable("unexpected opcode");
4545 case ISD::SIGN_EXTEND:
4546 Opc = ARMISD::VGETLANEs;
4548 case ISD::ZERO_EXTEND:
4549 case ISD::ANY_EXTEND:
4550 Opc = ARMISD::VGETLANEu;
4553 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4560 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4561 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4562 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4563 const ARMSubtarget *ST) {
4564 // If the target supports NEON, try to use vmax/vmin instructions for f32
4565 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4566 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4567 // a NaN; only do the transformation when it matches that behavior.
4569 // For now only do this when using NEON for FP operations; if using VFP, it
4570 // is not obvious that the benefit outweighs the cost of switching to the
4572 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4573 N->getValueType(0) != MVT::f32)
4576 SDValue CondLHS = N->getOperand(0);
4577 SDValue CondRHS = N->getOperand(1);
4578 SDValue LHS = N->getOperand(2);
4579 SDValue RHS = N->getOperand(3);
4580 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4582 unsigned Opcode = 0;
4584 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4585 IsReversed = false; // x CC y ? x : y
4586 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4587 IsReversed = true ; // x CC y ? y : x
4601 // If LHS is NaN, an ordered comparison will be false and the result will
4602 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4603 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4604 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4605 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4607 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4608 // will return -0, so vmin can only be used for unsafe math or if one of
4609 // the operands is known to be nonzero.
4610 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4612 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4614 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4623 // If LHS is NaN, an ordered comparison will be false and the result will
4624 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4625 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4626 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4627 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4629 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4630 // will return +0, so vmax can only be used for unsafe math or if one of
4631 // the operands is known to be nonzero.
4632 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4634 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4636 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4642 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4645 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4646 DAGCombinerInfo &DCI) const {
4647 switch (N->getOpcode()) {
4649 case ISD::ADD: return PerformADDCombine(N, DCI);
4650 case ISD::SUB: return PerformSUBCombine(N, DCI);
4651 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4652 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4653 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
4654 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4657 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4658 case ISD::SIGN_EXTEND:
4659 case ISD::ZERO_EXTEND:
4660 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4661 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4666 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4667 if (!Subtarget->hasV6Ops())
4668 // Pre-v6 does not support unaligned mem access.
4671 // v6+ may or may not support unaligned mem access depending on the system
4673 // FIXME: This is pretty conservative. Should we provide cmdline option to
4674 // control the behaviour?
4675 if (!Subtarget->isTargetDarwin())
4678 switch (VT.getSimpleVT().SimpleTy) {
4685 // FIXME: VLD1 etc with standard alignment is legal.
4689 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4694 switch (VT.getSimpleVT().SimpleTy) {
4695 default: return false;
4710 if ((V & (Scale - 1)) != 0)
4713 return V == (V & ((1LL << 5) - 1));
4716 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4717 const ARMSubtarget *Subtarget) {
4724 switch (VT.getSimpleVT().SimpleTy) {
4725 default: return false;
4730 // + imm12 or - imm8
4732 return V == (V & ((1LL << 8) - 1));
4733 return V == (V & ((1LL << 12) - 1));
4736 // Same as ARM mode. FIXME: NEON?
4737 if (!Subtarget->hasVFP2())
4742 return V == (V & ((1LL << 8) - 1));
4746 /// isLegalAddressImmediate - Return true if the integer value can be used
4747 /// as the offset of the target addressing mode for load / store of the
4749 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4750 const ARMSubtarget *Subtarget) {
4757 if (Subtarget->isThumb1Only())
4758 return isLegalT1AddressImmediate(V, VT);
4759 else if (Subtarget->isThumb2())
4760 return isLegalT2AddressImmediate(V, VT, Subtarget);
4765 switch (VT.getSimpleVT().SimpleTy) {
4766 default: return false;
4771 return V == (V & ((1LL << 12) - 1));
4774 return V == (V & ((1LL << 8) - 1));
4777 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4782 return V == (V & ((1LL << 8) - 1));
4786 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4788 int Scale = AM.Scale;
4792 switch (VT.getSimpleVT().SimpleTy) {
4793 default: return false;
4802 return Scale == 2 || Scale == 4 || Scale == 8;
4805 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4809 // Note, we allow "void" uses (basically, uses that aren't loads or
4810 // stores), because arm allows folding a scale into many arithmetic
4811 // operations. This should be made more precise and revisited later.
4813 // Allow r << imm, but the imm has to be a multiple of two.
4814 if (Scale & 1) return false;
4815 return isPowerOf2_32(Scale);
4819 /// isLegalAddressingMode - Return true if the addressing mode represented
4820 /// by AM is legal for this target, for a load/store of the specified type.
4821 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4822 const Type *Ty) const {
4823 EVT VT = getValueType(Ty, true);
4824 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4827 // Can never fold addr of global into load/store.
4832 case 0: // no scale reg, must be "r+i" or "r", or "i".
4835 if (Subtarget->isThumb1Only())
4839 // ARM doesn't support any R+R*scale+imm addr modes.
4846 if (Subtarget->isThumb2())
4847 return isLegalT2ScaledAddressingMode(AM, VT);
4849 int Scale = AM.Scale;
4850 switch (VT.getSimpleVT().SimpleTy) {
4851 default: return false;
4855 if (Scale < 0) Scale = -Scale;
4859 return isPowerOf2_32(Scale & ~1);
4863 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4868 // Note, we allow "void" uses (basically, uses that aren't loads or
4869 // stores), because arm allows folding a scale into many arithmetic
4870 // operations. This should be made more precise and revisited later.
4872 // Allow r << imm, but the imm has to be a multiple of two.
4873 if (Scale & 1) return false;
4874 return isPowerOf2_32(Scale);
4881 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4882 /// icmp immediate, that is the target has icmp instructions which can compare
4883 /// a register against the immediate without having to materialize the
4884 /// immediate into a register.
4885 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4886 if (!Subtarget->isThumb())
4887 return ARM_AM::getSOImmVal(Imm) != -1;
4888 if (Subtarget->isThumb2())
4889 return ARM_AM::getT2SOImmVal(Imm) != -1;
4890 return Imm >= 0 && Imm <= 255;
4893 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4894 bool isSEXTLoad, SDValue &Base,
4895 SDValue &Offset, bool &isInc,
4896 SelectionDAG &DAG) {
4897 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4900 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4902 Base = Ptr->getOperand(0);
4903 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4904 int RHSC = (int)RHS->getZExtValue();
4905 if (RHSC < 0 && RHSC > -256) {
4906 assert(Ptr->getOpcode() == ISD::ADD);
4908 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4912 isInc = (Ptr->getOpcode() == ISD::ADD);
4913 Offset = Ptr->getOperand(1);
4915 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4917 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4918 int RHSC = (int)RHS->getZExtValue();
4919 if (RHSC < 0 && RHSC > -0x1000) {
4920 assert(Ptr->getOpcode() == ISD::ADD);
4922 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4923 Base = Ptr->getOperand(0);
4928 if (Ptr->getOpcode() == ISD::ADD) {
4930 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4931 if (ShOpcVal != ARM_AM::no_shift) {
4932 Base = Ptr->getOperand(1);
4933 Offset = Ptr->getOperand(0);
4935 Base = Ptr->getOperand(0);
4936 Offset = Ptr->getOperand(1);
4941 isInc = (Ptr->getOpcode() == ISD::ADD);
4942 Base = Ptr->getOperand(0);
4943 Offset = Ptr->getOperand(1);
4947 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4951 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4952 bool isSEXTLoad, SDValue &Base,
4953 SDValue &Offset, bool &isInc,
4954 SelectionDAG &DAG) {
4955 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4958 Base = Ptr->getOperand(0);
4959 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4960 int RHSC = (int)RHS->getZExtValue();
4961 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4962 assert(Ptr->getOpcode() == ISD::ADD);
4964 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4966 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4967 isInc = Ptr->getOpcode() == ISD::ADD;
4968 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4976 /// getPreIndexedAddressParts - returns true by value, base pointer and
4977 /// offset pointer and addressing mode by reference if the node's address
4978 /// can be legally represented as pre-indexed load / store address.
4980 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4982 ISD::MemIndexedMode &AM,
4983 SelectionDAG &DAG) const {
4984 if (Subtarget->isThumb1Only())
4989 bool isSEXTLoad = false;
4990 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4991 Ptr = LD->getBasePtr();
4992 VT = LD->getMemoryVT();
4993 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4994 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4995 Ptr = ST->getBasePtr();
4996 VT = ST->getMemoryVT();
5001 bool isLegal = false;
5002 if (Subtarget->isThumb2())
5003 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5004 Offset, isInc, DAG);
5006 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5007 Offset, isInc, DAG);
5011 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5015 /// getPostIndexedAddressParts - returns true by value, base pointer and
5016 /// offset pointer and addressing mode by reference if this node can be
5017 /// combined with a load / store to form a post-indexed load / store.
5018 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5021 ISD::MemIndexedMode &AM,
5022 SelectionDAG &DAG) const {
5023 if (Subtarget->isThumb1Only())
5028 bool isSEXTLoad = false;
5029 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5030 VT = LD->getMemoryVT();
5031 Ptr = LD->getBasePtr();
5032 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5033 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5034 VT = ST->getMemoryVT();
5035 Ptr = ST->getBasePtr();
5040 bool isLegal = false;
5041 if (Subtarget->isThumb2())
5042 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5045 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5051 // Swap base ptr and offset to catch more post-index load / store when
5052 // it's legal. In Thumb2 mode, offset must be an immediate.
5053 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5054 !Subtarget->isThumb2())
5055 std::swap(Base, Offset);
5057 // Post-indexed load / store update the base pointer.
5062 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5066 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5070 const SelectionDAG &DAG,
5071 unsigned Depth) const {
5072 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5073 switch (Op.getOpcode()) {
5075 case ARMISD::CMOV: {
5076 // Bits are known zero/one if known on the LHS and RHS.
5077 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5078 if (KnownZero == 0 && KnownOne == 0) return;
5080 APInt KnownZeroRHS, KnownOneRHS;
5081 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5082 KnownZeroRHS, KnownOneRHS, Depth+1);
5083 KnownZero &= KnownZeroRHS;
5084 KnownOne &= KnownOneRHS;
5090 //===----------------------------------------------------------------------===//
5091 // ARM Inline Assembly Support
5092 //===----------------------------------------------------------------------===//
5094 /// getConstraintType - Given a constraint letter, return the type of
5095 /// constraint it is for this target.
5096 ARMTargetLowering::ConstraintType
5097 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5098 if (Constraint.size() == 1) {
5099 switch (Constraint[0]) {
5101 case 'l': return C_RegisterClass;
5102 case 'w': return C_RegisterClass;
5105 return TargetLowering::getConstraintType(Constraint);
5108 std::pair<unsigned, const TargetRegisterClass*>
5109 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5111 if (Constraint.size() == 1) {
5112 // GCC ARM Constraint Letters
5113 switch (Constraint[0]) {
5115 if (Subtarget->isThumb())
5116 return std::make_pair(0U, ARM::tGPRRegisterClass);
5118 return std::make_pair(0U, ARM::GPRRegisterClass);
5120 return std::make_pair(0U, ARM::GPRRegisterClass);
5123 return std::make_pair(0U, ARM::SPRRegisterClass);
5124 if (VT.getSizeInBits() == 64)
5125 return std::make_pair(0U, ARM::DPRRegisterClass);
5126 if (VT.getSizeInBits() == 128)
5127 return std::make_pair(0U, ARM::QPRRegisterClass);
5131 if (StringRef("{cc}").equals_lower(Constraint))
5132 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5134 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5137 std::vector<unsigned> ARMTargetLowering::
5138 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5140 if (Constraint.size() != 1)
5141 return std::vector<unsigned>();
5143 switch (Constraint[0]) { // GCC ARM Constraint Letters
5146 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5147 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5150 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5151 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5152 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5153 ARM::R12, ARM::LR, 0);
5156 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5157 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5158 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5159 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5160 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5161 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5162 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5163 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5164 if (VT.getSizeInBits() == 64)
5165 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5166 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5167 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5168 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5169 if (VT.getSizeInBits() == 128)
5170 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5171 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5175 return std::vector<unsigned>();
5178 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5179 /// vector. If it is invalid, don't add anything to Ops.
5180 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5182 std::vector<SDValue>&Ops,
5183 SelectionDAG &DAG) const {
5184 SDValue Result(0, 0);
5186 switch (Constraint) {
5188 case 'I': case 'J': case 'K': case 'L':
5189 case 'M': case 'N': case 'O':
5190 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5194 int64_t CVal64 = C->getSExtValue();
5195 int CVal = (int) CVal64;
5196 // None of these constraints allow values larger than 32 bits. Check
5197 // that the value fits in an int.
5201 switch (Constraint) {
5203 if (Subtarget->isThumb1Only()) {
5204 // This must be a constant between 0 and 255, for ADD
5206 if (CVal >= 0 && CVal <= 255)
5208 } else if (Subtarget->isThumb2()) {
5209 // A constant that can be used as an immediate value in a
5210 // data-processing instruction.
5211 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5214 // A constant that can be used as an immediate value in a
5215 // data-processing instruction.
5216 if (ARM_AM::getSOImmVal(CVal) != -1)
5222 if (Subtarget->isThumb()) { // FIXME thumb2
5223 // This must be a constant between -255 and -1, for negated ADD
5224 // immediates. This can be used in GCC with an "n" modifier that
5225 // prints the negated value, for use with SUB instructions. It is
5226 // not useful otherwise but is implemented for compatibility.
5227 if (CVal >= -255 && CVal <= -1)
5230 // This must be a constant between -4095 and 4095. It is not clear
5231 // what this constraint is intended for. Implemented for
5232 // compatibility with GCC.
5233 if (CVal >= -4095 && CVal <= 4095)
5239 if (Subtarget->isThumb1Only()) {
5240 // A 32-bit value where only one byte has a nonzero value. Exclude
5241 // zero to match GCC. This constraint is used by GCC internally for
5242 // constants that can be loaded with a move/shift combination.
5243 // It is not useful otherwise but is implemented for compatibility.
5244 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5246 } else if (Subtarget->isThumb2()) {
5247 // A constant whose bitwise inverse can be used as an immediate
5248 // value in a data-processing instruction. This can be used in GCC
5249 // with a "B" modifier that prints the inverted value, for use with
5250 // BIC and MVN instructions. It is not useful otherwise but is
5251 // implemented for compatibility.
5252 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5255 // A constant whose bitwise inverse can be used as an immediate
5256 // value in a data-processing instruction. This can be used in GCC
5257 // with a "B" modifier that prints the inverted value, for use with
5258 // BIC and MVN instructions. It is not useful otherwise but is
5259 // implemented for compatibility.
5260 if (ARM_AM::getSOImmVal(~CVal) != -1)
5266 if (Subtarget->isThumb1Only()) {
5267 // This must be a constant between -7 and 7,
5268 // for 3-operand ADD/SUB immediate instructions.
5269 if (CVal >= -7 && CVal < 7)
5271 } else if (Subtarget->isThumb2()) {
5272 // A constant whose negation can be used as an immediate value in a
5273 // data-processing instruction. This can be used in GCC with an "n"
5274 // modifier that prints the negated value, for use with SUB
5275 // instructions. It is not useful otherwise but is implemented for
5277 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5280 // A constant whose negation can be used as an immediate value in a
5281 // data-processing instruction. This can be used in GCC with an "n"
5282 // modifier that prints the negated value, for use with SUB
5283 // instructions. It is not useful otherwise but is implemented for
5285 if (ARM_AM::getSOImmVal(-CVal) != -1)
5291 if (Subtarget->isThumb()) { // FIXME thumb2
5292 // This must be a multiple of 4 between 0 and 1020, for
5293 // ADD sp + immediate.
5294 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5297 // A power of two or a constant between 0 and 32. This is used in
5298 // GCC for the shift amount on shifted register operands, but it is
5299 // useful in general for any shift amounts.
5300 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5306 if (Subtarget->isThumb()) { // FIXME thumb2
5307 // This must be a constant between 0 and 31, for shift amounts.
5308 if (CVal >= 0 && CVal <= 31)
5314 if (Subtarget->isThumb()) { // FIXME thumb2
5315 // This must be a multiple of 4 between -508 and 508, for
5316 // ADD/SUB sp = sp + immediate.
5317 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5322 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5326 if (Result.getNode()) {
5327 Ops.push_back(Result);
5330 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5334 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5335 // The ARM target isn't yet aware of offsets.
5339 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5340 APInt Imm = FPImm.bitcastToAPInt();
5341 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5342 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5343 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5345 // We can handle 4 bits of mantissa.
5346 // mantissa = (16+UInt(e:f:g:h))/16.
5347 if (Mantissa & 0x7ffff)
5350 if ((Mantissa & 0xf) != Mantissa)
5353 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5354 if (Exp < -3 || Exp > 4)
5356 Exp = ((Exp+3) & 0x7) ^ 4;
5358 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5361 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5362 APInt Imm = FPImm.bitcastToAPInt();
5363 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5364 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5365 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5367 // We can handle 4 bits of mantissa.
5368 // mantissa = (16+UInt(e:f:g:h))/16.
5369 if (Mantissa & 0xffffffffffffLL)
5372 if ((Mantissa & 0xf) != Mantissa)
5375 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5376 if (Exp < -3 || Exp > 4)
5378 Exp = ((Exp+3) & 0x7) ^ 4;
5380 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5383 /// isFPImmLegal - Returns true if the target can instruction select the
5384 /// specified FP immediate natively. If false, the legalizer will
5385 /// materialize the FP immediate as a load from a constant pool.
5386 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5387 if (!Subtarget->hasVFP3())
5390 return ARM::getVFPf32Imm(Imm) != -1;
5392 return ARM::getVFPf64Imm(Imm) != -1;