1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/IRBuilder.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "arm-isel"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
58 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 class ARMCCState : public CCState {
73 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
74 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
76 : CCState(CC, isVarArg, MF, locs, C) {
77 assert(((PC == Call) || (PC == Prologue)) &&
78 "ARMCCState users must specify whether their context is call"
79 "or prologue generation.");
85 // The APCS parameter registers.
86 static const MCPhysReg GPRArgRegs[] = {
87 ARM::R0, ARM::R1, ARM::R2, ARM::R3
90 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
91 MVT PromotedBitwiseVT) {
92 if (VT != PromotedLdStVT) {
93 setOperationAction(ISD::LOAD, VT, Promote);
94 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
96 setOperationAction(ISD::STORE, VT, Promote);
97 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
100 MVT ElemTy = VT.getVectorElementType();
101 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
102 setOperationAction(ISD::SETCC, VT, Custom);
103 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
105 if (ElemTy == MVT::i32) {
106 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
107 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
108 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
109 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
111 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
112 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
114 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
116 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
117 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
118 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
119 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
120 setOperationAction(ISD::SELECT, VT, Expand);
121 setOperationAction(ISD::SELECT_CC, VT, Expand);
122 setOperationAction(ISD::VSELECT, VT, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT, Custom);
126 setOperationAction(ISD::SRA, VT, Custom);
127 setOperationAction(ISD::SRL, VT, Custom);
130 // Promote all bit-wise operations.
131 if (VT.isInteger() && VT != PromotedBitwiseVT) {
132 setOperationAction(ISD::AND, VT, Promote);
133 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::OR, VT, Promote);
135 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
136 setOperationAction(ISD::XOR, VT, Promote);
137 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT, Expand);
142 setOperationAction(ISD::UDIV, VT, Expand);
143 setOperationAction(ISD::FDIV, VT, Expand);
144 setOperationAction(ISD::SREM, VT, Expand);
145 setOperationAction(ISD::UREM, VT, Expand);
146 setOperationAction(ISD::FREM, VT, Expand);
149 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
150 addRegisterClass(VT, &ARM::DPRRegClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
155 addRegisterClass(VT, &ARM::DPairRegClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
160 if (TT.isOSBinFormatMachO())
161 return new TargetLoweringObjectFileMachO();
162 if (TT.isOSWindows())
163 return new TargetLoweringObjectFileCOFF();
164 return new ARMElfTargetObjectFile();
167 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
168 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
169 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 RegInfo = TM.getSubtargetImpl()->getRegisterInfo();
171 Itins = TM.getSubtargetImpl()->getInstrItineraryData();
173 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
175 if (Subtarget->isTargetMachO()) {
176 // Uses VFP for Thumb libfuncs if available.
177 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
178 Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {
179 // Single-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
181 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
182 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
183 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
185 // Double-precision floating-point arithmetic.
186 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
187 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
188 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
189 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
191 // Single-precision comparisons.
192 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
193 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
194 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
195 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
196 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
197 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
198 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
199 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
201 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
210 // Double-precision comparisons.
211 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
212 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
213 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
214 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
215 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
216 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
217 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
218 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
220 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
223 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
224 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
225 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
229 // Floating-point to integer conversions.
230 // i64 conversions are done via library routines even when generating VFP
231 // instructions, so use the same ones.
232 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
233 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
234 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
235 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
237 // Conversions between floating types.
238 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
239 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
241 // Integer to floating-point conversions.
242 // i64 conversions are done via library routines even when generating VFP
243 // instructions, so use the same ones.
244 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
245 // e.g., __floatunsidf vs. __floatunssidfvfp.
246 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
247 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
248 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
249 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
253 // These libcalls are not available in 32-bit.
254 setLibcallName(RTLIB::SHL_I128, nullptr);
255 setLibcallName(RTLIB::SRL_I128, nullptr);
256 setLibcallName(RTLIB::SRA_I128, nullptr);
258 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
259 !Subtarget->isTargetWindows()) {
260 static const struct {
261 const RTLIB::Libcall Op;
262 const char * const Name;
263 const CallingConv::ID CC;
264 const ISD::CondCode Cond;
266 // Double-precision floating-point arithmetic helper functions
267 // RTABI chapter 4.1.2, Table 2
268 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
269 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
270 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
271 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
273 // Double-precision floating-point comparison helper functions
274 // RTABI chapter 4.1.2, Table 3
275 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
276 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
277 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
278 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
279 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
280 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
281 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
282 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
284 // Single-precision floating-point arithmetic helper functions
285 // RTABI chapter 4.1.2, Table 4
286 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
287 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
288 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
289 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
291 // Single-precision floating-point comparison helper functions
292 // RTABI chapter 4.1.2, Table 5
293 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
294 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
295 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
296 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
297 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
298 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
299 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
300 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
302 // Floating-point to integer conversions.
303 // RTABI chapter 4.1.2, Table 6
304 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
306 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
307 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
309 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
310 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
313 // Conversions between floating types.
314 // RTABI chapter 4.1.2, Table 7
315 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
316 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 // Integer to floating-point conversions.
320 // RTABI chapter 4.1.2, Table 8
321 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
323 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
324 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
326 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
327 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
328 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
330 // Long long helper functions
331 // RTABI chapter 4.2, Table 9
332 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 // Integer division functions
338 // RTABI chapter 4.3.1
339 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
342 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
345 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
346 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349 // RTABI chapter 4.3.4
350 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
352 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
355 for (const auto &LC : LibraryCalls) {
356 setLibcallName(LC.Op, LC.Name);
357 setLibcallCallingConv(LC.Op, LC.CC);
358 if (LC.Cond != ISD::SETCC_INVALID)
359 setCmpLibcallCC(LC.Op, LC.Cond);
363 if (Subtarget->isTargetWindows()) {
364 static const struct {
365 const RTLIB::Libcall Op;
366 const char * const Name;
367 const CallingConv::ID CC;
369 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
370 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
371 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
372 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
373 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
374 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
375 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
376 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
379 for (const auto &LC : LibraryCalls) {
380 setLibcallName(LC.Op, LC.Name);
381 setLibcallCallingConv(LC.Op, LC.CC);
385 // Use divmod compiler-rt calls for iOS 5.0 and later.
386 if (Subtarget->getTargetTriple().isiOS() &&
387 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
388 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
389 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
392 // The half <-> float conversion functions are always soft-float, but are
393 // needed for some targets which use a hard-float calling convention by
395 if (Subtarget->isAAPCS_ABI()) {
396 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
400 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
401 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
402 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
405 if (Subtarget->isThumb1Only())
406 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
408 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
409 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
410 !Subtarget->isThumb1Only()) {
411 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
412 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
415 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
416 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
417 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
418 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
419 setTruncStoreAction((MVT::SimpleValueType)VT,
420 (MVT::SimpleValueType)InnerVT, Expand);
421 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
422 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
423 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
425 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
426 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
427 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
428 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
430 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
433 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
434 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
436 if (Subtarget->hasNEON()) {
437 addDRTypeForNEON(MVT::v2f32);
438 addDRTypeForNEON(MVT::v8i8);
439 addDRTypeForNEON(MVT::v4i16);
440 addDRTypeForNEON(MVT::v2i32);
441 addDRTypeForNEON(MVT::v1i64);
443 addQRTypeForNEON(MVT::v4f32);
444 addQRTypeForNEON(MVT::v2f64);
445 addQRTypeForNEON(MVT::v16i8);
446 addQRTypeForNEON(MVT::v8i16);
447 addQRTypeForNEON(MVT::v4i32);
448 addQRTypeForNEON(MVT::v2i64);
450 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
451 // neither Neon nor VFP support any arithmetic operations on it.
452 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
453 // supported for v4f32.
454 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
455 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
456 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
457 // FIXME: Code duplication: FDIV and FREM are expanded always, see
458 // ARMTargetLowering::addTypeForNEON method for details.
459 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
460 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
461 // FIXME: Create unittest.
462 // In another words, find a way when "copysign" appears in DAG with vector
464 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
465 // FIXME: Code duplication: SETCC has custom operation action, see
466 // ARMTargetLowering::addTypeForNEON method for details.
467 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
468 // FIXME: Create unittest for FNEG and for FABS.
469 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
470 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
471 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
472 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
473 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
474 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
475 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
476 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
477 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
478 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
479 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
480 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
481 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
482 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
483 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
484 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
485 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
486 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
487 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
489 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
490 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
491 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
492 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
493 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
494 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
495 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
496 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
497 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
498 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
499 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
500 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
501 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
502 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
503 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
505 // Mark v2f32 intrinsics.
506 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
507 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
508 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
509 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
510 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
511 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
512 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
513 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
514 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
515 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
516 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
517 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
518 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
519 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
520 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
522 // Neon does not support some operations on v1i64 and v2i64 types.
523 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
524 // Custom handling for some quad-vector types to detect VMULL.
525 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
526 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
528 // Custom handling for some vector types to avoid expensive expansions
529 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
530 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
531 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
532 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
533 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
534 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
535 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
536 // a destination type that is wider than the source, and nor does
537 // it have a FP_TO_[SU]INT instruction with a narrower destination than
539 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
540 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
541 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
542 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
544 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
545 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
547 // NEON does not have single instruction CTPOP for vectors with element
548 // types wider than 8-bits. However, custom lowering can leverage the
549 // v8i8/v16i8 vcnt instruction.
550 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
551 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
552 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
553 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
555 // NEON only has FMA instructions as of VFP4.
556 if (!Subtarget->hasVFP4()) {
557 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
558 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
561 setTargetDAGCombine(ISD::INTRINSIC_VOID);
562 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
563 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
564 setTargetDAGCombine(ISD::SHL);
565 setTargetDAGCombine(ISD::SRL);
566 setTargetDAGCombine(ISD::SRA);
567 setTargetDAGCombine(ISD::SIGN_EXTEND);
568 setTargetDAGCombine(ISD::ZERO_EXTEND);
569 setTargetDAGCombine(ISD::ANY_EXTEND);
570 setTargetDAGCombine(ISD::SELECT_CC);
571 setTargetDAGCombine(ISD::BUILD_VECTOR);
572 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
573 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
574 setTargetDAGCombine(ISD::STORE);
575 setTargetDAGCombine(ISD::FP_TO_SINT);
576 setTargetDAGCombine(ISD::FP_TO_UINT);
577 setTargetDAGCombine(ISD::FDIV);
579 // It is legal to extload from v4i8 to v4i16 or v4i32.
580 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
581 MVT::v4i16, MVT::v2i16,
583 for (unsigned i = 0; i < 6; ++i) {
584 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
585 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
586 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
590 // ARM and Thumb2 support UMLAL/SMLAL.
591 if (!Subtarget->isThumb1Only())
592 setTargetDAGCombine(ISD::ADDC);
594 if (Subtarget->isFPOnlySP()) {
595 // When targetting a floating-point unit with only single-precision
596 // operations, f64 is legal for the few double-precision instructions which
597 // are present However, no double-precision operations other than moves,
598 // loads and stores are provided by the hardware.
599 setOperationAction(ISD::FADD, MVT::f64, Expand);
600 setOperationAction(ISD::FSUB, MVT::f64, Expand);
601 setOperationAction(ISD::FMUL, MVT::f64, Expand);
602 setOperationAction(ISD::FMA, MVT::f64, Expand);
603 setOperationAction(ISD::FDIV, MVT::f64, Expand);
604 setOperationAction(ISD::FREM, MVT::f64, Expand);
605 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
606 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
607 setOperationAction(ISD::FNEG, MVT::f64, Expand);
608 setOperationAction(ISD::FABS, MVT::f64, Expand);
609 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
610 setOperationAction(ISD::FSIN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOS, MVT::f64, Expand);
612 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
613 setOperationAction(ISD::FPOW, MVT::f64, Expand);
614 setOperationAction(ISD::FLOG, MVT::f64, Expand);
615 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
616 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
617 setOperationAction(ISD::FEXP, MVT::f64, Expand);
618 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
619 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
620 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
621 setOperationAction(ISD::FRINT, MVT::f64, Expand);
622 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
623 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
624 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
625 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
628 computeRegisterProperties();
630 // ARM does not have floating-point extending loads.
631 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
632 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
634 // ... or truncating stores
635 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
636 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
637 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
639 // ARM does not have i1 sign extending load.
640 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
642 // ARM supports all 4 flavors of integer indexed load / store.
643 if (!Subtarget->isThumb1Only()) {
644 for (unsigned im = (unsigned)ISD::PRE_INC;
645 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
646 setIndexedLoadAction(im, MVT::i1, Legal);
647 setIndexedLoadAction(im, MVT::i8, Legal);
648 setIndexedLoadAction(im, MVT::i16, Legal);
649 setIndexedLoadAction(im, MVT::i32, Legal);
650 setIndexedStoreAction(im, MVT::i1, Legal);
651 setIndexedStoreAction(im, MVT::i8, Legal);
652 setIndexedStoreAction(im, MVT::i16, Legal);
653 setIndexedStoreAction(im, MVT::i32, Legal);
657 setOperationAction(ISD::SADDO, MVT::i32, Custom);
658 setOperationAction(ISD::UADDO, MVT::i32, Custom);
659 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
660 setOperationAction(ISD::USUBO, MVT::i32, Custom);
662 // i64 operation support.
663 setOperationAction(ISD::MUL, MVT::i64, Expand);
664 setOperationAction(ISD::MULHU, MVT::i32, Expand);
665 if (Subtarget->isThumb1Only()) {
666 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
667 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
669 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
670 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
671 setOperationAction(ISD::MULHS, MVT::i32, Expand);
673 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
674 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
675 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
676 setOperationAction(ISD::SRL, MVT::i64, Custom);
677 setOperationAction(ISD::SRA, MVT::i64, Custom);
679 if (!Subtarget->isThumb1Only()) {
680 // FIXME: We should do this for Thumb1 as well.
681 setOperationAction(ISD::ADDC, MVT::i32, Custom);
682 setOperationAction(ISD::ADDE, MVT::i32, Custom);
683 setOperationAction(ISD::SUBC, MVT::i32, Custom);
684 setOperationAction(ISD::SUBE, MVT::i32, Custom);
687 // ARM does not have ROTL.
688 setOperationAction(ISD::ROTL, MVT::i32, Expand);
689 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
690 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
691 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
692 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
694 // These just redirect to CTTZ and CTLZ on ARM.
695 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
696 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
698 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
700 // Only ARMv6 has BSWAP.
701 if (!Subtarget->hasV6Ops())
702 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
704 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
705 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
706 // These are expanded into libcalls if the cpu doesn't have HW divider.
707 setOperationAction(ISD::SDIV, MVT::i32, Expand);
708 setOperationAction(ISD::UDIV, MVT::i32, Expand);
711 // FIXME: Also set divmod for SREM on EABI
712 setOperationAction(ISD::SREM, MVT::i32, Expand);
713 setOperationAction(ISD::UREM, MVT::i32, Expand);
714 // Register based DivRem for AEABI (RTABI 4.2)
715 if (Subtarget->isTargetAEABI()) {
716 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
717 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
718 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
719 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
720 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
721 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
722 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
723 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
725 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
726 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
727 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
728 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
729 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
730 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
731 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
732 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
734 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
735 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
737 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
738 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
741 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
742 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
743 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
744 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
745 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
747 setOperationAction(ISD::TRAP, MVT::Other, Legal);
749 // Use the default implementation.
750 setOperationAction(ISD::VASTART, MVT::Other, Custom);
751 setOperationAction(ISD::VAARG, MVT::Other, Expand);
752 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
753 setOperationAction(ISD::VAEND, MVT::Other, Expand);
754 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
755 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
757 if (!Subtarget->isTargetMachO()) {
758 // Non-MachO platforms may return values in these registers via the
759 // personality function.
760 setExceptionPointerRegister(ARM::R0);
761 setExceptionSelectorRegister(ARM::R1);
764 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
765 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
767 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
769 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
770 // the default expansion. If we are targeting a single threaded system,
771 // then set them all for expand so we can lower them later into their
773 if (TM.Options.ThreadModel == ThreadModel::Single)
774 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
775 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
776 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
777 // to ldrex/strex loops already.
778 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
780 // On v8, we have particularly efficient implementations of atomic fences
781 // if they can be combined with nearby atomic loads and stores.
782 if (!Subtarget->hasV8Ops()) {
783 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
784 setInsertFencesForAtomic(true);
787 // If there's anything we can use as a barrier, go through custom lowering
789 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
790 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
792 // Set them all for expansion, which will force libcalls.
793 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
794 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
795 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
796 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
797 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
798 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
799 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
800 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
801 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
802 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
803 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
804 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
805 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
806 // Unordered/Monotonic case.
807 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
808 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
811 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
813 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
814 if (!Subtarget->hasV6Ops()) {
815 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
816 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
818 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
820 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
821 !Subtarget->isThumb1Only()) {
822 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
823 // iff target supports vfp2.
824 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
825 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
828 // We want to custom lower some of our intrinsics.
829 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
830 if (Subtarget->isTargetDarwin()) {
831 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
832 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
833 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
836 setOperationAction(ISD::SETCC, MVT::i32, Expand);
837 setOperationAction(ISD::SETCC, MVT::f32, Expand);
838 setOperationAction(ISD::SETCC, MVT::f64, Expand);
839 setOperationAction(ISD::SELECT, MVT::i32, Custom);
840 setOperationAction(ISD::SELECT, MVT::f32, Custom);
841 setOperationAction(ISD::SELECT, MVT::f64, Custom);
842 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
843 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
844 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
846 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
847 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
848 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
849 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
850 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
852 // We don't support sin/cos/fmod/copysign/pow
853 setOperationAction(ISD::FSIN, MVT::f64, Expand);
854 setOperationAction(ISD::FSIN, MVT::f32, Expand);
855 setOperationAction(ISD::FCOS, MVT::f32, Expand);
856 setOperationAction(ISD::FCOS, MVT::f64, Expand);
857 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
858 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
859 setOperationAction(ISD::FREM, MVT::f64, Expand);
860 setOperationAction(ISD::FREM, MVT::f32, Expand);
861 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
862 !Subtarget->isThumb1Only()) {
863 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
864 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
866 setOperationAction(ISD::FPOW, MVT::f64, Expand);
867 setOperationAction(ISD::FPOW, MVT::f32, Expand);
869 if (!Subtarget->hasVFP4()) {
870 setOperationAction(ISD::FMA, MVT::f64, Expand);
871 setOperationAction(ISD::FMA, MVT::f32, Expand);
874 // Various VFP goodness
875 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
876 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
877 if (Subtarget->hasVFP2()) {
878 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
879 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
880 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
881 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
884 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
885 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
886 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
887 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
890 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
891 if (!Subtarget->hasFP16()) {
892 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
893 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
897 // Combine sin / cos into one node or libcall if possible.
898 if (Subtarget->hasSinCos()) {
899 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
900 setLibcallName(RTLIB::SINCOS_F64, "sincos");
901 if (Subtarget->getTargetTriple().isiOS()) {
902 // For iOS, we don't want to the normal expansion of a libcall to
903 // sincos. We want to issue a libcall to __sincos_stret.
904 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
905 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
909 // FP-ARMv8 implements a lot of rounding-like FP operations.
910 if (Subtarget->hasFPARMv8()) {
911 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
912 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
913 setOperationAction(ISD::FROUND, MVT::f32, Legal);
914 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
915 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
916 setOperationAction(ISD::FRINT, MVT::f32, Legal);
917 if (!Subtarget->isFPOnlySP()) {
918 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
919 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
920 setOperationAction(ISD::FROUND, MVT::f64, Legal);
921 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
922 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
923 setOperationAction(ISD::FRINT, MVT::f64, Legal);
926 // We have target-specific dag combine patterns for the following nodes:
927 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
928 setTargetDAGCombine(ISD::ADD);
929 setTargetDAGCombine(ISD::SUB);
930 setTargetDAGCombine(ISD::MUL);
931 setTargetDAGCombine(ISD::AND);
932 setTargetDAGCombine(ISD::OR);
933 setTargetDAGCombine(ISD::XOR);
935 if (Subtarget->hasV6Ops())
936 setTargetDAGCombine(ISD::SRL);
938 setStackPointerRegisterToSaveRestore(ARM::SP);
940 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
941 !Subtarget->hasVFP2())
942 setSchedulingPreference(Sched::RegPressure);
944 setSchedulingPreference(Sched::Hybrid);
946 //// temporary - rewrite interface to use type
947 MaxStoresPerMemset = 8;
948 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
949 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
950 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
951 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
952 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
954 // On ARM arguments smaller than 4 bytes are extended, so all arguments
955 // are at least 4 bytes aligned.
956 setMinStackArgumentAlignment(4);
958 // Prefer likely predicted branches to selects on out-of-order cores.
959 PredictableSelectIsExpensive = Subtarget->isLikeA9();
961 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
964 // FIXME: It might make sense to define the representative register class as the
965 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
966 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
967 // SPR's representative would be DPR_VFP2. This should work well if register
968 // pressure tracking were modified such that a register use would increment the
969 // pressure of the register class's representative and all of it's super
970 // classes' representatives transitively. We have not implemented this because
971 // of the difficulty prior to coalescing of modeling operand register classes
972 // due to the common occurrence of cross class copies and subregister insertions
974 std::pair<const TargetRegisterClass*, uint8_t>
975 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
976 const TargetRegisterClass *RRC = nullptr;
978 switch (VT.SimpleTy) {
980 return TargetLowering::findRepresentativeClass(VT);
981 // Use DPR as representative register class for all floating point
982 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
983 // the cost is 1 for both f32 and f64.
984 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
985 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
986 RRC = &ARM::DPRRegClass;
987 // When NEON is used for SP, only half of the register file is available
988 // because operations that define both SP and DP results will be constrained
989 // to the VFP2 class (D0-D15). We currently model this constraint prior to
990 // coalescing by double-counting the SP regs. See the FIXME above.
991 if (Subtarget->useNEONForSinglePrecisionFP())
994 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
995 case MVT::v4f32: case MVT::v2f64:
996 RRC = &ARM::DPRRegClass;
1000 RRC = &ARM::DPRRegClass;
1004 RRC = &ARM::DPRRegClass;
1008 return std::make_pair(RRC, Cost);
1011 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1013 default: return nullptr;
1014 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1015 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1016 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1017 case ARMISD::CALL: return "ARMISD::CALL";
1018 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1019 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1020 case ARMISD::tCALL: return "ARMISD::tCALL";
1021 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1022 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1023 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1024 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1025 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1026 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1027 case ARMISD::CMP: return "ARMISD::CMP";
1028 case ARMISD::CMN: return "ARMISD::CMN";
1029 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1030 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1031 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1032 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1033 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1035 case ARMISD::CMOV: return "ARMISD::CMOV";
1037 case ARMISD::RBIT: return "ARMISD::RBIT";
1039 case ARMISD::FTOSI: return "ARMISD::FTOSI";
1040 case ARMISD::FTOUI: return "ARMISD::FTOUI";
1041 case ARMISD::SITOF: return "ARMISD::SITOF";
1042 case ARMISD::UITOF: return "ARMISD::UITOF";
1044 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1045 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1046 case ARMISD::RRX: return "ARMISD::RRX";
1048 case ARMISD::ADDC: return "ARMISD::ADDC";
1049 case ARMISD::ADDE: return "ARMISD::ADDE";
1050 case ARMISD::SUBC: return "ARMISD::SUBC";
1051 case ARMISD::SUBE: return "ARMISD::SUBE";
1053 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1054 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1056 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1057 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1059 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1061 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1063 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1065 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1067 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1069 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1071 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1072 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1073 case ARMISD::VCGE: return "ARMISD::VCGE";
1074 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1075 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1076 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1077 case ARMISD::VCGT: return "ARMISD::VCGT";
1078 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1079 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1080 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1081 case ARMISD::VTST: return "ARMISD::VTST";
1083 case ARMISD::VSHL: return "ARMISD::VSHL";
1084 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1085 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1086 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1087 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1088 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1089 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1090 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1091 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1092 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1093 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1094 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1095 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1096 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1097 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1098 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1099 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1100 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1101 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1102 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1103 case ARMISD::VDUP: return "ARMISD::VDUP";
1104 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1105 case ARMISD::VEXT: return "ARMISD::VEXT";
1106 case ARMISD::VREV64: return "ARMISD::VREV64";
1107 case ARMISD::VREV32: return "ARMISD::VREV32";
1108 case ARMISD::VREV16: return "ARMISD::VREV16";
1109 case ARMISD::VZIP: return "ARMISD::VZIP";
1110 case ARMISD::VUZP: return "ARMISD::VUZP";
1111 case ARMISD::VTRN: return "ARMISD::VTRN";
1112 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1113 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1114 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1115 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1116 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1117 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1118 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1119 case ARMISD::FMAX: return "ARMISD::FMAX";
1120 case ARMISD::FMIN: return "ARMISD::FMIN";
1121 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1122 case ARMISD::VMINNM: return "ARMISD::VMIN";
1123 case ARMISD::BFI: return "ARMISD::BFI";
1124 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1125 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1126 case ARMISD::VBSL: return "ARMISD::VBSL";
1127 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1128 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1129 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1130 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1131 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1132 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1133 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1134 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1135 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1136 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1137 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1138 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1139 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1140 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1141 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1142 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1143 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1144 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1145 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1146 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1150 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1151 if (!VT.isVector()) return getPointerTy();
1152 return VT.changeVectorElementTypeToInteger();
1155 /// getRegClassFor - Return the register class that should be used for the
1156 /// specified value type.
1157 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1158 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1159 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1160 // load / store 4 to 8 consecutive D registers.
1161 if (Subtarget->hasNEON()) {
1162 if (VT == MVT::v4i64)
1163 return &ARM::QQPRRegClass;
1164 if (VT == MVT::v8i64)
1165 return &ARM::QQQQPRRegClass;
1167 return TargetLowering::getRegClassFor(VT);
1170 // Create a fast isel object.
1172 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1173 const TargetLibraryInfo *libInfo) const {
1174 return ARM::createFastISel(funcInfo, libInfo);
1177 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1178 /// be used for loads / stores from the global.
1179 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1180 return (Subtarget->isThumb1Only() ? 127 : 4095);
1183 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1184 unsigned NumVals = N->getNumValues();
1186 return Sched::RegPressure;
1188 for (unsigned i = 0; i != NumVals; ++i) {
1189 EVT VT = N->getValueType(i);
1190 if (VT == MVT::Glue || VT == MVT::Other)
1192 if (VT.isFloatingPoint() || VT.isVector())
1196 if (!N->isMachineOpcode())
1197 return Sched::RegPressure;
1199 // Load are scheduled for latency even if there instruction itinerary
1200 // is not available.
1201 const TargetInstrInfo *TII =
1202 getTargetMachine().getSubtargetImpl()->getInstrInfo();
1203 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1205 if (MCID.getNumDefs() == 0)
1206 return Sched::RegPressure;
1207 if (!Itins->isEmpty() &&
1208 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1211 return Sched::RegPressure;
1214 //===----------------------------------------------------------------------===//
1216 //===----------------------------------------------------------------------===//
1218 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1219 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1221 default: llvm_unreachable("Unknown condition code!");
1222 case ISD::SETNE: return ARMCC::NE;
1223 case ISD::SETEQ: return ARMCC::EQ;
1224 case ISD::SETGT: return ARMCC::GT;
1225 case ISD::SETGE: return ARMCC::GE;
1226 case ISD::SETLT: return ARMCC::LT;
1227 case ISD::SETLE: return ARMCC::LE;
1228 case ISD::SETUGT: return ARMCC::HI;
1229 case ISD::SETUGE: return ARMCC::HS;
1230 case ISD::SETULT: return ARMCC::LO;
1231 case ISD::SETULE: return ARMCC::LS;
1235 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1236 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1237 ARMCC::CondCodes &CondCode2) {
1238 CondCode2 = ARMCC::AL;
1240 default: llvm_unreachable("Unknown FP condition!");
1242 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1244 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1246 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1247 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1248 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1249 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1250 case ISD::SETO: CondCode = ARMCC::VC; break;
1251 case ISD::SETUO: CondCode = ARMCC::VS; break;
1252 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1253 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1254 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1256 case ISD::SETULT: CondCode = ARMCC::LT; break;
1258 case ISD::SETULE: CondCode = ARMCC::LE; break;
1260 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1264 //===----------------------------------------------------------------------===//
1265 // Calling Convention Implementation
1266 //===----------------------------------------------------------------------===//
1268 #include "ARMGenCallingConv.inc"
1270 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1271 /// account presence of floating point hardware and calling convention
1272 /// limitations, such as support for variadic functions.
1274 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1275 bool isVarArg) const {
1278 llvm_unreachable("Unsupported calling convention");
1279 case CallingConv::ARM_AAPCS:
1280 case CallingConv::ARM_APCS:
1281 case CallingConv::GHC:
1283 case CallingConv::ARM_AAPCS_VFP:
1284 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1285 case CallingConv::C:
1286 if (!Subtarget->isAAPCS_ABI())
1287 return CallingConv::ARM_APCS;
1288 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1289 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1291 return CallingConv::ARM_AAPCS_VFP;
1293 return CallingConv::ARM_AAPCS;
1294 case CallingConv::Fast:
1295 if (!Subtarget->isAAPCS_ABI()) {
1296 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1297 return CallingConv::Fast;
1298 return CallingConv::ARM_APCS;
1299 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1300 return CallingConv::ARM_AAPCS_VFP;
1302 return CallingConv::ARM_AAPCS;
1306 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1307 /// CallingConvention.
1308 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1310 bool isVarArg) const {
1311 switch (getEffectiveCallingConv(CC, isVarArg)) {
1313 llvm_unreachable("Unsupported calling convention");
1314 case CallingConv::ARM_APCS:
1315 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1316 case CallingConv::ARM_AAPCS:
1317 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1318 case CallingConv::ARM_AAPCS_VFP:
1319 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1320 case CallingConv::Fast:
1321 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1322 case CallingConv::GHC:
1323 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1327 /// LowerCallResult - Lower the result values of a call into the
1328 /// appropriate copies out of appropriate physical registers.
1330 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1331 CallingConv::ID CallConv, bool isVarArg,
1332 const SmallVectorImpl<ISD::InputArg> &Ins,
1333 SDLoc dl, SelectionDAG &DAG,
1334 SmallVectorImpl<SDValue> &InVals,
1335 bool isThisReturn, SDValue ThisVal) const {
1337 // Assign locations to each value returned by this call.
1338 SmallVector<CCValAssign, 16> RVLocs;
1339 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1340 *DAG.getContext(), Call);
1341 CCInfo.AnalyzeCallResult(Ins,
1342 CCAssignFnForNode(CallConv, /* Return*/ true,
1345 // Copy all of the result registers out of their specified physreg.
1346 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1347 CCValAssign VA = RVLocs[i];
1349 // Pass 'this' value directly from the argument to return value, to avoid
1350 // reg unit interference
1351 if (i == 0 && isThisReturn) {
1352 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1353 "unexpected return calling convention register assignment");
1354 InVals.push_back(ThisVal);
1359 if (VA.needsCustom()) {
1360 // Handle f64 or half of a v2f64.
1361 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1363 Chain = Lo.getValue(1);
1364 InFlag = Lo.getValue(2);
1365 VA = RVLocs[++i]; // skip ahead to next loc
1366 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1368 Chain = Hi.getValue(1);
1369 InFlag = Hi.getValue(2);
1370 if (!Subtarget->isLittle())
1372 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1374 if (VA.getLocVT() == MVT::v2f64) {
1375 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1376 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1377 DAG.getConstant(0, MVT::i32));
1379 VA = RVLocs[++i]; // skip ahead to next loc
1380 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1381 Chain = Lo.getValue(1);
1382 InFlag = Lo.getValue(2);
1383 VA = RVLocs[++i]; // skip ahead to next loc
1384 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1385 Chain = Hi.getValue(1);
1386 InFlag = Hi.getValue(2);
1387 if (!Subtarget->isLittle())
1389 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1390 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1391 DAG.getConstant(1, MVT::i32));
1394 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1396 Chain = Val.getValue(1);
1397 InFlag = Val.getValue(2);
1400 switch (VA.getLocInfo()) {
1401 default: llvm_unreachable("Unknown loc info!");
1402 case CCValAssign::Full: break;
1403 case CCValAssign::BCvt:
1404 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1408 InVals.push_back(Val);
1414 /// LowerMemOpCallTo - Store the argument to the stack.
1416 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1417 SDValue StackPtr, SDValue Arg,
1418 SDLoc dl, SelectionDAG &DAG,
1419 const CCValAssign &VA,
1420 ISD::ArgFlagsTy Flags) const {
1421 unsigned LocMemOffset = VA.getLocMemOffset();
1422 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1423 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1424 return DAG.getStore(Chain, dl, Arg, PtrOff,
1425 MachinePointerInfo::getStack(LocMemOffset),
1429 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1430 SDValue Chain, SDValue &Arg,
1431 RegsToPassVector &RegsToPass,
1432 CCValAssign &VA, CCValAssign &NextVA,
1434 SmallVectorImpl<SDValue> &MemOpChains,
1435 ISD::ArgFlagsTy Flags) const {
1437 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1438 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1439 unsigned id = Subtarget->isLittle() ? 0 : 1;
1440 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1442 if (NextVA.isRegLoc())
1443 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1445 assert(NextVA.isMemLoc());
1446 if (!StackPtr.getNode())
1447 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1449 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1455 /// LowerCall - Lowering a call into a callseq_start <-
1456 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1459 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1460 SmallVectorImpl<SDValue> &InVals) const {
1461 SelectionDAG &DAG = CLI.DAG;
1463 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1464 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1465 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1466 SDValue Chain = CLI.Chain;
1467 SDValue Callee = CLI.Callee;
1468 bool &isTailCall = CLI.IsTailCall;
1469 CallingConv::ID CallConv = CLI.CallConv;
1470 bool doesNotRet = CLI.DoesNotReturn;
1471 bool isVarArg = CLI.IsVarArg;
1473 MachineFunction &MF = DAG.getMachineFunction();
1474 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1475 bool isThisReturn = false;
1476 bool isSibCall = false;
1478 // Disable tail calls if they're not supported.
1479 if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
1483 // Check if it's really possible to do a tail call.
1484 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1485 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1486 Outs, OutVals, Ins, DAG);
1487 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1488 report_fatal_error("failed to perform tail call elimination on a call "
1489 "site marked musttail");
1490 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1491 // detected sibcalls.
1498 // Analyze operands of the call, assigning locations to each operand.
1499 SmallVector<CCValAssign, 16> ArgLocs;
1500 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1501 *DAG.getContext(), Call);
1502 CCInfo.AnalyzeCallOperands(Outs,
1503 CCAssignFnForNode(CallConv, /* Return*/ false,
1506 // Get a count of how many bytes are to be pushed on the stack.
1507 unsigned NumBytes = CCInfo.getNextStackOffset();
1509 // For tail calls, memory operands are available in our caller's stack.
1513 // Adjust the stack pointer for the new arguments...
1514 // These operations are automatically eliminated by the prolog/epilog pass
1516 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1519 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1521 RegsToPassVector RegsToPass;
1522 SmallVector<SDValue, 8> MemOpChains;
1524 // Walk the register/memloc assignments, inserting copies/loads. In the case
1525 // of tail call optimization, arguments are handled later.
1526 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1528 ++i, ++realArgIdx) {
1529 CCValAssign &VA = ArgLocs[i];
1530 SDValue Arg = OutVals[realArgIdx];
1531 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1532 bool isByVal = Flags.isByVal();
1534 // Promote the value if needed.
1535 switch (VA.getLocInfo()) {
1536 default: llvm_unreachable("Unknown loc info!");
1537 case CCValAssign::Full: break;
1538 case CCValAssign::SExt:
1539 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1541 case CCValAssign::ZExt:
1542 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1544 case CCValAssign::AExt:
1545 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1547 case CCValAssign::BCvt:
1548 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1552 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1553 if (VA.needsCustom()) {
1554 if (VA.getLocVT() == MVT::v2f64) {
1555 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1556 DAG.getConstant(0, MVT::i32));
1557 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1558 DAG.getConstant(1, MVT::i32));
1560 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1561 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1563 VA = ArgLocs[++i]; // skip ahead to next loc
1564 if (VA.isRegLoc()) {
1565 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1566 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1568 assert(VA.isMemLoc());
1570 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1571 dl, DAG, VA, Flags));
1574 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1575 StackPtr, MemOpChains, Flags);
1577 } else if (VA.isRegLoc()) {
1578 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1579 assert(VA.getLocVT() == MVT::i32 &&
1580 "unexpected calling convention register assignment");
1581 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1582 "unexpected use of 'returned'");
1583 isThisReturn = true;
1585 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1586 } else if (isByVal) {
1587 assert(VA.isMemLoc());
1588 unsigned offset = 0;
1590 // True if this byval aggregate will be split between registers
1592 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1593 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1595 if (CurByValIdx < ByValArgsCount) {
1597 unsigned RegBegin, RegEnd;
1598 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1600 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1602 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1603 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1604 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1605 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1606 MachinePointerInfo(),
1607 false, false, false,
1608 DAG.InferPtrAlignment(AddArg));
1609 MemOpChains.push_back(Load.getValue(1));
1610 RegsToPass.push_back(std::make_pair(j, Load));
1613 // If parameter size outsides register area, "offset" value
1614 // helps us to calculate stack slot for remained part properly.
1615 offset = RegEnd - RegBegin;
1617 CCInfo.nextInRegsParam();
1620 if (Flags.getByValSize() > 4*offset) {
1621 unsigned LocMemOffset = VA.getLocMemOffset();
1622 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1623 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1625 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1626 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1627 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1629 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1631 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1632 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1633 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1636 } else if (!isSibCall) {
1637 assert(VA.isMemLoc());
1639 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1640 dl, DAG, VA, Flags));
1644 if (!MemOpChains.empty())
1645 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1647 // Build a sequence of copy-to-reg nodes chained together with token chain
1648 // and flag operands which copy the outgoing args into the appropriate regs.
1650 // Tail call byval lowering might overwrite argument registers so in case of
1651 // tail call optimization the copies to registers are lowered later.
1653 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1654 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1655 RegsToPass[i].second, InFlag);
1656 InFlag = Chain.getValue(1);
1659 // For tail calls lower the arguments to the 'real' stack slot.
1661 // Force all the incoming stack arguments to be loaded from the stack
1662 // before any new outgoing arguments are stored to the stack, because the
1663 // outgoing stack slots may alias the incoming argument stack slots, and
1664 // the alias isn't otherwise explicit. This is slightly more conservative
1665 // than necessary, because it means that each store effectively depends
1666 // on every argument instead of just those arguments it would clobber.
1668 // Do not flag preceding copytoreg stuff together with the following stuff.
1670 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1671 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1672 RegsToPass[i].second, InFlag);
1673 InFlag = Chain.getValue(1);
1678 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1679 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1680 // node so that legalize doesn't hack it.
1681 bool isDirect = false;
1682 bool isARMFunc = false;
1683 bool isLocalARMFunc = false;
1684 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1686 if (EnableARMLongCalls) {
1687 assert((Subtarget->isTargetWindows() ||
1688 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1689 "long-calls with non-static relocation model!");
1690 // Handle a global address or an external symbol. If it's not one of
1691 // those, the target's already in a register, so we don't need to do
1693 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1694 const GlobalValue *GV = G->getGlobal();
1695 // Create a constant pool entry for the callee address
1696 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1697 ARMConstantPoolValue *CPV =
1698 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1700 // Get the address of the callee into a register
1701 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1702 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1703 Callee = DAG.getLoad(getPointerTy(), dl,
1704 DAG.getEntryNode(), CPAddr,
1705 MachinePointerInfo::getConstantPool(),
1706 false, false, false, 0);
1707 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1708 const char *Sym = S->getSymbol();
1710 // Create a constant pool entry for the callee address
1711 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1712 ARMConstantPoolValue *CPV =
1713 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1714 ARMPCLabelIndex, 0);
1715 // Get the address of the callee into a register
1716 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1717 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1718 Callee = DAG.getLoad(getPointerTy(), dl,
1719 DAG.getEntryNode(), CPAddr,
1720 MachinePointerInfo::getConstantPool(),
1721 false, false, false, 0);
1723 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1724 const GlobalValue *GV = G->getGlobal();
1726 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1727 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1728 getTargetMachine().getRelocationModel() != Reloc::Static;
1729 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1730 // ARM call to a local ARM function is predicable.
1731 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1732 // tBX takes a register source operand.
1733 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1734 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1735 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1736 DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
1737 0, ARMII::MO_NONLAZY));
1738 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
1739 MachinePointerInfo::getGOT(), false, false, true, 0);
1740 } else if (Subtarget->isTargetCOFF()) {
1741 assert(Subtarget->isTargetWindows() &&
1742 "Windows is the only supported COFF target");
1743 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1744 ? ARMII::MO_DLLIMPORT
1745 : ARMII::MO_NO_FLAG;
1746 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1748 if (GV->hasDLLImportStorageClass())
1749 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1750 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1751 Callee), MachinePointerInfo::getGOT(),
1752 false, false, false, 0);
1754 // On ELF targets for PIC code, direct calls should go through the PLT
1755 unsigned OpFlags = 0;
1756 if (Subtarget->isTargetELF() &&
1757 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1758 OpFlags = ARMII::MO_PLT;
1759 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1761 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1763 bool isStub = Subtarget->isTargetMachO() &&
1764 getTargetMachine().getRelocationModel() != Reloc::Static;
1765 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1766 // tBX takes a register source operand.
1767 const char *Sym = S->getSymbol();
1768 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1769 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1770 ARMConstantPoolValue *CPV =
1771 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1772 ARMPCLabelIndex, 4);
1773 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1774 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1775 Callee = DAG.getLoad(getPointerTy(), dl,
1776 DAG.getEntryNode(), CPAddr,
1777 MachinePointerInfo::getConstantPool(),
1778 false, false, false, 0);
1779 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1780 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1781 getPointerTy(), Callee, PICLabel);
1783 unsigned OpFlags = 0;
1784 // On ELF targets for PIC code, direct calls should go through the PLT
1785 if (Subtarget->isTargetELF() &&
1786 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1787 OpFlags = ARMII::MO_PLT;
1788 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1792 // FIXME: handle tail calls differently.
1794 bool HasMinSizeAttr = MF.getFunction()->getAttributes().hasAttribute(
1795 AttributeSet::FunctionIndex, Attribute::MinSize);
1796 if (Subtarget->isThumb()) {
1797 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1798 CallOpc = ARMISD::CALL_NOLINK;
1800 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1802 if (!isDirect && !Subtarget->hasV5TOps())
1803 CallOpc = ARMISD::CALL_NOLINK;
1804 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1805 // Emit regular call when code size is the priority
1807 // "mov lr, pc; b _foo" to avoid confusing the RSP
1808 CallOpc = ARMISD::CALL_NOLINK;
1810 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1813 std::vector<SDValue> Ops;
1814 Ops.push_back(Chain);
1815 Ops.push_back(Callee);
1817 // Add argument registers to the end of the list so that they are known live
1819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1820 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1821 RegsToPass[i].second.getValueType()));
1823 // Add a register mask operand representing the call-preserved registers.
1825 const uint32_t *Mask;
1826 const TargetRegisterInfo *TRI =
1827 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1828 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1830 // For 'this' returns, use the R0-preserving mask if applicable
1831 Mask = ARI->getThisReturnPreservedMask(CallConv);
1833 // Set isThisReturn to false if the calling convention is not one that
1834 // allows 'returned' to be modeled in this way, so LowerCallResult does
1835 // not try to pass 'this' straight through
1836 isThisReturn = false;
1837 Mask = ARI->getCallPreservedMask(CallConv);
1840 Mask = ARI->getCallPreservedMask(CallConv);
1842 assert(Mask && "Missing call preserved mask for calling convention");
1843 Ops.push_back(DAG.getRegisterMask(Mask));
1846 if (InFlag.getNode())
1847 Ops.push_back(InFlag);
1849 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1851 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1853 // Returns a chain and a flag for retval copy to use.
1854 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1855 InFlag = Chain.getValue(1);
1857 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1858 DAG.getIntPtrConstant(0, true), InFlag, dl);
1860 InFlag = Chain.getValue(1);
1862 // Handle result values, copying them out of physregs into vregs that we
1864 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1865 InVals, isThisReturn,
1866 isThisReturn ? OutVals[0] : SDValue());
1869 /// HandleByVal - Every parameter *after* a byval parameter is passed
1870 /// on the stack. Remember the next parameter register to allocate,
1871 /// and then confiscate the rest of the parameter registers to insure
1874 ARMTargetLowering::HandleByVal(
1875 CCState *State, unsigned &size, unsigned Align) const {
1876 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1877 assert((State->getCallOrPrologue() == Prologue ||
1878 State->getCallOrPrologue() == Call) &&
1879 "unhandled ParmContext");
1881 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1882 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1883 unsigned AlignInRegs = Align / 4;
1884 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1885 for (unsigned i = 0; i < Waste; ++i)
1886 reg = State->AllocateReg(GPRArgRegs, 4);
1889 unsigned excess = 4 * (ARM::R4 - reg);
1891 // Special case when NSAA != SP and parameter size greater than size of
1892 // all remained GPR regs. In that case we can't split parameter, we must
1893 // send it to stack. We also must set NCRN to R4, so waste all
1894 // remained registers.
1895 const unsigned NSAAOffset = State->getNextStackOffset();
1896 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1897 while (State->AllocateReg(GPRArgRegs, 4))
1902 // First register for byval parameter is the first register that wasn't
1903 // allocated before this method call, so it would be "reg".
1904 // If parameter is small enough to be saved in range [reg, r4), then
1905 // the end (first after last) register would be reg + param-size-in-regs,
1906 // else parameter would be splitted between registers and stack,
1907 // end register would be r4 in this case.
1908 unsigned ByValRegBegin = reg;
1909 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1910 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1911 // Note, first register is allocated in the beginning of function already,
1912 // allocate remained amount of registers we need.
1913 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1914 State->AllocateReg(GPRArgRegs, 4);
1915 // A byval parameter that is split between registers and memory needs its
1916 // size truncated here.
1917 // In the case where the entire structure fits in registers, we set the
1918 // size in memory to zero.
1927 /// MatchingStackOffset - Return true if the given stack call argument is
1928 /// already available in the same position (relatively) of the caller's
1929 /// incoming argument stack.
1931 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1932 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1933 const TargetInstrInfo *TII) {
1934 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1936 if (Arg.getOpcode() == ISD::CopyFromReg) {
1937 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1938 if (!TargetRegisterInfo::isVirtualRegister(VR))
1940 MachineInstr *Def = MRI->getVRegDef(VR);
1943 if (!Flags.isByVal()) {
1944 if (!TII->isLoadFromStackSlot(Def, FI))
1949 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1950 if (Flags.isByVal())
1951 // ByVal argument is passed in as a pointer but it's now being
1952 // dereferenced. e.g.
1953 // define @foo(%struct.X* %A) {
1954 // tail call @bar(%struct.X* byval %A)
1957 SDValue Ptr = Ld->getBasePtr();
1958 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1961 FI = FINode->getIndex();
1965 assert(FI != INT_MAX);
1966 if (!MFI->isFixedObjectIndex(FI))
1968 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1971 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1972 /// for tail call optimization. Targets which want to do tail call
1973 /// optimization should implement this function.
1975 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1976 CallingConv::ID CalleeCC,
1978 bool isCalleeStructRet,
1979 bool isCallerStructRet,
1980 const SmallVectorImpl<ISD::OutputArg> &Outs,
1981 const SmallVectorImpl<SDValue> &OutVals,
1982 const SmallVectorImpl<ISD::InputArg> &Ins,
1983 SelectionDAG& DAG) const {
1984 const Function *CallerF = DAG.getMachineFunction().getFunction();
1985 CallingConv::ID CallerCC = CallerF->getCallingConv();
1986 bool CCMatch = CallerCC == CalleeCC;
1988 // Look for obvious safe cases to perform tail call optimization that do not
1989 // require ABI changes. This is what gcc calls sibcall.
1991 // Do not sibcall optimize vararg calls unless the call site is not passing
1993 if (isVarArg && !Outs.empty())
1996 // Exception-handling functions need a special set of instructions to indicate
1997 // a return to the hardware. Tail-calling another function would probably
1999 if (CallerF->hasFnAttribute("interrupt"))
2002 // Also avoid sibcall optimization if either caller or callee uses struct
2003 // return semantics.
2004 if (isCalleeStructRet || isCallerStructRet)
2007 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
2008 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2009 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2010 // support in the assembler and linker to be used. This would need to be
2011 // fixed to fully support tail calls in Thumb1.
2013 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2014 // LR. This means if we need to reload LR, it takes an extra instructions,
2015 // which outweighs the value of the tail call; but here we don't know yet
2016 // whether LR is going to be used. Probably the right approach is to
2017 // generate the tail call here and turn it back into CALL/RET in
2018 // emitEpilogue if LR is used.
2020 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2021 // but we need to make sure there are enough registers; the only valid
2022 // registers are the 4 used for parameters. We don't currently do this
2024 if (Subtarget->isThumb1Only())
2027 // Externally-defined functions with weak linkage should not be
2028 // tail-called on ARM when the OS does not support dynamic
2029 // pre-emption of symbols, as the AAELF spec requires normal calls
2030 // to undefined weak functions to be replaced with a NOP or jump to the
2031 // next instruction. The behaviour of branch instructions in this
2032 // situation (as used for tail calls) is implementation-defined, so we
2033 // cannot rely on the linker replacing the tail call with a return.
2034 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2035 const GlobalValue *GV = G->getGlobal();
2036 if (GV->hasExternalWeakLinkage())
2040 // If the calling conventions do not match, then we'd better make sure the
2041 // results are returned in the same way as what the caller expects.
2043 SmallVector<CCValAssign, 16> RVLocs1;
2044 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2045 *DAG.getContext(), Call);
2046 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2048 SmallVector<CCValAssign, 16> RVLocs2;
2049 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2050 *DAG.getContext(), Call);
2051 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2053 if (RVLocs1.size() != RVLocs2.size())
2055 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2056 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2058 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2060 if (RVLocs1[i].isRegLoc()) {
2061 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2064 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2070 // If Caller's vararg or byval argument has been split between registers and
2071 // stack, do not perform tail call, since part of the argument is in caller's
2073 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2074 getInfo<ARMFunctionInfo>();
2075 if (AFI_Caller->getArgRegsSaveSize())
2078 // If the callee takes no arguments then go on to check the results of the
2080 if (!Outs.empty()) {
2081 // Check if stack adjustment is needed. For now, do not do this if any
2082 // argument is passed on the stack.
2083 SmallVector<CCValAssign, 16> ArgLocs;
2084 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2085 *DAG.getContext(), Call);
2086 CCInfo.AnalyzeCallOperands(Outs,
2087 CCAssignFnForNode(CalleeCC, false, isVarArg));
2088 if (CCInfo.getNextStackOffset()) {
2089 MachineFunction &MF = DAG.getMachineFunction();
2091 // Check if the arguments are already laid out in the right way as
2092 // the caller's fixed stack objects.
2093 MachineFrameInfo *MFI = MF.getFrameInfo();
2094 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2095 const TargetInstrInfo *TII =
2096 getTargetMachine().getSubtargetImpl()->getInstrInfo();
2097 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2099 ++i, ++realArgIdx) {
2100 CCValAssign &VA = ArgLocs[i];
2101 EVT RegVT = VA.getLocVT();
2102 SDValue Arg = OutVals[realArgIdx];
2103 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2104 if (VA.getLocInfo() == CCValAssign::Indirect)
2106 if (VA.needsCustom()) {
2107 // f64 and vector types are split into multiple registers or
2108 // register/stack-slot combinations. The types will not match
2109 // the registers; give up on memory f64 refs until we figure
2110 // out what to do about this.
2113 if (!ArgLocs[++i].isRegLoc())
2115 if (RegVT == MVT::v2f64) {
2116 if (!ArgLocs[++i].isRegLoc())
2118 if (!ArgLocs[++i].isRegLoc())
2121 } else if (!VA.isRegLoc()) {
2122 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2134 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2135 MachineFunction &MF, bool isVarArg,
2136 const SmallVectorImpl<ISD::OutputArg> &Outs,
2137 LLVMContext &Context) const {
2138 SmallVector<CCValAssign, 16> RVLocs;
2139 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2140 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2144 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2145 SDLoc DL, SelectionDAG &DAG) {
2146 const MachineFunction &MF = DAG.getMachineFunction();
2147 const Function *F = MF.getFunction();
2149 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2151 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2152 // version of the "preferred return address". These offsets affect the return
2153 // instruction if this is a return from PL1 without hypervisor extensions.
2154 // IRQ/FIQ: +4 "subs pc, lr, #4"
2155 // SWI: 0 "subs pc, lr, #0"
2156 // ABORT: +4 "subs pc, lr, #4"
2157 // UNDEF: +4/+2 "subs pc, lr, #0"
2158 // UNDEF varies depending on where the exception came from ARM or Thumb
2159 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2162 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2165 else if (IntKind == "SWI" || IntKind == "UNDEF")
2168 report_fatal_error("Unsupported interrupt attribute. If present, value "
2169 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2171 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2173 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2177 ARMTargetLowering::LowerReturn(SDValue Chain,
2178 CallingConv::ID CallConv, bool isVarArg,
2179 const SmallVectorImpl<ISD::OutputArg> &Outs,
2180 const SmallVectorImpl<SDValue> &OutVals,
2181 SDLoc dl, SelectionDAG &DAG) const {
2183 // CCValAssign - represent the assignment of the return value to a location.
2184 SmallVector<CCValAssign, 16> RVLocs;
2186 // CCState - Info about the registers and stack slots.
2187 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2188 *DAG.getContext(), Call);
2190 // Analyze outgoing return values.
2191 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2195 SmallVector<SDValue, 4> RetOps;
2196 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2197 bool isLittleEndian = Subtarget->isLittle();
2199 MachineFunction &MF = DAG.getMachineFunction();
2200 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2201 AFI->setReturnRegsCount(RVLocs.size());
2203 // Copy the result values into the output registers.
2204 for (unsigned i = 0, realRVLocIdx = 0;
2206 ++i, ++realRVLocIdx) {
2207 CCValAssign &VA = RVLocs[i];
2208 assert(VA.isRegLoc() && "Can only return in registers!");
2210 SDValue Arg = OutVals[realRVLocIdx];
2212 switch (VA.getLocInfo()) {
2213 default: llvm_unreachable("Unknown loc info!");
2214 case CCValAssign::Full: break;
2215 case CCValAssign::BCvt:
2216 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2220 if (VA.needsCustom()) {
2221 if (VA.getLocVT() == MVT::v2f64) {
2222 // Extract the first half and return it in two registers.
2223 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2224 DAG.getConstant(0, MVT::i32));
2225 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2226 DAG.getVTList(MVT::i32, MVT::i32), Half);
2228 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2229 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2231 Flag = Chain.getValue(1);
2232 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2233 VA = RVLocs[++i]; // skip ahead to next loc
2234 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2235 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2237 Flag = Chain.getValue(1);
2238 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2239 VA = RVLocs[++i]; // skip ahead to next loc
2241 // Extract the 2nd half and fall through to handle it as an f64 value.
2242 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2243 DAG.getConstant(1, MVT::i32));
2245 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2247 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2248 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2249 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2250 fmrrd.getValue(isLittleEndian ? 0 : 1),
2252 Flag = Chain.getValue(1);
2253 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2254 VA = RVLocs[++i]; // skip ahead to next loc
2255 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2256 fmrrd.getValue(isLittleEndian ? 1 : 0),
2259 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2261 // Guarantee that all emitted copies are
2262 // stuck together, avoiding something bad.
2263 Flag = Chain.getValue(1);
2264 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2267 // Update chain and glue.
2270 RetOps.push_back(Flag);
2272 // CPUs which aren't M-class use a special sequence to return from
2273 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2274 // though we use "subs pc, lr, #N").
2276 // M-class CPUs actually use a normal return sequence with a special
2277 // (hardware-provided) value in LR, so the normal code path works.
2278 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2279 !Subtarget->isMClass()) {
2280 if (Subtarget->isThumb1Only())
2281 report_fatal_error("interrupt attribute is not supported in Thumb1");
2282 return LowerInterruptReturn(RetOps, dl, DAG);
2285 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2288 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2289 if (N->getNumValues() != 1)
2291 if (!N->hasNUsesOfValue(1, 0))
2294 SDValue TCChain = Chain;
2295 SDNode *Copy = *N->use_begin();
2296 if (Copy->getOpcode() == ISD::CopyToReg) {
2297 // If the copy has a glue operand, we conservatively assume it isn't safe to
2298 // perform a tail call.
2299 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2301 TCChain = Copy->getOperand(0);
2302 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2303 SDNode *VMov = Copy;
2304 // f64 returned in a pair of GPRs.
2305 SmallPtrSet<SDNode*, 2> Copies;
2306 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2308 if (UI->getOpcode() != ISD::CopyToReg)
2312 if (Copies.size() > 2)
2315 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2317 SDValue UseChain = UI->getOperand(0);
2318 if (Copies.count(UseChain.getNode()))
2322 // We are at the top of this chain.
2323 // If the copy has a glue operand, we conservatively assume it
2324 // isn't safe to perform a tail call.
2325 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2331 } else if (Copy->getOpcode() == ISD::BITCAST) {
2332 // f32 returned in a single GPR.
2333 if (!Copy->hasOneUse())
2335 Copy = *Copy->use_begin();
2336 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2338 // If the copy has a glue operand, we conservatively assume it isn't safe to
2339 // perform a tail call.
2340 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2342 TCChain = Copy->getOperand(0);
2347 bool HasRet = false;
2348 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2350 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2351 UI->getOpcode() != ARMISD::INTRET_FLAG)
2363 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2364 if (!Subtarget->supportsTailCall())
2367 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2370 return !Subtarget->isThumb1Only();
2373 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2374 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2375 // one of the above mentioned nodes. It has to be wrapped because otherwise
2376 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2377 // be used to form addressing mode. These wrapped nodes will be selected
2379 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2380 EVT PtrVT = Op.getValueType();
2381 // FIXME there is no actual debug info here
2383 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2385 if (CP->isMachineConstantPoolEntry())
2386 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2387 CP->getAlignment());
2389 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2390 CP->getAlignment());
2391 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2394 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2395 return MachineJumpTableInfo::EK_Inline;
2398 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2399 SelectionDAG &DAG) const {
2400 MachineFunction &MF = DAG.getMachineFunction();
2401 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2402 unsigned ARMPCLabelIndex = 0;
2404 EVT PtrVT = getPointerTy();
2405 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2406 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2408 if (RelocM == Reloc::Static) {
2409 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2411 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2412 ARMPCLabelIndex = AFI->createPICLabelUId();
2413 ARMConstantPoolValue *CPV =
2414 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2415 ARMCP::CPBlockAddress, PCAdj);
2416 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2418 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2419 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2420 MachinePointerInfo::getConstantPool(),
2421 false, false, false, 0);
2422 if (RelocM == Reloc::Static)
2424 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2425 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2428 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2430 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2431 SelectionDAG &DAG) const {
2433 EVT PtrVT = getPointerTy();
2434 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2435 MachineFunction &MF = DAG.getMachineFunction();
2436 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2437 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2438 ARMConstantPoolValue *CPV =
2439 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2440 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2441 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2442 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2443 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2444 MachinePointerInfo::getConstantPool(),
2445 false, false, false, 0);
2446 SDValue Chain = Argument.getValue(1);
2448 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2449 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2451 // call __tls_get_addr.
2454 Entry.Node = Argument;
2455 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2456 Args.push_back(Entry);
2458 // FIXME: is there useful debug info available here?
2459 TargetLowering::CallLoweringInfo CLI(DAG);
2460 CLI.setDebugLoc(dl).setChain(Chain)
2461 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2462 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2465 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2466 return CallResult.first;
2469 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2470 // "local exec" model.
2472 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2474 TLSModel::Model model) const {
2475 const GlobalValue *GV = GA->getGlobal();
2478 SDValue Chain = DAG.getEntryNode();
2479 EVT PtrVT = getPointerTy();
2480 // Get the Thread Pointer
2481 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2483 if (model == TLSModel::InitialExec) {
2484 MachineFunction &MF = DAG.getMachineFunction();
2485 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2486 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2487 // Initial exec model.
2488 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2489 ARMConstantPoolValue *CPV =
2490 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2491 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2493 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2494 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2495 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2496 MachinePointerInfo::getConstantPool(),
2497 false, false, false, 0);
2498 Chain = Offset.getValue(1);
2500 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2501 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2503 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2504 MachinePointerInfo::getConstantPool(),
2505 false, false, false, 0);
2508 assert(model == TLSModel::LocalExec);
2509 ARMConstantPoolValue *CPV =
2510 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2511 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2512 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2513 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2514 MachinePointerInfo::getConstantPool(),
2515 false, false, false, 0);
2518 // The address of the thread local variable is the add of the thread
2519 // pointer with the offset of the variable.
2520 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2524 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2525 // TODO: implement the "local dynamic" model
2526 assert(Subtarget->isTargetELF() &&
2527 "TLS not implemented for non-ELF targets");
2528 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2530 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2533 case TLSModel::GeneralDynamic:
2534 case TLSModel::LocalDynamic:
2535 return LowerToTLSGeneralDynamicModel(GA, DAG);
2536 case TLSModel::InitialExec:
2537 case TLSModel::LocalExec:
2538 return LowerToTLSExecModels(GA, DAG, model);
2540 llvm_unreachable("bogus TLS model");
2543 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2544 SelectionDAG &DAG) const {
2545 EVT PtrVT = getPointerTy();
2547 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2548 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2549 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2550 ARMConstantPoolValue *CPV =
2551 ARMConstantPoolConstant::Create(GV,
2552 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2553 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2554 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2555 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2557 MachinePointerInfo::getConstantPool(),
2558 false, false, false, 0);
2559 SDValue Chain = Result.getValue(1);
2560 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2561 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2563 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2564 MachinePointerInfo::getGOT(),
2565 false, false, false, 0);
2569 // If we have T2 ops, we can materialize the address directly via movt/movw
2570 // pair. This is always cheaper.
2571 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2573 // FIXME: Once remat is capable of dealing with instructions with register
2574 // operands, expand this into two nodes.
2575 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2576 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2578 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2579 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2580 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2581 MachinePointerInfo::getConstantPool(),
2582 false, false, false, 0);
2586 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2587 SelectionDAG &DAG) const {
2588 EVT PtrVT = getPointerTy();
2590 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2591 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2593 if (Subtarget->useMovt(DAG.getMachineFunction()))
2596 // FIXME: Once remat is capable of dealing with instructions with register
2597 // operands, expand this into multiple nodes
2599 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2601 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2602 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2604 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2605 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2606 MachinePointerInfo::getGOT(), false, false, false, 0);
2610 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2611 SelectionDAG &DAG) const {
2612 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2613 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2614 "Windows on ARM expects to use movw/movt");
2616 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2617 const ARMII::TOF TargetFlags =
2618 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2619 EVT PtrVT = getPointerTy();
2625 // FIXME: Once remat is capable of dealing with instructions with register
2626 // operands, expand this into two nodes.
2627 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2628 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2630 if (GV->hasDLLImportStorageClass())
2631 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2632 MachinePointerInfo::getGOT(), false, false, false, 0);
2636 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2637 SelectionDAG &DAG) const {
2638 assert(Subtarget->isTargetELF() &&
2639 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2640 MachineFunction &MF = DAG.getMachineFunction();
2641 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2642 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2643 EVT PtrVT = getPointerTy();
2645 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2646 ARMConstantPoolValue *CPV =
2647 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2648 ARMPCLabelIndex, PCAdj);
2649 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2650 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2651 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2652 MachinePointerInfo::getConstantPool(),
2653 false, false, false, 0);
2654 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2655 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2659 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2661 SDValue Val = DAG.getConstant(0, MVT::i32);
2662 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2663 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2664 Op.getOperand(1), Val);
2668 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2670 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2671 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2675 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2676 const ARMSubtarget *Subtarget) const {
2677 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2680 default: return SDValue(); // Don't custom lower most intrinsics.
2681 case Intrinsic::arm_rbit: {
2682 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2683 "RBIT intrinsic must have i32 type!");
2684 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2686 case Intrinsic::arm_thread_pointer: {
2687 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2688 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2690 case Intrinsic::eh_sjlj_lsda: {
2691 MachineFunction &MF = DAG.getMachineFunction();
2692 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2693 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2694 EVT PtrVT = getPointerTy();
2695 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2697 unsigned PCAdj = (RelocM != Reloc::PIC_)
2698 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2699 ARMConstantPoolValue *CPV =
2700 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2701 ARMCP::CPLSDA, PCAdj);
2702 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2703 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2705 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2706 MachinePointerInfo::getConstantPool(),
2707 false, false, false, 0);
2709 if (RelocM == Reloc::PIC_) {
2710 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2711 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2715 case Intrinsic::arm_neon_vmulls:
2716 case Intrinsic::arm_neon_vmullu: {
2717 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2718 ? ARMISD::VMULLs : ARMISD::VMULLu;
2719 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2720 Op.getOperand(1), Op.getOperand(2));
2725 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2726 const ARMSubtarget *Subtarget) {
2727 // FIXME: handle "fence singlethread" more efficiently.
2729 if (!Subtarget->hasDataBarrier()) {
2730 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2731 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2733 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2734 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2735 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2736 DAG.getConstant(0, MVT::i32));
2739 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2740 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2741 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2742 if (Subtarget->isMClass()) {
2743 // Only a full system barrier exists in the M-class architectures.
2744 Domain = ARM_MB::SY;
2745 } else if (Subtarget->isSwift() && Ord == Release) {
2746 // Swift happens to implement ISHST barriers in a way that's compatible with
2747 // Release semantics but weaker than ISH so we'd be fools not to use
2748 // it. Beware: other processors probably don't!
2749 Domain = ARM_MB::ISHST;
2752 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2753 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2754 DAG.getConstant(Domain, MVT::i32));
2757 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2758 const ARMSubtarget *Subtarget) {
2759 // ARM pre v5TE and Thumb1 does not have preload instructions.
2760 if (!(Subtarget->isThumb2() ||
2761 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2762 // Just preserve the chain.
2763 return Op.getOperand(0);
2766 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2768 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2769 // ARMv7 with MP extension has PLDW.
2770 return Op.getOperand(0);
2772 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2773 if (Subtarget->isThumb()) {
2775 isRead = ~isRead & 1;
2776 isData = ~isData & 1;
2779 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2780 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2781 DAG.getConstant(isData, MVT::i32));
2784 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2785 MachineFunction &MF = DAG.getMachineFunction();
2786 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2788 // vastart just stores the address of the VarArgsFrameIndex slot into the
2789 // memory location argument.
2791 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2792 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2793 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2794 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2795 MachinePointerInfo(SV), false, false, 0);
2799 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2800 SDValue &Root, SelectionDAG &DAG,
2802 MachineFunction &MF = DAG.getMachineFunction();
2803 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2805 const TargetRegisterClass *RC;
2806 if (AFI->isThumb1OnlyFunction())
2807 RC = &ARM::tGPRRegClass;
2809 RC = &ARM::GPRRegClass;
2811 // Transform the arguments stored in physical registers into virtual ones.
2812 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2813 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2816 if (NextVA.isMemLoc()) {
2817 MachineFrameInfo *MFI = MF.getFrameInfo();
2818 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2820 // Create load node to retrieve arguments from the stack.
2821 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2822 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2823 MachinePointerInfo::getFixedStack(FI),
2824 false, false, false, 0);
2826 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2827 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2829 if (!Subtarget->isLittle())
2830 std::swap (ArgValue, ArgValue2);
2831 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2835 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2836 unsigned InRegsParamRecordIdx,
2838 unsigned &ArgRegsSize,
2839 unsigned &ArgRegsSaveSize)
2842 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2843 unsigned RBegin, REnd;
2844 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2845 NumGPRs = REnd - RBegin;
2847 unsigned int firstUnalloced;
2848 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2849 sizeof(GPRArgRegs) /
2850 sizeof(GPRArgRegs[0]));
2851 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2854 unsigned Align = MF.getTarget()
2856 ->getFrameLowering()
2857 ->getStackAlignment();
2858 ArgRegsSize = NumGPRs * 4;
2860 // If parameter is split between stack and GPRs...
2861 if (NumGPRs && Align > 4 &&
2862 (ArgRegsSize < ArgSize ||
2863 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2864 // Add padding for part of param recovered from GPRs. For example,
2865 // if Align == 8, its last byte must be at address K*8 - 1.
2866 // We need to do it, since remained (stack) part of parameter has
2867 // stack alignment, and we need to "attach" "GPRs head" without gaps
2870 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2871 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2873 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2875 OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
2876 ArgRegsSaveSize = ArgRegsSize + Padding;
2878 // We don't need to extend regs save size for byval parameters if they
2879 // are passed via GPRs only.
2880 ArgRegsSaveSize = ArgRegsSize;
2883 // The remaining GPRs hold either the beginning of variable-argument
2884 // data, or the beginning of an aggregate passed by value (usually
2885 // byval). Either way, we allocate stack slots adjacent to the data
2886 // provided by our caller, and store the unallocated registers there.
2887 // If this is a variadic function, the va_list pointer will begin with
2888 // these values; otherwise, this reassembles a (byval) structure that
2889 // was split between registers and memory.
2890 // Return: The frame index registers were stored into.
2892 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2893 SDLoc dl, SDValue &Chain,
2894 const Value *OrigArg,
2895 unsigned InRegsParamRecordIdx,
2896 unsigned OffsetFromOrigArg,
2900 unsigned ByValStoreOffset,
2901 unsigned TotalArgRegsSaveSize) const {
2903 // Currently, two use-cases possible:
2904 // Case #1. Non-var-args function, and we meet first byval parameter.
2905 // Setup first unallocated register as first byval register;
2906 // eat all remained registers
2907 // (these two actions are performed by HandleByVal method).
2908 // Then, here, we initialize stack frame with
2909 // "store-reg" instructions.
2910 // Case #2. Var-args function, that doesn't contain byval parameters.
2911 // The same: eat all remained unallocated registers,
2912 // initialize stack frame.
2914 MachineFunction &MF = DAG.getMachineFunction();
2915 MachineFrameInfo *MFI = MF.getFrameInfo();
2916 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2917 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2918 unsigned RBegin, REnd;
2919 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2920 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2921 firstRegToSaveIndex = RBegin - ARM::R0;
2922 lastRegToSaveIndex = REnd - ARM::R0;
2924 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2925 (GPRArgRegs, array_lengthof(GPRArgRegs));
2926 lastRegToSaveIndex = 4;
2929 unsigned ArgRegsSize, ArgRegsSaveSize;
2930 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2931 ArgRegsSize, ArgRegsSaveSize);
2933 // Store any by-val regs to their spots on the stack so that they may be
2934 // loaded by deferencing the result of formal parameter pointer or va_next.
2935 // Note: once stack area for byval/varargs registers
2936 // was initialized, it can't be initialized again.
2937 if (ArgRegsSaveSize) {
2938 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2941 assert(AFI->getStoredByValParamsPadding() == 0 &&
2942 "The only parameter may be padded.");
2943 AFI->setStoredByValParamsPadding(Padding);
2946 int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2949 (int64_t)TotalArgRegsSaveSize,
2951 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2953 MFI->CreateFixedObject(Padding,
2954 ArgOffset + ByValStoreOffset -
2955 (int64_t)ArgRegsSaveSize,
2959 SmallVector<SDValue, 4> MemOps;
2960 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2961 ++firstRegToSaveIndex, ++i) {
2962 const TargetRegisterClass *RC;
2963 if (AFI->isThumb1OnlyFunction())
2964 RC = &ARM::tGPRRegClass;
2966 RC = &ARM::GPRRegClass;
2968 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2971 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2972 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2974 MemOps.push_back(Store);
2975 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2976 DAG.getConstant(4, getPointerTy()));
2979 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2981 if (!MemOps.empty())
2982 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2986 // We cannot allocate a zero-byte object for the first variadic argument,
2987 // so just make up a size.
2990 // This will point to the next argument passed via stack.
2991 return MFI->CreateFixedObject(
2992 ArgSize, ArgOffset, !ForceMutable);
2996 // Setup stack frame, the va_list pointer will start from.
2998 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2999 SDLoc dl, SDValue &Chain,
3001 unsigned TotalArgRegsSaveSize,
3002 bool ForceMutable) const {
3003 MachineFunction &MF = DAG.getMachineFunction();
3004 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3006 // Try to store any remaining integer argument regs
3007 // to their spots on the stack so that they may be loaded by deferencing
3008 // the result of va_next.
3009 // If there is no regs to be stored, just point address after last
3010 // argument passed via stack.
3012 StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3013 CCInfo.getInRegsParamsCount(), 0, ArgOffset, 0, ForceMutable,
3014 0, TotalArgRegsSaveSize);
3016 AFI->setVarArgsFrameIndex(FrameIndex);
3020 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
3021 CallingConv::ID CallConv, bool isVarArg,
3022 const SmallVectorImpl<ISD::InputArg>
3024 SDLoc dl, SelectionDAG &DAG,
3025 SmallVectorImpl<SDValue> &InVals)
3027 MachineFunction &MF = DAG.getMachineFunction();
3028 MachineFrameInfo *MFI = MF.getFrameInfo();
3030 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3032 // Assign locations to all of the incoming arguments.
3033 SmallVector<CCValAssign, 16> ArgLocs;
3034 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3035 *DAG.getContext(), Prologue);
3036 CCInfo.AnalyzeFormalArguments(Ins,
3037 CCAssignFnForNode(CallConv, /* Return*/ false,
3040 SmallVector<SDValue, 16> ArgValues;
3041 int lastInsIndex = -1;
3043 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3044 unsigned CurArgIdx = 0;
3046 // Initially ArgRegsSaveSize is zero.
3047 // Then we increase this value each time we meet byval parameter.
3048 // We also increase this value in case of varargs function.
3049 AFI->setArgRegsSaveSize(0);
3051 unsigned ByValStoreOffset = 0;
3052 unsigned TotalArgRegsSaveSize = 0;
3053 unsigned ArgRegsSaveSizeMaxAlign = 4;
3055 // Calculate the amount of stack space that we need to allocate to store
3056 // byval and variadic arguments that are passed in registers.
3057 // We need to know this before we allocate the first byval or variadic
3058 // argument, as they will be allocated a stack slot below the CFA (Canonical
3059 // Frame Address, the stack pointer at entry to the function).
3060 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3061 CCValAssign &VA = ArgLocs[i];
3062 if (VA.isMemLoc()) {
3063 int index = VA.getValNo();
3064 if (index != lastInsIndex) {
3065 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3066 if (Flags.isByVal()) {
3067 unsigned ExtraArgRegsSize;
3068 unsigned ExtraArgRegsSaveSize;
3069 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProcessed(),
3070 Flags.getByValSize(),
3071 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3073 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3074 if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
3075 ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
3076 CCInfo.nextInRegsParam();
3078 lastInsIndex = index;
3082 CCInfo.rewindByValRegsInfo();
3084 if (isVarArg && MFI->hasVAStart()) {
3085 unsigned ExtraArgRegsSize;
3086 unsigned ExtraArgRegsSaveSize;
3087 computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
3088 ExtraArgRegsSize, ExtraArgRegsSaveSize);
3089 TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
3091 // If the arg regs save area contains N-byte aligned values, the
3092 // bottom of it must be at least N-byte aligned.
3093 TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
3094 TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
3096 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3097 CCValAssign &VA = ArgLocs[i];
3098 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
3099 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
3100 // Arguments stored in registers.
3101 if (VA.isRegLoc()) {
3102 EVT RegVT = VA.getLocVT();
3104 if (VA.needsCustom()) {
3105 // f64 and vector types are split up into multiple registers or
3106 // combinations of registers and stack slots.
3107 if (VA.getLocVT() == MVT::v2f64) {
3108 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3110 VA = ArgLocs[++i]; // skip ahead to next loc
3112 if (VA.isMemLoc()) {
3113 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3114 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3115 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3116 MachinePointerInfo::getFixedStack(FI),
3117 false, false, false, 0);
3119 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3122 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3123 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3124 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
3125 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3126 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
3128 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3131 const TargetRegisterClass *RC;
3133 if (RegVT == MVT::f32)
3134 RC = &ARM::SPRRegClass;
3135 else if (RegVT == MVT::f64)
3136 RC = &ARM::DPRRegClass;
3137 else if (RegVT == MVT::v2f64)
3138 RC = &ARM::QPRRegClass;
3139 else if (RegVT == MVT::i32)
3140 RC = AFI->isThumb1OnlyFunction() ?
3141 (const TargetRegisterClass*)&ARM::tGPRRegClass :
3142 (const TargetRegisterClass*)&ARM::GPRRegClass;
3144 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3146 // Transform the arguments in physical registers into virtual ones.
3147 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3148 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3151 // If this is an 8 or 16-bit value, it is really passed promoted
3152 // to 32 bits. Insert an assert[sz]ext to capture this, then
3153 // truncate to the right size.
3154 switch (VA.getLocInfo()) {
3155 default: llvm_unreachable("Unknown loc info!");
3156 case CCValAssign::Full: break;
3157 case CCValAssign::BCvt:
3158 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3160 case CCValAssign::SExt:
3161 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3162 DAG.getValueType(VA.getValVT()));
3163 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3165 case CCValAssign::ZExt:
3166 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3167 DAG.getValueType(VA.getValVT()));
3168 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3172 InVals.push_back(ArgValue);
3174 } else { // VA.isRegLoc()
3177 assert(VA.isMemLoc());
3178 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3180 int index = ArgLocs[i].getValNo();
3182 // Some Ins[] entries become multiple ArgLoc[] entries.
3183 // Process them only once.
3184 if (index != lastInsIndex)
3186 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3187 // FIXME: For now, all byval parameter objects are marked mutable.
3188 // This can be changed with more analysis.
3189 // In case of tail call optimization mark all arguments mutable.
3190 // Since they could be overwritten by lowering of arguments in case of
3192 if (Flags.isByVal()) {
3193 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3195 ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
3196 int FrameIndex = StoreByValRegs(
3197 CCInfo, DAG, dl, Chain, CurOrigArg,
3199 Ins[VA.getValNo()].PartOffset,
3200 VA.getLocMemOffset(),
3201 Flags.getByValSize(),
3202 true /*force mutable frames*/,
3204 TotalArgRegsSaveSize);
3205 ByValStoreOffset += Flags.getByValSize();
3206 ByValStoreOffset = std::min(ByValStoreOffset, 16U);
3207 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3208 CCInfo.nextInRegsParam();
3210 unsigned FIOffset = VA.getLocMemOffset();
3211 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3214 // Create load nodes to retrieve arguments from the stack.
3215 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3216 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3217 MachinePointerInfo::getFixedStack(FI),
3218 false, false, false, 0));
3220 lastInsIndex = index;
3226 if (isVarArg && MFI->hasVAStart())
3227 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3228 CCInfo.getNextStackOffset(),
3229 TotalArgRegsSaveSize);
3231 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3236 /// isFloatingPointZero - Return true if this is +0.0.
3237 static bool isFloatingPointZero(SDValue Op) {
3238 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3239 return CFP->getValueAPF().isPosZero();
3240 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3241 // Maybe this has already been legalized into the constant pool?
3242 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3243 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3244 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3245 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3246 return CFP->getValueAPF().isPosZero();
3248 } else if (Op->getOpcode() == ISD::BITCAST &&
3249 Op->getValueType(0) == MVT::f64) {
3250 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3251 // created by LowerConstantFP().
3252 SDValue BitcastOp = Op->getOperand(0);
3253 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3254 SDValue MoveOp = BitcastOp->getOperand(0);
3255 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3256 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3264 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3265 /// the given operands.
3267 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3268 SDValue &ARMcc, SelectionDAG &DAG,
3270 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3271 unsigned C = RHSC->getZExtValue();
3272 if (!isLegalICmpImmediate(C)) {
3273 // Constant does not fit, try adjusting it by one?
3278 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3279 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3280 RHS = DAG.getConstant(C-1, MVT::i32);
3285 if (C != 0 && isLegalICmpImmediate(C-1)) {
3286 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3287 RHS = DAG.getConstant(C-1, MVT::i32);
3292 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3293 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3294 RHS = DAG.getConstant(C+1, MVT::i32);
3299 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3300 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3301 RHS = DAG.getConstant(C+1, MVT::i32);
3308 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3309 ARMISD::NodeType CompareType;
3312 CompareType = ARMISD::CMP;
3317 CompareType = ARMISD::CMPZ;
3320 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3321 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3324 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3326 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3328 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3330 if (!isFloatingPointZero(RHS))
3331 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3333 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3334 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3337 /// duplicateCmp - Glue values can have only one use, so this function
3338 /// duplicates a comparison node.
3340 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3341 unsigned Opc = Cmp.getOpcode();
3343 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3344 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3346 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3347 Cmp = Cmp.getOperand(0);
3348 Opc = Cmp.getOpcode();
3349 if (Opc == ARMISD::CMPFP)
3350 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3352 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3353 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3355 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3358 std::pair<SDValue, SDValue>
3359 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3360 SDValue &ARMcc) const {
3361 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3363 SDValue Value, OverflowCmp;
3364 SDValue LHS = Op.getOperand(0);
3365 SDValue RHS = Op.getOperand(1);
3368 // FIXME: We are currently always generating CMPs because we don't support
3369 // generating CMN through the backend. This is not as good as the natural
3370 // CMP case because it causes a register dependency and cannot be folded
3373 switch (Op.getOpcode()) {
3375 llvm_unreachable("Unknown overflow instruction!");
3377 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3378 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3379 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3382 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3383 Value = DAG.getNode(ISD::ADD, SDLoc(Op), Op.getValueType(), LHS, RHS);
3384 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, Value, LHS);
3387 ARMcc = DAG.getConstant(ARMCC::VC, MVT::i32);
3388 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3389 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3392 ARMcc = DAG.getConstant(ARMCC::HS, MVT::i32);
3393 Value = DAG.getNode(ISD::SUB, SDLoc(Op), Op.getValueType(), LHS, RHS);
3394 OverflowCmp = DAG.getNode(ARMISD::CMP, SDLoc(Op), MVT::Glue, LHS, RHS);
3398 return std::make_pair(Value, OverflowCmp);
3403 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3404 // Let legalize expand this if it isn't a legal type yet.
3405 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3408 SDValue Value, OverflowCmp;
3410 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3411 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3412 // We use 0 and 1 as false and true values.
3413 SDValue TVal = DAG.getConstant(1, MVT::i32);
3414 SDValue FVal = DAG.getConstant(0, MVT::i32);
3415 EVT VT = Op.getValueType();
3417 SDValue Overflow = DAG.getNode(ARMISD::CMOV, SDLoc(Op), VT, TVal, FVal,
3418 ARMcc, CCR, OverflowCmp);
3420 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3421 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
3425 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3426 SDValue Cond = Op.getOperand(0);
3427 SDValue SelectTrue = Op.getOperand(1);
3428 SDValue SelectFalse = Op.getOperand(2);
3430 unsigned Opc = Cond.getOpcode();
3432 if (Cond.getResNo() == 1 &&
3433 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3434 Opc == ISD::USUBO)) {
3435 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3438 SDValue Value, OverflowCmp;
3440 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3441 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3442 EVT VT = Op.getValueType();
3444 return getCMOV(SDLoc(Op), VT, SelectTrue, SelectFalse, ARMcc, CCR,
3450 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3451 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3453 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3454 const ConstantSDNode *CMOVTrue =
3455 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3456 const ConstantSDNode *CMOVFalse =
3457 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3459 if (CMOVTrue && CMOVFalse) {
3460 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3461 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3465 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3467 False = SelectFalse;
3468 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3473 if (True.getNode() && False.getNode()) {
3474 EVT VT = Op.getValueType();
3475 SDValue ARMcc = Cond.getOperand(2);
3476 SDValue CCR = Cond.getOperand(3);
3477 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3478 assert(True.getValueType() == VT);
3479 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3484 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3485 // undefined bits before doing a full-word comparison with zero.
3486 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3487 DAG.getConstant(1, Cond.getValueType()));
3489 return DAG.getSelectCC(dl, Cond,
3490 DAG.getConstant(0, Cond.getValueType()),
3491 SelectTrue, SelectFalse, ISD::SETNE);
3494 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3495 if (CC == ISD::SETNE)
3497 return ISD::getSetCCInverse(CC, true);
3500 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3501 bool &swpCmpOps, bool &swpVselOps) {
3502 // Start by selecting the GE condition code for opcodes that return true for
3504 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3506 CondCode = ARMCC::GE;
3508 // and GT for opcodes that return false for 'equality'.
3509 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3511 CondCode = ARMCC::GT;
3513 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3514 // to swap the compare operands.
3515 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3519 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3520 // If we have an unordered opcode, we need to swap the operands to the VSEL
3521 // instruction (effectively negating the condition).
3523 // This also has the effect of swapping which one of 'less' or 'greater'
3524 // returns true, so we also swap the compare operands. It also switches
3525 // whether we return true for 'equality', so we compensate by picking the
3526 // opposite condition code to our original choice.
3527 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3528 CC == ISD::SETUGT) {
3529 swpCmpOps = !swpCmpOps;
3530 swpVselOps = !swpVselOps;
3531 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3534 // 'ordered' is 'anything but unordered', so use the VS condition code and
3535 // swap the VSEL operands.
3536 if (CC == ISD::SETO) {
3537 CondCode = ARMCC::VS;
3541 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3542 // code and swap the VSEL operands.
3543 if (CC == ISD::SETUNE) {
3544 CondCode = ARMCC::EQ;
3549 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3550 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3551 SDValue Cmp, SelectionDAG &DAG) const {
3552 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3553 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3554 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3555 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3556 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3558 SDValue TrueLow = TrueVal.getValue(0);
3559 SDValue TrueHigh = TrueVal.getValue(1);
3560 SDValue FalseLow = FalseVal.getValue(0);
3561 SDValue FalseHigh = FalseVal.getValue(1);
3563 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3565 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3566 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3568 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3570 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3575 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3576 EVT VT = Op.getValueType();
3577 SDValue LHS = Op.getOperand(0);
3578 SDValue RHS = Op.getOperand(1);
3579 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3580 SDValue TrueVal = Op.getOperand(2);
3581 SDValue FalseVal = Op.getOperand(3);
3584 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3585 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3588 // If softenSetCCOperands only returned one value, we should compare it to
3590 if (!RHS.getNode()) {
3591 RHS = DAG.getConstant(0, LHS.getValueType());
3596 if (LHS.getValueType() == MVT::i32) {
3597 // Try to generate VSEL on ARMv8.
3598 // The VSEL instruction can't use all the usual ARM condition
3599 // codes: it only has two bits to select the condition code, so it's
3600 // constrained to use only GE, GT, VS and EQ.
3602 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3603 // swap the operands of the previous compare instruction (effectively
3604 // inverting the compare condition, swapping 'less' and 'greater') and
3605 // sometimes need to swap the operands to the VSEL (which inverts the
3606 // condition in the sense of firing whenever the previous condition didn't)
3607 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3608 TrueVal.getValueType() == MVT::f64)) {
3609 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3610 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3611 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3612 CC = getInverseCCForVSEL(CC);
3613 std::swap(TrueVal, FalseVal);
3618 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3619 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3620 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3623 ARMCC::CondCodes CondCode, CondCode2;
3624 FPCCToARMCC(CC, CondCode, CondCode2);
3626 // Try to generate VSEL on ARMv8.
3627 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3628 TrueVal.getValueType() == MVT::f64)) {
3629 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3630 // same operands, as follows:
3631 // c = fcmp [ogt, olt, ugt, ult] a, b
3633 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3634 // handled differently than the original code sequence.
3635 if (getTargetMachine().Options.UnsafeFPMath) {
3636 if (LHS == TrueVal && RHS == FalseVal) {
3637 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3638 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3639 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3640 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3641 } else if (LHS == FalseVal && RHS == TrueVal) {
3642 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3643 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3644 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3645 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3649 bool swpCmpOps = false;
3650 bool swpVselOps = false;
3651 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3653 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3654 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3656 std::swap(LHS, RHS);
3658 std::swap(TrueVal, FalseVal);
3662 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3663 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3664 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3665 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3666 if (CondCode2 != ARMCC::AL) {
3667 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3668 // FIXME: Needs another CMP because flag can have but one use.
3669 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3670 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3675 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3676 /// to morph to an integer compare sequence.
3677 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3678 const ARMSubtarget *Subtarget) {
3679 SDNode *N = Op.getNode();
3680 if (!N->hasOneUse())
3681 // Otherwise it requires moving the value from fp to integer registers.
3683 if (!N->getNumValues())
3685 EVT VT = Op.getValueType();
3686 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3687 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3688 // vmrs are very slow, e.g. cortex-a8.
3691 if (isFloatingPointZero(Op)) {
3695 return ISD::isNormalLoad(N);
3698 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3699 if (isFloatingPointZero(Op))
3700 return DAG.getConstant(0, MVT::i32);
3702 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3703 return DAG.getLoad(MVT::i32, SDLoc(Op),
3704 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3705 Ld->isVolatile(), Ld->isNonTemporal(),
3706 Ld->isInvariant(), Ld->getAlignment());
3708 llvm_unreachable("Unknown VFP cmp argument!");
3711 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3712 SDValue &RetVal1, SDValue &RetVal2) {
3713 if (isFloatingPointZero(Op)) {
3714 RetVal1 = DAG.getConstant(0, MVT::i32);
3715 RetVal2 = DAG.getConstant(0, MVT::i32);
3719 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3720 SDValue Ptr = Ld->getBasePtr();
3721 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3722 Ld->getChain(), Ptr,
3723 Ld->getPointerInfo(),
3724 Ld->isVolatile(), Ld->isNonTemporal(),
3725 Ld->isInvariant(), Ld->getAlignment());
3727 EVT PtrType = Ptr.getValueType();
3728 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3729 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3730 PtrType, Ptr, DAG.getConstant(4, PtrType));
3731 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3732 Ld->getChain(), NewPtr,
3733 Ld->getPointerInfo().getWithOffset(4),
3734 Ld->isVolatile(), Ld->isNonTemporal(),
3735 Ld->isInvariant(), NewAlign);
3739 llvm_unreachable("Unknown VFP cmp argument!");
3742 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3743 /// f32 and even f64 comparisons to integer ones.
3745 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3746 SDValue Chain = Op.getOperand(0);
3747 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3748 SDValue LHS = Op.getOperand(2);
3749 SDValue RHS = Op.getOperand(3);
3750 SDValue Dest = Op.getOperand(4);
3753 bool LHSSeenZero = false;
3754 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3755 bool RHSSeenZero = false;
3756 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3757 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3758 // If unsafe fp math optimization is enabled and there are no other uses of
3759 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3760 // to an integer comparison.
3761 if (CC == ISD::SETOEQ)
3763 else if (CC == ISD::SETUNE)
3766 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3768 if (LHS.getValueType() == MVT::f32) {
3769 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3770 bitcastf32Toi32(LHS, DAG), Mask);
3771 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3772 bitcastf32Toi32(RHS, DAG), Mask);
3773 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3774 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3775 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3776 Chain, Dest, ARMcc, CCR, Cmp);
3781 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3782 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3783 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3784 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3785 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3786 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3787 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3788 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3789 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3795 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3796 SDValue Chain = Op.getOperand(0);
3797 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3798 SDValue LHS = Op.getOperand(2);
3799 SDValue RHS = Op.getOperand(3);
3800 SDValue Dest = Op.getOperand(4);
3803 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3804 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3807 // If softenSetCCOperands only returned one value, we should compare it to
3809 if (!RHS.getNode()) {
3810 RHS = DAG.getConstant(0, LHS.getValueType());
3815 if (LHS.getValueType() == MVT::i32) {
3817 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3818 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3819 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3820 Chain, Dest, ARMcc, CCR, Cmp);
3823 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3825 if (getTargetMachine().Options.UnsafeFPMath &&
3826 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3827 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3828 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3829 if (Result.getNode())
3833 ARMCC::CondCodes CondCode, CondCode2;
3834 FPCCToARMCC(CC, CondCode, CondCode2);
3836 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3837 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3838 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3839 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3840 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3841 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3842 if (CondCode2 != ARMCC::AL) {
3843 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3844 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3845 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3850 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3851 SDValue Chain = Op.getOperand(0);
3852 SDValue Table = Op.getOperand(1);
3853 SDValue Index = Op.getOperand(2);
3856 EVT PTy = getPointerTy();
3857 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3858 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3859 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3860 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3861 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3862 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3863 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3864 if (Subtarget->isThumb2()) {
3865 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3866 // which does another jump to the destination. This also makes it easier
3867 // to translate it to TBB / TBH later.
3868 // FIXME: This might not work if the function is extremely large.
3869 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3870 Addr, Op.getOperand(2), JTI, UId);
3872 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3873 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3874 MachinePointerInfo::getJumpTable(),
3875 false, false, false, 0);
3876 Chain = Addr.getValue(1);
3877 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3878 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3880 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3881 MachinePointerInfo::getJumpTable(),
3882 false, false, false, 0);
3883 Chain = Addr.getValue(1);
3884 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3888 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3889 EVT VT = Op.getValueType();
3892 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3893 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3895 return DAG.UnrollVectorOp(Op.getNode());
3898 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3899 "Invalid type for custom lowering!");
3900 if (VT != MVT::v4i16)
3901 return DAG.UnrollVectorOp(Op.getNode());
3903 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3904 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3907 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3908 EVT VT = Op.getValueType();
3910 return LowerVectorFP_TO_INT(Op, DAG);
3912 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3914 if (Op.getOpcode() == ISD::FP_TO_SINT)
3915 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3918 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3920 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3921 /*isSigned*/ false, SDLoc(Op)).first;
3927 switch (Op.getOpcode()) {
3928 default: llvm_unreachable("Invalid opcode!");
3929 case ISD::FP_TO_SINT:
3930 Opc = ARMISD::FTOSI;
3932 case ISD::FP_TO_UINT:
3933 Opc = ARMISD::FTOUI;
3936 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3937 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3940 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3941 EVT VT = Op.getValueType();
3944 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3945 if (VT.getVectorElementType() == MVT::f32)
3947 return DAG.UnrollVectorOp(Op.getNode());
3950 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3951 "Invalid type for custom lowering!");
3952 if (VT != MVT::v4f32)
3953 return DAG.UnrollVectorOp(Op.getNode());
3957 switch (Op.getOpcode()) {
3958 default: llvm_unreachable("Invalid opcode!");
3959 case ISD::SINT_TO_FP:
3960 CastOpc = ISD::SIGN_EXTEND;
3961 Opc = ISD::SINT_TO_FP;
3963 case ISD::UINT_TO_FP:
3964 CastOpc = ISD::ZERO_EXTEND;
3965 Opc = ISD::UINT_TO_FP;
3969 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3970 return DAG.getNode(Opc, dl, VT, Op);
3973 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3974 EVT VT = Op.getValueType();
3976 return LowerVectorINT_TO_FP(Op, DAG);
3978 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3980 if (Op.getOpcode() == ISD::SINT_TO_FP)
3981 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3984 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3986 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3987 /*isSigned*/ false, SDLoc(Op)).first;
3993 switch (Op.getOpcode()) {
3994 default: llvm_unreachable("Invalid opcode!");
3995 case ISD::SINT_TO_FP:
3996 Opc = ARMISD::SITOF;
3998 case ISD::UINT_TO_FP:
3999 Opc = ARMISD::UITOF;
4003 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
4004 return DAG.getNode(Opc, dl, VT, Op);
4007 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4008 // Implement fcopysign with a fabs and a conditional fneg.
4009 SDValue Tmp0 = Op.getOperand(0);
4010 SDValue Tmp1 = Op.getOperand(1);
4012 EVT VT = Op.getValueType();
4013 EVT SrcVT = Tmp1.getValueType();
4014 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4015 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4016 bool UseNEON = !InGPR && Subtarget->hasNEON();
4019 // Use VBSL to copy the sign bit.
4020 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4021 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4022 DAG.getTargetConstant(EncodedVal, MVT::i32));
4023 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4025 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4026 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4027 DAG.getConstant(32, MVT::i32));
4028 else /*if (VT == MVT::f32)*/
4029 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4030 if (SrcVT == MVT::f32) {
4031 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4033 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4034 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4035 DAG.getConstant(32, MVT::i32));
4036 } else if (VT == MVT::f32)
4037 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4038 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4039 DAG.getConstant(32, MVT::i32));
4040 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4041 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4043 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4045 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4046 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4047 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4049 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4050 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4051 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4052 if (VT == MVT::f32) {
4053 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4054 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4055 DAG.getConstant(0, MVT::i32));
4057 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4063 // Bitcast operand 1 to i32.
4064 if (SrcVT == MVT::f64)
4065 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4067 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4069 // Or in the signbit with integer operations.
4070 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
4071 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
4072 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4073 if (VT == MVT::f32) {
4074 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4075 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4076 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4077 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4080 // f64: Or the high part with signbit and then combine two parts.
4081 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4083 SDValue Lo = Tmp0.getValue(0);
4084 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4085 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4086 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4089 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4090 MachineFunction &MF = DAG.getMachineFunction();
4091 MachineFrameInfo *MFI = MF.getFrameInfo();
4092 MFI->setReturnAddressIsTaken(true);
4094 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4097 EVT VT = Op.getValueType();
4099 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4101 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4102 SDValue Offset = DAG.getConstant(4, MVT::i32);
4103 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4104 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4105 MachinePointerInfo(), false, false, false, 0);
4108 // Return LR, which contains the return address. Mark it an implicit live-in.
4109 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4110 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4113 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4114 const ARMBaseRegisterInfo &ARI =
4115 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4116 MachineFunction &MF = DAG.getMachineFunction();
4117 MachineFrameInfo *MFI = MF.getFrameInfo();
4118 MFI->setFrameAddressIsTaken(true);
4120 EVT VT = Op.getValueType();
4121 SDLoc dl(Op); // FIXME probably not meaningful
4122 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4123 unsigned FrameReg = ARI.getFrameRegister(MF);
4124 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4126 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4127 MachinePointerInfo(),
4128 false, false, false, 0);
4132 // FIXME? Maybe this could be a TableGen attribute on some registers and
4133 // this table could be generated automatically from RegInfo.
4134 unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
4136 unsigned Reg = StringSwitch<unsigned>(RegName)
4137 .Case("sp", ARM::SP)
4141 report_fatal_error("Invalid register name global variable");
4144 /// ExpandBITCAST - If the target supports VFP, this function is called to
4145 /// expand a bit convert where either the source or destination type is i64 to
4146 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4147 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4148 /// vectors), since the legalizer won't know what to do with that.
4149 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4152 SDValue Op = N->getOperand(0);
4154 // This function is only supposed to be called for i64 types, either as the
4155 // source or destination of the bit convert.
4156 EVT SrcVT = Op.getValueType();
4157 EVT DstVT = N->getValueType(0);
4158 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4159 "ExpandBITCAST called for non-i64 type");
4161 // Turn i64->f64 into VMOVDRR.
4162 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4163 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4164 DAG.getConstant(0, MVT::i32));
4165 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4166 DAG.getConstant(1, MVT::i32));
4167 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4168 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4171 // Turn f64->i64 into VMOVRRD.
4172 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4174 if (TLI.isBigEndian() && SrcVT.isVector() &&
4175 SrcVT.getVectorNumElements() > 1)
4176 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4177 DAG.getVTList(MVT::i32, MVT::i32),
4178 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4180 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4181 DAG.getVTList(MVT::i32, MVT::i32), Op);
4182 // Merge the pieces into a single i64 value.
4183 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4189 /// getZeroVector - Returns a vector of specified type with all zero elements.
4190 /// Zero vectors are used to represent vector negation and in those cases
4191 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4192 /// not support i64 elements, so sometimes the zero vectors will need to be
4193 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4195 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4196 assert(VT.isVector() && "Expected a vector type");
4197 // The canonical modified immediate encoding of a zero vector is....0!
4198 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
4199 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4200 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4201 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4204 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4205 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4206 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4207 SelectionDAG &DAG) const {
4208 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4209 EVT VT = Op.getValueType();
4210 unsigned VTBits = VT.getSizeInBits();
4212 SDValue ShOpLo = Op.getOperand(0);
4213 SDValue ShOpHi = Op.getOperand(1);
4214 SDValue ShAmt = Op.getOperand(2);
4216 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4218 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4220 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4221 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4222 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4223 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4224 DAG.getConstant(VTBits, MVT::i32));
4225 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4226 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4227 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4229 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4230 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4232 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4233 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4236 SDValue Ops[2] = { Lo, Hi };
4237 return DAG.getMergeValues(Ops, dl);
4240 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4241 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4242 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4243 SelectionDAG &DAG) const {
4244 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4245 EVT VT = Op.getValueType();
4246 unsigned VTBits = VT.getSizeInBits();
4248 SDValue ShOpLo = Op.getOperand(0);
4249 SDValue ShOpHi = Op.getOperand(1);
4250 SDValue ShAmt = Op.getOperand(2);
4253 assert(Op.getOpcode() == ISD::SHL_PARTS);
4254 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4255 DAG.getConstant(VTBits, MVT::i32), ShAmt);
4256 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4257 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4258 DAG.getConstant(VTBits, MVT::i32));
4259 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4260 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4262 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4263 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4264 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4266 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4267 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4270 SDValue Ops[2] = { Lo, Hi };
4271 return DAG.getMergeValues(Ops, dl);
4274 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4275 SelectionDAG &DAG) const {
4276 // The rounding mode is in bits 23:22 of the FPSCR.
4277 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4278 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4279 // so that the shift + and get folded into a bitfield extract.
4281 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4282 DAG.getConstant(Intrinsic::arm_get_fpscr,
4284 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4285 DAG.getConstant(1U << 22, MVT::i32));
4286 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4287 DAG.getConstant(22, MVT::i32));
4288 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4289 DAG.getConstant(3, MVT::i32));
4292 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4293 const ARMSubtarget *ST) {
4294 EVT VT = N->getValueType(0);
4297 if (!ST->hasV6T2Ops())
4300 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4301 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4304 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4305 /// for each 16-bit element from operand, repeated. The basic idea is to
4306 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4308 /// Trace for v4i16:
4309 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4310 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4311 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4312 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4313 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4314 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4315 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4316 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4317 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4318 EVT VT = N->getValueType(0);
4321 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4322 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4323 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4324 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4325 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4326 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4329 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4330 /// bit-count for each 16-bit element from the operand. We need slightly
4331 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4332 /// 64/128-bit registers.
4334 /// Trace for v4i16:
4335 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4336 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4337 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4338 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4339 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4340 EVT VT = N->getValueType(0);
4343 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4344 if (VT.is64BitVector()) {
4345 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4346 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4347 DAG.getIntPtrConstant(0));
4349 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4350 BitCounts, DAG.getIntPtrConstant(0));
4351 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4355 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4356 /// bit-count for each 32-bit element from the operand. The idea here is
4357 /// to split the vector into 16-bit elements, leverage the 16-bit count
4358 /// routine, and then combine the results.
4360 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4361 /// input = [v0 v1 ] (vi: 32-bit elements)
4362 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4363 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4364 /// vrev: N0 = [k1 k0 k3 k2 ]
4366 /// N1 =+[k1 k0 k3 k2 ]
4368 /// N2 =+[k1 k3 k0 k2 ]
4370 /// Extended =+[k1 k3 k0 k2 ]
4372 /// Extracted=+[k1 k3 ]
4374 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4375 EVT VT = N->getValueType(0);
4378 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4380 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4381 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4382 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4383 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4384 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4386 if (VT.is64BitVector()) {
4387 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4388 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4389 DAG.getIntPtrConstant(0));
4391 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4392 DAG.getIntPtrConstant(0));
4393 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4397 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4398 const ARMSubtarget *ST) {
4399 EVT VT = N->getValueType(0);
4401 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4402 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4403 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4404 "Unexpected type for custom ctpop lowering");
4406 if (VT.getVectorElementType() == MVT::i32)
4407 return lowerCTPOP32BitElements(N, DAG);
4409 return lowerCTPOP16BitElements(N, DAG);
4412 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4413 const ARMSubtarget *ST) {
4414 EVT VT = N->getValueType(0);
4420 // Lower vector shifts on NEON to use VSHL.
4421 assert(ST->hasNEON() && "unexpected vector shift");
4423 // Left shifts translate directly to the vshiftu intrinsic.
4424 if (N->getOpcode() == ISD::SHL)
4425 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4426 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4427 N->getOperand(0), N->getOperand(1));
4429 assert((N->getOpcode() == ISD::SRA ||
4430 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4432 // NEON uses the same intrinsics for both left and right shifts. For
4433 // right shifts, the shift amounts are negative, so negate the vector of
4435 EVT ShiftVT = N->getOperand(1).getValueType();
4436 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4437 getZeroVector(ShiftVT, DAG, dl),
4439 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4440 Intrinsic::arm_neon_vshifts :
4441 Intrinsic::arm_neon_vshiftu);
4442 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4443 DAG.getConstant(vshiftInt, MVT::i32),
4444 N->getOperand(0), NegatedCount);
4447 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4448 const ARMSubtarget *ST) {
4449 EVT VT = N->getValueType(0);
4452 // We can get here for a node like i32 = ISD::SHL i32, i64
4456 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4457 "Unknown shift to lower!");
4459 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4460 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4461 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4464 // If we are in thumb mode, we don't have RRX.
4465 if (ST->isThumb1Only()) return SDValue();
4467 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4468 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4469 DAG.getConstant(0, MVT::i32));
4470 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4471 DAG.getConstant(1, MVT::i32));
4473 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4474 // captures the result into a carry flag.
4475 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4476 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4478 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4479 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4481 // Merge the pieces into a single i64 value.
4482 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4485 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4486 SDValue TmpOp0, TmpOp1;
4487 bool Invert = false;
4491 SDValue Op0 = Op.getOperand(0);
4492 SDValue Op1 = Op.getOperand(1);
4493 SDValue CC = Op.getOperand(2);
4494 EVT VT = Op.getValueType();
4495 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4498 if (Op1.getValueType().isFloatingPoint()) {
4499 switch (SetCCOpcode) {
4500 default: llvm_unreachable("Illegal FP comparison");
4502 case ISD::SETNE: Invert = true; // Fallthrough
4504 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4506 case ISD::SETLT: Swap = true; // Fallthrough
4508 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4510 case ISD::SETLE: Swap = true; // Fallthrough
4512 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4513 case ISD::SETUGE: Swap = true; // Fallthrough
4514 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4515 case ISD::SETUGT: Swap = true; // Fallthrough
4516 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4517 case ISD::SETUEQ: Invert = true; // Fallthrough
4519 // Expand this to (OLT | OGT).
4523 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4524 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4526 case ISD::SETUO: Invert = true; // Fallthrough
4528 // Expand this to (OLT | OGE).
4532 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4533 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4537 // Integer comparisons.
4538 switch (SetCCOpcode) {
4539 default: llvm_unreachable("Illegal integer comparison");
4540 case ISD::SETNE: Invert = true;
4541 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4542 case ISD::SETLT: Swap = true;
4543 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4544 case ISD::SETLE: Swap = true;
4545 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4546 case ISD::SETULT: Swap = true;
4547 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4548 case ISD::SETULE: Swap = true;
4549 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4552 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4553 if (Opc == ARMISD::VCEQ) {
4556 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4558 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4561 // Ignore bitconvert.
4562 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4563 AndOp = AndOp.getOperand(0);
4565 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4567 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4568 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4575 std::swap(Op0, Op1);
4577 // If one of the operands is a constant vector zero, attempt to fold the
4578 // comparison to a specialized compare-against-zero form.
4580 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4582 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4583 if (Opc == ARMISD::VCGE)
4584 Opc = ARMISD::VCLEZ;
4585 else if (Opc == ARMISD::VCGT)
4586 Opc = ARMISD::VCLTZ;
4591 if (SingleOp.getNode()) {
4594 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4596 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4598 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4600 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4602 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4604 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4607 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4611 Result = DAG.getNOT(dl, Result, VT);
4616 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4617 /// valid vector constant for a NEON instruction with a "modified immediate"
4618 /// operand (e.g., VMOV). If so, return the encoded value.
4619 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4620 unsigned SplatBitSize, SelectionDAG &DAG,
4621 EVT &VT, bool is128Bits, NEONModImmType type) {
4622 unsigned OpCmode, Imm;
4624 // SplatBitSize is set to the smallest size that splats the vector, so a
4625 // zero vector will always have SplatBitSize == 8. However, NEON modified
4626 // immediate instructions others than VMOV do not support the 8-bit encoding
4627 // of a zero vector, and the default encoding of zero is supposed to be the
4632 switch (SplatBitSize) {
4634 if (type != VMOVModImm)
4636 // Any 1-byte value is OK. Op=0, Cmode=1110.
4637 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4640 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4644 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4645 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4646 if ((SplatBits & ~0xff) == 0) {
4647 // Value = 0x00nn: Op=x, Cmode=100x.
4652 if ((SplatBits & ~0xff00) == 0) {
4653 // Value = 0xnn00: Op=x, Cmode=101x.
4655 Imm = SplatBits >> 8;
4661 // NEON's 32-bit VMOV supports splat values where:
4662 // * only one byte is nonzero, or
4663 // * the least significant byte is 0xff and the second byte is nonzero, or
4664 // * the least significant 2 bytes are 0xff and the third is nonzero.
4665 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4666 if ((SplatBits & ~0xff) == 0) {
4667 // Value = 0x000000nn: Op=x, Cmode=000x.
4672 if ((SplatBits & ~0xff00) == 0) {
4673 // Value = 0x0000nn00: Op=x, Cmode=001x.
4675 Imm = SplatBits >> 8;
4678 if ((SplatBits & ~0xff0000) == 0) {
4679 // Value = 0x00nn0000: Op=x, Cmode=010x.
4681 Imm = SplatBits >> 16;
4684 if ((SplatBits & ~0xff000000) == 0) {
4685 // Value = 0xnn000000: Op=x, Cmode=011x.
4687 Imm = SplatBits >> 24;
4691 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4692 if (type == OtherModImm) return SDValue();
4694 if ((SplatBits & ~0xffff) == 0 &&
4695 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4696 // Value = 0x0000nnff: Op=x, Cmode=1100.
4698 Imm = SplatBits >> 8;
4702 if ((SplatBits & ~0xffffff) == 0 &&
4703 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4704 // Value = 0x00nnffff: Op=x, Cmode=1101.
4706 Imm = SplatBits >> 16;
4710 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4711 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4712 // VMOV.I32. A (very) minor optimization would be to replicate the value
4713 // and fall through here to test for a valid 64-bit splat. But, then the
4714 // caller would also need to check and handle the change in size.
4718 if (type != VMOVModImm)
4720 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4721 uint64_t BitMask = 0xff;
4723 unsigned ImmMask = 1;
4725 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4726 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4729 } else if ((SplatBits & BitMask) != 0) {
4736 if (DAG.getTargetLoweringInfo().isBigEndian())
4737 // swap higher and lower 32 bit word
4738 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4740 // Op=1, Cmode=1110.
4742 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4747 llvm_unreachable("unexpected size for isNEONModifiedImm");
4750 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4751 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4754 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4755 const ARMSubtarget *ST) const {
4759 bool IsDouble = Op.getValueType() == MVT::f64;
4760 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4762 // Use the default (constant pool) lowering for double constants when we have
4764 if (IsDouble && Subtarget->isFPOnlySP())
4767 // Try splatting with a VMOV.f32...
4768 APFloat FPVal = CFP->getValueAPF();
4769 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4772 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4773 // We have code in place to select a valid ConstantFP already, no need to
4778 // It's a float and we are trying to use NEON operations where
4779 // possible. Lower it to a splat followed by an extract.
4781 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4782 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4785 DAG.getConstant(0, MVT::i32));
4788 // The rest of our options are NEON only, make sure that's allowed before
4790 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4794 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4796 // It wouldn't really be worth bothering for doubles except for one very
4797 // important value, which does happen to match: 0.0. So make sure we don't do
4799 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4802 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4803 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4805 if (NewVal != SDValue()) {
4807 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4810 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4812 // It's a float: cast and extract a vector element.
4813 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4815 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4816 DAG.getConstant(0, MVT::i32));
4819 // Finally, try a VMVN.i32
4820 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4822 if (NewVal != SDValue()) {
4824 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4827 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4829 // It's a float: cast and extract a vector element.
4830 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4832 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4833 DAG.getConstant(0, MVT::i32));
4839 // check if an VEXT instruction can handle the shuffle mask when the
4840 // vector sources of the shuffle are the same.
4841 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4842 unsigned NumElts = VT.getVectorNumElements();
4844 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4850 // If this is a VEXT shuffle, the immediate value is the index of the first
4851 // element. The other shuffle indices must be the successive elements after
4853 unsigned ExpectedElt = Imm;
4854 for (unsigned i = 1; i < NumElts; ++i) {
4855 // Increment the expected index. If it wraps around, just follow it
4856 // back to index zero and keep going.
4858 if (ExpectedElt == NumElts)
4861 if (M[i] < 0) continue; // ignore UNDEF indices
4862 if (ExpectedElt != static_cast<unsigned>(M[i]))
4870 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4871 bool &ReverseVEXT, unsigned &Imm) {
4872 unsigned NumElts = VT.getVectorNumElements();
4873 ReverseVEXT = false;
4875 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4881 // If this is a VEXT shuffle, the immediate value is the index of the first
4882 // element. The other shuffle indices must be the successive elements after
4884 unsigned ExpectedElt = Imm;
4885 for (unsigned i = 1; i < NumElts; ++i) {
4886 // Increment the expected index. If it wraps around, it may still be
4887 // a VEXT but the source vectors must be swapped.
4889 if (ExpectedElt == NumElts * 2) {
4894 if (M[i] < 0) continue; // ignore UNDEF indices
4895 if (ExpectedElt != static_cast<unsigned>(M[i]))
4899 // Adjust the index value if the source operands will be swapped.
4906 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4907 /// instruction with the specified blocksize. (The order of the elements
4908 /// within each block of the vector is reversed.)
4909 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4910 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4911 "Only possible block sizes for VREV are: 16, 32, 64");
4913 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4917 unsigned NumElts = VT.getVectorNumElements();
4918 unsigned BlockElts = M[0] + 1;
4919 // If the first shuffle index is UNDEF, be optimistic.
4921 BlockElts = BlockSize / EltSz;
4923 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4926 for (unsigned i = 0; i < NumElts; ++i) {
4927 if (M[i] < 0) continue; // ignore UNDEF indices
4928 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4935 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4936 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4937 // range, then 0 is placed into the resulting vector. So pretty much any mask
4938 // of 8 elements can work here.
4939 return VT == MVT::v8i8 && M.size() == 8;
4942 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4943 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4947 unsigned NumElts = VT.getVectorNumElements();
4948 WhichResult = (M[0] == 0 ? 0 : 1);
4949 for (unsigned i = 0; i < NumElts; i += 2) {
4950 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4951 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4957 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4958 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4959 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4960 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4961 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4965 unsigned NumElts = VT.getVectorNumElements();
4966 WhichResult = (M[0] == 0 ? 0 : 1);
4967 for (unsigned i = 0; i < NumElts; i += 2) {
4968 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4969 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4975 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4976 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4980 unsigned NumElts = VT.getVectorNumElements();
4981 WhichResult = (M[0] == 0 ? 0 : 1);
4982 for (unsigned i = 0; i != NumElts; ++i) {
4983 if (M[i] < 0) continue; // ignore UNDEF indices
4984 if ((unsigned) M[i] != 2 * i + WhichResult)
4988 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4989 if (VT.is64BitVector() && EltSz == 32)
4995 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4996 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4997 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4998 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4999 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5003 unsigned Half = VT.getVectorNumElements() / 2;
5004 WhichResult = (M[0] == 0 ? 0 : 1);
5005 for (unsigned j = 0; j != 2; ++j) {
5006 unsigned Idx = WhichResult;
5007 for (unsigned i = 0; i != Half; ++i) {
5008 int MIdx = M[i + j * Half];
5009 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5015 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5016 if (VT.is64BitVector() && EltSz == 32)
5022 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5023 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5027 unsigned NumElts = VT.getVectorNumElements();
5028 WhichResult = (M[0] == 0 ? 0 : 1);
5029 unsigned Idx = WhichResult * NumElts / 2;
5030 for (unsigned i = 0; i != NumElts; i += 2) {
5031 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5032 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
5037 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5038 if (VT.is64BitVector() && EltSz == 32)
5044 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5045 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5046 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5047 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5048 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5052 unsigned NumElts = VT.getVectorNumElements();
5053 WhichResult = (M[0] == 0 ? 0 : 1);
5054 unsigned Idx = WhichResult * NumElts / 2;
5055 for (unsigned i = 0; i != NumElts; i += 2) {
5056 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5057 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
5062 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5063 if (VT.is64BitVector() && EltSz == 32)
5069 /// \return true if this is a reverse operation on an vector.
5070 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5071 unsigned NumElts = VT.getVectorNumElements();
5072 // Make sure the mask has the right size.
5073 if (NumElts != M.size())
5076 // Look for <15, ..., 3, -1, 1, 0>.
5077 for (unsigned i = 0; i != NumElts; ++i)
5078 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5084 // If N is an integer constant that can be moved into a register in one
5085 // instruction, return an SDValue of such a constant (will become a MOV
5086 // instruction). Otherwise return null.
5087 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5088 const ARMSubtarget *ST, SDLoc dl) {
5090 if (!isa<ConstantSDNode>(N))
5092 Val = cast<ConstantSDNode>(N)->getZExtValue();
5094 if (ST->isThumb1Only()) {
5095 if (Val <= 255 || ~Val <= 255)
5096 return DAG.getConstant(Val, MVT::i32);
5098 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5099 return DAG.getConstant(Val, MVT::i32);
5104 // If this is a case we can't handle, return null and let the default
5105 // expansion code take care of it.
5106 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5107 const ARMSubtarget *ST) const {
5108 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5110 EVT VT = Op.getValueType();
5112 APInt SplatBits, SplatUndef;
5113 unsigned SplatBitSize;
5115 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5116 if (SplatBitSize <= 64) {
5117 // Check if an immediate VMOV works.
5119 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5120 SplatUndef.getZExtValue(), SplatBitSize,
5121 DAG, VmovVT, VT.is128BitVector(),
5123 if (Val.getNode()) {
5124 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5128 // Try an immediate VMVN.
5129 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5130 Val = isNEONModifiedImm(NegatedImm,
5131 SplatUndef.getZExtValue(), SplatBitSize,
5132 DAG, VmovVT, VT.is128BitVector(),
5134 if (Val.getNode()) {
5135 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5136 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5139 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5140 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5141 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5143 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
5144 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5150 // Scan through the operands to see if only one value is used.
5152 // As an optimisation, even if more than one value is used it may be more
5153 // profitable to splat with one value then change some lanes.
5155 // Heuristically we decide to do this if the vector has a "dominant" value,
5156 // defined as splatted to more than half of the lanes.
5157 unsigned NumElts = VT.getVectorNumElements();
5158 bool isOnlyLowElement = true;
5159 bool usesOnlyOneValue = true;
5160 bool hasDominantValue = false;
5161 bool isConstant = true;
5163 // Map of the number of times a particular SDValue appears in the
5165 DenseMap<SDValue, unsigned> ValueCounts;
5167 for (unsigned i = 0; i < NumElts; ++i) {
5168 SDValue V = Op.getOperand(i);
5169 if (V.getOpcode() == ISD::UNDEF)
5172 isOnlyLowElement = false;
5173 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5176 ValueCounts.insert(std::make_pair(V, 0));
5177 unsigned &Count = ValueCounts[V];
5179 // Is this value dominant? (takes up more than half of the lanes)
5180 if (++Count > (NumElts / 2)) {
5181 hasDominantValue = true;
5185 if (ValueCounts.size() != 1)
5186 usesOnlyOneValue = false;
5187 if (!Value.getNode() && ValueCounts.size() > 0)
5188 Value = ValueCounts.begin()->first;
5190 if (ValueCounts.size() == 0)
5191 return DAG.getUNDEF(VT);
5193 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5194 // Keep going if we are hitting this case.
5195 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5196 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5198 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5200 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5201 // i32 and try again.
5202 if (hasDominantValue && EltSize <= 32) {
5206 // If we are VDUPing a value that comes directly from a vector, that will
5207 // cause an unnecessary move to and from a GPR, where instead we could
5208 // just use VDUPLANE. We can only do this if the lane being extracted
5209 // is at a constant index, as the VDUP from lane instructions only have
5210 // constant-index forms.
5211 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5212 isa<ConstantSDNode>(Value->getOperand(1))) {
5213 // We need to create a new undef vector to use for the VDUPLANE if the
5214 // size of the vector from which we get the value is different than the
5215 // size of the vector that we need to create. We will insert the element
5216 // such that the register coalescer will remove unnecessary copies.
5217 if (VT != Value->getOperand(0).getValueType()) {
5218 ConstantSDNode *constIndex;
5219 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5220 assert(constIndex && "The index is not a constant!");
5221 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5222 VT.getVectorNumElements();
5223 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5224 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5225 Value, DAG.getConstant(index, MVT::i32)),
5226 DAG.getConstant(index, MVT::i32));
5228 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5229 Value->getOperand(0), Value->getOperand(1));
5231 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5233 if (!usesOnlyOneValue) {
5234 // The dominant value was splatted as 'N', but we now have to insert
5235 // all differing elements.
5236 for (unsigned I = 0; I < NumElts; ++I) {
5237 if (Op.getOperand(I) == Value)
5239 SmallVector<SDValue, 3> Ops;
5241 Ops.push_back(Op.getOperand(I));
5242 Ops.push_back(DAG.getConstant(I, MVT::i32));
5243 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5248 if (VT.getVectorElementType().isFloatingPoint()) {
5249 SmallVector<SDValue, 8> Ops;
5250 for (unsigned i = 0; i < NumElts; ++i)
5251 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5253 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5254 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5255 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5257 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5259 if (usesOnlyOneValue) {
5260 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5261 if (isConstant && Val.getNode())
5262 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5266 // If all elements are constants and the case above didn't get hit, fall back
5267 // to the default expansion, which will generate a load from the constant
5272 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5274 SDValue shuffle = ReconstructShuffle(Op, DAG);
5275 if (shuffle != SDValue())
5279 // Vectors with 32- or 64-bit elements can be built by directly assigning
5280 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5281 // will be legalized.
5282 if (EltSize >= 32) {
5283 // Do the expansion with floating-point types, since that is what the VFP
5284 // registers are defined to use, and since i64 is not legal.
5285 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5286 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5287 SmallVector<SDValue, 8> Ops;
5288 for (unsigned i = 0; i < NumElts; ++i)
5289 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5290 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5291 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5294 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5295 // know the default expansion would otherwise fall back on something even
5296 // worse. For a vector with one or two non-undef values, that's
5297 // scalar_to_vector for the elements followed by a shuffle (provided the
5298 // shuffle is valid for the target) and materialization element by element
5299 // on the stack followed by a load for everything else.
5300 if (!isConstant && !usesOnlyOneValue) {
5301 SDValue Vec = DAG.getUNDEF(VT);
5302 for (unsigned i = 0 ; i < NumElts; ++i) {
5303 SDValue V = Op.getOperand(i);
5304 if (V.getOpcode() == ISD::UNDEF)
5306 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
5307 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5315 // Gather data to see if the operation can be modelled as a
5316 // shuffle in combination with VEXTs.
5317 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5318 SelectionDAG &DAG) const {
5320 EVT VT = Op.getValueType();
5321 unsigned NumElts = VT.getVectorNumElements();
5323 SmallVector<SDValue, 2> SourceVecs;
5324 SmallVector<unsigned, 2> MinElts;
5325 SmallVector<unsigned, 2> MaxElts;
5327 for (unsigned i = 0; i < NumElts; ++i) {
5328 SDValue V = Op.getOperand(i);
5329 if (V.getOpcode() == ISD::UNDEF)
5331 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5332 // A shuffle can only come from building a vector from various
5333 // elements of other vectors.
5335 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5336 VT.getVectorElementType()) {
5337 // This code doesn't know how to handle shuffles where the vector
5338 // element types do not match (this happens because type legalization
5339 // promotes the return type of EXTRACT_VECTOR_ELT).
5340 // FIXME: It might be appropriate to extend this code to handle
5341 // mismatched types.
5345 // Record this extraction against the appropriate vector if possible...
5346 SDValue SourceVec = V.getOperand(0);
5347 // If the element number isn't a constant, we can't effectively
5348 // analyze what's going on.
5349 if (!isa<ConstantSDNode>(V.getOperand(1)))
5351 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5352 bool FoundSource = false;
5353 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5354 if (SourceVecs[j] == SourceVec) {
5355 if (MinElts[j] > EltNo)
5357 if (MaxElts[j] < EltNo)
5364 // Or record a new source if not...
5366 SourceVecs.push_back(SourceVec);
5367 MinElts.push_back(EltNo);
5368 MaxElts.push_back(EltNo);
5372 // Currently only do something sane when at most two source vectors
5374 if (SourceVecs.size() > 2)
5377 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5378 int VEXTOffsets[2] = {0, 0};
5380 // This loop extracts the usage patterns of the source vectors
5381 // and prepares appropriate SDValues for a shuffle if possible.
5382 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5383 if (SourceVecs[i].getValueType() == VT) {
5384 // No VEXT necessary
5385 ShuffleSrcs[i] = SourceVecs[i];
5388 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5389 // It probably isn't worth padding out a smaller vector just to
5390 // break it down again in a shuffle.
5394 // Since only 64-bit and 128-bit vectors are legal on ARM and
5395 // we've eliminated the other cases...
5396 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5397 "unexpected vector sizes in ReconstructShuffle");
5399 if (MaxElts[i] - MinElts[i] >= NumElts) {
5400 // Span too large for a VEXT to cope
5404 if (MinElts[i] >= NumElts) {
5405 // The extraction can just take the second half
5406 VEXTOffsets[i] = NumElts;
5407 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5409 DAG.getIntPtrConstant(NumElts));
5410 } else if (MaxElts[i] < NumElts) {
5411 // The extraction can just take the first half
5413 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5415 DAG.getIntPtrConstant(0));
5417 // An actual VEXT is needed
5418 VEXTOffsets[i] = MinElts[i];
5419 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5421 DAG.getIntPtrConstant(0));
5422 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5424 DAG.getIntPtrConstant(NumElts));
5425 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5426 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5430 SmallVector<int, 8> Mask;
5432 for (unsigned i = 0; i < NumElts; ++i) {
5433 SDValue Entry = Op.getOperand(i);
5434 if (Entry.getOpcode() == ISD::UNDEF) {
5439 SDValue ExtractVec = Entry.getOperand(0);
5440 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5441 .getOperand(1))->getSExtValue();
5442 if (ExtractVec == SourceVecs[0]) {
5443 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5445 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5449 // Final check before we try to produce nonsense...
5450 if (isShuffleMaskLegal(Mask, VT))
5451 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5457 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5458 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5459 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5460 /// are assumed to be legal.
5462 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5464 if (VT.getVectorNumElements() == 4 &&
5465 (VT.is128BitVector() || VT.is64BitVector())) {
5466 unsigned PFIndexes[4];
5467 for (unsigned i = 0; i != 4; ++i) {
5471 PFIndexes[i] = M[i];
5474 // Compute the index in the perfect shuffle table.
5475 unsigned PFTableIndex =
5476 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5477 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5478 unsigned Cost = (PFEntry >> 30);
5485 unsigned Imm, WhichResult;
5487 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5488 return (EltSize >= 32 ||
5489 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5490 isVREVMask(M, VT, 64) ||
5491 isVREVMask(M, VT, 32) ||
5492 isVREVMask(M, VT, 16) ||
5493 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5494 isVTBLMask(M, VT) ||
5495 isVTRNMask(M, VT, WhichResult) ||
5496 isVUZPMask(M, VT, WhichResult) ||
5497 isVZIPMask(M, VT, WhichResult) ||
5498 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5499 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5500 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5501 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5504 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5505 /// the specified operations to build the shuffle.
5506 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5507 SDValue RHS, SelectionDAG &DAG,
5509 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5510 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5511 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5514 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5523 OP_VUZPL, // VUZP, left result
5524 OP_VUZPR, // VUZP, right result
5525 OP_VZIPL, // VZIP, left result
5526 OP_VZIPR, // VZIP, right result
5527 OP_VTRNL, // VTRN, left result
5528 OP_VTRNR // VTRN, right result
5531 if (OpNum == OP_COPY) {
5532 if (LHSID == (1*9+2)*9+3) return LHS;
5533 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5537 SDValue OpLHS, OpRHS;
5538 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5539 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5540 EVT VT = OpLHS.getValueType();
5543 default: llvm_unreachable("Unknown shuffle opcode!");
5545 // VREV divides the vector in half and swaps within the half.
5546 if (VT.getVectorElementType() == MVT::i32 ||
5547 VT.getVectorElementType() == MVT::f32)
5548 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5549 // vrev <4 x i16> -> VREV32
5550 if (VT.getVectorElementType() == MVT::i16)
5551 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5552 // vrev <4 x i8> -> VREV16
5553 assert(VT.getVectorElementType() == MVT::i8);
5554 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5559 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5560 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5564 return DAG.getNode(ARMISD::VEXT, dl, VT,
5566 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5569 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5570 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5573 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5574 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5577 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5578 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5582 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5583 ArrayRef<int> ShuffleMask,
5584 SelectionDAG &DAG) {
5585 // Check to see if we can use the VTBL instruction.
5586 SDValue V1 = Op.getOperand(0);
5587 SDValue V2 = Op.getOperand(1);
5590 SmallVector<SDValue, 8> VTBLMask;
5591 for (ArrayRef<int>::iterator
5592 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5593 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5595 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5596 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5597 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5599 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5600 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5603 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5604 SelectionDAG &DAG) {
5606 SDValue OpLHS = Op.getOperand(0);
5607 EVT VT = OpLHS.getValueType();
5609 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5610 "Expect an v8i16/v16i8 type");
5611 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5612 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5613 // extract the first 8 bytes into the top double word and the last 8 bytes
5614 // into the bottom double word. The v8i16 case is similar.
5615 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5616 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5617 DAG.getConstant(ExtractNum, MVT::i32));
5620 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5621 SDValue V1 = Op.getOperand(0);
5622 SDValue V2 = Op.getOperand(1);
5624 EVT VT = Op.getValueType();
5625 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5627 // Convert shuffles that are directly supported on NEON to target-specific
5628 // DAG nodes, instead of keeping them as shuffles and matching them again
5629 // during code selection. This is more efficient and avoids the possibility
5630 // of inconsistencies between legalization and selection.
5631 // FIXME: floating-point vectors should be canonicalized to integer vectors
5632 // of the same time so that they get CSEd properly.
5633 ArrayRef<int> ShuffleMask = SVN->getMask();
5635 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5636 if (EltSize <= 32) {
5637 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5638 int Lane = SVN->getSplatIndex();
5639 // If this is undef splat, generate it via "just" vdup, if possible.
5640 if (Lane == -1) Lane = 0;
5642 // Test if V1 is a SCALAR_TO_VECTOR.
5643 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5644 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5646 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5647 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5649 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5650 !isa<ConstantSDNode>(V1.getOperand(0))) {
5651 bool IsScalarToVector = true;
5652 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5653 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5654 IsScalarToVector = false;
5657 if (IsScalarToVector)
5658 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5660 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5661 DAG.getConstant(Lane, MVT::i32));
5666 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5669 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5670 DAG.getConstant(Imm, MVT::i32));
5673 if (isVREVMask(ShuffleMask, VT, 64))
5674 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5675 if (isVREVMask(ShuffleMask, VT, 32))
5676 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5677 if (isVREVMask(ShuffleMask, VT, 16))
5678 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5680 if (V2->getOpcode() == ISD::UNDEF &&
5681 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5682 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5683 DAG.getConstant(Imm, MVT::i32));
5686 // Check for Neon shuffles that modify both input vectors in place.
5687 // If both results are used, i.e., if there are two shuffles with the same
5688 // source operands and with masks corresponding to both results of one of
5689 // these operations, DAG memoization will ensure that a single node is
5690 // used for both shuffles.
5691 unsigned WhichResult;
5692 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5693 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5694 V1, V2).getValue(WhichResult);
5695 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5696 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5697 V1, V2).getValue(WhichResult);
5698 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5699 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5700 V1, V2).getValue(WhichResult);
5702 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5703 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5704 V1, V1).getValue(WhichResult);
5705 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5706 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5707 V1, V1).getValue(WhichResult);
5708 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5709 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5710 V1, V1).getValue(WhichResult);
5713 // If the shuffle is not directly supported and it has 4 elements, use
5714 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5715 unsigned NumElts = VT.getVectorNumElements();
5717 unsigned PFIndexes[4];
5718 for (unsigned i = 0; i != 4; ++i) {
5719 if (ShuffleMask[i] < 0)
5722 PFIndexes[i] = ShuffleMask[i];
5725 // Compute the index in the perfect shuffle table.
5726 unsigned PFTableIndex =
5727 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5728 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5729 unsigned Cost = (PFEntry >> 30);
5732 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5735 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5736 if (EltSize >= 32) {
5737 // Do the expansion with floating-point types, since that is what the VFP
5738 // registers are defined to use, and since i64 is not legal.
5739 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5740 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5741 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5742 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5743 SmallVector<SDValue, 8> Ops;
5744 for (unsigned i = 0; i < NumElts; ++i) {
5745 if (ShuffleMask[i] < 0)
5746 Ops.push_back(DAG.getUNDEF(EltVT));
5748 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5749 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5750 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5753 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5754 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5757 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5758 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5760 if (VT == MVT::v8i8) {
5761 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5762 if (NewOp.getNode())
5769 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5770 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5771 SDValue Lane = Op.getOperand(2);
5772 if (!isa<ConstantSDNode>(Lane))
5778 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5779 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5780 SDValue Lane = Op.getOperand(1);
5781 if (!isa<ConstantSDNode>(Lane))
5784 SDValue Vec = Op.getOperand(0);
5785 if (Op.getValueType() == MVT::i32 &&
5786 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5788 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5794 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5795 // The only time a CONCAT_VECTORS operation can have legal types is when
5796 // two 64-bit vectors are concatenated to a 128-bit vector.
5797 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5798 "unexpected CONCAT_VECTORS");
5800 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5801 SDValue Op0 = Op.getOperand(0);
5802 SDValue Op1 = Op.getOperand(1);
5803 if (Op0.getOpcode() != ISD::UNDEF)
5804 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5805 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5806 DAG.getIntPtrConstant(0));
5807 if (Op1.getOpcode() != ISD::UNDEF)
5808 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5809 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5810 DAG.getIntPtrConstant(1));
5811 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5814 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5815 /// element has been zero/sign-extended, depending on the isSigned parameter,
5816 /// from an integer type half its size.
5817 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5819 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5820 EVT VT = N->getValueType(0);
5821 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5822 SDNode *BVN = N->getOperand(0).getNode();
5823 if (BVN->getValueType(0) != MVT::v4i32 ||
5824 BVN->getOpcode() != ISD::BUILD_VECTOR)
5826 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5827 unsigned HiElt = 1 - LoElt;
5828 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5829 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5830 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5831 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5832 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5835 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5836 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5839 if (Hi0->isNullValue() && Hi1->isNullValue())
5845 if (N->getOpcode() != ISD::BUILD_VECTOR)
5848 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5849 SDNode *Elt = N->getOperand(i).getNode();
5850 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5851 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5852 unsigned HalfSize = EltSize / 2;
5854 if (!isIntN(HalfSize, C->getSExtValue()))
5857 if (!isUIntN(HalfSize, C->getZExtValue()))
5868 /// isSignExtended - Check if a node is a vector value that is sign-extended
5869 /// or a constant BUILD_VECTOR with sign-extended elements.
5870 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5871 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5873 if (isExtendedBUILD_VECTOR(N, DAG, true))
5878 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5879 /// or a constant BUILD_VECTOR with zero-extended elements.
5880 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5881 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5883 if (isExtendedBUILD_VECTOR(N, DAG, false))
5888 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5889 if (OrigVT.getSizeInBits() >= 64)
5892 assert(OrigVT.isSimple() && "Expecting a simple value type");
5894 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5895 switch (OrigSimpleTy) {
5896 default: llvm_unreachable("Unexpected Vector Type");
5905 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5906 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5907 /// We insert the required extension here to get the vector to fill a D register.
5908 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5911 unsigned ExtOpcode) {
5912 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5913 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5914 // 64-bits we need to insert a new extension so that it will be 64-bits.
5915 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5916 if (OrigTy.getSizeInBits() >= 64)
5919 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5920 EVT NewVT = getExtensionTo64Bits(OrigTy);
5922 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5925 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5926 /// does not do any sign/zero extension. If the original vector is less
5927 /// than 64 bits, an appropriate extension will be added after the load to
5928 /// reach a total size of 64 bits. We have to add the extension separately
5929 /// because ARM does not have a sign/zero extending load for vectors.
5930 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5931 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5933 // The load already has the right type.
5934 if (ExtendedTy == LD->getMemoryVT())
5935 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5936 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5937 LD->isNonTemporal(), LD->isInvariant(),
5938 LD->getAlignment());
5940 // We need to create a zextload/sextload. We cannot just create a load
5941 // followed by a zext/zext node because LowerMUL is also run during normal
5942 // operation legalization where we can't create illegal types.
5943 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5944 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5945 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
5946 LD->isNonTemporal(), LD->getAlignment());
5949 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5950 /// extending load, or BUILD_VECTOR with extended elements, return the
5951 /// unextended value. The unextended vector should be 64 bits so that it can
5952 /// be used as an operand to a VMULL instruction. If the original vector size
5953 /// before extension is less than 64 bits we add a an extension to resize
5954 /// the vector to 64 bits.
5955 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5956 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5957 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5958 N->getOperand(0)->getValueType(0),
5962 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5963 return SkipLoadExtensionForVMULL(LD, DAG);
5965 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5966 // have been legalized as a BITCAST from v4i32.
5967 if (N->getOpcode() == ISD::BITCAST) {
5968 SDNode *BVN = N->getOperand(0).getNode();
5969 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5970 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5971 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5972 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5973 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5975 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5976 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5977 EVT VT = N->getValueType(0);
5978 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5979 unsigned NumElts = VT.getVectorNumElements();
5980 MVT TruncVT = MVT::getIntegerVT(EltSize);
5981 SmallVector<SDValue, 8> Ops;
5982 for (unsigned i = 0; i != NumElts; ++i) {
5983 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5984 const APInt &CInt = C->getAPIntValue();
5985 // Element types smaller than 32 bits are not legal, so use i32 elements.
5986 // The values are implicitly truncated so sext vs. zext doesn't matter.
5987 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5989 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5990 MVT::getVectorVT(TruncVT, NumElts), Ops);
5993 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5994 unsigned Opcode = N->getOpcode();
5995 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5996 SDNode *N0 = N->getOperand(0).getNode();
5997 SDNode *N1 = N->getOperand(1).getNode();
5998 return N0->hasOneUse() && N1->hasOneUse() &&
5999 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
6004 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
6005 unsigned Opcode = N->getOpcode();
6006 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6007 SDNode *N0 = N->getOperand(0).getNode();
6008 SDNode *N1 = N->getOperand(1).getNode();
6009 return N0->hasOneUse() && N1->hasOneUse() &&
6010 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6015 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6016 // Multiplications are only custom-lowered for 128-bit vectors so that
6017 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6018 EVT VT = Op.getValueType();
6019 assert(VT.is128BitVector() && VT.isInteger() &&
6020 "unexpected type for custom-lowering ISD::MUL");
6021 SDNode *N0 = Op.getOperand(0).getNode();
6022 SDNode *N1 = Op.getOperand(1).getNode();
6023 unsigned NewOpc = 0;
6025 bool isN0SExt = isSignExtended(N0, DAG);
6026 bool isN1SExt = isSignExtended(N1, DAG);
6027 if (isN0SExt && isN1SExt)
6028 NewOpc = ARMISD::VMULLs;
6030 bool isN0ZExt = isZeroExtended(N0, DAG);
6031 bool isN1ZExt = isZeroExtended(N1, DAG);
6032 if (isN0ZExt && isN1ZExt)
6033 NewOpc = ARMISD::VMULLu;
6034 else if (isN1SExt || isN1ZExt) {
6035 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6036 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6037 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6038 NewOpc = ARMISD::VMULLs;
6040 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6041 NewOpc = ARMISD::VMULLu;
6043 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6045 NewOpc = ARMISD::VMULLu;
6051 if (VT == MVT::v2i64)
6052 // Fall through to expand this. It is not legal.
6055 // Other vector multiplications are legal.
6060 // Legalize to a VMULL instruction.
6063 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6065 Op0 = SkipExtensionForVMULL(N0, DAG);
6066 assert(Op0.getValueType().is64BitVector() &&
6067 Op1.getValueType().is64BitVector() &&
6068 "unexpected types for extended operands to VMULL");
6069 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6072 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6073 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6080 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6081 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6082 EVT Op1VT = Op1.getValueType();
6083 return DAG.getNode(N0->getOpcode(), DL, VT,
6084 DAG.getNode(NewOpc, DL, VT,
6085 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6086 DAG.getNode(NewOpc, DL, VT,
6087 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6091 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6093 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6094 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6095 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6096 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6097 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6098 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6099 // Get reciprocal estimate.
6100 // float4 recip = vrecpeq_f32(yf);
6101 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6102 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
6103 // Because char has a smaller range than uchar, we can actually get away
6104 // without any newton steps. This requires that we use a weird bias
6105 // of 0xb000, however (again, this has been exhaustively tested).
6106 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6107 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6108 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6109 Y = DAG.getConstant(0xb000, MVT::i32);
6110 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6111 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6112 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6113 // Convert back to short.
6114 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6115 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6120 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6122 // Convert to float.
6123 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6124 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6125 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6126 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6127 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6128 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6130 // Use reciprocal estimate and one refinement step.
6131 // float4 recip = vrecpeq_f32(yf);
6132 // recip *= vrecpsq_f32(yf, recip);
6133 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6134 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
6135 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6136 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6138 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6139 // Because short has a smaller range than ushort, we can actually get away
6140 // with only a single newton step. This requires that we use a weird bias
6141 // of 89, however (again, this has been exhaustively tested).
6142 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6143 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6144 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6145 N1 = DAG.getConstant(0x89, MVT::i32);
6146 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6147 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6148 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6149 // Convert back to integer and return.
6150 // return vmovn_s32(vcvt_s32_f32(result));
6151 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6152 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6156 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6157 EVT VT = Op.getValueType();
6158 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6159 "unexpected type for custom-lowering ISD::SDIV");
6162 SDValue N0 = Op.getOperand(0);
6163 SDValue N1 = Op.getOperand(1);
6166 if (VT == MVT::v8i8) {
6167 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6168 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6170 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6171 DAG.getIntPtrConstant(4));
6172 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6173 DAG.getIntPtrConstant(4));
6174 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6175 DAG.getIntPtrConstant(0));
6176 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6177 DAG.getIntPtrConstant(0));
6179 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6180 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6182 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6183 N0 = LowerCONCAT_VECTORS(N0, DAG);
6185 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6188 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6191 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6192 EVT VT = Op.getValueType();
6193 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6194 "unexpected type for custom-lowering ISD::UDIV");
6197 SDValue N0 = Op.getOperand(0);
6198 SDValue N1 = Op.getOperand(1);
6201 if (VT == MVT::v8i8) {
6202 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6203 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6205 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6206 DAG.getIntPtrConstant(4));
6207 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6208 DAG.getIntPtrConstant(4));
6209 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6210 DAG.getIntPtrConstant(0));
6211 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6212 DAG.getIntPtrConstant(0));
6214 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6215 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6217 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6218 N0 = LowerCONCAT_VECTORS(N0, DAG);
6220 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6221 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
6226 // v4i16 sdiv ... Convert to float.
6227 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6228 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6229 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6230 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6231 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6232 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6234 // Use reciprocal estimate and two refinement steps.
6235 // float4 recip = vrecpeq_f32(yf);
6236 // recip *= vrecpsq_f32(yf, recip);
6237 // recip *= vrecpsq_f32(yf, recip);
6238 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6239 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
6240 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6241 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6243 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6244 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6245 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
6247 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6248 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6249 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6250 // and that it will never cause us to return an answer too large).
6251 // float4 result = as_float4(as_int4(xf*recip) + 2);
6252 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6253 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6254 N1 = DAG.getConstant(2, MVT::i32);
6255 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6256 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6257 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6258 // Convert back to integer and return.
6259 // return vmovn_u32(vcvt_s32_f32(result));
6260 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6261 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6265 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6266 EVT VT = Op.getNode()->getValueType(0);
6267 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6270 bool ExtraOp = false;
6271 switch (Op.getOpcode()) {
6272 default: llvm_unreachable("Invalid code");
6273 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6274 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6275 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6276 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6280 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6282 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6283 Op.getOperand(1), Op.getOperand(2));
6286 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6287 assert(Subtarget->isTargetDarwin());
6289 // For iOS, we want to call an alternative entry point: __sincos_stret,
6290 // return values are passed via sret.
6292 SDValue Arg = Op.getOperand(0);
6293 EVT ArgVT = Arg.getValueType();
6294 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6296 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6299 // Pair of floats / doubles used to pass the result.
6300 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
6302 // Create stack object for sret.
6303 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6304 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6305 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6306 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6312 Entry.Ty = RetTy->getPointerTo();
6313 Entry.isSExt = false;
6314 Entry.isZExt = false;
6315 Entry.isSRet = true;
6316 Args.push_back(Entry);
6320 Entry.isSExt = false;
6321 Entry.isZExt = false;
6322 Args.push_back(Entry);
6324 const char *LibcallName = (ArgVT == MVT::f64)
6325 ? "__sincos_stret" : "__sincosf_stret";
6326 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6328 TargetLowering::CallLoweringInfo CLI(DAG);
6329 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6330 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6332 .setDiscardResult();
6334 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6336 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6337 MachinePointerInfo(), false, false, false, 0);
6339 // Address of cos field.
6340 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6341 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
6342 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6343 MachinePointerInfo(), false, false, false, 0);
6345 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6346 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6347 LoadSin.getValue(0), LoadCos.getValue(0));
6350 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6351 // Monotonic load/store is legal for all targets
6352 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6355 // Acquire/Release load/store is not legal for targets without a
6356 // dmb or equivalent available.
6360 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6361 SmallVectorImpl<SDValue> &Results,
6363 const ARMSubtarget *Subtarget) {
6365 SDValue Cycles32, OutChain;
6367 if (Subtarget->hasPerfMon()) {
6368 // Under Power Management extensions, the cycle-count is:
6369 // mrc p15, #0, <Rt>, c9, c13, #0
6370 SDValue Ops[] = { N->getOperand(0), // Chain
6371 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6372 DAG.getConstant(15, MVT::i32),
6373 DAG.getConstant(0, MVT::i32),
6374 DAG.getConstant(9, MVT::i32),
6375 DAG.getConstant(13, MVT::i32),
6376 DAG.getConstant(0, MVT::i32)
6379 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6380 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6381 OutChain = Cycles32.getValue(1);
6383 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6384 // there are older ARM CPUs that have implementation-specific ways of
6385 // obtaining this information (FIXME!).
6386 Cycles32 = DAG.getConstant(0, MVT::i32);
6387 OutChain = DAG.getEntryNode();
6391 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6392 Cycles32, DAG.getConstant(0, MVT::i32));
6393 Results.push_back(Cycles64);
6394 Results.push_back(OutChain);
6397 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6398 switch (Op.getOpcode()) {
6399 default: llvm_unreachable("Don't know how to custom lower this!");
6400 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6401 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6402 case ISD::GlobalAddress:
6403 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6404 default: llvm_unreachable("unknown object format");
6406 return LowerGlobalAddressWindows(Op, DAG);
6408 return LowerGlobalAddressELF(Op, DAG);
6410 return LowerGlobalAddressDarwin(Op, DAG);
6412 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6413 case ISD::SELECT: return LowerSELECT(Op, DAG);
6414 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6415 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6416 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6417 case ISD::VASTART: return LowerVASTART(Op, DAG);
6418 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6419 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6420 case ISD::SINT_TO_FP:
6421 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6422 case ISD::FP_TO_SINT:
6423 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6424 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6425 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6426 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6427 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6428 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6429 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6430 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6432 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6435 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6436 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6437 case ISD::SRL_PARTS:
6438 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6439 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6440 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6441 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6442 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6443 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6444 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6445 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6446 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6447 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6448 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6449 case ISD::MUL: return LowerMUL(Op, DAG);
6450 case ISD::SDIV: return LowerSDIV(Op, DAG);
6451 case ISD::UDIV: return LowerUDIV(Op, DAG);
6455 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6460 return LowerXALUO(Op, DAG);
6461 case ISD::ATOMIC_LOAD:
6462 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6463 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6465 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6466 case ISD::DYNAMIC_STACKALLOC:
6467 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6468 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6469 llvm_unreachable("Don't know how to custom lower this!");
6470 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6471 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6475 /// ReplaceNodeResults - Replace the results of node with an illegal result
6476 /// type with new values built out of custom code.
6477 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6478 SmallVectorImpl<SDValue>&Results,
6479 SelectionDAG &DAG) const {
6481 switch (N->getOpcode()) {
6483 llvm_unreachable("Don't know how to custom expand this!");
6485 Res = ExpandBITCAST(N, DAG);
6489 Res = Expand64BitShift(N, DAG, Subtarget);
6491 case ISD::READCYCLECOUNTER:
6492 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6496 Results.push_back(Res);
6499 //===----------------------------------------------------------------------===//
6500 // ARM Scheduler Hooks
6501 //===----------------------------------------------------------------------===//
6503 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6504 /// registers the function context.
6505 void ARMTargetLowering::
6506 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6507 MachineBasicBlock *DispatchBB, int FI) const {
6508 const TargetInstrInfo *TII =
6509 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6510 DebugLoc dl = MI->getDebugLoc();
6511 MachineFunction *MF = MBB->getParent();
6512 MachineRegisterInfo *MRI = &MF->getRegInfo();
6513 MachineConstantPool *MCP = MF->getConstantPool();
6514 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6515 const Function *F = MF->getFunction();
6517 bool isThumb = Subtarget->isThumb();
6518 bool isThumb2 = Subtarget->isThumb2();
6520 unsigned PCLabelId = AFI->createPICLabelUId();
6521 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6522 ARMConstantPoolValue *CPV =
6523 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6524 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6526 const TargetRegisterClass *TRC = isThumb ?
6527 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6528 (const TargetRegisterClass*)&ARM::GPRRegClass;
6530 // Grab constant pool and fixed stack memory operands.
6531 MachineMemOperand *CPMMO =
6532 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6533 MachineMemOperand::MOLoad, 4, 4);
6535 MachineMemOperand *FIMMOSt =
6536 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6537 MachineMemOperand::MOStore, 4, 4);
6539 // Load the address of the dispatch MBB into the jump buffer.
6541 // Incoming value: jbuf
6542 // ldr.n r5, LCPI1_1
6545 // str r5, [$jbuf, #+4] ; &jbuf[1]
6546 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6547 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6548 .addConstantPoolIndex(CPI)
6549 .addMemOperand(CPMMO));
6550 // Set the low bit because of thumb mode.
6551 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6553 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6554 .addReg(NewVReg1, RegState::Kill)
6556 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6557 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6558 .addReg(NewVReg2, RegState::Kill)
6560 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6561 .addReg(NewVReg3, RegState::Kill)
6563 .addImm(36) // &jbuf[1] :: pc
6564 .addMemOperand(FIMMOSt));
6565 } else if (isThumb) {
6566 // Incoming value: jbuf
6567 // ldr.n r1, LCPI1_4
6571 // add r2, $jbuf, #+4 ; &jbuf[1]
6573 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6574 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6575 .addConstantPoolIndex(CPI)
6576 .addMemOperand(CPMMO));
6577 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6578 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6579 .addReg(NewVReg1, RegState::Kill)
6581 // Set the low bit because of thumb mode.
6582 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6583 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6584 .addReg(ARM::CPSR, RegState::Define)
6586 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6587 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6588 .addReg(ARM::CPSR, RegState::Define)
6589 .addReg(NewVReg2, RegState::Kill)
6590 .addReg(NewVReg3, RegState::Kill));
6591 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6592 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6594 .addImm(36); // &jbuf[1] :: pc
6595 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6596 .addReg(NewVReg4, RegState::Kill)
6597 .addReg(NewVReg5, RegState::Kill)
6599 .addMemOperand(FIMMOSt));
6601 // Incoming value: jbuf
6604 // str r1, [$jbuf, #+4] ; &jbuf[1]
6605 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6606 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6607 .addConstantPoolIndex(CPI)
6609 .addMemOperand(CPMMO));
6610 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6611 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6612 .addReg(NewVReg1, RegState::Kill)
6613 .addImm(PCLabelId));
6614 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6615 .addReg(NewVReg2, RegState::Kill)
6617 .addImm(36) // &jbuf[1] :: pc
6618 .addMemOperand(FIMMOSt));
6622 MachineBasicBlock *ARMTargetLowering::
6623 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6624 const TargetInstrInfo *TII =
6625 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6626 DebugLoc dl = MI->getDebugLoc();
6627 MachineFunction *MF = MBB->getParent();
6628 MachineRegisterInfo *MRI = &MF->getRegInfo();
6629 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6630 MachineFrameInfo *MFI = MF->getFrameInfo();
6631 int FI = MFI->getFunctionContextIndex();
6633 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6634 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6635 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6637 // Get a mapping of the call site numbers to all of the landing pads they're
6639 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6640 unsigned MaxCSNum = 0;
6641 MachineModuleInfo &MMI = MF->getMMI();
6642 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6644 if (!BB->isLandingPad()) continue;
6646 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6648 for (MachineBasicBlock::iterator
6649 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6650 if (!II->isEHLabel()) continue;
6652 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6653 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6655 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6656 for (SmallVectorImpl<unsigned>::iterator
6657 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6658 CSI != CSE; ++CSI) {
6659 CallSiteNumToLPad[*CSI].push_back(BB);
6660 MaxCSNum = std::max(MaxCSNum, *CSI);
6666 // Get an ordered list of the machine basic blocks for the jump table.
6667 std::vector<MachineBasicBlock*> LPadList;
6668 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6669 LPadList.reserve(CallSiteNumToLPad.size());
6670 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6671 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6672 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6673 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6674 LPadList.push_back(*II);
6675 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6679 assert(!LPadList.empty() &&
6680 "No landing pad destinations for the dispatch jump table!");
6682 // Create the jump table and associated information.
6683 MachineJumpTableInfo *JTI =
6684 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6685 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6686 unsigned UId = AFI->createJumpTableUId();
6687 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6689 // Create the MBBs for the dispatch code.
6691 // Shove the dispatch's address into the return slot in the function context.
6692 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6693 DispatchBB->setIsLandingPad();
6695 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6696 unsigned trap_opcode;
6697 if (Subtarget->isThumb())
6698 trap_opcode = ARM::tTRAP;
6700 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6702 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6703 DispatchBB->addSuccessor(TrapBB);
6705 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6706 DispatchBB->addSuccessor(DispContBB);
6709 MF->insert(MF->end(), DispatchBB);
6710 MF->insert(MF->end(), DispContBB);
6711 MF->insert(MF->end(), TrapBB);
6713 // Insert code into the entry block that creates and registers the function
6715 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6717 MachineMemOperand *FIMMOLd =
6718 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6719 MachineMemOperand::MOLoad |
6720 MachineMemOperand::MOVolatile, 4, 4);
6722 MachineInstrBuilder MIB;
6723 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6725 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6726 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6728 // Add a register mask with no preserved registers. This results in all
6729 // registers being marked as clobbered.
6730 MIB.addRegMask(RI.getNoPreservedMask());
6732 unsigned NumLPads = LPadList.size();
6733 if (Subtarget->isThumb2()) {
6734 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6735 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6738 .addMemOperand(FIMMOLd));
6740 if (NumLPads < 256) {
6741 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6743 .addImm(LPadList.size()));
6745 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6746 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6747 .addImm(NumLPads & 0xFFFF));
6749 unsigned VReg2 = VReg1;
6750 if ((NumLPads & 0xFFFF0000) != 0) {
6751 VReg2 = MRI->createVirtualRegister(TRC);
6752 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6754 .addImm(NumLPads >> 16));
6757 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6762 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6767 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6768 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6769 .addJumpTableIndex(MJTI)
6772 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6775 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6776 .addReg(NewVReg3, RegState::Kill)
6778 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6780 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6781 .addReg(NewVReg4, RegState::Kill)
6783 .addJumpTableIndex(MJTI)
6785 } else if (Subtarget->isThumb()) {
6786 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6787 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6790 .addMemOperand(FIMMOLd));
6792 if (NumLPads < 256) {
6793 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6797 MachineConstantPool *ConstantPool = MF->getConstantPool();
6798 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6799 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6801 // MachineConstantPool wants an explicit alignment.
6802 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6804 Align = getDataLayout()->getTypeAllocSize(C->getType());
6805 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6807 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6808 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6809 .addReg(VReg1, RegState::Define)
6810 .addConstantPoolIndex(Idx));
6811 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6816 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6821 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6822 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6823 .addReg(ARM::CPSR, RegState::Define)
6827 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6828 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6829 .addJumpTableIndex(MJTI)
6832 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6833 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6834 .addReg(ARM::CPSR, RegState::Define)
6835 .addReg(NewVReg2, RegState::Kill)
6838 MachineMemOperand *JTMMOLd =
6839 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6840 MachineMemOperand::MOLoad, 4, 4);
6842 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6843 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6844 .addReg(NewVReg4, RegState::Kill)
6846 .addMemOperand(JTMMOLd));
6848 unsigned NewVReg6 = NewVReg5;
6849 if (RelocM == Reloc::PIC_) {
6850 NewVReg6 = MRI->createVirtualRegister(TRC);
6851 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6852 .addReg(ARM::CPSR, RegState::Define)
6853 .addReg(NewVReg5, RegState::Kill)
6857 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6858 .addReg(NewVReg6, RegState::Kill)
6859 .addJumpTableIndex(MJTI)
6862 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6863 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6866 .addMemOperand(FIMMOLd));
6868 if (NumLPads < 256) {
6869 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6872 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6873 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6874 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6875 .addImm(NumLPads & 0xFFFF));
6877 unsigned VReg2 = VReg1;
6878 if ((NumLPads & 0xFFFF0000) != 0) {
6879 VReg2 = MRI->createVirtualRegister(TRC);
6880 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6882 .addImm(NumLPads >> 16));
6885 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6889 MachineConstantPool *ConstantPool = MF->getConstantPool();
6890 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6891 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6893 // MachineConstantPool wants an explicit alignment.
6894 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6896 Align = getDataLayout()->getTypeAllocSize(C->getType());
6897 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6899 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6900 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6901 .addReg(VReg1, RegState::Define)
6902 .addConstantPoolIndex(Idx)
6904 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6906 .addReg(VReg1, RegState::Kill));
6909 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6914 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6916 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6918 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6919 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6920 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6921 .addJumpTableIndex(MJTI)
6924 MachineMemOperand *JTMMOLd =
6925 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6926 MachineMemOperand::MOLoad, 4, 4);
6927 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6929 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6930 .addReg(NewVReg3, RegState::Kill)
6933 .addMemOperand(JTMMOLd));
6935 if (RelocM == Reloc::PIC_) {
6936 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6937 .addReg(NewVReg5, RegState::Kill)
6939 .addJumpTableIndex(MJTI)
6942 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6943 .addReg(NewVReg5, RegState::Kill)
6944 .addJumpTableIndex(MJTI)
6949 // Add the jump table entries as successors to the MBB.
6950 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6951 for (std::vector<MachineBasicBlock*>::iterator
6952 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6953 MachineBasicBlock *CurMBB = *I;
6954 if (SeenMBBs.insert(CurMBB))
6955 DispContBB->addSuccessor(CurMBB);
6958 // N.B. the order the invoke BBs are processed in doesn't matter here.
6959 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6960 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6961 for (MachineBasicBlock *BB : InvokeBBs) {
6963 // Remove the landing pad successor from the invoke block and replace it
6964 // with the new dispatch block.
6965 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6967 while (!Successors.empty()) {
6968 MachineBasicBlock *SMBB = Successors.pop_back_val();
6969 if (SMBB->isLandingPad()) {
6970 BB->removeSuccessor(SMBB);
6971 MBBLPads.push_back(SMBB);
6975 BB->addSuccessor(DispatchBB);
6977 // Find the invoke call and mark all of the callee-saved registers as
6978 // 'implicit defined' so that they're spilled. This prevents code from
6979 // moving instructions to before the EH block, where they will never be
6981 for (MachineBasicBlock::reverse_iterator
6982 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6983 if (!II->isCall()) continue;
6985 DenseMap<unsigned, bool> DefRegs;
6986 for (MachineInstr::mop_iterator
6987 OI = II->operands_begin(), OE = II->operands_end();
6989 if (!OI->isReg()) continue;
6990 DefRegs[OI->getReg()] = true;
6993 MachineInstrBuilder MIB(*MF, &*II);
6995 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6996 unsigned Reg = SavedRegs[i];
6997 if (Subtarget->isThumb2() &&
6998 !ARM::tGPRRegClass.contains(Reg) &&
6999 !ARM::hGPRRegClass.contains(Reg))
7001 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
7003 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7006 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7013 // Mark all former landing pads as non-landing pads. The dispatch is the only
7015 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7016 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7017 (*I)->setIsLandingPad(false);
7019 // The instruction is gone now.
7020 MI->eraseFromParent();
7026 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7027 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7028 E = MBB->succ_end(); I != E; ++I)
7031 llvm_unreachable("Expecting a BB with two successors!");
7034 /// Return the load opcode for a given load size. If load size >= 8,
7035 /// neon opcode will be returned.
7036 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7038 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7039 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7041 return LdSize == 4 ? ARM::tLDRi
7042 : LdSize == 2 ? ARM::tLDRHi
7043 : LdSize == 1 ? ARM::tLDRBi : 0;
7045 return LdSize == 4 ? ARM::t2LDR_POST
7046 : LdSize == 2 ? ARM::t2LDRH_POST
7047 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7048 return LdSize == 4 ? ARM::LDR_POST_IMM
7049 : LdSize == 2 ? ARM::LDRH_POST
7050 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7053 /// Return the store opcode for a given store size. If store size >= 8,
7054 /// neon opcode will be returned.
7055 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7057 return StSize == 16 ? ARM::VST1q32wb_fixed
7058 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7060 return StSize == 4 ? ARM::tSTRi
7061 : StSize == 2 ? ARM::tSTRHi
7062 : StSize == 1 ? ARM::tSTRBi : 0;
7064 return StSize == 4 ? ARM::t2STR_POST
7065 : StSize == 2 ? ARM::t2STRH_POST
7066 : StSize == 1 ? ARM::t2STRB_POST : 0;
7067 return StSize == 4 ? ARM::STR_POST_IMM
7068 : StSize == 2 ? ARM::STRH_POST
7069 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7072 /// Emit a post-increment load operation with given size. The instructions
7073 /// will be added to BB at Pos.
7074 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7075 const TargetInstrInfo *TII, DebugLoc dl,
7076 unsigned LdSize, unsigned Data, unsigned AddrIn,
7077 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7078 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7079 assert(LdOpc != 0 && "Should have a load opcode");
7081 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7082 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7084 } else if (IsThumb1) {
7085 // load + update AddrIn
7086 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7087 .addReg(AddrIn).addImm(0));
7088 MachineInstrBuilder MIB =
7089 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7090 MIB = AddDefaultT1CC(MIB);
7091 MIB.addReg(AddrIn).addImm(LdSize);
7092 AddDefaultPred(MIB);
7093 } else if (IsThumb2) {
7094 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7095 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7098 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7099 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7100 .addReg(0).addImm(LdSize));
7104 /// Emit a post-increment store operation with given size. The instructions
7105 /// will be added to BB at Pos.
7106 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7107 const TargetInstrInfo *TII, DebugLoc dl,
7108 unsigned StSize, unsigned Data, unsigned AddrIn,
7109 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7110 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7111 assert(StOpc != 0 && "Should have a store opcode");
7113 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7114 .addReg(AddrIn).addImm(0).addReg(Data));
7115 } else if (IsThumb1) {
7116 // store + update AddrIn
7117 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7118 .addReg(AddrIn).addImm(0));
7119 MachineInstrBuilder MIB =
7120 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7121 MIB = AddDefaultT1CC(MIB);
7122 MIB.addReg(AddrIn).addImm(StSize);
7123 AddDefaultPred(MIB);
7124 } else if (IsThumb2) {
7125 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7126 .addReg(Data).addReg(AddrIn).addImm(StSize));
7128 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7129 .addReg(Data).addReg(AddrIn).addReg(0)
7135 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7136 MachineBasicBlock *BB) const {
7137 // This pseudo instruction has 3 operands: dst, src, size
7138 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7139 // Otherwise, we will generate unrolled scalar copies.
7140 const TargetInstrInfo *TII =
7141 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7142 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7143 MachineFunction::iterator It = BB;
7146 unsigned dest = MI->getOperand(0).getReg();
7147 unsigned src = MI->getOperand(1).getReg();
7148 unsigned SizeVal = MI->getOperand(2).getImm();
7149 unsigned Align = MI->getOperand(3).getImm();
7150 DebugLoc dl = MI->getDebugLoc();
7152 MachineFunction *MF = BB->getParent();
7153 MachineRegisterInfo &MRI = MF->getRegInfo();
7154 unsigned UnitSize = 0;
7155 const TargetRegisterClass *TRC = nullptr;
7156 const TargetRegisterClass *VecTRC = nullptr;
7158 bool IsThumb1 = Subtarget->isThumb1Only();
7159 bool IsThumb2 = Subtarget->isThumb2();
7163 } else if (Align & 2) {
7166 // Check whether we can use NEON instructions.
7167 if (!MF->getFunction()->getAttributes().
7168 hasAttribute(AttributeSet::FunctionIndex,
7169 Attribute::NoImplicitFloat) &&
7170 Subtarget->hasNEON()) {
7171 if ((Align % 16 == 0) && SizeVal >= 16)
7173 else if ((Align % 8 == 0) && SizeVal >= 8)
7176 // Can't use NEON instructions.
7181 // Select the correct opcode and register class for unit size load/store
7182 bool IsNeon = UnitSize >= 8;
7183 TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
7184 : (const TargetRegisterClass *)&ARM::GPRRegClass;
7186 VecTRC = UnitSize == 16
7187 ? (const TargetRegisterClass *)&ARM::DPairRegClass
7189 ? (const TargetRegisterClass *)&ARM::DPRRegClass
7192 unsigned BytesLeft = SizeVal % UnitSize;
7193 unsigned LoopSize = SizeVal - BytesLeft;
7195 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7196 // Use LDR and STR to copy.
7197 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7198 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7199 unsigned srcIn = src;
7200 unsigned destIn = dest;
7201 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7202 unsigned srcOut = MRI.createVirtualRegister(TRC);
7203 unsigned destOut = MRI.createVirtualRegister(TRC);
7204 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7205 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7206 IsThumb1, IsThumb2);
7207 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7208 IsThumb1, IsThumb2);
7213 // Handle the leftover bytes with LDRB and STRB.
7214 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7215 // [destOut] = STRB_POST(scratch, destIn, 1)
7216 for (unsigned i = 0; i < BytesLeft; i++) {
7217 unsigned srcOut = MRI.createVirtualRegister(TRC);
7218 unsigned destOut = MRI.createVirtualRegister(TRC);
7219 unsigned scratch = MRI.createVirtualRegister(TRC);
7220 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7221 IsThumb1, IsThumb2);
7222 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7223 IsThumb1, IsThumb2);
7227 MI->eraseFromParent(); // The instruction is gone now.
7231 // Expand the pseudo op to a loop.
7234 // movw varEnd, # --> with thumb2
7236 // ldrcp varEnd, idx --> without thumb2
7237 // fallthrough --> loopMBB
7239 // PHI varPhi, varEnd, varLoop
7240 // PHI srcPhi, src, srcLoop
7241 // PHI destPhi, dst, destLoop
7242 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7243 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7244 // subs varLoop, varPhi, #UnitSize
7246 // fallthrough --> exitMBB
7248 // epilogue to handle left-over bytes
7249 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7250 // [destOut] = STRB_POST(scratch, destLoop, 1)
7251 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7252 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7253 MF->insert(It, loopMBB);
7254 MF->insert(It, exitMBB);
7256 // Transfer the remainder of BB and its successor edges to exitMBB.
7257 exitMBB->splice(exitMBB->begin(), BB,
7258 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7259 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7261 // Load an immediate to varEnd.
7262 unsigned varEnd = MRI.createVirtualRegister(TRC);
7264 unsigned Vtmp = varEnd;
7265 if ((LoopSize & 0xFFFF0000) != 0)
7266 Vtmp = MRI.createVirtualRegister(TRC);
7267 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7268 .addImm(LoopSize & 0xFFFF));
7270 if ((LoopSize & 0xFFFF0000) != 0)
7271 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7272 .addReg(Vtmp).addImm(LoopSize >> 16));
7274 MachineConstantPool *ConstantPool = MF->getConstantPool();
7275 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7276 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7278 // MachineConstantPool wants an explicit alignment.
7279 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7281 Align = getDataLayout()->getTypeAllocSize(C->getType());
7282 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7285 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7286 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7288 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7289 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7291 BB->addSuccessor(loopMBB);
7293 // Generate the loop body:
7294 // varPhi = PHI(varLoop, varEnd)
7295 // srcPhi = PHI(srcLoop, src)
7296 // destPhi = PHI(destLoop, dst)
7297 MachineBasicBlock *entryBB = BB;
7299 unsigned varLoop = MRI.createVirtualRegister(TRC);
7300 unsigned varPhi = MRI.createVirtualRegister(TRC);
7301 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7302 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7303 unsigned destLoop = MRI.createVirtualRegister(TRC);
7304 unsigned destPhi = MRI.createVirtualRegister(TRC);
7306 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7307 .addReg(varLoop).addMBB(loopMBB)
7308 .addReg(varEnd).addMBB(entryBB);
7309 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7310 .addReg(srcLoop).addMBB(loopMBB)
7311 .addReg(src).addMBB(entryBB);
7312 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7313 .addReg(destLoop).addMBB(loopMBB)
7314 .addReg(dest).addMBB(entryBB);
7316 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7317 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7318 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7319 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7320 IsThumb1, IsThumb2);
7321 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7322 IsThumb1, IsThumb2);
7324 // Decrement loop variable by UnitSize.
7326 MachineInstrBuilder MIB =
7327 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7328 MIB = AddDefaultT1CC(MIB);
7329 MIB.addReg(varPhi).addImm(UnitSize);
7330 AddDefaultPred(MIB);
7332 MachineInstrBuilder MIB =
7333 BuildMI(*BB, BB->end(), dl,
7334 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7335 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7336 MIB->getOperand(5).setReg(ARM::CPSR);
7337 MIB->getOperand(5).setIsDef(true);
7339 BuildMI(*BB, BB->end(), dl,
7340 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7341 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7343 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7344 BB->addSuccessor(loopMBB);
7345 BB->addSuccessor(exitMBB);
7347 // Add epilogue to handle BytesLeft.
7349 MachineInstr *StartOfExit = exitMBB->begin();
7351 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7352 // [destOut] = STRB_POST(scratch, destLoop, 1)
7353 unsigned srcIn = srcLoop;
7354 unsigned destIn = destLoop;
7355 for (unsigned i = 0; i < BytesLeft; i++) {
7356 unsigned srcOut = MRI.createVirtualRegister(TRC);
7357 unsigned destOut = MRI.createVirtualRegister(TRC);
7358 unsigned scratch = MRI.createVirtualRegister(TRC);
7359 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7360 IsThumb1, IsThumb2);
7361 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7362 IsThumb1, IsThumb2);
7367 MI->eraseFromParent(); // The instruction is gone now.
7372 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7373 MachineBasicBlock *MBB) const {
7374 const TargetMachine &TM = getTargetMachine();
7375 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
7376 DebugLoc DL = MI->getDebugLoc();
7378 assert(Subtarget->isTargetWindows() &&
7379 "__chkstk is only supported on Windows");
7380 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7382 // __chkstk takes the number of words to allocate on the stack in R4, and
7383 // returns the stack adjustment in number of bytes in R4. This will not
7384 // clober any other registers (other than the obvious lr).
7386 // Although, technically, IP should be considered a register which may be
7387 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7388 // thumb-2 environment, so there is no interworking required. As a result, we
7389 // do not expect a veneer to be emitted by the linker, clobbering IP.
7391 // Each module receives its own copy of __chkstk, so no import thunk is
7392 // required, again, ensuring that IP is not clobbered.
7394 // Finally, although some linkers may theoretically provide a trampoline for
7395 // out of range calls (which is quite common due to a 32M range limitation of
7396 // branches for Thumb), we can generate the long-call version via
7397 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7400 switch (TM.getCodeModel()) {
7401 case CodeModel::Small:
7402 case CodeModel::Medium:
7403 case CodeModel::Default:
7404 case CodeModel::Kernel:
7405 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7406 .addImm((unsigned)ARMCC::AL).addReg(0)
7407 .addExternalSymbol("__chkstk")
7408 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7409 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7410 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7412 case CodeModel::Large:
7413 case CodeModel::JITDefault: {
7414 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7415 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7417 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7418 .addExternalSymbol("__chkstk");
7419 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7420 .addImm((unsigned)ARMCC::AL).addReg(0)
7421 .addReg(Reg, RegState::Kill)
7422 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7423 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7424 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7429 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7431 .addReg(ARM::SP).addReg(ARM::R4)));
7433 MI->eraseFromParent();
7438 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7439 MachineBasicBlock *BB) const {
7440 const TargetInstrInfo *TII =
7441 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7442 DebugLoc dl = MI->getDebugLoc();
7443 bool isThumb2 = Subtarget->isThumb2();
7444 switch (MI->getOpcode()) {
7447 llvm_unreachable("Unexpected instr type to insert");
7449 // The Thumb2 pre-indexed stores have the same MI operands, they just
7450 // define them differently in the .td files from the isel patterns, so
7451 // they need pseudos.
7452 case ARM::t2STR_preidx:
7453 MI->setDesc(TII->get(ARM::t2STR_PRE));
7455 case ARM::t2STRB_preidx:
7456 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7458 case ARM::t2STRH_preidx:
7459 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7462 case ARM::STRi_preidx:
7463 case ARM::STRBi_preidx: {
7464 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7465 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7466 // Decode the offset.
7467 unsigned Offset = MI->getOperand(4).getImm();
7468 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7469 Offset = ARM_AM::getAM2Offset(Offset);
7473 MachineMemOperand *MMO = *MI->memoperands_begin();
7474 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7475 .addOperand(MI->getOperand(0)) // Rn_wb
7476 .addOperand(MI->getOperand(1)) // Rt
7477 .addOperand(MI->getOperand(2)) // Rn
7478 .addImm(Offset) // offset (skip GPR==zero_reg)
7479 .addOperand(MI->getOperand(5)) // pred
7480 .addOperand(MI->getOperand(6))
7481 .addMemOperand(MMO);
7482 MI->eraseFromParent();
7485 case ARM::STRr_preidx:
7486 case ARM::STRBr_preidx:
7487 case ARM::STRH_preidx: {
7489 switch (MI->getOpcode()) {
7490 default: llvm_unreachable("unexpected opcode!");
7491 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7492 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7493 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7495 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7496 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7497 MIB.addOperand(MI->getOperand(i));
7498 MI->eraseFromParent();
7502 case ARM::tMOVCCr_pseudo: {
7503 // To "insert" a SELECT_CC instruction, we actually have to insert the
7504 // diamond control-flow pattern. The incoming instruction knows the
7505 // destination vreg to set, the condition code register to branch on, the
7506 // true/false values to select between, and a branch opcode to use.
7507 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7508 MachineFunction::iterator It = BB;
7514 // cmpTY ccX, r1, r2
7516 // fallthrough --> copy0MBB
7517 MachineBasicBlock *thisMBB = BB;
7518 MachineFunction *F = BB->getParent();
7519 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7520 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7521 F->insert(It, copy0MBB);
7522 F->insert(It, sinkMBB);
7524 // Transfer the remainder of BB and its successor edges to sinkMBB.
7525 sinkMBB->splice(sinkMBB->begin(), BB,
7526 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7527 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7529 BB->addSuccessor(copy0MBB);
7530 BB->addSuccessor(sinkMBB);
7532 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7533 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7536 // %FalseValue = ...
7537 // # fallthrough to sinkMBB
7540 // Update machine-CFG edges
7541 BB->addSuccessor(sinkMBB);
7544 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7547 BuildMI(*BB, BB->begin(), dl,
7548 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7549 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7550 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7552 MI->eraseFromParent(); // The pseudo instruction is gone now.
7557 case ARM::BCCZi64: {
7558 // If there is an unconditional branch to the other successor, remove it.
7559 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7561 // Compare both parts that make up the double comparison separately for
7563 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7565 unsigned LHS1 = MI->getOperand(1).getReg();
7566 unsigned LHS2 = MI->getOperand(2).getReg();
7568 AddDefaultPred(BuildMI(BB, dl,
7569 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7570 .addReg(LHS1).addImm(0));
7571 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7572 .addReg(LHS2).addImm(0)
7573 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7575 unsigned RHS1 = MI->getOperand(3).getReg();
7576 unsigned RHS2 = MI->getOperand(4).getReg();
7577 AddDefaultPred(BuildMI(BB, dl,
7578 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7579 .addReg(LHS1).addReg(RHS1));
7580 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7581 .addReg(LHS2).addReg(RHS2)
7582 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7585 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7586 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7587 if (MI->getOperand(0).getImm() == ARMCC::NE)
7588 std::swap(destMBB, exitMBB);
7590 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7591 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7593 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7595 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7597 MI->eraseFromParent(); // The pseudo instruction is gone now.
7601 case ARM::Int_eh_sjlj_setjmp:
7602 case ARM::Int_eh_sjlj_setjmp_nofp:
7603 case ARM::tInt_eh_sjlj_setjmp:
7604 case ARM::t2Int_eh_sjlj_setjmp:
7605 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7606 EmitSjLjDispatchBlock(MI, BB);
7611 // To insert an ABS instruction, we have to insert the
7612 // diamond control-flow pattern. The incoming instruction knows the
7613 // source vreg to test against 0, the destination vreg to set,
7614 // the condition code register to branch on, the
7615 // true/false values to select between, and a branch opcode to use.
7620 // BCC (branch to SinkBB if V0 >= 0)
7621 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7622 // SinkBB: V1 = PHI(V2, V3)
7623 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7624 MachineFunction::iterator BBI = BB;
7626 MachineFunction *Fn = BB->getParent();
7627 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7628 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7629 Fn->insert(BBI, RSBBB);
7630 Fn->insert(BBI, SinkBB);
7632 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7633 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7634 bool isThumb2 = Subtarget->isThumb2();
7635 MachineRegisterInfo &MRI = Fn->getRegInfo();
7636 // In Thumb mode S must not be specified if source register is the SP or
7637 // PC and if destination register is the SP, so restrict register class
7638 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7639 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7640 (const TargetRegisterClass*)&ARM::GPRRegClass);
7642 // Transfer the remainder of BB and its successor edges to sinkMBB.
7643 SinkBB->splice(SinkBB->begin(), BB,
7644 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7645 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7647 BB->addSuccessor(RSBBB);
7648 BB->addSuccessor(SinkBB);
7650 // fall through to SinkMBB
7651 RSBBB->addSuccessor(SinkBB);
7653 // insert a cmp at the end of BB
7654 AddDefaultPred(BuildMI(BB, dl,
7655 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7656 .addReg(ABSSrcReg).addImm(0));
7658 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7660 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7661 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7663 // insert rsbri in RSBBB
7664 // Note: BCC and rsbri will be converted into predicated rsbmi
7665 // by if-conversion pass
7666 BuildMI(*RSBBB, RSBBB->begin(), dl,
7667 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7668 .addReg(ABSSrcReg, RegState::Kill)
7669 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7671 // insert PHI in SinkBB,
7672 // reuse ABSDstReg to not change uses of ABS instruction
7673 BuildMI(*SinkBB, SinkBB->begin(), dl,
7674 TII->get(ARM::PHI), ABSDstReg)
7675 .addReg(NewRsbDstReg).addMBB(RSBBB)
7676 .addReg(ABSSrcReg).addMBB(BB);
7678 // remove ABS instruction
7679 MI->eraseFromParent();
7681 // return last added BB
7684 case ARM::COPY_STRUCT_BYVAL_I32:
7686 return EmitStructByval(MI, BB);
7687 case ARM::WIN__CHKSTK:
7688 return EmitLowered__chkstk(MI, BB);
7692 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7693 SDNode *Node) const {
7694 const MCInstrDesc *MCID = &MI->getDesc();
7695 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7696 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7697 // operand is still set to noreg. If needed, set the optional operand's
7698 // register to CPSR, and remove the redundant implicit def.
7700 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7702 // Rename pseudo opcodes.
7703 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7705 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
7706 getTargetMachine().getSubtargetImpl()->getInstrInfo());
7707 MCID = &TII->get(NewOpc);
7709 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7710 "converted opcode should be the same except for cc_out");
7714 // Add the optional cc_out operand
7715 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7717 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7719 // Any ARM instruction that sets the 's' bit should specify an optional
7720 // "cc_out" operand in the last operand position.
7721 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7722 assert(!NewOpc && "Optional cc_out operand required");
7725 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7726 // since we already have an optional CPSR def.
7727 bool definesCPSR = false;
7728 bool deadCPSR = false;
7729 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7731 const MachineOperand &MO = MI->getOperand(i);
7732 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7736 MI->RemoveOperand(i);
7741 assert(!NewOpc && "Optional cc_out operand required");
7744 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7746 assert(!MI->getOperand(ccOutIdx).getReg() &&
7747 "expect uninitialized optional cc_out operand");
7751 // If this instruction was defined with an optional CPSR def and its dag node
7752 // had a live implicit CPSR def, then activate the optional CPSR def.
7753 MachineOperand &MO = MI->getOperand(ccOutIdx);
7754 MO.setReg(ARM::CPSR);
7758 //===----------------------------------------------------------------------===//
7759 // ARM Optimization Hooks
7760 //===----------------------------------------------------------------------===//
7762 // Helper function that checks if N is a null or all ones constant.
7763 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7764 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7767 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7770 // Return true if N is conditionally 0 or all ones.
7771 // Detects these expressions where cc is an i1 value:
7773 // (select cc 0, y) [AllOnes=0]
7774 // (select cc y, 0) [AllOnes=0]
7775 // (zext cc) [AllOnes=0]
7776 // (sext cc) [AllOnes=0/1]
7777 // (select cc -1, y) [AllOnes=1]
7778 // (select cc y, -1) [AllOnes=1]
7780 // Invert is set when N is the null/all ones constant when CC is false.
7781 // OtherOp is set to the alternative value of N.
7782 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7783 SDValue &CC, bool &Invert,
7785 SelectionDAG &DAG) {
7786 switch (N->getOpcode()) {
7787 default: return false;
7789 CC = N->getOperand(0);
7790 SDValue N1 = N->getOperand(1);
7791 SDValue N2 = N->getOperand(2);
7792 if (isZeroOrAllOnes(N1, AllOnes)) {
7797 if (isZeroOrAllOnes(N2, AllOnes)) {
7804 case ISD::ZERO_EXTEND:
7805 // (zext cc) can never be the all ones value.
7809 case ISD::SIGN_EXTEND: {
7810 EVT VT = N->getValueType(0);
7811 CC = N->getOperand(0);
7812 if (CC.getValueType() != MVT::i1)
7816 // When looking for an AllOnes constant, N is an sext, and the 'other'
7818 OtherOp = DAG.getConstant(0, VT);
7819 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7820 // When looking for a 0 constant, N can be zext or sext.
7821 OtherOp = DAG.getConstant(1, VT);
7823 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7829 // Combine a constant select operand into its use:
7831 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7832 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7833 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7834 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7835 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7837 // The transform is rejected if the select doesn't have a constant operand that
7838 // is null, or all ones when AllOnes is set.
7840 // Also recognize sext/zext from i1:
7842 // (add (zext cc), x) -> (select cc (add x, 1), x)
7843 // (add (sext cc), x) -> (select cc (add x, -1), x)
7845 // These transformations eventually create predicated instructions.
7847 // @param N The node to transform.
7848 // @param Slct The N operand that is a select.
7849 // @param OtherOp The other N operand (x above).
7850 // @param DCI Context.
7851 // @param AllOnes Require the select constant to be all ones instead of null.
7852 // @returns The new node, or SDValue() on failure.
7854 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7855 TargetLowering::DAGCombinerInfo &DCI,
7856 bool AllOnes = false) {
7857 SelectionDAG &DAG = DCI.DAG;
7858 EVT VT = N->getValueType(0);
7859 SDValue NonConstantVal;
7862 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7863 NonConstantVal, DAG))
7866 // Slct is now know to be the desired identity constant when CC is true.
7867 SDValue TrueVal = OtherOp;
7868 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7869 OtherOp, NonConstantVal);
7870 // Unless SwapSelectOps says CC should be false.
7872 std::swap(TrueVal, FalseVal);
7874 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7875 CCOp, TrueVal, FalseVal);
7878 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7880 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7881 TargetLowering::DAGCombinerInfo &DCI) {
7882 SDValue N0 = N->getOperand(0);
7883 SDValue N1 = N->getOperand(1);
7884 if (N0.getNode()->hasOneUse()) {
7885 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7886 if (Result.getNode())
7889 if (N1.getNode()->hasOneUse()) {
7890 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7891 if (Result.getNode())
7897 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7898 // (only after legalization).
7899 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7900 TargetLowering::DAGCombinerInfo &DCI,
7901 const ARMSubtarget *Subtarget) {
7903 // Only perform optimization if after legalize, and if NEON is available. We
7904 // also expected both operands to be BUILD_VECTORs.
7905 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7906 || N0.getOpcode() != ISD::BUILD_VECTOR
7907 || N1.getOpcode() != ISD::BUILD_VECTOR)
7910 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7911 EVT VT = N->getValueType(0);
7912 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7915 // Check that the vector operands are of the right form.
7916 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7917 // operands, where N is the size of the formed vector.
7918 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7919 // index such that we have a pair wise add pattern.
7921 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7922 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7924 SDValue Vec = N0->getOperand(0)->getOperand(0);
7925 SDNode *V = Vec.getNode();
7926 unsigned nextIndex = 0;
7928 // For each operands to the ADD which are BUILD_VECTORs,
7929 // check to see if each of their operands are an EXTRACT_VECTOR with
7930 // the same vector and appropriate index.
7931 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7932 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7933 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7935 SDValue ExtVec0 = N0->getOperand(i);
7936 SDValue ExtVec1 = N1->getOperand(i);
7938 // First operand is the vector, verify its the same.
7939 if (V != ExtVec0->getOperand(0).getNode() ||
7940 V != ExtVec1->getOperand(0).getNode())
7943 // Second is the constant, verify its correct.
7944 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7945 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7947 // For the constant, we want to see all the even or all the odd.
7948 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7949 || C1->getZExtValue() != nextIndex+1)
7958 // Create VPADDL node.
7959 SelectionDAG &DAG = DCI.DAG;
7960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7962 // Build operand list.
7963 SmallVector<SDValue, 8> Ops;
7964 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7965 TLI.getPointerTy()));
7967 // Input is the vector.
7970 // Get widened type and narrowed type.
7972 unsigned numElem = VT.getVectorNumElements();
7974 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7975 switch (inputLaneType.getSimpleVT().SimpleTy) {
7976 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7977 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7978 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7980 llvm_unreachable("Invalid vector element type for padd optimization.");
7983 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), widenType, Ops);
7984 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7985 return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
7988 static SDValue findMUL_LOHI(SDValue V) {
7989 if (V->getOpcode() == ISD::UMUL_LOHI ||
7990 V->getOpcode() == ISD::SMUL_LOHI)
7995 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7996 TargetLowering::DAGCombinerInfo &DCI,
7997 const ARMSubtarget *Subtarget) {
7999 if (Subtarget->isThumb1Only()) return SDValue();
8001 // Only perform the checks after legalize when the pattern is available.
8002 if (DCI.isBeforeLegalize()) return SDValue();
8004 // Look for multiply add opportunities.
8005 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8006 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8007 // a glue link from the first add to the second add.
8008 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8009 // a S/UMLAL instruction.
8012 // \ / \ [no multiline comment]
8018 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8019 SDValue AddcOp0 = AddcNode->getOperand(0);
8020 SDValue AddcOp1 = AddcNode->getOperand(1);
8022 // Check if the two operands are from the same mul_lohi node.
8023 if (AddcOp0.getNode() == AddcOp1.getNode())
8026 assert(AddcNode->getNumValues() == 2 &&
8027 AddcNode->getValueType(0) == MVT::i32 &&
8028 "Expect ADDC with two result values. First: i32");
8030 // Check that we have a glued ADDC node.
8031 if (AddcNode->getValueType(1) != MVT::Glue)
8034 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8035 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8036 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8037 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8038 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8041 // Look for the glued ADDE.
8042 SDNode* AddeNode = AddcNode->getGluedUser();
8046 // Make sure it is really an ADDE.
8047 if (AddeNode->getOpcode() != ISD::ADDE)
8050 assert(AddeNode->getNumOperands() == 3 &&
8051 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8052 "ADDE node has the wrong inputs");
8054 // Check for the triangle shape.
8055 SDValue AddeOp0 = AddeNode->getOperand(0);
8056 SDValue AddeOp1 = AddeNode->getOperand(1);
8058 // Make sure that the ADDE operands are not coming from the same node.
8059 if (AddeOp0.getNode() == AddeOp1.getNode())
8062 // Find the MUL_LOHI node walking up ADDE's operands.
8063 bool IsLeftOperandMUL = false;
8064 SDValue MULOp = findMUL_LOHI(AddeOp0);
8065 if (MULOp == SDValue())
8066 MULOp = findMUL_LOHI(AddeOp1);
8068 IsLeftOperandMUL = true;
8069 if (MULOp == SDValue())
8072 // Figure out the right opcode.
8073 unsigned Opc = MULOp->getOpcode();
8074 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8076 // Figure out the high and low input values to the MLAL node.
8077 SDValue* HiMul = &MULOp;
8078 SDValue* HiAdd = nullptr;
8079 SDValue* LoMul = nullptr;
8080 SDValue* LowAdd = nullptr;
8082 if (IsLeftOperandMUL)
8088 if (AddcOp0->getOpcode() == Opc) {
8092 if (AddcOp1->getOpcode() == Opc) {
8100 if (LoMul->getNode() != HiMul->getNode())
8103 // Create the merged node.
8104 SelectionDAG &DAG = DCI.DAG;
8106 // Build operand list.
8107 SmallVector<SDValue, 8> Ops;
8108 Ops.push_back(LoMul->getOperand(0));
8109 Ops.push_back(LoMul->getOperand(1));
8110 Ops.push_back(*LowAdd);
8111 Ops.push_back(*HiAdd);
8113 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8114 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8116 // Replace the ADDs' nodes uses by the MLA node's values.
8117 SDValue HiMLALResult(MLALNode.getNode(), 1);
8118 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8120 SDValue LoMLALResult(MLALNode.getNode(), 0);
8121 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8123 // Return original node to notify the driver to stop replacing.
8124 SDValue resNode(AddcNode, 0);
8128 /// PerformADDCCombine - Target-specific dag combine transform from
8129 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8130 static SDValue PerformADDCCombine(SDNode *N,
8131 TargetLowering::DAGCombinerInfo &DCI,
8132 const ARMSubtarget *Subtarget) {
8134 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8138 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8139 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8140 /// called with the default operands, and if that fails, with commuted
8142 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8143 TargetLowering::DAGCombinerInfo &DCI,
8144 const ARMSubtarget *Subtarget){
8146 // Attempt to create vpaddl for this add.
8147 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8148 if (Result.getNode())
8151 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8152 if (N0.getNode()->hasOneUse()) {
8153 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8154 if (Result.getNode()) return Result;
8159 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8161 static SDValue PerformADDCombine(SDNode *N,
8162 TargetLowering::DAGCombinerInfo &DCI,
8163 const ARMSubtarget *Subtarget) {
8164 SDValue N0 = N->getOperand(0);
8165 SDValue N1 = N->getOperand(1);
8167 // First try with the default operand order.
8168 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8169 if (Result.getNode())
8172 // If that didn't work, try again with the operands commuted.
8173 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8176 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8178 static SDValue PerformSUBCombine(SDNode *N,
8179 TargetLowering::DAGCombinerInfo &DCI) {
8180 SDValue N0 = N->getOperand(0);
8181 SDValue N1 = N->getOperand(1);
8183 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8184 if (N1.getNode()->hasOneUse()) {
8185 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8186 if (Result.getNode()) return Result;
8192 /// PerformVMULCombine
8193 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8194 /// special multiplier accumulator forwarding.
8200 // However, for (A + B) * (A + B),
8207 static SDValue PerformVMULCombine(SDNode *N,
8208 TargetLowering::DAGCombinerInfo &DCI,
8209 const ARMSubtarget *Subtarget) {
8210 if (!Subtarget->hasVMLxForwarding())
8213 SelectionDAG &DAG = DCI.DAG;
8214 SDValue N0 = N->getOperand(0);
8215 SDValue N1 = N->getOperand(1);
8216 unsigned Opcode = N0.getOpcode();
8217 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8218 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8219 Opcode = N1.getOpcode();
8220 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8221 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8229 EVT VT = N->getValueType(0);
8231 SDValue N00 = N0->getOperand(0);
8232 SDValue N01 = N0->getOperand(1);
8233 return DAG.getNode(Opcode, DL, VT,
8234 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8235 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8238 static SDValue PerformMULCombine(SDNode *N,
8239 TargetLowering::DAGCombinerInfo &DCI,
8240 const ARMSubtarget *Subtarget) {
8241 SelectionDAG &DAG = DCI.DAG;
8243 if (Subtarget->isThumb1Only())
8246 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8249 EVT VT = N->getValueType(0);
8250 if (VT.is64BitVector() || VT.is128BitVector())
8251 return PerformVMULCombine(N, DCI, Subtarget);
8255 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8259 int64_t MulAmt = C->getSExtValue();
8260 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8262 ShiftAmt = ShiftAmt & (32 - 1);
8263 SDValue V = N->getOperand(0);
8267 MulAmt >>= ShiftAmt;
8270 if (isPowerOf2_32(MulAmt - 1)) {
8271 // (mul x, 2^N + 1) => (add (shl x, N), x)
8272 Res = DAG.getNode(ISD::ADD, DL, VT,
8274 DAG.getNode(ISD::SHL, DL, VT,
8276 DAG.getConstant(Log2_32(MulAmt - 1),
8278 } else if (isPowerOf2_32(MulAmt + 1)) {
8279 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8280 Res = DAG.getNode(ISD::SUB, DL, VT,
8281 DAG.getNode(ISD::SHL, DL, VT,
8283 DAG.getConstant(Log2_32(MulAmt + 1),
8289 uint64_t MulAmtAbs = -MulAmt;
8290 if (isPowerOf2_32(MulAmtAbs + 1)) {
8291 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8292 Res = DAG.getNode(ISD::SUB, DL, VT,
8294 DAG.getNode(ISD::SHL, DL, VT,
8296 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8298 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8299 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8300 Res = DAG.getNode(ISD::ADD, DL, VT,
8302 DAG.getNode(ISD::SHL, DL, VT,
8304 DAG.getConstant(Log2_32(MulAmtAbs-1),
8306 Res = DAG.getNode(ISD::SUB, DL, VT,
8307 DAG.getConstant(0, MVT::i32),Res);
8314 Res = DAG.getNode(ISD::SHL, DL, VT,
8315 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8317 // Do not add new nodes to DAG combiner worklist.
8318 DCI.CombineTo(N, Res, false);
8322 static SDValue PerformANDCombine(SDNode *N,
8323 TargetLowering::DAGCombinerInfo &DCI,
8324 const ARMSubtarget *Subtarget) {
8326 // Attempt to use immediate-form VBIC
8327 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8329 EVT VT = N->getValueType(0);
8330 SelectionDAG &DAG = DCI.DAG;
8332 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8335 APInt SplatBits, SplatUndef;
8336 unsigned SplatBitSize;
8339 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8340 if (SplatBitSize <= 64) {
8342 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8343 SplatUndef.getZExtValue(), SplatBitSize,
8344 DAG, VbicVT, VT.is128BitVector(),
8346 if (Val.getNode()) {
8348 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8349 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8350 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8355 if (!Subtarget->isThumb1Only()) {
8356 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8357 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8358 if (Result.getNode())
8365 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8366 static SDValue PerformORCombine(SDNode *N,
8367 TargetLowering::DAGCombinerInfo &DCI,
8368 const ARMSubtarget *Subtarget) {
8369 // Attempt to use immediate-form VORR
8370 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8372 EVT VT = N->getValueType(0);
8373 SelectionDAG &DAG = DCI.DAG;
8375 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8378 APInt SplatBits, SplatUndef;
8379 unsigned SplatBitSize;
8381 if (BVN && Subtarget->hasNEON() &&
8382 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8383 if (SplatBitSize <= 64) {
8385 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8386 SplatUndef.getZExtValue(), SplatBitSize,
8387 DAG, VorrVT, VT.is128BitVector(),
8389 if (Val.getNode()) {
8391 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8392 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8393 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8398 if (!Subtarget->isThumb1Only()) {
8399 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8400 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8401 if (Result.getNode())
8405 // The code below optimizes (or (and X, Y), Z).
8406 // The AND operand needs to have a single user to make these optimizations
8408 SDValue N0 = N->getOperand(0);
8409 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8411 SDValue N1 = N->getOperand(1);
8413 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8414 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8415 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8417 unsigned SplatBitSize;
8420 APInt SplatBits0, SplatBits1;
8421 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8422 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8423 // Ensure that the second operand of both ands are constants
8424 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8425 HasAnyUndefs) && !HasAnyUndefs) {
8426 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8427 HasAnyUndefs) && !HasAnyUndefs) {
8428 // Ensure that the bit width of the constants are the same and that
8429 // the splat arguments are logical inverses as per the pattern we
8430 // are trying to simplify.
8431 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8432 SplatBits0 == ~SplatBits1) {
8433 // Canonicalize the vector type to make instruction selection
8435 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8436 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8440 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8446 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8449 // BFI is only available on V6T2+
8450 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8454 // 1) or (and A, mask), val => ARMbfi A, val, mask
8455 // iff (val & mask) == val
8457 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8458 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8459 // && mask == ~mask2
8460 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8461 // && ~mask == mask2
8462 // (i.e., copy a bitfield value into another bitfield of the same width)
8467 SDValue N00 = N0.getOperand(0);
8469 // The value and the mask need to be constants so we can verify this is
8470 // actually a bitfield set. If the mask is 0xffff, we can do better
8471 // via a movt instruction, so don't use BFI in that case.
8472 SDValue MaskOp = N0.getOperand(1);
8473 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8476 unsigned Mask = MaskC->getZExtValue();
8480 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8483 unsigned Val = N1C->getZExtValue();
8484 if ((Val & ~Mask) != Val)
8487 if (ARM::isBitFieldInvertedMask(Mask)) {
8488 Val >>= countTrailingZeros(~Mask);
8490 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8491 DAG.getConstant(Val, MVT::i32),
8492 DAG.getConstant(Mask, MVT::i32));
8494 // Do not add new nodes to DAG combiner worklist.
8495 DCI.CombineTo(N, Res, false);
8498 } else if (N1.getOpcode() == ISD::AND) {
8499 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8500 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8503 unsigned Mask2 = N11C->getZExtValue();
8505 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8507 if (ARM::isBitFieldInvertedMask(Mask) &&
8509 // The pack halfword instruction works better for masks that fit it,
8510 // so use that when it's available.
8511 if (Subtarget->hasT2ExtractPack() &&
8512 (Mask == 0xffff || Mask == 0xffff0000))
8515 unsigned amt = countTrailingZeros(Mask2);
8516 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8517 DAG.getConstant(amt, MVT::i32));
8518 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8519 DAG.getConstant(Mask, MVT::i32));
8520 // Do not add new nodes to DAG combiner worklist.
8521 DCI.CombineTo(N, Res, false);
8523 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8525 // The pack halfword instruction works better for masks that fit it,
8526 // so use that when it's available.
8527 if (Subtarget->hasT2ExtractPack() &&
8528 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8531 unsigned lsb = countTrailingZeros(Mask);
8532 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8533 DAG.getConstant(lsb, MVT::i32));
8534 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8535 DAG.getConstant(Mask2, MVT::i32));
8536 // Do not add new nodes to DAG combiner worklist.
8537 DCI.CombineTo(N, Res, false);
8542 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8543 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8544 ARM::isBitFieldInvertedMask(~Mask)) {
8545 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8546 // where lsb(mask) == #shamt and masked bits of B are known zero.
8547 SDValue ShAmt = N00.getOperand(1);
8548 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8549 unsigned LSB = countTrailingZeros(Mask);
8553 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8554 DAG.getConstant(~Mask, MVT::i32));
8556 // Do not add new nodes to DAG combiner worklist.
8557 DCI.CombineTo(N, Res, false);
8563 static SDValue PerformXORCombine(SDNode *N,
8564 TargetLowering::DAGCombinerInfo &DCI,
8565 const ARMSubtarget *Subtarget) {
8566 EVT VT = N->getValueType(0);
8567 SelectionDAG &DAG = DCI.DAG;
8569 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8572 if (!Subtarget->isThumb1Only()) {
8573 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8574 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8575 if (Result.getNode())
8582 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8583 /// the bits being cleared by the AND are not demanded by the BFI.
8584 static SDValue PerformBFICombine(SDNode *N,
8585 TargetLowering::DAGCombinerInfo &DCI) {
8586 SDValue N1 = N->getOperand(1);
8587 if (N1.getOpcode() == ISD::AND) {
8588 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8591 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8592 unsigned LSB = countTrailingZeros(~InvMask);
8593 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8594 unsigned Mask = (1 << Width)-1;
8595 unsigned Mask2 = N11C->getZExtValue();
8596 if ((Mask & (~Mask2)) == 0)
8597 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8598 N->getOperand(0), N1.getOperand(0),
8604 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8605 /// ARMISD::VMOVRRD.
8606 static SDValue PerformVMOVRRDCombine(SDNode *N,
8607 TargetLowering::DAGCombinerInfo &DCI,
8608 const ARMSubtarget *Subtarget) {
8609 // vmovrrd(vmovdrr x, y) -> x,y
8610 SDValue InDouble = N->getOperand(0);
8611 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8612 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8614 // vmovrrd(load f64) -> (load i32), (load i32)
8615 SDNode *InNode = InDouble.getNode();
8616 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8617 InNode->getValueType(0) == MVT::f64 &&
8618 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8619 !cast<LoadSDNode>(InNode)->isVolatile()) {
8620 // TODO: Should this be done for non-FrameIndex operands?
8621 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8623 SelectionDAG &DAG = DCI.DAG;
8625 SDValue BasePtr = LD->getBasePtr();
8626 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8627 LD->getPointerInfo(), LD->isVolatile(),
8628 LD->isNonTemporal(), LD->isInvariant(),
8629 LD->getAlignment());
8631 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8632 DAG.getConstant(4, MVT::i32));
8633 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8634 LD->getPointerInfo(), LD->isVolatile(),
8635 LD->isNonTemporal(), LD->isInvariant(),
8636 std::min(4U, LD->getAlignment() / 2));
8638 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8639 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8640 std::swap (NewLD1, NewLD2);
8641 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8648 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8649 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8650 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8651 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8652 SDValue Op0 = N->getOperand(0);
8653 SDValue Op1 = N->getOperand(1);
8654 if (Op0.getOpcode() == ISD::BITCAST)
8655 Op0 = Op0.getOperand(0);
8656 if (Op1.getOpcode() == ISD::BITCAST)
8657 Op1 = Op1.getOperand(0);
8658 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8659 Op0.getNode() == Op1.getNode() &&
8660 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8661 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8662 N->getValueType(0), Op0.getOperand(0));
8666 /// PerformSTORECombine - Target-specific dag combine xforms for
8668 static SDValue PerformSTORECombine(SDNode *N,
8669 TargetLowering::DAGCombinerInfo &DCI) {
8670 StoreSDNode *St = cast<StoreSDNode>(N);
8671 if (St->isVolatile())
8674 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
8675 // pack all of the elements in one place. Next, store to memory in fewer
8677 SDValue StVal = St->getValue();
8678 EVT VT = StVal.getValueType();
8679 if (St->isTruncatingStore() && VT.isVector()) {
8680 SelectionDAG &DAG = DCI.DAG;
8681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8682 EVT StVT = St->getMemoryVT();
8683 unsigned NumElems = VT.getVectorNumElements();
8684 assert(StVT != VT && "Cannot truncate to the same type");
8685 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8686 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8688 // From, To sizes and ElemCount must be pow of two
8689 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8691 // We are going to use the original vector elt for storing.
8692 // Accumulated smaller vector elements must be a multiple of the store size.
8693 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8695 unsigned SizeRatio = FromEltSz / ToEltSz;
8696 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8698 // Create a type on which we perform the shuffle.
8699 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8700 NumElems*SizeRatio);
8701 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8704 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8705 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8706 for (unsigned i = 0; i < NumElems; ++i)
8707 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
8709 // Can't shuffle using an illegal type.
8710 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8712 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8713 DAG.getUNDEF(WideVec.getValueType()),
8715 // At this point all of the data is stored at the bottom of the
8716 // register. We now need to save it to mem.
8718 // Find the largest store unit
8719 MVT StoreType = MVT::i8;
8720 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8721 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8722 MVT Tp = (MVT::SimpleValueType)tp;
8723 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8726 // Didn't find a legal store type.
8727 if (!TLI.isTypeLegal(StoreType))
8730 // Bitcast the original vector into a vector of store-size units
8731 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8732 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8733 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8734 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8735 SmallVector<SDValue, 8> Chains;
8736 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8737 TLI.getPointerTy());
8738 SDValue BasePtr = St->getBasePtr();
8740 // Perform one or more big stores into memory.
8741 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8742 for (unsigned I = 0; I < E; I++) {
8743 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8744 StoreType, ShuffWide,
8745 DAG.getIntPtrConstant(I));
8746 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8747 St->getPointerInfo(), St->isVolatile(),
8748 St->isNonTemporal(), St->getAlignment());
8749 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8751 Chains.push_back(Ch);
8753 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
8756 if (!ISD::isNormalStore(St))
8759 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8760 // ARM stores of arguments in the same cache line.
8761 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8762 StVal.getNode()->hasOneUse()) {
8763 SelectionDAG &DAG = DCI.DAG;
8764 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
8766 SDValue BasePtr = St->getBasePtr();
8767 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8768 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
8769 BasePtr, St->getPointerInfo(), St->isVolatile(),
8770 St->isNonTemporal(), St->getAlignment());
8772 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8773 DAG.getConstant(4, MVT::i32));
8774 return DAG.getStore(NewST1.getValue(0), DL,
8775 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
8776 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8777 St->isNonTemporal(),
8778 std::min(4U, St->getAlignment() / 2));
8781 if (StVal.getValueType() != MVT::i64 ||
8782 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8785 // Bitcast an i64 store extracted from a vector to f64.
8786 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8787 SelectionDAG &DAG = DCI.DAG;
8789 SDValue IntVec = StVal.getOperand(0);
8790 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8791 IntVec.getValueType().getVectorNumElements());
8792 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8793 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8794 Vec, StVal.getOperand(1));
8796 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8797 // Make the DAGCombiner fold the bitcasts.
8798 DCI.AddToWorklist(Vec.getNode());
8799 DCI.AddToWorklist(ExtElt.getNode());
8800 DCI.AddToWorklist(V.getNode());
8801 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8802 St->getPointerInfo(), St->isVolatile(),
8803 St->isNonTemporal(), St->getAlignment(),
8807 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8808 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8809 /// i64 vector to have f64 elements, since the value can then be loaded
8810 /// directly into a VFP register.
8811 static bool hasNormalLoadOperand(SDNode *N) {
8812 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8813 for (unsigned i = 0; i < NumElts; ++i) {
8814 SDNode *Elt = N->getOperand(i).getNode();
8815 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8821 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8822 /// ISD::BUILD_VECTOR.
8823 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8824 TargetLowering::DAGCombinerInfo &DCI,
8825 const ARMSubtarget *Subtarget) {
8826 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8827 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8828 // into a pair of GPRs, which is fine when the value is used as a scalar,
8829 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8830 SelectionDAG &DAG = DCI.DAG;
8831 if (N->getNumOperands() == 2) {
8832 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8837 // Load i64 elements as f64 values so that type legalization does not split
8838 // them up into i32 values.
8839 EVT VT = N->getValueType(0);
8840 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8843 SmallVector<SDValue, 8> Ops;
8844 unsigned NumElts = VT.getVectorNumElements();
8845 for (unsigned i = 0; i < NumElts; ++i) {
8846 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8848 // Make the DAGCombiner fold the bitcast.
8849 DCI.AddToWorklist(V.getNode());
8851 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8852 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8853 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8856 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8858 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8859 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8860 // At that time, we may have inserted bitcasts from integer to float.
8861 // If these bitcasts have survived DAGCombine, change the lowering of this
8862 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8863 // force to use floating point types.
8865 // Make sure we can change the type of the vector.
8866 // This is possible iff:
8867 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8868 // 1.1. Vector is used only once.
8869 // 1.2. Use is a bit convert to an integer type.
8870 // 2. The size of its operands are 32-bits (64-bits are not legal).
8871 EVT VT = N->getValueType(0);
8872 EVT EltVT = VT.getVectorElementType();
8874 // Check 1.1. and 2.
8875 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8878 // By construction, the input type must be float.
8879 assert(EltVT == MVT::f32 && "Unexpected type!");
8882 SDNode *Use = *N->use_begin();
8883 if (Use->getOpcode() != ISD::BITCAST ||
8884 Use->getValueType(0).isFloatingPoint())
8887 // Check profitability.
8888 // Model is, if more than half of the relevant operands are bitcast from
8889 // i32, turn the build_vector into a sequence of insert_vector_elt.
8890 // Relevant operands are everything that is not statically
8891 // (i.e., at compile time) bitcasted.
8892 unsigned NumOfBitCastedElts = 0;
8893 unsigned NumElts = VT.getVectorNumElements();
8894 unsigned NumOfRelevantElts = NumElts;
8895 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8896 SDValue Elt = N->getOperand(Idx);
8897 if (Elt->getOpcode() == ISD::BITCAST) {
8898 // Assume only bit cast to i32 will go away.
8899 if (Elt->getOperand(0).getValueType() == MVT::i32)
8900 ++NumOfBitCastedElts;
8901 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8902 // Constants are statically casted, thus do not count them as
8903 // relevant operands.
8904 --NumOfRelevantElts;
8907 // Check if more than half of the elements require a non-free bitcast.
8908 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8911 SelectionDAG &DAG = DCI.DAG;
8912 // Create the new vector type.
8913 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8914 // Check if the type is legal.
8915 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8916 if (!TLI.isTypeLegal(VecVT))
8920 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8921 // => BITCAST INSERT_VECTOR_ELT
8922 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8924 SDValue Vec = DAG.getUNDEF(VecVT);
8926 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8927 SDValue V = N->getOperand(Idx);
8928 if (V.getOpcode() == ISD::UNDEF)
8930 if (V.getOpcode() == ISD::BITCAST &&
8931 V->getOperand(0).getValueType() == MVT::i32)
8932 // Fold obvious case.
8933 V = V.getOperand(0);
8935 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8936 // Make the DAGCombiner fold the bitcasts.
8937 DCI.AddToWorklist(V.getNode());
8939 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8940 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8942 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8943 // Make the DAGCombiner fold the bitcasts.
8944 DCI.AddToWorklist(Vec.getNode());
8948 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8949 /// ISD::INSERT_VECTOR_ELT.
8950 static SDValue PerformInsertEltCombine(SDNode *N,
8951 TargetLowering::DAGCombinerInfo &DCI) {
8952 // Bitcast an i64 load inserted into a vector to f64.
8953 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8954 EVT VT = N->getValueType(0);
8955 SDNode *Elt = N->getOperand(1).getNode();
8956 if (VT.getVectorElementType() != MVT::i64 ||
8957 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8960 SelectionDAG &DAG = DCI.DAG;
8962 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8963 VT.getVectorNumElements());
8964 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8965 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8966 // Make the DAGCombiner fold the bitcasts.
8967 DCI.AddToWorklist(Vec.getNode());
8968 DCI.AddToWorklist(V.getNode());
8969 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8970 Vec, V, N->getOperand(2));
8971 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8974 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8975 /// ISD::VECTOR_SHUFFLE.
8976 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8977 // The LLVM shufflevector instruction does not require the shuffle mask
8978 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8979 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8980 // operands do not match the mask length, they are extended by concatenating
8981 // them with undef vectors. That is probably the right thing for other
8982 // targets, but for NEON it is better to concatenate two double-register
8983 // size vector operands into a single quad-register size vector. Do that
8984 // transformation here:
8985 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8986 // shuffle(concat(v1, v2), undef)
8987 SDValue Op0 = N->getOperand(0);
8988 SDValue Op1 = N->getOperand(1);
8989 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8990 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8991 Op0.getNumOperands() != 2 ||
8992 Op1.getNumOperands() != 2)
8994 SDValue Concat0Op1 = Op0.getOperand(1);
8995 SDValue Concat1Op1 = Op1.getOperand(1);
8996 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8997 Concat1Op1.getOpcode() != ISD::UNDEF)
8999 // Skip the transformation if any of the types are illegal.
9000 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9001 EVT VT = N->getValueType(0);
9002 if (!TLI.isTypeLegal(VT) ||
9003 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
9004 !TLI.isTypeLegal(Concat1Op1.getValueType()))
9007 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9008 Op0.getOperand(0), Op1.getOperand(0));
9009 // Translate the shuffle mask.
9010 SmallVector<int, 16> NewMask;
9011 unsigned NumElts = VT.getVectorNumElements();
9012 unsigned HalfElts = NumElts/2;
9013 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9014 for (unsigned n = 0; n < NumElts; ++n) {
9015 int MaskElt = SVN->getMaskElt(n);
9017 if (MaskElt < (int)HalfElts)
9019 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9020 NewElt = HalfElts + MaskElt - NumElts;
9021 NewMask.push_back(NewElt);
9023 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9024 DAG.getUNDEF(VT), NewMask.data());
9027 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
9028 /// NEON load/store intrinsics to merge base address updates.
9029 static SDValue CombineBaseUpdate(SDNode *N,
9030 TargetLowering::DAGCombinerInfo &DCI) {
9031 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9034 SelectionDAG &DAG = DCI.DAG;
9035 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9036 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9037 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
9038 SDValue Addr = N->getOperand(AddrOpIdx);
9040 // Search for a use of the address operand that is an increment.
9041 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9042 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9044 if (User->getOpcode() != ISD::ADD ||
9045 UI.getUse().getResNo() != Addr.getResNo())
9048 // Check that the add is independent of the load/store. Otherwise, folding
9049 // it would create a cycle.
9050 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9053 // Find the new opcode for the updating load/store.
9055 bool isLaneOp = false;
9056 unsigned NewOpc = 0;
9057 unsigned NumVecs = 0;
9059 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9061 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9062 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9064 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9066 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9068 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9070 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9071 NumVecs = 2; isLaneOp = true; break;
9072 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9073 NumVecs = 3; isLaneOp = true; break;
9074 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9075 NumVecs = 4; isLaneOp = true; break;
9076 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9077 NumVecs = 1; isLoad = false; break;
9078 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9079 NumVecs = 2; isLoad = false; break;
9080 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9081 NumVecs = 3; isLoad = false; break;
9082 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9083 NumVecs = 4; isLoad = false; break;
9084 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9085 NumVecs = 2; isLoad = false; isLaneOp = true; break;
9086 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9087 NumVecs = 3; isLoad = false; isLaneOp = true; break;
9088 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9089 NumVecs = 4; isLoad = false; isLaneOp = true; break;
9093 switch (N->getOpcode()) {
9094 default: llvm_unreachable("unexpected opcode for Neon base update");
9095 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9096 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9097 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9101 // Find the size of memory referenced by the load/store.
9104 VecTy = N->getValueType(0);
9106 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9107 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9109 NumBytes /= VecTy.getVectorNumElements();
9111 // If the increment is a constant, it must match the memory ref size.
9112 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9113 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9114 uint64_t IncVal = CInc->getZExtValue();
9115 if (IncVal != NumBytes)
9117 } else if (NumBytes >= 3 * 16) {
9118 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9119 // separate instructions that make it harder to use a non-constant update.
9123 // Create the new updating load/store node.
9125 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
9127 for (n = 0; n < NumResultVecs; ++n)
9129 Tys[n++] = MVT::i32;
9130 Tys[n] = MVT::Other;
9131 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9132 SmallVector<SDValue, 8> Ops;
9133 Ops.push_back(N->getOperand(0)); // incoming chain
9134 Ops.push_back(N->getOperand(AddrOpIdx));
9136 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
9137 Ops.push_back(N->getOperand(i));
9139 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9140 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9141 Ops, MemInt->getMemoryVT(),
9142 MemInt->getMemOperand());
9145 std::vector<SDValue> NewResults;
9146 for (unsigned i = 0; i < NumResultVecs; ++i) {
9147 NewResults.push_back(SDValue(UpdN.getNode(), i));
9149 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9150 DCI.CombineTo(N, NewResults);
9151 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9158 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9159 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9160 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9162 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9163 SelectionDAG &DAG = DCI.DAG;
9164 EVT VT = N->getValueType(0);
9165 // vldN-dup instructions only support 64-bit vectors for N > 1.
9166 if (!VT.is64BitVector())
9169 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9170 SDNode *VLD = N->getOperand(0).getNode();
9171 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9173 unsigned NumVecs = 0;
9174 unsigned NewOpc = 0;
9175 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9176 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9178 NewOpc = ARMISD::VLD2DUP;
9179 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9181 NewOpc = ARMISD::VLD3DUP;
9182 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9184 NewOpc = ARMISD::VLD4DUP;
9189 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9190 // numbers match the load.
9191 unsigned VLDLaneNo =
9192 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9193 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9195 // Ignore uses of the chain result.
9196 if (UI.getUse().getResNo() == NumVecs)
9199 if (User->getOpcode() != ARMISD::VDUPLANE ||
9200 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9204 // Create the vldN-dup node.
9207 for (n = 0; n < NumVecs; ++n)
9209 Tys[n] = MVT::Other;
9210 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9211 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9212 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9213 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9214 Ops, VLDMemInt->getMemoryVT(),
9215 VLDMemInt->getMemOperand());
9218 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9220 unsigned ResNo = UI.getUse().getResNo();
9221 // Ignore uses of the chain result.
9222 if (ResNo == NumVecs)
9225 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9228 // Now the vldN-lane intrinsic is dead except for its chain result.
9229 // Update uses of the chain.
9230 std::vector<SDValue> VLDDupResults;
9231 for (unsigned n = 0; n < NumVecs; ++n)
9232 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9233 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9234 DCI.CombineTo(VLD, VLDDupResults);
9239 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9240 /// ARMISD::VDUPLANE.
9241 static SDValue PerformVDUPLANECombine(SDNode *N,
9242 TargetLowering::DAGCombinerInfo &DCI) {
9243 SDValue Op = N->getOperand(0);
9245 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9246 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9247 if (CombineVLDDUP(N, DCI))
9248 return SDValue(N, 0);
9250 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9251 // redundant. Ignore bit_converts for now; element sizes are checked below.
9252 while (Op.getOpcode() == ISD::BITCAST)
9253 Op = Op.getOperand(0);
9254 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9257 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9258 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9259 // The canonical VMOV for a zero vector uses a 32-bit element size.
9260 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9262 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9264 EVT VT = N->getValueType(0);
9265 if (EltSize > VT.getVectorElementType().getSizeInBits())
9268 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9271 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9272 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9273 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9277 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9279 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9284 APFloat APF = C->getValueAPF();
9285 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9286 != APFloat::opOK || !isExact)
9289 c0 = (I == 0) ? cN : c0;
9290 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9297 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9298 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9299 /// when the VMUL has a constant operand that is a power of 2.
9301 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9302 /// vmul.f32 d16, d17, d16
9303 /// vcvt.s32.f32 d16, d16
9305 /// vcvt.s32.f32 d16, d16, #3
9306 static SDValue PerformVCVTCombine(SDNode *N,
9307 TargetLowering::DAGCombinerInfo &DCI,
9308 const ARMSubtarget *Subtarget) {
9309 SelectionDAG &DAG = DCI.DAG;
9310 SDValue Op = N->getOperand(0);
9312 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9313 Op.getOpcode() != ISD::FMUL)
9317 SDValue N0 = Op->getOperand(0);
9318 SDValue ConstVec = Op->getOperand(1);
9319 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9321 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9322 !isConstVecPow2(ConstVec, isSigned, C))
9325 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9326 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9327 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9328 // These instructions only exist converting from f32 to i32. We can handle
9329 // smaller integers by generating an extra truncate, but larger ones would
9334 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9335 Intrinsic::arm_neon_vcvtfp2fxu;
9336 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9337 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9338 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9339 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9340 DAG.getConstant(Log2_64(C), MVT::i32));
9342 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9343 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9348 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9349 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9350 /// when the VDIV has a constant operand that is a power of 2.
9352 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9353 /// vcvt.f32.s32 d16, d16
9354 /// vdiv.f32 d16, d17, d16
9356 /// vcvt.f32.s32 d16, d16, #3
9357 static SDValue PerformVDIVCombine(SDNode *N,
9358 TargetLowering::DAGCombinerInfo &DCI,
9359 const ARMSubtarget *Subtarget) {
9360 SelectionDAG &DAG = DCI.DAG;
9361 SDValue Op = N->getOperand(0);
9362 unsigned OpOpcode = Op.getNode()->getOpcode();
9364 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9365 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9369 SDValue ConstVec = N->getOperand(1);
9370 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9372 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9373 !isConstVecPow2(ConstVec, isSigned, C))
9376 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9377 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9378 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9379 // These instructions only exist converting from i32 to f32. We can handle
9380 // smaller integers by generating an extra extend, but larger ones would
9385 SDValue ConvInput = Op.getOperand(0);
9386 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9387 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9388 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9389 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9392 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9393 Intrinsic::arm_neon_vcvtfxu2fp;
9394 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9396 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9397 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9400 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9401 /// operand of a vector shift operation, where all the elements of the
9402 /// build_vector must have the same constant integer value.
9403 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9404 // Ignore bit_converts.
9405 while (Op.getOpcode() == ISD::BITCAST)
9406 Op = Op.getOperand(0);
9407 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9408 APInt SplatBits, SplatUndef;
9409 unsigned SplatBitSize;
9411 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9412 HasAnyUndefs, ElementBits) ||
9413 SplatBitSize > ElementBits)
9415 Cnt = SplatBits.getSExtValue();
9419 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9420 /// operand of a vector shift left operation. That value must be in the range:
9421 /// 0 <= Value < ElementBits for a left shift; or
9422 /// 0 <= Value <= ElementBits for a long left shift.
9423 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9424 assert(VT.isVector() && "vector shift count is not a vector type");
9425 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9426 if (! getVShiftImm(Op, ElementBits, Cnt))
9428 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9431 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9432 /// operand of a vector shift right operation. For a shift opcode, the value
9433 /// is positive, but for an intrinsic the value count must be negative. The
9434 /// absolute value must be in the range:
9435 /// 1 <= |Value| <= ElementBits for a right shift; or
9436 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9437 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9439 assert(VT.isVector() && "vector shift count is not a vector type");
9440 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9441 if (! getVShiftImm(Op, ElementBits, Cnt))
9445 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9448 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9449 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9450 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9453 // Don't do anything for most intrinsics.
9456 // Vector shifts: check for immediate versions and lower them.
9457 // Note: This is done during DAG combining instead of DAG legalizing because
9458 // the build_vectors for 64-bit vector element shift counts are generally
9459 // not legal, and it is hard to see their values after they get legalized to
9460 // loads from a constant pool.
9461 case Intrinsic::arm_neon_vshifts:
9462 case Intrinsic::arm_neon_vshiftu:
9463 case Intrinsic::arm_neon_vrshifts:
9464 case Intrinsic::arm_neon_vrshiftu:
9465 case Intrinsic::arm_neon_vrshiftn:
9466 case Intrinsic::arm_neon_vqshifts:
9467 case Intrinsic::arm_neon_vqshiftu:
9468 case Intrinsic::arm_neon_vqshiftsu:
9469 case Intrinsic::arm_neon_vqshiftns:
9470 case Intrinsic::arm_neon_vqshiftnu:
9471 case Intrinsic::arm_neon_vqshiftnsu:
9472 case Intrinsic::arm_neon_vqrshiftns:
9473 case Intrinsic::arm_neon_vqrshiftnu:
9474 case Intrinsic::arm_neon_vqrshiftnsu: {
9475 EVT VT = N->getOperand(1).getValueType();
9477 unsigned VShiftOpc = 0;
9480 case Intrinsic::arm_neon_vshifts:
9481 case Intrinsic::arm_neon_vshiftu:
9482 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9483 VShiftOpc = ARMISD::VSHL;
9486 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9487 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9488 ARMISD::VSHRs : ARMISD::VSHRu);
9493 case Intrinsic::arm_neon_vrshifts:
9494 case Intrinsic::arm_neon_vrshiftu:
9495 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9499 case Intrinsic::arm_neon_vqshifts:
9500 case Intrinsic::arm_neon_vqshiftu:
9501 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9505 case Intrinsic::arm_neon_vqshiftsu:
9506 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9508 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9510 case Intrinsic::arm_neon_vrshiftn:
9511 case Intrinsic::arm_neon_vqshiftns:
9512 case Intrinsic::arm_neon_vqshiftnu:
9513 case Intrinsic::arm_neon_vqshiftnsu:
9514 case Intrinsic::arm_neon_vqrshiftns:
9515 case Intrinsic::arm_neon_vqrshiftnu:
9516 case Intrinsic::arm_neon_vqrshiftnsu:
9517 // Narrowing shifts require an immediate right shift.
9518 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9520 llvm_unreachable("invalid shift count for narrowing vector shift "
9524 llvm_unreachable("unhandled vector shift");
9528 case Intrinsic::arm_neon_vshifts:
9529 case Intrinsic::arm_neon_vshiftu:
9530 // Opcode already set above.
9532 case Intrinsic::arm_neon_vrshifts:
9533 VShiftOpc = ARMISD::VRSHRs; break;
9534 case Intrinsic::arm_neon_vrshiftu:
9535 VShiftOpc = ARMISD::VRSHRu; break;
9536 case Intrinsic::arm_neon_vrshiftn:
9537 VShiftOpc = ARMISD::VRSHRN; break;
9538 case Intrinsic::arm_neon_vqshifts:
9539 VShiftOpc = ARMISD::VQSHLs; break;
9540 case Intrinsic::arm_neon_vqshiftu:
9541 VShiftOpc = ARMISD::VQSHLu; break;
9542 case Intrinsic::arm_neon_vqshiftsu:
9543 VShiftOpc = ARMISD::VQSHLsu; break;
9544 case Intrinsic::arm_neon_vqshiftns:
9545 VShiftOpc = ARMISD::VQSHRNs; break;
9546 case Intrinsic::arm_neon_vqshiftnu:
9547 VShiftOpc = ARMISD::VQSHRNu; break;
9548 case Intrinsic::arm_neon_vqshiftnsu:
9549 VShiftOpc = ARMISD::VQSHRNsu; break;
9550 case Intrinsic::arm_neon_vqrshiftns:
9551 VShiftOpc = ARMISD::VQRSHRNs; break;
9552 case Intrinsic::arm_neon_vqrshiftnu:
9553 VShiftOpc = ARMISD::VQRSHRNu; break;
9554 case Intrinsic::arm_neon_vqrshiftnsu:
9555 VShiftOpc = ARMISD::VQRSHRNsu; break;
9558 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9559 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9562 case Intrinsic::arm_neon_vshiftins: {
9563 EVT VT = N->getOperand(1).getValueType();
9565 unsigned VShiftOpc = 0;
9567 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9568 VShiftOpc = ARMISD::VSLI;
9569 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9570 VShiftOpc = ARMISD::VSRI;
9572 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9575 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9576 N->getOperand(1), N->getOperand(2),
9577 DAG.getConstant(Cnt, MVT::i32));
9580 case Intrinsic::arm_neon_vqrshifts:
9581 case Intrinsic::arm_neon_vqrshiftu:
9582 // No immediate versions of these to check for.
9589 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9590 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9591 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9592 /// vector element shift counts are generally not legal, and it is hard to see
9593 /// their values after they get legalized to loads from a constant pool.
9594 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9595 const ARMSubtarget *ST) {
9596 EVT VT = N->getValueType(0);
9597 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9598 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9599 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9600 SDValue N1 = N->getOperand(1);
9601 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9602 SDValue N0 = N->getOperand(0);
9603 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9604 DAG.MaskedValueIsZero(N0.getOperand(0),
9605 APInt::getHighBitsSet(32, 16)))
9606 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9610 // Nothing to be done for scalar shifts.
9611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9612 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9615 assert(ST->hasNEON() && "unexpected vector shift");
9618 switch (N->getOpcode()) {
9619 default: llvm_unreachable("unexpected shift opcode");
9622 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9623 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9624 DAG.getConstant(Cnt, MVT::i32));
9629 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9630 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9631 ARMISD::VSHRs : ARMISD::VSHRu);
9632 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9633 DAG.getConstant(Cnt, MVT::i32));
9639 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9640 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9641 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9642 const ARMSubtarget *ST) {
9643 SDValue N0 = N->getOperand(0);
9645 // Check for sign- and zero-extensions of vector extract operations of 8-
9646 // and 16-bit vector elements. NEON supports these directly. They are
9647 // handled during DAG combining because type legalization will promote them
9648 // to 32-bit types and it is messy to recognize the operations after that.
9649 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9650 SDValue Vec = N0.getOperand(0);
9651 SDValue Lane = N0.getOperand(1);
9652 EVT VT = N->getValueType(0);
9653 EVT EltVT = N0.getValueType();
9654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9656 if (VT == MVT::i32 &&
9657 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9658 TLI.isTypeLegal(Vec.getValueType()) &&
9659 isa<ConstantSDNode>(Lane)) {
9662 switch (N->getOpcode()) {
9663 default: llvm_unreachable("unexpected opcode");
9664 case ISD::SIGN_EXTEND:
9665 Opc = ARMISD::VGETLANEs;
9667 case ISD::ZERO_EXTEND:
9668 case ISD::ANY_EXTEND:
9669 Opc = ARMISD::VGETLANEu;
9672 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9679 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9680 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9681 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9682 const ARMSubtarget *ST) {
9683 // If the target supports NEON, try to use vmax/vmin instructions for f32
9684 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9685 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9686 // a NaN; only do the transformation when it matches that behavior.
9688 // For now only do this when using NEON for FP operations; if using VFP, it
9689 // is not obvious that the benefit outweighs the cost of switching to the
9691 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9692 N->getValueType(0) != MVT::f32)
9695 SDValue CondLHS = N->getOperand(0);
9696 SDValue CondRHS = N->getOperand(1);
9697 SDValue LHS = N->getOperand(2);
9698 SDValue RHS = N->getOperand(3);
9699 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9701 unsigned Opcode = 0;
9703 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9704 IsReversed = false; // x CC y ? x : y
9705 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9706 IsReversed = true ; // x CC y ? y : x
9720 // If LHS is NaN, an ordered comparison will be false and the result will
9721 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9722 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9723 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9724 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9726 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9727 // will return -0, so vmin can only be used for unsafe math or if one of
9728 // the operands is known to be nonzero.
9729 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9730 !DAG.getTarget().Options.UnsafeFPMath &&
9731 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9733 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9742 // If LHS is NaN, an ordered comparison will be false and the result will
9743 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9744 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9745 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9746 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9748 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9749 // will return +0, so vmax can only be used for unsafe math or if one of
9750 // the operands is known to be nonzero.
9751 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9752 !DAG.getTarget().Options.UnsafeFPMath &&
9753 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9755 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9761 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9764 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9766 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9767 SDValue Cmp = N->getOperand(4);
9768 if (Cmp.getOpcode() != ARMISD::CMPZ)
9769 // Only looking at EQ and NE cases.
9772 EVT VT = N->getValueType(0);
9774 SDValue LHS = Cmp.getOperand(0);
9775 SDValue RHS = Cmp.getOperand(1);
9776 SDValue FalseVal = N->getOperand(0);
9777 SDValue TrueVal = N->getOperand(1);
9778 SDValue ARMcc = N->getOperand(2);
9779 ARMCC::CondCodes CC =
9780 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9798 /// FIXME: Turn this into a target neutral optimization?
9800 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9801 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9802 N->getOperand(3), Cmp);
9803 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9805 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9806 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9807 N->getOperand(3), NewCmp);
9810 if (Res.getNode()) {
9811 APInt KnownZero, KnownOne;
9812 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9813 // Capture demanded bits information that would be otherwise lost.
9814 if (KnownZero == 0xfffffffe)
9815 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9816 DAG.getValueType(MVT::i1));
9817 else if (KnownZero == 0xffffff00)
9818 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9819 DAG.getValueType(MVT::i8));
9820 else if (KnownZero == 0xffff0000)
9821 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9822 DAG.getValueType(MVT::i16));
9828 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9829 DAGCombinerInfo &DCI) const {
9830 switch (N->getOpcode()) {
9832 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9833 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9834 case ISD::SUB: return PerformSUBCombine(N, DCI);
9835 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9836 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9837 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9838 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9839 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9840 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
9841 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9842 case ISD::STORE: return PerformSTORECombine(N, DCI);
9843 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
9844 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9845 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9846 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9847 case ISD::FP_TO_SINT:
9848 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9849 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9850 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9853 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9854 case ISD::SIGN_EXTEND:
9855 case ISD::ZERO_EXTEND:
9856 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9857 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9858 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9859 case ARMISD::VLD2DUP:
9860 case ARMISD::VLD3DUP:
9861 case ARMISD::VLD4DUP:
9862 return CombineBaseUpdate(N, DCI);
9863 case ARMISD::BUILD_VECTOR:
9864 return PerformARMBUILD_VECTORCombine(N, DCI);
9865 case ISD::INTRINSIC_VOID:
9866 case ISD::INTRINSIC_W_CHAIN:
9867 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9868 case Intrinsic::arm_neon_vld1:
9869 case Intrinsic::arm_neon_vld2:
9870 case Intrinsic::arm_neon_vld3:
9871 case Intrinsic::arm_neon_vld4:
9872 case Intrinsic::arm_neon_vld2lane:
9873 case Intrinsic::arm_neon_vld3lane:
9874 case Intrinsic::arm_neon_vld4lane:
9875 case Intrinsic::arm_neon_vst1:
9876 case Intrinsic::arm_neon_vst2:
9877 case Intrinsic::arm_neon_vst3:
9878 case Intrinsic::arm_neon_vst4:
9879 case Intrinsic::arm_neon_vst2lane:
9880 case Intrinsic::arm_neon_vst3lane:
9881 case Intrinsic::arm_neon_vst4lane:
9882 return CombineBaseUpdate(N, DCI);
9890 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9892 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9895 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9899 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9900 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9902 switch (VT.getSimpleVT().SimpleTy) {
9908 // Unaligned access can use (for example) LRDB, LRDH, LDR
9909 if (AllowsUnaligned) {
9911 *Fast = Subtarget->hasV7Ops();
9918 // For any little-endian targets with neon, we can support unaligned ld/st
9919 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9920 // A big-endian target may also explicitly support unaligned accesses
9921 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9931 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9932 unsigned AlignCheck) {
9933 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9934 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9937 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9938 unsigned DstAlign, unsigned SrcAlign,
9939 bool IsMemset, bool ZeroMemset,
9941 MachineFunction &MF) const {
9942 const Function *F = MF.getFunction();
9944 // See if we can use NEON instructions for this...
9945 if ((!IsMemset || ZeroMemset) &&
9946 Subtarget->hasNEON() &&
9947 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
9948 Attribute::NoImplicitFloat)) {
9951 (memOpAlign(SrcAlign, DstAlign, 16) ||
9952 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
9954 } else if (Size >= 8 &&
9955 (memOpAlign(SrcAlign, DstAlign, 8) ||
9956 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
9962 // Lowering to i32/i16 if the size permits.
9968 // Let the target-independent logic figure it out.
9972 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9973 if (Val.getOpcode() != ISD::LOAD)
9976 EVT VT1 = Val.getValueType();
9977 if (!VT1.isSimple() || !VT1.isInteger() ||
9978 !VT2.isSimple() || !VT2.isInteger())
9981 switch (VT1.getSimpleVT().SimpleTy) {
9986 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9993 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
9994 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9997 if (!isTypeLegal(EVT::getEVT(Ty1)))
10000 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10002 // Assuming the caller doesn't have a zeroext or signext return parameter,
10003 // truncation all the way down to i1 is valid.
10008 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10012 unsigned Scale = 1;
10013 switch (VT.getSimpleVT().SimpleTy) {
10014 default: return false;
10029 if ((V & (Scale - 1)) != 0)
10032 return V == (V & ((1LL << 5) - 1));
10035 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10036 const ARMSubtarget *Subtarget) {
10037 bool isNeg = false;
10043 switch (VT.getSimpleVT().SimpleTy) {
10044 default: return false;
10049 // + imm12 or - imm8
10051 return V == (V & ((1LL << 8) - 1));
10052 return V == (V & ((1LL << 12) - 1));
10055 // Same as ARM mode. FIXME: NEON?
10056 if (!Subtarget->hasVFP2())
10061 return V == (V & ((1LL << 8) - 1));
10065 /// isLegalAddressImmediate - Return true if the integer value can be used
10066 /// as the offset of the target addressing mode for load / store of the
10068 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10069 const ARMSubtarget *Subtarget) {
10073 if (!VT.isSimple())
10076 if (Subtarget->isThumb1Only())
10077 return isLegalT1AddressImmediate(V, VT);
10078 else if (Subtarget->isThumb2())
10079 return isLegalT2AddressImmediate(V, VT, Subtarget);
10084 switch (VT.getSimpleVT().SimpleTy) {
10085 default: return false;
10090 return V == (V & ((1LL << 12) - 1));
10093 return V == (V & ((1LL << 8) - 1));
10096 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10101 return V == (V & ((1LL << 8) - 1));
10105 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10107 int Scale = AM.Scale;
10111 switch (VT.getSimpleVT().SimpleTy) {
10112 default: return false;
10120 Scale = Scale & ~1;
10121 return Scale == 2 || Scale == 4 || Scale == 8;
10124 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10128 // Note, we allow "void" uses (basically, uses that aren't loads or
10129 // stores), because arm allows folding a scale into many arithmetic
10130 // operations. This should be made more precise and revisited later.
10132 // Allow r << imm, but the imm has to be a multiple of two.
10133 if (Scale & 1) return false;
10134 return isPowerOf2_32(Scale);
10138 /// isLegalAddressingMode - Return true if the addressing mode represented
10139 /// by AM is legal for this target, for a load/store of the specified type.
10140 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10142 EVT VT = getValueType(Ty, true);
10143 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10146 // Can never fold addr of global into load/store.
10150 switch (AM.Scale) {
10151 case 0: // no scale reg, must be "r+i" or "r", or "i".
10154 if (Subtarget->isThumb1Only())
10158 // ARM doesn't support any R+R*scale+imm addr modes.
10162 if (!VT.isSimple())
10165 if (Subtarget->isThumb2())
10166 return isLegalT2ScaledAddressingMode(AM, VT);
10168 int Scale = AM.Scale;
10169 switch (VT.getSimpleVT().SimpleTy) {
10170 default: return false;
10174 if (Scale < 0) Scale = -Scale;
10178 return isPowerOf2_32(Scale & ~1);
10182 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10187 // Note, we allow "void" uses (basically, uses that aren't loads or
10188 // stores), because arm allows folding a scale into many arithmetic
10189 // operations. This should be made more precise and revisited later.
10191 // Allow r << imm, but the imm has to be a multiple of two.
10192 if (Scale & 1) return false;
10193 return isPowerOf2_32(Scale);
10199 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10200 /// icmp immediate, that is the target has icmp instructions which can compare
10201 /// a register against the immediate without having to materialize the
10202 /// immediate into a register.
10203 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10204 // Thumb2 and ARM modes can use cmn for negative immediates.
10205 if (!Subtarget->isThumb())
10206 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10207 if (Subtarget->isThumb2())
10208 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10209 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10210 return Imm >= 0 && Imm <= 255;
10213 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10214 /// *or sub* immediate, that is the target has add or sub instructions which can
10215 /// add a register with the immediate without having to materialize the
10216 /// immediate into a register.
10217 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10218 // Same encoding for add/sub, just flip the sign.
10219 int64_t AbsImm = llvm::abs64(Imm);
10220 if (!Subtarget->isThumb())
10221 return ARM_AM::getSOImmVal(AbsImm) != -1;
10222 if (Subtarget->isThumb2())
10223 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10224 // Thumb1 only has 8-bit unsigned immediate.
10225 return AbsImm >= 0 && AbsImm <= 255;
10228 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10229 bool isSEXTLoad, SDValue &Base,
10230 SDValue &Offset, bool &isInc,
10231 SelectionDAG &DAG) {
10232 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10235 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10236 // AddressingMode 3
10237 Base = Ptr->getOperand(0);
10238 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10239 int RHSC = (int)RHS->getZExtValue();
10240 if (RHSC < 0 && RHSC > -256) {
10241 assert(Ptr->getOpcode() == ISD::ADD);
10243 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10247 isInc = (Ptr->getOpcode() == ISD::ADD);
10248 Offset = Ptr->getOperand(1);
10250 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10251 // AddressingMode 2
10252 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10253 int RHSC = (int)RHS->getZExtValue();
10254 if (RHSC < 0 && RHSC > -0x1000) {
10255 assert(Ptr->getOpcode() == ISD::ADD);
10257 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10258 Base = Ptr->getOperand(0);
10263 if (Ptr->getOpcode() == ISD::ADD) {
10265 ARM_AM::ShiftOpc ShOpcVal=
10266 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10267 if (ShOpcVal != ARM_AM::no_shift) {
10268 Base = Ptr->getOperand(1);
10269 Offset = Ptr->getOperand(0);
10271 Base = Ptr->getOperand(0);
10272 Offset = Ptr->getOperand(1);
10277 isInc = (Ptr->getOpcode() == ISD::ADD);
10278 Base = Ptr->getOperand(0);
10279 Offset = Ptr->getOperand(1);
10283 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10287 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10288 bool isSEXTLoad, SDValue &Base,
10289 SDValue &Offset, bool &isInc,
10290 SelectionDAG &DAG) {
10291 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10294 Base = Ptr->getOperand(0);
10295 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10296 int RHSC = (int)RHS->getZExtValue();
10297 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10298 assert(Ptr->getOpcode() == ISD::ADD);
10300 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10302 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10303 isInc = Ptr->getOpcode() == ISD::ADD;
10304 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10312 /// getPreIndexedAddressParts - returns true by value, base pointer and
10313 /// offset pointer and addressing mode by reference if the node's address
10314 /// can be legally represented as pre-indexed load / store address.
10316 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10318 ISD::MemIndexedMode &AM,
10319 SelectionDAG &DAG) const {
10320 if (Subtarget->isThumb1Only())
10325 bool isSEXTLoad = false;
10326 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10327 Ptr = LD->getBasePtr();
10328 VT = LD->getMemoryVT();
10329 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10330 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10331 Ptr = ST->getBasePtr();
10332 VT = ST->getMemoryVT();
10337 bool isLegal = false;
10338 if (Subtarget->isThumb2())
10339 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10340 Offset, isInc, DAG);
10342 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10343 Offset, isInc, DAG);
10347 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10351 /// getPostIndexedAddressParts - returns true by value, base pointer and
10352 /// offset pointer and addressing mode by reference if this node can be
10353 /// combined with a load / store to form a post-indexed load / store.
10354 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10357 ISD::MemIndexedMode &AM,
10358 SelectionDAG &DAG) const {
10359 if (Subtarget->isThumb1Only())
10364 bool isSEXTLoad = false;
10365 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10366 VT = LD->getMemoryVT();
10367 Ptr = LD->getBasePtr();
10368 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10369 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10370 VT = ST->getMemoryVT();
10371 Ptr = ST->getBasePtr();
10376 bool isLegal = false;
10377 if (Subtarget->isThumb2())
10378 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10381 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10387 // Swap base ptr and offset to catch more post-index load / store when
10388 // it's legal. In Thumb2 mode, offset must be an immediate.
10389 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10390 !Subtarget->isThumb2())
10391 std::swap(Base, Offset);
10393 // Post-indexed load / store update the base pointer.
10398 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10402 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10405 const SelectionDAG &DAG,
10406 unsigned Depth) const {
10407 unsigned BitWidth = KnownOne.getBitWidth();
10408 KnownZero = KnownOne = APInt(BitWidth, 0);
10409 switch (Op.getOpcode()) {
10415 // These nodes' second result is a boolean
10416 if (Op.getResNo() == 0)
10418 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10420 case ARMISD::CMOV: {
10421 // Bits are known zero/one if known on the LHS and RHS.
10422 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10423 if (KnownZero == 0 && KnownOne == 0) return;
10425 APInt KnownZeroRHS, KnownOneRHS;
10426 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10427 KnownZero &= KnownZeroRHS;
10428 KnownOne &= KnownOneRHS;
10431 case ISD::INTRINSIC_W_CHAIN: {
10432 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10433 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10436 case Intrinsic::arm_ldaex:
10437 case Intrinsic::arm_ldrex: {
10438 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10439 unsigned MemBits = VT.getScalarType().getSizeInBits();
10440 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10448 //===----------------------------------------------------------------------===//
10449 // ARM Inline Assembly Support
10450 //===----------------------------------------------------------------------===//
10452 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10453 // Looking for "rev" which is V6+.
10454 if (!Subtarget->hasV6Ops())
10457 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10458 std::string AsmStr = IA->getAsmString();
10459 SmallVector<StringRef, 4> AsmPieces;
10460 SplitString(AsmStr, AsmPieces, ";\n");
10462 switch (AsmPieces.size()) {
10463 default: return false;
10465 AsmStr = AsmPieces[0];
10467 SplitString(AsmStr, AsmPieces, " \t,");
10470 if (AsmPieces.size() == 3 &&
10471 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10472 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10473 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10474 if (Ty && Ty->getBitWidth() == 32)
10475 return IntrinsicLowering::LowerToByteSwap(CI);
10483 /// getConstraintType - Given a constraint letter, return the type of
10484 /// constraint it is for this target.
10485 ARMTargetLowering::ConstraintType
10486 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10487 if (Constraint.size() == 1) {
10488 switch (Constraint[0]) {
10490 case 'l': return C_RegisterClass;
10491 case 'w': return C_RegisterClass;
10492 case 'h': return C_RegisterClass;
10493 case 'x': return C_RegisterClass;
10494 case 't': return C_RegisterClass;
10495 case 'j': return C_Other; // Constant for movw.
10496 // An address with a single base register. Due to the way we
10497 // currently handle addresses it is the same as an 'r' memory constraint.
10498 case 'Q': return C_Memory;
10500 } else if (Constraint.size() == 2) {
10501 switch (Constraint[0]) {
10503 // All 'U+' constraints are addresses.
10504 case 'U': return C_Memory;
10507 return TargetLowering::getConstraintType(Constraint);
10510 /// Examine constraint type and operand type and determine a weight value.
10511 /// This object must already have been set up with the operand type
10512 /// and the current alternative constraint selected.
10513 TargetLowering::ConstraintWeight
10514 ARMTargetLowering::getSingleConstraintMatchWeight(
10515 AsmOperandInfo &info, const char *constraint) const {
10516 ConstraintWeight weight = CW_Invalid;
10517 Value *CallOperandVal = info.CallOperandVal;
10518 // If we don't have a value, we can't do a match,
10519 // but allow it at the lowest weight.
10520 if (!CallOperandVal)
10522 Type *type = CallOperandVal->getType();
10523 // Look at the constraint type.
10524 switch (*constraint) {
10526 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10529 if (type->isIntegerTy()) {
10530 if (Subtarget->isThumb())
10531 weight = CW_SpecificReg;
10533 weight = CW_Register;
10537 if (type->isFloatingPointTy())
10538 weight = CW_Register;
10544 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10546 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10548 if (Constraint.size() == 1) {
10549 // GCC ARM Constraint Letters
10550 switch (Constraint[0]) {
10551 case 'l': // Low regs or general regs.
10552 if (Subtarget->isThumb())
10553 return RCPair(0U, &ARM::tGPRRegClass);
10554 return RCPair(0U, &ARM::GPRRegClass);
10555 case 'h': // High regs or no regs.
10556 if (Subtarget->isThumb())
10557 return RCPair(0U, &ARM::hGPRRegClass);
10560 return RCPair(0U, &ARM::GPRRegClass);
10562 if (VT == MVT::Other)
10564 if (VT == MVT::f32)
10565 return RCPair(0U, &ARM::SPRRegClass);
10566 if (VT.getSizeInBits() == 64)
10567 return RCPair(0U, &ARM::DPRRegClass);
10568 if (VT.getSizeInBits() == 128)
10569 return RCPair(0U, &ARM::QPRRegClass);
10572 if (VT == MVT::Other)
10574 if (VT == MVT::f32)
10575 return RCPair(0U, &ARM::SPR_8RegClass);
10576 if (VT.getSizeInBits() == 64)
10577 return RCPair(0U, &ARM::DPR_8RegClass);
10578 if (VT.getSizeInBits() == 128)
10579 return RCPair(0U, &ARM::QPR_8RegClass);
10582 if (VT == MVT::f32)
10583 return RCPair(0U, &ARM::SPRRegClass);
10587 if (StringRef("{cc}").equals_lower(Constraint))
10588 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10590 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10593 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10594 /// vector. If it is invalid, don't add anything to Ops.
10595 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10596 std::string &Constraint,
10597 std::vector<SDValue>&Ops,
10598 SelectionDAG &DAG) const {
10601 // Currently only support length 1 constraints.
10602 if (Constraint.length() != 1) return;
10604 char ConstraintLetter = Constraint[0];
10605 switch (ConstraintLetter) {
10608 case 'I': case 'J': case 'K': case 'L':
10609 case 'M': case 'N': case 'O':
10610 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10614 int64_t CVal64 = C->getSExtValue();
10615 int CVal = (int) CVal64;
10616 // None of these constraints allow values larger than 32 bits. Check
10617 // that the value fits in an int.
10618 if (CVal != CVal64)
10621 switch (ConstraintLetter) {
10623 // Constant suitable for movw, must be between 0 and
10625 if (Subtarget->hasV6T2Ops())
10626 if (CVal >= 0 && CVal <= 65535)
10630 if (Subtarget->isThumb1Only()) {
10631 // This must be a constant between 0 and 255, for ADD
10633 if (CVal >= 0 && CVal <= 255)
10635 } else if (Subtarget->isThumb2()) {
10636 // A constant that can be used as an immediate value in a
10637 // data-processing instruction.
10638 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10641 // A constant that can be used as an immediate value in a
10642 // data-processing instruction.
10643 if (ARM_AM::getSOImmVal(CVal) != -1)
10649 if (Subtarget->isThumb()) { // FIXME thumb2
10650 // This must be a constant between -255 and -1, for negated ADD
10651 // immediates. This can be used in GCC with an "n" modifier that
10652 // prints the negated value, for use with SUB instructions. It is
10653 // not useful otherwise but is implemented for compatibility.
10654 if (CVal >= -255 && CVal <= -1)
10657 // This must be a constant between -4095 and 4095. It is not clear
10658 // what this constraint is intended for. Implemented for
10659 // compatibility with GCC.
10660 if (CVal >= -4095 && CVal <= 4095)
10666 if (Subtarget->isThumb1Only()) {
10667 // A 32-bit value where only one byte has a nonzero value. Exclude
10668 // zero to match GCC. This constraint is used by GCC internally for
10669 // constants that can be loaded with a move/shift combination.
10670 // It is not useful otherwise but is implemented for compatibility.
10671 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10673 } else if (Subtarget->isThumb2()) {
10674 // A constant whose bitwise inverse can be used as an immediate
10675 // value in a data-processing instruction. This can be used in GCC
10676 // with a "B" modifier that prints the inverted value, for use with
10677 // BIC and MVN instructions. It is not useful otherwise but is
10678 // implemented for compatibility.
10679 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10682 // A constant whose bitwise inverse can be used as an immediate
10683 // value in a data-processing instruction. This can be used in GCC
10684 // with a "B" modifier that prints the inverted value, for use with
10685 // BIC and MVN instructions. It is not useful otherwise but is
10686 // implemented for compatibility.
10687 if (ARM_AM::getSOImmVal(~CVal) != -1)
10693 if (Subtarget->isThumb1Only()) {
10694 // This must be a constant between -7 and 7,
10695 // for 3-operand ADD/SUB immediate instructions.
10696 if (CVal >= -7 && CVal < 7)
10698 } else if (Subtarget->isThumb2()) {
10699 // A constant whose negation can be used as an immediate value in a
10700 // data-processing instruction. This can be used in GCC with an "n"
10701 // modifier that prints the negated value, for use with SUB
10702 // instructions. It is not useful otherwise but is implemented for
10704 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10707 // A constant whose negation can be used as an immediate value in a
10708 // data-processing instruction. This can be used in GCC with an "n"
10709 // modifier that prints the negated value, for use with SUB
10710 // instructions. It is not useful otherwise but is implemented for
10712 if (ARM_AM::getSOImmVal(-CVal) != -1)
10718 if (Subtarget->isThumb()) { // FIXME thumb2
10719 // This must be a multiple of 4 between 0 and 1020, for
10720 // ADD sp + immediate.
10721 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10724 // A power of two or a constant between 0 and 32. This is used in
10725 // GCC for the shift amount on shifted register operands, but it is
10726 // useful in general for any shift amounts.
10727 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10733 if (Subtarget->isThumb()) { // FIXME thumb2
10734 // This must be a constant between 0 and 31, for shift amounts.
10735 if (CVal >= 0 && CVal <= 31)
10741 if (Subtarget->isThumb()) { // FIXME thumb2
10742 // This must be a multiple of 4 between -508 and 508, for
10743 // ADD/SUB sp = sp + immediate.
10744 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10749 Result = DAG.getTargetConstant(CVal, Op.getValueType());
10753 if (Result.getNode()) {
10754 Ops.push_back(Result);
10757 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10760 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10761 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10762 unsigned Opcode = Op->getOpcode();
10763 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10764 "Invalid opcode for Div/Rem lowering");
10765 bool isSigned = (Opcode == ISD::SDIVREM);
10766 EVT VT = Op->getValueType(0);
10767 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10770 switch (VT.getSimpleVT().SimpleTy) {
10771 default: llvm_unreachable("Unexpected request for libcall!");
10772 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10773 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10774 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10775 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10778 SDValue InChain = DAG.getEntryNode();
10780 TargetLowering::ArgListTy Args;
10781 TargetLowering::ArgListEntry Entry;
10782 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10783 EVT ArgVT = Op->getOperand(i).getValueType();
10784 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10785 Entry.Node = Op->getOperand(i);
10787 Entry.isSExt = isSigned;
10788 Entry.isZExt = !isSigned;
10789 Args.push_back(Entry);
10792 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10795 Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
10798 TargetLowering::CallLoweringInfo CLI(DAG);
10799 CLI.setDebugLoc(dl).setChain(InChain)
10800 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10801 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10803 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10804 return CallInfo.first;
10808 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10809 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10813 SDValue Chain = Op.getOperand(0);
10814 SDValue Size = Op.getOperand(1);
10816 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10817 DAG.getConstant(2, MVT::i32));
10820 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10821 Flag = Chain.getValue(1);
10823 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10824 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10826 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10827 Chain = NewSP.getValue(1);
10829 SDValue Ops[2] = { NewSP, Chain };
10830 return DAG.getMergeValues(Ops, DL);
10833 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
10834 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
10835 "Unexpected type for custom-lowering FP_EXTEND");
10838 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
10840 SDValue SrcVal = Op.getOperand(0);
10841 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10842 /*isSigned*/ false, SDLoc(Op)).first;
10845 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
10846 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
10847 Subtarget->isFPOnlySP() &&
10848 "Unexpected type for custom-lowering FP_ROUND");
10851 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
10853 SDValue SrcVal = Op.getOperand(0);
10854 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10855 /*isSigned*/ false, SDLoc(Op)).first;
10859 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10860 // The ARM target isn't yet aware of offsets.
10864 bool ARM::isBitFieldInvertedMask(unsigned v) {
10865 if (v == 0xffffffff)
10868 // there can be 1's on either or both "outsides", all the "inside"
10869 // bits must be 0's
10870 unsigned TO = CountTrailingOnes_32(v);
10871 unsigned LO = CountLeadingOnes_32(v);
10872 v = (v >> TO) << TO;
10873 v = (v << LO) >> LO;
10877 /// isFPImmLegal - Returns true if the target can instruction select the
10878 /// specified FP immediate natively. If false, the legalizer will
10879 /// materialize the FP immediate as a load from a constant pool.
10880 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10881 if (!Subtarget->hasVFP3())
10883 if (VT == MVT::f32)
10884 return ARM_AM::getFP32Imm(Imm) != -1;
10885 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
10886 return ARM_AM::getFP64Imm(Imm) != -1;
10890 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10891 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10892 /// specified in the intrinsic calls.
10893 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10895 unsigned Intrinsic) const {
10896 switch (Intrinsic) {
10897 case Intrinsic::arm_neon_vld1:
10898 case Intrinsic::arm_neon_vld2:
10899 case Intrinsic::arm_neon_vld3:
10900 case Intrinsic::arm_neon_vld4:
10901 case Intrinsic::arm_neon_vld2lane:
10902 case Intrinsic::arm_neon_vld3lane:
10903 case Intrinsic::arm_neon_vld4lane: {
10904 Info.opc = ISD::INTRINSIC_W_CHAIN;
10905 // Conservatively set memVT to the entire set of vectors loaded.
10906 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10907 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10908 Info.ptrVal = I.getArgOperand(0);
10910 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10911 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10912 Info.vol = false; // volatile loads with NEON intrinsics not supported
10913 Info.readMem = true;
10914 Info.writeMem = false;
10917 case Intrinsic::arm_neon_vst1:
10918 case Intrinsic::arm_neon_vst2:
10919 case Intrinsic::arm_neon_vst3:
10920 case Intrinsic::arm_neon_vst4:
10921 case Intrinsic::arm_neon_vst2lane:
10922 case Intrinsic::arm_neon_vst3lane:
10923 case Intrinsic::arm_neon_vst4lane: {
10924 Info.opc = ISD::INTRINSIC_VOID;
10925 // Conservatively set memVT to the entire set of vectors stored.
10926 unsigned NumElts = 0;
10927 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10928 Type *ArgTy = I.getArgOperand(ArgI)->getType();
10929 if (!ArgTy->isVectorTy())
10931 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10933 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10934 Info.ptrVal = I.getArgOperand(0);
10936 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10937 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10938 Info.vol = false; // volatile stores with NEON intrinsics not supported
10939 Info.readMem = false;
10940 Info.writeMem = true;
10943 case Intrinsic::arm_ldaex:
10944 case Intrinsic::arm_ldrex: {
10945 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10946 Info.opc = ISD::INTRINSIC_W_CHAIN;
10947 Info.memVT = MVT::getVT(PtrTy->getElementType());
10948 Info.ptrVal = I.getArgOperand(0);
10950 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10952 Info.readMem = true;
10953 Info.writeMem = false;
10956 case Intrinsic::arm_stlex:
10957 case Intrinsic::arm_strex: {
10958 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10959 Info.opc = ISD::INTRINSIC_W_CHAIN;
10960 Info.memVT = MVT::getVT(PtrTy->getElementType());
10961 Info.ptrVal = I.getArgOperand(1);
10963 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10965 Info.readMem = false;
10966 Info.writeMem = true;
10969 case Intrinsic::arm_stlexd:
10970 case Intrinsic::arm_strexd: {
10971 Info.opc = ISD::INTRINSIC_W_CHAIN;
10972 Info.memVT = MVT::i64;
10973 Info.ptrVal = I.getArgOperand(2);
10977 Info.readMem = false;
10978 Info.writeMem = true;
10981 case Intrinsic::arm_ldaexd:
10982 case Intrinsic::arm_ldrexd: {
10983 Info.opc = ISD::INTRINSIC_W_CHAIN;
10984 Info.memVT = MVT::i64;
10985 Info.ptrVal = I.getArgOperand(0);
10989 Info.readMem = true;
10990 Info.writeMem = false;
11000 /// \brief Returns true if it is beneficial to convert a load of a constant
11001 /// to just the constant itself.
11002 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11004 assert(Ty->isIntegerTy());
11006 unsigned Bits = Ty->getPrimitiveSizeInBits();
11007 if (Bits == 0 || Bits > 32)
11012 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11014 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11015 ARM_MB::MemBOpt Domain) const {
11016 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11018 // First, if the target has no DMB, see what fallback we can use.
11019 if (!Subtarget->hasDataBarrier()) {
11020 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11021 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11023 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11024 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11025 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11026 Builder.getInt32(0), Builder.getInt32(7),
11027 Builder.getInt32(10), Builder.getInt32(5)};
11028 return Builder.CreateCall(MCR, args);
11030 // Instead of using barriers, atomic accesses on these subtargets use
11032 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11035 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11036 // Only a full system barrier exists in the M-class architectures.
11037 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11038 Constant *CDomain = Builder.getInt32(Domain);
11039 return Builder.CreateCall(DMB, CDomain);
11043 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11044 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11045 AtomicOrdering Ord, bool IsStore,
11046 bool IsLoad) const {
11047 if (!getInsertFencesForAtomic())
11053 llvm_unreachable("Invalid fence: unordered/non-atomic");
11056 return nullptr; // Nothing to do
11057 case SequentiallyConsistent:
11059 return nullptr; // Nothing to do
11062 case AcquireRelease:
11063 if (Subtarget->isSwift())
11064 return makeDMB(Builder, ARM_MB::ISHST);
11065 // FIXME: add a comment with a link to documentation justifying this.
11067 return makeDMB(Builder, ARM_MB::ISH);
11069 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11072 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11073 AtomicOrdering Ord, bool IsStore,
11074 bool IsLoad) const {
11075 if (!getInsertFencesForAtomic())
11081 llvm_unreachable("Invalid fence: unordered/not-atomic");
11084 return nullptr; // Nothing to do
11086 case AcquireRelease:
11087 case SequentiallyConsistent:
11088 return makeDMB(Builder, ARM_MB::ISH);
11090 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11093 // Loads and stores less than 64-bits are already atomic; ones above that
11094 // are doomed anyway, so defer to the default libcall and blame the OS when
11095 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11096 // anything for those.
11097 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11098 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11099 return (Size == 64) && !Subtarget->isMClass();
11102 // Loads and stores less than 64-bits are already atomic; ones above that
11103 // are doomed anyway, so defer to the default libcall and blame the OS when
11104 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11105 // anything for those.
11106 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11107 // guarantee, see DDI0406C ARM architecture reference manual,
11108 // sections A8.8.72-74 LDRD)
11109 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11110 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11111 return (Size == 64) && !Subtarget->isMClass();
11114 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11115 // and up to 64 bits on the non-M profiles
11116 bool ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11117 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11118 return Size <= (Subtarget->isMClass() ? 32U : 64U);
11121 // This has so far only been implemented for MachO.
11122 bool ARMTargetLowering::useLoadStackGuardNode() const {
11123 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO;
11126 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11127 unsigned &Cost) const {
11128 // If we do not have NEON, vector types are not natively supported.
11129 if (!Subtarget->hasNEON())
11132 // Floating point values and vector values map to the same register file.
11133 // Therefore, althought we could do a store extract of a vector type, this is
11134 // better to leave at float as we have more freedom in the addressing mode for
11136 if (VectorTy->isFPOrFPVectorTy())
11139 // If the index is unknown at compile time, this is very expensive to lower
11140 // and it is not possible to combine the store with the extract.
11141 if (!isa<ConstantInt>(Idx))
11144 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11145 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11146 // We can do a store + vector extract on any vector that fits perfectly in a D
11148 if (BitWidth == 64 || BitWidth == 128) {
11155 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11156 AtomicOrdering Ord) const {
11157 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11158 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11159 bool IsAcquire = isAtLeastAcquire(Ord);
11161 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11162 // intrinsic must return {i32, i32} and we have to recombine them into a
11163 // single i64 here.
11164 if (ValTy->getPrimitiveSizeInBits() == 64) {
11165 Intrinsic::ID Int =
11166 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11167 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11169 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11170 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11172 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11173 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11174 if (!Subtarget->isLittle())
11175 std::swap (Lo, Hi);
11176 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11177 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11178 return Builder.CreateOr(
11179 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11182 Type *Tys[] = { Addr->getType() };
11183 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11184 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11186 return Builder.CreateTruncOrBitCast(
11187 Builder.CreateCall(Ldrex, Addr),
11188 cast<PointerType>(Addr->getType())->getElementType());
11191 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11193 AtomicOrdering Ord) const {
11194 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11195 bool IsRelease = isAtLeastRelease(Ord);
11197 // Since the intrinsics must have legal type, the i64 intrinsics take two
11198 // parameters: "i32, i32". We must marshal Val into the appropriate form
11199 // before the call.
11200 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11201 Intrinsic::ID Int =
11202 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11203 Function *Strex = Intrinsic::getDeclaration(M, Int);
11204 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11206 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11207 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11208 if (!Subtarget->isLittle())
11209 std::swap (Lo, Hi);
11210 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11211 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
11214 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11215 Type *Tys[] = { Addr->getType() };
11216 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11218 return Builder.CreateCall2(
11219 Strex, Builder.CreateZExtOrBitCast(
11220 Val, Strex->getFunctionType()->getParamType(0)),
11232 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11233 uint64_t &Members) {
11234 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11235 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11236 uint64_t SubMembers = 0;
11237 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11239 Members += SubMembers;
11241 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11242 uint64_t SubMembers = 0;
11243 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11245 Members += SubMembers * AT->getNumElements();
11246 } else if (Ty->isFloatTy()) {
11247 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11251 } else if (Ty->isDoubleTy()) {
11252 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11256 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11263 return VT->getBitWidth() == 64;
11265 return VT->getBitWidth() == 128;
11267 switch (VT->getBitWidth()) {
11280 return (Members > 0 && Members <= 4);
11283 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate.
11284 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11285 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11286 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11287 CallingConv::ARM_AAPCS_VFP)
11290 HABaseType Base = HA_UNKNOWN;
11291 uint64_t Members = 0;
11292 bool result = isHomogeneousAggregate(Ty, Base, Members);
11293 DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump());