1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
88 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
89 if (ElemTy != MVT::i32) {
90 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
97 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
98 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
101 if (VT.isInteger()) {
102 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
105 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
106 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
107 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
108 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
109 setTruncStoreAction(VT.getSimpleVT(),
110 (MVT::SimpleValueType)InnerVT, Expand);
112 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
114 // Promote all bit-wise operations.
115 if (VT.isInteger() && VT != PromotedBitwiseVT) {
116 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
117 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
118 PromotedBitwiseVT.getSimpleVT());
119 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
120 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
121 PromotedBitwiseVT.getSimpleVT());
122 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
123 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
124 PromotedBitwiseVT.getSimpleVT());
127 // Neon does not support vector divide/remainder operations.
128 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
136 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
137 addRegisterClass(VT, ARM::DPRRegisterClass);
138 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
141 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
142 addRegisterClass(VT, ARM::QPRRegisterClass);
143 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
146 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
147 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
148 return new TargetLoweringObjectFileMachO();
150 return new ARMElfTargetObjectFile();
153 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
154 : TargetLowering(TM, createTLOF(TM)) {
155 Subtarget = &TM.getSubtarget<ARMSubtarget>();
156 RegInfo = TM.getRegisterInfo();
157 Itins = TM.getInstrItineraryData();
159 if (Subtarget->isTargetDarwin()) {
160 // Uses VFP for Thumb libfuncs if available.
161 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
162 // Single-precision floating-point arithmetic.
163 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
164 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
165 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
166 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
168 // Double-precision floating-point arithmetic.
169 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
170 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
171 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
172 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
174 // Single-precision comparisons.
175 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
176 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
177 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
178 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
179 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
180 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
181 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
182 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
184 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
193 // Double-precision comparisons.
194 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
195 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
196 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
197 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
198 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
199 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
200 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
201 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
203 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
212 // Floating-point to integer conversions.
213 // i64 conversions are done via library routines even when generating VFP
214 // instructions, so use the same ones.
215 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
216 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
217 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
218 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
220 // Conversions between floating types.
221 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
222 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
224 // Integer to floating-point conversions.
225 // i64 conversions are done via library routines even when generating VFP
226 // instructions, so use the same ones.
227 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
228 // e.g., __floatunsidf vs. __floatunssidfvfp.
229 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
230 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
231 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
232 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
236 // These libcalls are not available in 32-bit.
237 setLibcallName(RTLIB::SHL_I128, 0);
238 setLibcallName(RTLIB::SRL_I128, 0);
239 setLibcallName(RTLIB::SRA_I128, 0);
241 if (Subtarget->isAAPCS_ABI()) {
242 // Double-precision floating-point arithmetic helper functions
243 // RTABI chapter 4.1.2, Table 2
244 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
245 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
246 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
247 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
248 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
251 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
253 // Double-precision floating-point comparison helper functions
254 // RTABI chapter 4.1.2, Table 3
255 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
256 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
257 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
258 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
259 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
260 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
261 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
262 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
263 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
264 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
265 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
266 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
267 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
268 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
269 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
270 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
271 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
280 // Single-precision floating-point arithmetic helper functions
281 // RTABI chapter 4.1.2, Table 4
282 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
283 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
284 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
285 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
286 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
289 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
291 // Single-precision floating-point comparison helper functions
292 // RTABI chapter 4.1.2, Table 5
293 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
294 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
295 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
296 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
297 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
298 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
299 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
300 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
301 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
302 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
303 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
304 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
305 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
306 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
307 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
308 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
309 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
318 // Floating-point to integer conversions.
319 // RTABI chapter 4.1.2, Table 6
320 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
321 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
322 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
323 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
324 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
325 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
326 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
327 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
328 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
337 // Conversions between floating types.
338 // RTABI chapter 4.1.2, Table 7
339 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
340 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
341 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
342 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
344 // Integer to floating-point conversions.
345 // RTABI chapter 4.1.2, Table 8
346 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
347 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
348 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
349 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
350 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
351 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
352 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
353 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
354 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
363 // Long long helper functions
364 // RTABI chapter 4.2, Table 9
365 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
366 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
367 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
368 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
369 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
370 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
371 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
378 // Integer division functions
379 // RTABI chapter 4.3.1
380 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
382 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
383 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
385 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
386 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
394 if (Subtarget->isThumb1Only())
395 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
397 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
398 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
399 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
400 if (!Subtarget->isFPOnlySP())
401 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
403 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
406 if (Subtarget->hasNEON()) {
407 addDRTypeForNEON(MVT::v2f32);
408 addDRTypeForNEON(MVT::v8i8);
409 addDRTypeForNEON(MVT::v4i16);
410 addDRTypeForNEON(MVT::v2i32);
411 addDRTypeForNEON(MVT::v1i64);
413 addQRTypeForNEON(MVT::v4f32);
414 addQRTypeForNEON(MVT::v2f64);
415 addQRTypeForNEON(MVT::v16i8);
416 addQRTypeForNEON(MVT::v8i16);
417 addQRTypeForNEON(MVT::v4i32);
418 addQRTypeForNEON(MVT::v2i64);
420 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
421 // neither Neon nor VFP support any arithmetic operations on it.
422 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
423 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
424 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
425 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
426 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
427 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
428 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
429 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
430 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
432 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
433 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
435 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
438 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
440 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
441 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
442 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
443 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
445 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
447 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
449 // Neon does not support some operations on v1i64 and v2i64 types.
450 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
451 // Custom handling for some quad-vector types to detect VMULL.
452 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
453 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
454 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
455 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
456 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
458 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
459 setTargetDAGCombine(ISD::SHL);
460 setTargetDAGCombine(ISD::SRL);
461 setTargetDAGCombine(ISD::SRA);
462 setTargetDAGCombine(ISD::SIGN_EXTEND);
463 setTargetDAGCombine(ISD::ZERO_EXTEND);
464 setTargetDAGCombine(ISD::ANY_EXTEND);
465 setTargetDAGCombine(ISD::SELECT_CC);
466 setTargetDAGCombine(ISD::BUILD_VECTOR);
467 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
470 computeRegisterProperties();
472 // ARM does not have f32 extending load.
473 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
475 // ARM does not have i1 sign extending load.
476 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
478 // ARM supports all 4 flavors of integer indexed load / store.
479 if (!Subtarget->isThumb1Only()) {
480 for (unsigned im = (unsigned)ISD::PRE_INC;
481 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
482 setIndexedLoadAction(im, MVT::i1, Legal);
483 setIndexedLoadAction(im, MVT::i8, Legal);
484 setIndexedLoadAction(im, MVT::i16, Legal);
485 setIndexedLoadAction(im, MVT::i32, Legal);
486 setIndexedStoreAction(im, MVT::i1, Legal);
487 setIndexedStoreAction(im, MVT::i8, Legal);
488 setIndexedStoreAction(im, MVT::i16, Legal);
489 setIndexedStoreAction(im, MVT::i32, Legal);
493 // i64 operation support.
494 if (Subtarget->isThumb1Only()) {
495 setOperationAction(ISD::MUL, MVT::i64, Expand);
496 setOperationAction(ISD::MULHU, MVT::i32, Expand);
497 setOperationAction(ISD::MULHS, MVT::i32, Expand);
498 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
499 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
501 setOperationAction(ISD::MUL, MVT::i64, Expand);
502 setOperationAction(ISD::MULHU, MVT::i32, Expand);
503 if (!Subtarget->hasV6Ops())
504 setOperationAction(ISD::MULHS, MVT::i32, Expand);
506 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
507 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
509 setOperationAction(ISD::SRL, MVT::i64, Custom);
510 setOperationAction(ISD::SRA, MVT::i64, Custom);
512 // ARM does not have ROTL.
513 setOperationAction(ISD::ROTL, MVT::i32, Expand);
514 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
515 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
516 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
517 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
519 // Only ARMv6 has BSWAP.
520 if (!Subtarget->hasV6Ops())
521 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
523 // These are expanded into libcalls.
524 if (!Subtarget->hasDivide()) {
525 // v7M has a hardware divider
526 setOperationAction(ISD::SDIV, MVT::i32, Expand);
527 setOperationAction(ISD::UDIV, MVT::i32, Expand);
529 setOperationAction(ISD::SREM, MVT::i32, Expand);
530 setOperationAction(ISD::UREM, MVT::i32, Expand);
531 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
532 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
534 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
535 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
536 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
537 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
538 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
540 setOperationAction(ISD::TRAP, MVT::Other, Legal);
542 // Use the default implementation.
543 setOperationAction(ISD::VASTART, MVT::Other, Custom);
544 setOperationAction(ISD::VAARG, MVT::Other, Expand);
545 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
546 setOperationAction(ISD::VAEND, MVT::Other, Expand);
547 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
548 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
549 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
550 // FIXME: Shouldn't need this, since no register is used, but the legalizer
551 // doesn't yet know how to not do that for SjLj.
552 setExceptionSelectorRegister(ARM::R0);
553 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
554 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
555 // the default expansion.
556 if (Subtarget->hasDataBarrier() ||
557 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
558 // membarrier needs custom lowering; the rest are legal and handled
560 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
562 // Set them all for expansion, which will force libcalls.
563 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
564 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
566 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
567 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
569 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
570 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
588 // Since the libcalls include locking, fold in the fences
589 setShouldFoldAtomicFences(true);
591 // 64-bit versions are always libcalls (for now)
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
593 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
601 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
603 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
604 if (!Subtarget->hasV6Ops()) {
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
610 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
611 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
612 // iff target supports vfp2.
613 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
614 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
617 // We want to custom lower some of our intrinsics.
618 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
619 if (Subtarget->isTargetDarwin()) {
620 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
621 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
622 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
625 setOperationAction(ISD::SETCC, MVT::i32, Expand);
626 setOperationAction(ISD::SETCC, MVT::f32, Expand);
627 setOperationAction(ISD::SETCC, MVT::f64, Expand);
628 setOperationAction(ISD::SELECT, MVT::i32, Custom);
629 setOperationAction(ISD::SELECT, MVT::f32, Custom);
630 setOperationAction(ISD::SELECT, MVT::f64, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
633 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
635 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
636 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
637 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
638 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
639 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
641 // We don't support sin/cos/fmod/copysign/pow
642 setOperationAction(ISD::FSIN, MVT::f64, Expand);
643 setOperationAction(ISD::FSIN, MVT::f32, Expand);
644 setOperationAction(ISD::FCOS, MVT::f32, Expand);
645 setOperationAction(ISD::FCOS, MVT::f64, Expand);
646 setOperationAction(ISD::FREM, MVT::f64, Expand);
647 setOperationAction(ISD::FREM, MVT::f32, Expand);
648 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
649 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
650 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
652 setOperationAction(ISD::FPOW, MVT::f64, Expand);
653 setOperationAction(ISD::FPOW, MVT::f32, Expand);
655 // Various VFP goodness
656 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
657 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
658 if (Subtarget->hasVFP2()) {
659 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
660 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
661 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
662 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
664 // Special handling for half-precision FP.
665 if (!Subtarget->hasFP16()) {
666 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
667 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
671 // We have target-specific dag combine patterns for the following nodes:
672 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
673 setTargetDAGCombine(ISD::ADD);
674 setTargetDAGCombine(ISD::SUB);
675 setTargetDAGCombine(ISD::MUL);
677 if (Subtarget->hasV6T2Ops())
678 setTargetDAGCombine(ISD::OR);
680 setStackPointerRegisterToSaveRestore(ARM::SP);
682 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
683 setSchedulingPreference(Sched::RegPressure);
685 setSchedulingPreference(Sched::Hybrid);
687 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
689 // On ARM arguments smaller than 4 bytes are extended, so all arguments
690 // are at least 4 bytes aligned.
691 setMinStackArgumentAlignment(4);
693 benefitFromCodePlacementOpt = true;
696 std::pair<const TargetRegisterClass*, uint8_t>
697 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
698 const TargetRegisterClass *RRC = 0;
700 switch (VT.getSimpleVT().SimpleTy) {
702 return TargetLowering::findRepresentativeClass(VT);
703 // Use DPR as representative register class for all floating point
704 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
705 // the cost is 1 for both f32 and f64.
706 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
707 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
708 RRC = ARM::DPRRegisterClass;
710 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
711 case MVT::v4f32: case MVT::v2f64:
712 RRC = ARM::DPRRegisterClass;
716 RRC = ARM::DPRRegisterClass;
720 RRC = ARM::DPRRegisterClass;
724 return std::make_pair(RRC, Cost);
727 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
730 case ARMISD::Wrapper: return "ARMISD::Wrapper";
731 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
732 case ARMISD::CALL: return "ARMISD::CALL";
733 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
734 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
735 case ARMISD::tCALL: return "ARMISD::tCALL";
736 case ARMISD::BRCOND: return "ARMISD::BRCOND";
737 case ARMISD::BR_JT: return "ARMISD::BR_JT";
738 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
739 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
740 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
741 case ARMISD::CMP: return "ARMISD::CMP";
742 case ARMISD::CMPZ: return "ARMISD::CMPZ";
743 case ARMISD::CMPFP: return "ARMISD::CMPFP";
744 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
745 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
746 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
747 case ARMISD::CMOV: return "ARMISD::CMOV";
748 case ARMISD::CNEG: return "ARMISD::CNEG";
750 case ARMISD::RBIT: return "ARMISD::RBIT";
752 case ARMISD::FTOSI: return "ARMISD::FTOSI";
753 case ARMISD::FTOUI: return "ARMISD::FTOUI";
754 case ARMISD::SITOF: return "ARMISD::SITOF";
755 case ARMISD::UITOF: return "ARMISD::UITOF";
757 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
758 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
759 case ARMISD::RRX: return "ARMISD::RRX";
761 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
762 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
764 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
765 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
766 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
768 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
770 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
772 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
774 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
775 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
777 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
779 case ARMISD::VCEQ: return "ARMISD::VCEQ";
780 case ARMISD::VCGE: return "ARMISD::VCGE";
781 case ARMISD::VCGEU: return "ARMISD::VCGEU";
782 case ARMISD::VCGT: return "ARMISD::VCGT";
783 case ARMISD::VCGTU: return "ARMISD::VCGTU";
784 case ARMISD::VTST: return "ARMISD::VTST";
786 case ARMISD::VSHL: return "ARMISD::VSHL";
787 case ARMISD::VSHRs: return "ARMISD::VSHRs";
788 case ARMISD::VSHRu: return "ARMISD::VSHRu";
789 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
790 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
791 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
792 case ARMISD::VSHRN: return "ARMISD::VSHRN";
793 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
794 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
795 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
796 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
797 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
798 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
799 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
800 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
801 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
802 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
803 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
804 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
805 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
806 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
807 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
808 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
809 case ARMISD::VDUP: return "ARMISD::VDUP";
810 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
811 case ARMISD::VEXT: return "ARMISD::VEXT";
812 case ARMISD::VREV64: return "ARMISD::VREV64";
813 case ARMISD::VREV32: return "ARMISD::VREV32";
814 case ARMISD::VREV16: return "ARMISD::VREV16";
815 case ARMISD::VZIP: return "ARMISD::VZIP";
816 case ARMISD::VUZP: return "ARMISD::VUZP";
817 case ARMISD::VTRN: return "ARMISD::VTRN";
818 case ARMISD::VMULLs: return "ARMISD::VMULLs";
819 case ARMISD::VMULLu: return "ARMISD::VMULLu";
820 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
821 case ARMISD::FMAX: return "ARMISD::FMAX";
822 case ARMISD::FMIN: return "ARMISD::FMIN";
823 case ARMISD::BFI: return "ARMISD::BFI";
827 /// getRegClassFor - Return the register class that should be used for the
828 /// specified value type.
829 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
830 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
831 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
832 // load / store 4 to 8 consecutive D registers.
833 if (Subtarget->hasNEON()) {
834 if (VT == MVT::v4i64)
835 return ARM::QQPRRegisterClass;
836 else if (VT == MVT::v8i64)
837 return ARM::QQQQPRRegisterClass;
839 return TargetLowering::getRegClassFor(VT);
842 // Create a fast isel object.
844 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
845 return ARM::createFastISel(funcInfo);
848 /// getFunctionAlignment - Return the Log2 alignment of this function.
849 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
850 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
853 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
854 /// be used for loads / stores from the global.
855 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
856 return (Subtarget->isThumb1Only() ? 127 : 4095);
859 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
860 unsigned NumVals = N->getNumValues();
862 return Sched::RegPressure;
864 for (unsigned i = 0; i != NumVals; ++i) {
865 EVT VT = N->getValueType(i);
866 if (VT == MVT::Flag || VT == MVT::Other)
868 if (VT.isFloatingPoint() || VT.isVector())
869 return Sched::Latency;
872 if (!N->isMachineOpcode())
873 return Sched::RegPressure;
875 // Load are scheduled for latency even if there instruction itinerary
877 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
878 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
880 if (TID.getNumDefs() == 0)
881 return Sched::RegPressure;
882 if (!Itins->isEmpty() &&
883 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
884 return Sched::Latency;
886 return Sched::RegPressure;
890 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
891 MachineFunction &MF) const {
892 switch (RC->getID()) {
895 case ARM::tGPRRegClassID:
896 return RegInfo->hasFP(MF) ? 4 : 5;
897 case ARM::GPRRegClassID: {
898 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
899 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
901 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
902 case ARM::DPRRegClassID:
907 //===----------------------------------------------------------------------===//
909 //===----------------------------------------------------------------------===//
911 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
912 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
914 default: llvm_unreachable("Unknown condition code!");
915 case ISD::SETNE: return ARMCC::NE;
916 case ISD::SETEQ: return ARMCC::EQ;
917 case ISD::SETGT: return ARMCC::GT;
918 case ISD::SETGE: return ARMCC::GE;
919 case ISD::SETLT: return ARMCC::LT;
920 case ISD::SETLE: return ARMCC::LE;
921 case ISD::SETUGT: return ARMCC::HI;
922 case ISD::SETUGE: return ARMCC::HS;
923 case ISD::SETULT: return ARMCC::LO;
924 case ISD::SETULE: return ARMCC::LS;
928 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
929 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
930 ARMCC::CondCodes &CondCode2) {
931 CondCode2 = ARMCC::AL;
933 default: llvm_unreachable("Unknown FP condition!");
935 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
937 case ISD::SETOGT: CondCode = ARMCC::GT; break;
939 case ISD::SETOGE: CondCode = ARMCC::GE; break;
940 case ISD::SETOLT: CondCode = ARMCC::MI; break;
941 case ISD::SETOLE: CondCode = ARMCC::LS; break;
942 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
943 case ISD::SETO: CondCode = ARMCC::VC; break;
944 case ISD::SETUO: CondCode = ARMCC::VS; break;
945 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
946 case ISD::SETUGT: CondCode = ARMCC::HI; break;
947 case ISD::SETUGE: CondCode = ARMCC::PL; break;
949 case ISD::SETULT: CondCode = ARMCC::LT; break;
951 case ISD::SETULE: CondCode = ARMCC::LE; break;
953 case ISD::SETUNE: CondCode = ARMCC::NE; break;
957 //===----------------------------------------------------------------------===//
958 // Calling Convention Implementation
959 //===----------------------------------------------------------------------===//
961 #include "ARMGenCallingConv.inc"
963 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
964 /// given CallingConvention value.
965 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
967 bool isVarArg) const {
970 llvm_unreachable("Unsupported calling convention");
971 case CallingConv::Fast:
972 if (Subtarget->hasVFP2() && !isVarArg) {
973 if (!Subtarget->isAAPCS_ABI())
974 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
975 // For AAPCS ABI targets, just use VFP variant of the calling convention.
976 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
979 case CallingConv::C: {
980 // Use target triple & subtarget features to do actual dispatch.
981 if (!Subtarget->isAAPCS_ABI())
982 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
983 else if (Subtarget->hasVFP2() &&
984 FloatABIType == FloatABI::Hard && !isVarArg)
985 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
986 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
988 case CallingConv::ARM_AAPCS_VFP:
989 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
990 case CallingConv::ARM_AAPCS:
991 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
992 case CallingConv::ARM_APCS:
993 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
997 /// LowerCallResult - Lower the result values of a call into the
998 /// appropriate copies out of appropriate physical registers.
1000 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1001 CallingConv::ID CallConv, bool isVarArg,
1002 const SmallVectorImpl<ISD::InputArg> &Ins,
1003 DebugLoc dl, SelectionDAG &DAG,
1004 SmallVectorImpl<SDValue> &InVals) const {
1006 // Assign locations to each value returned by this call.
1007 SmallVector<CCValAssign, 16> RVLocs;
1008 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1009 RVLocs, *DAG.getContext());
1010 CCInfo.AnalyzeCallResult(Ins,
1011 CCAssignFnForNode(CallConv, /* Return*/ true,
1014 // Copy all of the result registers out of their specified physreg.
1015 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1016 CCValAssign VA = RVLocs[i];
1019 if (VA.needsCustom()) {
1020 // Handle f64 or half of a v2f64.
1021 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1023 Chain = Lo.getValue(1);
1024 InFlag = Lo.getValue(2);
1025 VA = RVLocs[++i]; // skip ahead to next loc
1026 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1028 Chain = Hi.getValue(1);
1029 InFlag = Hi.getValue(2);
1030 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1032 if (VA.getLocVT() == MVT::v2f64) {
1033 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1034 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1035 DAG.getConstant(0, MVT::i32));
1037 VA = RVLocs[++i]; // skip ahead to next loc
1038 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1039 Chain = Lo.getValue(1);
1040 InFlag = Lo.getValue(2);
1041 VA = RVLocs[++i]; // skip ahead to next loc
1042 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1043 Chain = Hi.getValue(1);
1044 InFlag = Hi.getValue(2);
1045 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1046 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1047 DAG.getConstant(1, MVT::i32));
1050 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1052 Chain = Val.getValue(1);
1053 InFlag = Val.getValue(2);
1056 switch (VA.getLocInfo()) {
1057 default: llvm_unreachable("Unknown loc info!");
1058 case CCValAssign::Full: break;
1059 case CCValAssign::BCvt:
1060 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1064 InVals.push_back(Val);
1070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1071 /// by "Src" to address "Dst" of size "Size". Alignment information is
1072 /// specified by the specific parameter attribute. The copy will be passed as
1073 /// a byval function parameter.
1074 /// Sometimes what we are copying is the end of a larger object, the part that
1075 /// does not fit in registers.
1077 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1078 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1080 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1081 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1082 /*isVolatile=*/false, /*AlwaysInline=*/false,
1083 MachinePointerInfo(0), MachinePointerInfo(0));
1086 /// LowerMemOpCallTo - Store the argument to the stack.
1088 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1089 SDValue StackPtr, SDValue Arg,
1090 DebugLoc dl, SelectionDAG &DAG,
1091 const CCValAssign &VA,
1092 ISD::ArgFlagsTy Flags) const {
1093 unsigned LocMemOffset = VA.getLocMemOffset();
1094 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1095 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1096 if (Flags.isByVal())
1097 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1099 return DAG.getStore(Chain, dl, Arg, PtrOff,
1100 MachinePointerInfo::getStack(LocMemOffset),
1104 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1105 SDValue Chain, SDValue &Arg,
1106 RegsToPassVector &RegsToPass,
1107 CCValAssign &VA, CCValAssign &NextVA,
1109 SmallVector<SDValue, 8> &MemOpChains,
1110 ISD::ArgFlagsTy Flags) const {
1112 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1113 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1114 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1116 if (NextVA.isRegLoc())
1117 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1119 assert(NextVA.isMemLoc());
1120 if (StackPtr.getNode() == 0)
1121 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1123 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1129 /// LowerCall - Lowering a call into a callseq_start <-
1130 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1133 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1134 CallingConv::ID CallConv, bool isVarArg,
1136 const SmallVectorImpl<ISD::OutputArg> &Outs,
1137 const SmallVectorImpl<SDValue> &OutVals,
1138 const SmallVectorImpl<ISD::InputArg> &Ins,
1139 DebugLoc dl, SelectionDAG &DAG,
1140 SmallVectorImpl<SDValue> &InVals) const {
1141 MachineFunction &MF = DAG.getMachineFunction();
1142 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1143 bool IsSibCall = false;
1144 // Temporarily disable tail calls so things don't break.
1145 if (!EnableARMTailCalls)
1148 // Check if it's really possible to do a tail call.
1149 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1150 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1151 Outs, OutVals, Ins, DAG);
1152 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1153 // detected sibcalls.
1160 // Analyze operands of the call, assigning locations to each operand.
1161 SmallVector<CCValAssign, 16> ArgLocs;
1162 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1164 CCInfo.AnalyzeCallOperands(Outs,
1165 CCAssignFnForNode(CallConv, /* Return*/ false,
1168 // Get a count of how many bytes are to be pushed on the stack.
1169 unsigned NumBytes = CCInfo.getNextStackOffset();
1171 // For tail calls, memory operands are available in our caller's stack.
1175 // Adjust the stack pointer for the new arguments...
1176 // These operations are automatically eliminated by the prolog/epilog pass
1178 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1180 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1182 RegsToPassVector RegsToPass;
1183 SmallVector<SDValue, 8> MemOpChains;
1185 // Walk the register/memloc assignments, inserting copies/loads. In the case
1186 // of tail call optimization, arguments are handled later.
1187 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1189 ++i, ++realArgIdx) {
1190 CCValAssign &VA = ArgLocs[i];
1191 SDValue Arg = OutVals[realArgIdx];
1192 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1194 // Promote the value if needed.
1195 switch (VA.getLocInfo()) {
1196 default: llvm_unreachable("Unknown loc info!");
1197 case CCValAssign::Full: break;
1198 case CCValAssign::SExt:
1199 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1201 case CCValAssign::ZExt:
1202 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1204 case CCValAssign::AExt:
1205 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1207 case CCValAssign::BCvt:
1208 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1212 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1213 if (VA.needsCustom()) {
1214 if (VA.getLocVT() == MVT::v2f64) {
1215 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1216 DAG.getConstant(0, MVT::i32));
1217 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1218 DAG.getConstant(1, MVT::i32));
1220 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1221 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1223 VA = ArgLocs[++i]; // skip ahead to next loc
1224 if (VA.isRegLoc()) {
1225 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1226 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1228 assert(VA.isMemLoc());
1230 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1231 dl, DAG, VA, Flags));
1234 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1235 StackPtr, MemOpChains, Flags);
1237 } else if (VA.isRegLoc()) {
1238 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1239 } else if (!IsSibCall) {
1240 assert(VA.isMemLoc());
1242 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1243 dl, DAG, VA, Flags));
1247 if (!MemOpChains.empty())
1248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1249 &MemOpChains[0], MemOpChains.size());
1251 // Build a sequence of copy-to-reg nodes chained together with token chain
1252 // and flag operands which copy the outgoing args into the appropriate regs.
1254 // Tail call byval lowering might overwrite argument registers so in case of
1255 // tail call optimization the copies to registers are lowered later.
1257 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1258 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1259 RegsToPass[i].second, InFlag);
1260 InFlag = Chain.getValue(1);
1263 // For tail calls lower the arguments to the 'real' stack slot.
1265 // Force all the incoming stack arguments to be loaded from the stack
1266 // before any new outgoing arguments are stored to the stack, because the
1267 // outgoing stack slots may alias the incoming argument stack slots, and
1268 // the alias isn't otherwise explicit. This is slightly more conservative
1269 // than necessary, because it means that each store effectively depends
1270 // on every argument instead of just those arguments it would clobber.
1272 // Do not flag preceeding copytoreg stuff together with the following stuff.
1274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1275 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1276 RegsToPass[i].second, InFlag);
1277 InFlag = Chain.getValue(1);
1282 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1283 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1284 // node so that legalize doesn't hack it.
1285 bool isDirect = false;
1286 bool isARMFunc = false;
1287 bool isLocalARMFunc = false;
1288 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1290 if (EnableARMLongCalls) {
1291 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1292 && "long-calls with non-static relocation model!");
1293 // Handle a global address or an external symbol. If it's not one of
1294 // those, the target's already in a register, so we don't need to do
1296 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1297 const GlobalValue *GV = G->getGlobal();
1298 // Create a constant pool entry for the callee address
1299 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1300 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1303 // Get the address of the callee into a register
1304 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1305 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1306 Callee = DAG.getLoad(getPointerTy(), dl,
1307 DAG.getEntryNode(), CPAddr,
1308 MachinePointerInfo::getConstantPool(),
1310 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1311 const char *Sym = S->getSymbol();
1313 // Create a constant pool entry for the callee address
1314 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1315 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1316 Sym, ARMPCLabelIndex, 0);
1317 // Get the address of the callee into a register
1318 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1319 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1320 Callee = DAG.getLoad(getPointerTy(), dl,
1321 DAG.getEntryNode(), CPAddr,
1322 MachinePointerInfo::getConstantPool(),
1325 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1326 const GlobalValue *GV = G->getGlobal();
1328 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1329 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1330 getTargetMachine().getRelocationModel() != Reloc::Static;
1331 isARMFunc = !Subtarget->isThumb() || isStub;
1332 // ARM call to a local ARM function is predicable.
1333 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1334 // tBX takes a register source operand.
1335 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1336 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1337 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1340 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1341 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1342 Callee = DAG.getLoad(getPointerTy(), dl,
1343 DAG.getEntryNode(), CPAddr,
1344 MachinePointerInfo::getConstantPool(),
1346 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1347 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1348 getPointerTy(), Callee, PICLabel);
1350 // On ELF targets for PIC code, direct calls should go through the PLT
1351 unsigned OpFlags = 0;
1352 if (Subtarget->isTargetELF() &&
1353 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1354 OpFlags = ARMII::MO_PLT;
1355 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1357 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1359 bool isStub = Subtarget->isTargetDarwin() &&
1360 getTargetMachine().getRelocationModel() != Reloc::Static;
1361 isARMFunc = !Subtarget->isThumb() || isStub;
1362 // tBX takes a register source operand.
1363 const char *Sym = S->getSymbol();
1364 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1365 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1366 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1367 Sym, ARMPCLabelIndex, 4);
1368 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1369 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1370 Callee = DAG.getLoad(getPointerTy(), dl,
1371 DAG.getEntryNode(), CPAddr,
1372 MachinePointerInfo::getConstantPool(),
1374 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1375 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1376 getPointerTy(), Callee, PICLabel);
1378 unsigned OpFlags = 0;
1379 // On ELF targets for PIC code, direct calls should go through the PLT
1380 if (Subtarget->isTargetELF() &&
1381 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1382 OpFlags = ARMII::MO_PLT;
1383 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1387 // FIXME: handle tail calls differently.
1389 if (Subtarget->isThumb()) {
1390 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1391 CallOpc = ARMISD::CALL_NOLINK;
1393 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1395 CallOpc = (isDirect || Subtarget->hasV5TOps())
1396 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1397 : ARMISD::CALL_NOLINK;
1400 std::vector<SDValue> Ops;
1401 Ops.push_back(Chain);
1402 Ops.push_back(Callee);
1404 // Add argument registers to the end of the list so that they are known live
1406 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1407 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1408 RegsToPass[i].second.getValueType()));
1410 if (InFlag.getNode())
1411 Ops.push_back(InFlag);
1413 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1415 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1417 // Returns a chain and a flag for retval copy to use.
1418 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1419 InFlag = Chain.getValue(1);
1421 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1422 DAG.getIntPtrConstant(0, true), InFlag);
1424 InFlag = Chain.getValue(1);
1426 // Handle result values, copying them out of physregs into vregs that we
1428 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1432 /// MatchingStackOffset - Return true if the given stack call argument is
1433 /// already available in the same position (relatively) of the caller's
1434 /// incoming argument stack.
1436 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1437 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1438 const ARMInstrInfo *TII) {
1439 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1441 if (Arg.getOpcode() == ISD::CopyFromReg) {
1442 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1443 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1445 MachineInstr *Def = MRI->getVRegDef(VR);
1448 if (!Flags.isByVal()) {
1449 if (!TII->isLoadFromStackSlot(Def, FI))
1454 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1455 if (Flags.isByVal())
1456 // ByVal argument is passed in as a pointer but it's now being
1457 // dereferenced. e.g.
1458 // define @foo(%struct.X* %A) {
1459 // tail call @bar(%struct.X* byval %A)
1462 SDValue Ptr = Ld->getBasePtr();
1463 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1466 FI = FINode->getIndex();
1470 assert(FI != INT_MAX);
1471 if (!MFI->isFixedObjectIndex(FI))
1473 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1476 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1477 /// for tail call optimization. Targets which want to do tail call
1478 /// optimization should implement this function.
1480 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1481 CallingConv::ID CalleeCC,
1483 bool isCalleeStructRet,
1484 bool isCallerStructRet,
1485 const SmallVectorImpl<ISD::OutputArg> &Outs,
1486 const SmallVectorImpl<SDValue> &OutVals,
1487 const SmallVectorImpl<ISD::InputArg> &Ins,
1488 SelectionDAG& DAG) const {
1489 const Function *CallerF = DAG.getMachineFunction().getFunction();
1490 CallingConv::ID CallerCC = CallerF->getCallingConv();
1491 bool CCMatch = CallerCC == CalleeCC;
1493 // Look for obvious safe cases to perform tail call optimization that do not
1494 // require ABI changes. This is what gcc calls sibcall.
1496 // Do not sibcall optimize vararg calls unless the call site is not passing
1498 if (isVarArg && !Outs.empty())
1501 // Also avoid sibcall optimization if either caller or callee uses struct
1502 // return semantics.
1503 if (isCalleeStructRet || isCallerStructRet)
1506 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1507 // emitEpilogue is not ready for them.
1508 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1509 // LR. This means if we need to reload LR, it takes an extra instructions,
1510 // which outweighs the value of the tail call; but here we don't know yet
1511 // whether LR is going to be used. Probably the right approach is to
1512 // generate the tail call here and turn it back into CALL/RET in
1513 // emitEpilogue if LR is used.
1514 if (Subtarget->isThumb1Only())
1517 // For the moment, we can only do this to functions defined in this
1518 // compilation, or to indirect calls. A Thumb B to an ARM function,
1519 // or vice versa, is not easily fixed up in the linker unlike BL.
1520 // (We could do this by loading the address of the callee into a register;
1521 // that is an extra instruction over the direct call and burns a register
1522 // as well, so is not likely to be a win.)
1524 // It might be safe to remove this restriction on non-Darwin.
1526 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1527 // but we need to make sure there are enough registers; the only valid
1528 // registers are the 4 used for parameters. We don't currently do this
1530 if (isa<ExternalSymbolSDNode>(Callee))
1533 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1534 const GlobalValue *GV = G->getGlobal();
1535 if (GV->isDeclaration() || GV->isWeakForLinker())
1539 // If the calling conventions do not match, then we'd better make sure the
1540 // results are returned in the same way as what the caller expects.
1542 SmallVector<CCValAssign, 16> RVLocs1;
1543 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1544 RVLocs1, *DAG.getContext());
1545 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1547 SmallVector<CCValAssign, 16> RVLocs2;
1548 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1549 RVLocs2, *DAG.getContext());
1550 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1552 if (RVLocs1.size() != RVLocs2.size())
1554 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1555 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1557 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1559 if (RVLocs1[i].isRegLoc()) {
1560 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1563 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1569 // If the callee takes no arguments then go on to check the results of the
1571 if (!Outs.empty()) {
1572 // Check if stack adjustment is needed. For now, do not do this if any
1573 // argument is passed on the stack.
1574 SmallVector<CCValAssign, 16> ArgLocs;
1575 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1576 ArgLocs, *DAG.getContext());
1577 CCInfo.AnalyzeCallOperands(Outs,
1578 CCAssignFnForNode(CalleeCC, false, isVarArg));
1579 if (CCInfo.getNextStackOffset()) {
1580 MachineFunction &MF = DAG.getMachineFunction();
1582 // Check if the arguments are already laid out in the right way as
1583 // the caller's fixed stack objects.
1584 MachineFrameInfo *MFI = MF.getFrameInfo();
1585 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1586 const ARMInstrInfo *TII =
1587 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1588 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1590 ++i, ++realArgIdx) {
1591 CCValAssign &VA = ArgLocs[i];
1592 EVT RegVT = VA.getLocVT();
1593 SDValue Arg = OutVals[realArgIdx];
1594 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1595 if (VA.getLocInfo() == CCValAssign::Indirect)
1597 if (VA.needsCustom()) {
1598 // f64 and vector types are split into multiple registers or
1599 // register/stack-slot combinations. The types will not match
1600 // the registers; give up on memory f64 refs until we figure
1601 // out what to do about this.
1604 if (!ArgLocs[++i].isRegLoc())
1606 if (RegVT == MVT::v2f64) {
1607 if (!ArgLocs[++i].isRegLoc())
1609 if (!ArgLocs[++i].isRegLoc())
1612 } else if (!VA.isRegLoc()) {
1613 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1625 ARMTargetLowering::LowerReturn(SDValue Chain,
1626 CallingConv::ID CallConv, bool isVarArg,
1627 const SmallVectorImpl<ISD::OutputArg> &Outs,
1628 const SmallVectorImpl<SDValue> &OutVals,
1629 DebugLoc dl, SelectionDAG &DAG) const {
1631 // CCValAssign - represent the assignment of the return value to a location.
1632 SmallVector<CCValAssign, 16> RVLocs;
1634 // CCState - Info about the registers and stack slots.
1635 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1638 // Analyze outgoing return values.
1639 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1642 // If this is the first return lowered for this function, add
1643 // the regs to the liveout set for the function.
1644 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1645 for (unsigned i = 0; i != RVLocs.size(); ++i)
1646 if (RVLocs[i].isRegLoc())
1647 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1652 // Copy the result values into the output registers.
1653 for (unsigned i = 0, realRVLocIdx = 0;
1655 ++i, ++realRVLocIdx) {
1656 CCValAssign &VA = RVLocs[i];
1657 assert(VA.isRegLoc() && "Can only return in registers!");
1659 SDValue Arg = OutVals[realRVLocIdx];
1661 switch (VA.getLocInfo()) {
1662 default: llvm_unreachable("Unknown loc info!");
1663 case CCValAssign::Full: break;
1664 case CCValAssign::BCvt:
1665 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1669 if (VA.needsCustom()) {
1670 if (VA.getLocVT() == MVT::v2f64) {
1671 // Extract the first half and return it in two registers.
1672 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1673 DAG.getConstant(0, MVT::i32));
1674 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1675 DAG.getVTList(MVT::i32, MVT::i32), Half);
1677 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1678 Flag = Chain.getValue(1);
1679 VA = RVLocs[++i]; // skip ahead to next loc
1680 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1681 HalfGPRs.getValue(1), Flag);
1682 Flag = Chain.getValue(1);
1683 VA = RVLocs[++i]; // skip ahead to next loc
1685 // Extract the 2nd half and fall through to handle it as an f64 value.
1686 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1687 DAG.getConstant(1, MVT::i32));
1689 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1691 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1692 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1693 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1694 Flag = Chain.getValue(1);
1695 VA = RVLocs[++i]; // skip ahead to next loc
1696 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1699 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1701 // Guarantee that all emitted copies are
1702 // stuck together, avoiding something bad.
1703 Flag = Chain.getValue(1);
1708 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1710 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1715 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1716 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1717 // one of the above mentioned nodes. It has to be wrapped because otherwise
1718 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1719 // be used to form addressing mode. These wrapped nodes will be selected
1721 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1722 EVT PtrVT = Op.getValueType();
1723 // FIXME there is no actual debug info here
1724 DebugLoc dl = Op.getDebugLoc();
1725 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1727 if (CP->isMachineConstantPoolEntry())
1728 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1729 CP->getAlignment());
1731 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1732 CP->getAlignment());
1733 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1736 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1737 return MachineJumpTableInfo::EK_Inline;
1740 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1741 SelectionDAG &DAG) const {
1742 MachineFunction &MF = DAG.getMachineFunction();
1743 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1744 unsigned ARMPCLabelIndex = 0;
1745 DebugLoc DL = Op.getDebugLoc();
1746 EVT PtrVT = getPointerTy();
1747 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1748 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1750 if (RelocM == Reloc::Static) {
1751 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1753 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1754 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1755 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1756 ARMCP::CPBlockAddress,
1758 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1760 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1761 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1762 MachinePointerInfo::getConstantPool(),
1764 if (RelocM == Reloc::Static)
1766 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1767 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1770 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1772 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1773 SelectionDAG &DAG) const {
1774 DebugLoc dl = GA->getDebugLoc();
1775 EVT PtrVT = getPointerTy();
1776 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1777 MachineFunction &MF = DAG.getMachineFunction();
1778 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1779 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1780 ARMConstantPoolValue *CPV =
1781 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1782 ARMCP::CPValue, PCAdj, "tlsgd", true);
1783 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1784 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1785 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1786 MachinePointerInfo::getConstantPool(),
1788 SDValue Chain = Argument.getValue(1);
1790 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1791 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1793 // call __tls_get_addr.
1796 Entry.Node = Argument;
1797 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1798 Args.push_back(Entry);
1799 // FIXME: is there useful debug info available here?
1800 std::pair<SDValue, SDValue> CallResult =
1801 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1802 false, false, false, false,
1803 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1804 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1805 return CallResult.first;
1808 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1809 // "local exec" model.
1811 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1812 SelectionDAG &DAG) const {
1813 const GlobalValue *GV = GA->getGlobal();
1814 DebugLoc dl = GA->getDebugLoc();
1816 SDValue Chain = DAG.getEntryNode();
1817 EVT PtrVT = getPointerTy();
1818 // Get the Thread Pointer
1819 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1821 if (GV->isDeclaration()) {
1822 MachineFunction &MF = DAG.getMachineFunction();
1823 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1824 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1825 // Initial exec model.
1826 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1827 ARMConstantPoolValue *CPV =
1828 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1829 ARMCP::CPValue, PCAdj, "gottpoff", true);
1830 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1831 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1832 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1833 MachinePointerInfo::getConstantPool(),
1835 Chain = Offset.getValue(1);
1837 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1838 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1840 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1841 MachinePointerInfo::getConstantPool(),
1845 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1846 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1847 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1848 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1849 MachinePointerInfo::getConstantPool(),
1853 // The address of the thread local variable is the add of the thread
1854 // pointer with the offset of the variable.
1855 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1859 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1860 // TODO: implement the "local dynamic" model
1861 assert(Subtarget->isTargetELF() &&
1862 "TLS not implemented for non-ELF targets");
1863 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1864 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1865 // otherwise use the "Local Exec" TLS Model
1866 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1867 return LowerToTLSGeneralDynamicModel(GA, DAG);
1869 return LowerToTLSExecModels(GA, DAG);
1872 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1873 SelectionDAG &DAG) const {
1874 EVT PtrVT = getPointerTy();
1875 DebugLoc dl = Op.getDebugLoc();
1876 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1877 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1878 if (RelocM == Reloc::PIC_) {
1879 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1880 ARMConstantPoolValue *CPV =
1881 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1882 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1883 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1884 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1886 MachinePointerInfo::getConstantPool(),
1888 SDValue Chain = Result.getValue(1);
1889 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1890 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1892 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1893 MachinePointerInfo::getGOT(), false, false, 0);
1896 // If we have T2 ops, we can materialize the address directly via movt/movw
1897 // pair. This is always cheaper.
1898 if (Subtarget->useMovt()) {
1899 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1900 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1902 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1903 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1904 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1905 MachinePointerInfo::getConstantPool(),
1911 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1912 SelectionDAG &DAG) const {
1913 MachineFunction &MF = DAG.getMachineFunction();
1914 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1915 unsigned ARMPCLabelIndex = 0;
1916 EVT PtrVT = getPointerTy();
1917 DebugLoc dl = Op.getDebugLoc();
1918 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1919 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1921 if (RelocM == Reloc::Static)
1922 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1924 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1925 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1926 ARMConstantPoolValue *CPV =
1927 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1928 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1930 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1932 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1933 MachinePointerInfo::getConstantPool(),
1935 SDValue Chain = Result.getValue(1);
1937 if (RelocM == Reloc::PIC_) {
1938 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1939 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1942 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1943 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1949 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1950 SelectionDAG &DAG) const {
1951 assert(Subtarget->isTargetELF() &&
1952 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1953 MachineFunction &MF = DAG.getMachineFunction();
1954 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1955 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1956 EVT PtrVT = getPointerTy();
1957 DebugLoc dl = Op.getDebugLoc();
1958 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1959 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1960 "_GLOBAL_OFFSET_TABLE_",
1961 ARMPCLabelIndex, PCAdj);
1962 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1963 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1964 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1965 MachinePointerInfo::getConstantPool(),
1967 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1968 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1972 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
1974 DebugLoc dl = Op.getDebugLoc();
1975 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
1976 Op.getOperand(0), Op.getOperand(1));
1980 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1981 DebugLoc dl = Op.getDebugLoc();
1982 SDValue Val = DAG.getConstant(0, MVT::i32);
1983 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1984 Op.getOperand(1), Val);
1988 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1989 DebugLoc dl = Op.getDebugLoc();
1990 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1991 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1995 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1996 const ARMSubtarget *Subtarget) const {
1997 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1998 DebugLoc dl = Op.getDebugLoc();
2000 default: return SDValue(); // Don't custom lower most intrinsics.
2001 case Intrinsic::arm_thread_pointer: {
2002 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2003 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2005 case Intrinsic::eh_sjlj_lsda: {
2006 MachineFunction &MF = DAG.getMachineFunction();
2007 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2008 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2009 EVT PtrVT = getPointerTy();
2010 DebugLoc dl = Op.getDebugLoc();
2011 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2013 unsigned PCAdj = (RelocM != Reloc::PIC_)
2014 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2015 ARMConstantPoolValue *CPV =
2016 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2017 ARMCP::CPLSDA, PCAdj);
2018 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2019 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2021 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2022 MachinePointerInfo::getConstantPool(),
2025 if (RelocM == Reloc::PIC_) {
2026 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2027 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2034 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2035 const ARMSubtarget *Subtarget) {
2036 DebugLoc dl = Op.getDebugLoc();
2037 if (!Subtarget->hasDataBarrier()) {
2038 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2039 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2041 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
2042 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2043 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2044 DAG.getConstant(0, MVT::i32));
2047 SDValue Op5 = Op.getOperand(5);
2048 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2049 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2050 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2051 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2053 ARM_MB::MemBOpt DMBOpt;
2054 if (isDeviceBarrier)
2055 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2057 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2058 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2059 DAG.getConstant(DMBOpt, MVT::i32));
2062 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2063 const ARMSubtarget *Subtarget) {
2064 // ARM pre v5TE and Thumb1 does not have preload instructions.
2065 if (!(Subtarget->isThumb2() ||
2066 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2067 // Just preserve the chain.
2068 return Op.getOperand(0);
2070 DebugLoc dl = Op.getDebugLoc();
2071 unsigned Flavor = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
2073 if (!Subtarget->hasV7Ops())
2074 return Op.getOperand(0);
2075 else if (Flavor == 2 && !Subtarget->hasMPExtension())
2076 return Op.getOperand(0);
2079 if (Subtarget->isThumb())
2081 Flavor = ~Flavor & 0x3;
2083 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2084 Op.getOperand(1), DAG.getConstant(Flavor, MVT::i32));
2087 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2088 MachineFunction &MF = DAG.getMachineFunction();
2089 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2091 // vastart just stores the address of the VarArgsFrameIndex slot into the
2092 // memory location argument.
2093 DebugLoc dl = Op.getDebugLoc();
2094 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2095 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2096 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2097 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2098 MachinePointerInfo(SV), false, false, 0);
2102 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2103 SDValue &Root, SelectionDAG &DAG,
2104 DebugLoc dl) const {
2105 MachineFunction &MF = DAG.getMachineFunction();
2106 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2108 TargetRegisterClass *RC;
2109 if (AFI->isThumb1OnlyFunction())
2110 RC = ARM::tGPRRegisterClass;
2112 RC = ARM::GPRRegisterClass;
2114 // Transform the arguments stored in physical registers into virtual ones.
2115 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2116 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2119 if (NextVA.isMemLoc()) {
2120 MachineFrameInfo *MFI = MF.getFrameInfo();
2121 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2123 // Create load node to retrieve arguments from the stack.
2124 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2125 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2126 MachinePointerInfo::getFixedStack(FI),
2129 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2130 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2133 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2137 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2138 CallingConv::ID CallConv, bool isVarArg,
2139 const SmallVectorImpl<ISD::InputArg>
2141 DebugLoc dl, SelectionDAG &DAG,
2142 SmallVectorImpl<SDValue> &InVals)
2145 MachineFunction &MF = DAG.getMachineFunction();
2146 MachineFrameInfo *MFI = MF.getFrameInfo();
2148 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2150 // Assign locations to all of the incoming arguments.
2151 SmallVector<CCValAssign, 16> ArgLocs;
2152 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2154 CCInfo.AnalyzeFormalArguments(Ins,
2155 CCAssignFnForNode(CallConv, /* Return*/ false,
2158 SmallVector<SDValue, 16> ArgValues;
2160 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2161 CCValAssign &VA = ArgLocs[i];
2163 // Arguments stored in registers.
2164 if (VA.isRegLoc()) {
2165 EVT RegVT = VA.getLocVT();
2168 if (VA.needsCustom()) {
2169 // f64 and vector types are split up into multiple registers or
2170 // combinations of registers and stack slots.
2171 if (VA.getLocVT() == MVT::v2f64) {
2172 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2174 VA = ArgLocs[++i]; // skip ahead to next loc
2176 if (VA.isMemLoc()) {
2177 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2178 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2179 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2180 MachinePointerInfo::getFixedStack(FI),
2183 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2186 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2187 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2188 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2189 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2190 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2192 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2195 TargetRegisterClass *RC;
2197 if (RegVT == MVT::f32)
2198 RC = ARM::SPRRegisterClass;
2199 else if (RegVT == MVT::f64)
2200 RC = ARM::DPRRegisterClass;
2201 else if (RegVT == MVT::v2f64)
2202 RC = ARM::QPRRegisterClass;
2203 else if (RegVT == MVT::i32)
2204 RC = (AFI->isThumb1OnlyFunction() ?
2205 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2207 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2209 // Transform the arguments in physical registers into virtual ones.
2210 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2211 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2214 // If this is an 8 or 16-bit value, it is really passed promoted
2215 // to 32 bits. Insert an assert[sz]ext to capture this, then
2216 // truncate to the right size.
2217 switch (VA.getLocInfo()) {
2218 default: llvm_unreachable("Unknown loc info!");
2219 case CCValAssign::Full: break;
2220 case CCValAssign::BCvt:
2221 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2223 case CCValAssign::SExt:
2224 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2225 DAG.getValueType(VA.getValVT()));
2226 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2228 case CCValAssign::ZExt:
2229 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2230 DAG.getValueType(VA.getValVT()));
2231 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2235 InVals.push_back(ArgValue);
2237 } else { // VA.isRegLoc()
2240 assert(VA.isMemLoc());
2241 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2243 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2244 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2246 // Create load nodes to retrieve arguments from the stack.
2247 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2248 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2249 MachinePointerInfo::getFixedStack(FI),
2256 static const unsigned GPRArgRegs[] = {
2257 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2260 unsigned NumGPRs = CCInfo.getFirstUnallocated
2261 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2263 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2264 unsigned VARegSize = (4 - NumGPRs) * 4;
2265 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2266 unsigned ArgOffset = CCInfo.getNextStackOffset();
2267 if (VARegSaveSize) {
2268 // If this function is vararg, store any remaining integer argument regs
2269 // to their spots on the stack so that they may be loaded by deferencing
2270 // the result of va_next.
2271 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2272 AFI->setVarArgsFrameIndex(
2273 MFI->CreateFixedObject(VARegSaveSize,
2274 ArgOffset + VARegSaveSize - VARegSize,
2276 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2279 SmallVector<SDValue, 4> MemOps;
2280 for (; NumGPRs < 4; ++NumGPRs) {
2281 TargetRegisterClass *RC;
2282 if (AFI->isThumb1OnlyFunction())
2283 RC = ARM::tGPRRegisterClass;
2285 RC = ARM::GPRRegisterClass;
2287 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2288 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2290 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2291 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2293 MemOps.push_back(Store);
2294 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2295 DAG.getConstant(4, getPointerTy()));
2297 if (!MemOps.empty())
2298 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2299 &MemOps[0], MemOps.size());
2301 // This will point to the next argument passed via stack.
2302 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2308 /// isFloatingPointZero - Return true if this is +0.0.
2309 static bool isFloatingPointZero(SDValue Op) {
2310 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2311 return CFP->getValueAPF().isPosZero();
2312 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2313 // Maybe this has already been legalized into the constant pool?
2314 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2315 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2316 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2317 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2318 return CFP->getValueAPF().isPosZero();
2324 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2325 /// the given operands.
2327 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2328 SDValue &ARMcc, SelectionDAG &DAG,
2329 DebugLoc dl) const {
2330 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2331 unsigned C = RHSC->getZExtValue();
2332 if (!isLegalICmpImmediate(C)) {
2333 // Constant does not fit, try adjusting it by one?
2338 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2339 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2340 RHS = DAG.getConstant(C-1, MVT::i32);
2345 if (C != 0 && isLegalICmpImmediate(C-1)) {
2346 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2347 RHS = DAG.getConstant(C-1, MVT::i32);
2352 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2353 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2354 RHS = DAG.getConstant(C+1, MVT::i32);
2359 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2360 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2361 RHS = DAG.getConstant(C+1, MVT::i32);
2368 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2369 ARMISD::NodeType CompareType;
2372 CompareType = ARMISD::CMP;
2377 CompareType = ARMISD::CMPZ;
2380 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2381 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2384 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2386 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2387 DebugLoc dl) const {
2389 if (!isFloatingPointZero(RHS))
2390 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2392 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2393 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2396 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2397 SDValue Cond = Op.getOperand(0);
2398 SDValue SelectTrue = Op.getOperand(1);
2399 SDValue SelectFalse = Op.getOperand(2);
2400 DebugLoc dl = Op.getDebugLoc();
2404 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2405 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2407 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2408 const ConstantSDNode *CMOVTrue =
2409 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2410 const ConstantSDNode *CMOVFalse =
2411 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2413 if (CMOVTrue && CMOVFalse) {
2414 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2415 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2419 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2421 False = SelectFalse;
2422 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2427 if (True.getNode() && False.getNode()) {
2428 EVT VT = Cond.getValueType();
2429 SDValue ARMcc = Cond.getOperand(2);
2430 SDValue CCR = Cond.getOperand(3);
2431 SDValue Cmp = Cond.getOperand(4);
2432 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2437 return DAG.getSelectCC(dl, Cond,
2438 DAG.getConstant(0, Cond.getValueType()),
2439 SelectTrue, SelectFalse, ISD::SETNE);
2442 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2443 EVT VT = Op.getValueType();
2444 SDValue LHS = Op.getOperand(0);
2445 SDValue RHS = Op.getOperand(1);
2446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2447 SDValue TrueVal = Op.getOperand(2);
2448 SDValue FalseVal = Op.getOperand(3);
2449 DebugLoc dl = Op.getDebugLoc();
2451 if (LHS.getValueType() == MVT::i32) {
2453 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2454 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2455 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2458 ARMCC::CondCodes CondCode, CondCode2;
2459 FPCCToARMCC(CC, CondCode, CondCode2);
2461 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2462 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2463 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2464 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2466 if (CondCode2 != ARMCC::AL) {
2467 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2468 // FIXME: Needs another CMP because flag can have but one use.
2469 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2470 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2471 Result, TrueVal, ARMcc2, CCR, Cmp2);
2476 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2477 /// to morph to an integer compare sequence.
2478 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2479 const ARMSubtarget *Subtarget) {
2480 SDNode *N = Op.getNode();
2481 if (!N->hasOneUse())
2482 // Otherwise it requires moving the value from fp to integer registers.
2484 if (!N->getNumValues())
2486 EVT VT = Op.getValueType();
2487 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2488 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2489 // vmrs are very slow, e.g. cortex-a8.
2492 if (isFloatingPointZero(Op)) {
2496 return ISD::isNormalLoad(N);
2499 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2500 if (isFloatingPointZero(Op))
2501 return DAG.getConstant(0, MVT::i32);
2503 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2504 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2505 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2506 Ld->isVolatile(), Ld->isNonTemporal(),
2507 Ld->getAlignment());
2509 llvm_unreachable("Unknown VFP cmp argument!");
2512 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2513 SDValue &RetVal1, SDValue &RetVal2) {
2514 if (isFloatingPointZero(Op)) {
2515 RetVal1 = DAG.getConstant(0, MVT::i32);
2516 RetVal2 = DAG.getConstant(0, MVT::i32);
2520 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2521 SDValue Ptr = Ld->getBasePtr();
2522 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2523 Ld->getChain(), Ptr,
2524 Ld->getPointerInfo(),
2525 Ld->isVolatile(), Ld->isNonTemporal(),
2526 Ld->getAlignment());
2528 EVT PtrType = Ptr.getValueType();
2529 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2530 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2531 PtrType, Ptr, DAG.getConstant(4, PtrType));
2532 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2533 Ld->getChain(), NewPtr,
2534 Ld->getPointerInfo().getWithOffset(4),
2535 Ld->isVolatile(), Ld->isNonTemporal(),
2540 llvm_unreachable("Unknown VFP cmp argument!");
2543 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2544 /// f32 and even f64 comparisons to integer ones.
2546 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2547 SDValue Chain = Op.getOperand(0);
2548 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2549 SDValue LHS = Op.getOperand(2);
2550 SDValue RHS = Op.getOperand(3);
2551 SDValue Dest = Op.getOperand(4);
2552 DebugLoc dl = Op.getDebugLoc();
2554 bool SeenZero = false;
2555 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2556 canChangeToInt(RHS, SeenZero, Subtarget) &&
2557 // If one of the operand is zero, it's safe to ignore the NaN case since
2558 // we only care about equality comparisons.
2559 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2560 // If unsafe fp math optimization is enabled and there are no othter uses of
2561 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2562 // to an integer comparison.
2563 if (CC == ISD::SETOEQ)
2565 else if (CC == ISD::SETUNE)
2569 if (LHS.getValueType() == MVT::f32) {
2570 LHS = bitcastf32Toi32(LHS, DAG);
2571 RHS = bitcastf32Toi32(RHS, DAG);
2572 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2573 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2574 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2575 Chain, Dest, ARMcc, CCR, Cmp);
2580 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2581 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2582 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2583 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2584 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2585 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2586 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2592 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2593 SDValue Chain = Op.getOperand(0);
2594 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2595 SDValue LHS = Op.getOperand(2);
2596 SDValue RHS = Op.getOperand(3);
2597 SDValue Dest = Op.getOperand(4);
2598 DebugLoc dl = Op.getDebugLoc();
2600 if (LHS.getValueType() == MVT::i32) {
2602 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2603 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2604 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2605 Chain, Dest, ARMcc, CCR, Cmp);
2608 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2611 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2612 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2613 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2614 if (Result.getNode())
2618 ARMCC::CondCodes CondCode, CondCode2;
2619 FPCCToARMCC(CC, CondCode, CondCode2);
2621 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2622 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2623 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2624 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2625 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2626 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2627 if (CondCode2 != ARMCC::AL) {
2628 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2629 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2630 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2635 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2636 SDValue Chain = Op.getOperand(0);
2637 SDValue Table = Op.getOperand(1);
2638 SDValue Index = Op.getOperand(2);
2639 DebugLoc dl = Op.getDebugLoc();
2641 EVT PTy = getPointerTy();
2642 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2643 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2644 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2645 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2646 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2647 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2648 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2649 if (Subtarget->isThumb2()) {
2650 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2651 // which does another jump to the destination. This also makes it easier
2652 // to translate it to TBB / TBH later.
2653 // FIXME: This might not work if the function is extremely large.
2654 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2655 Addr, Op.getOperand(2), JTI, UId);
2657 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2658 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2659 MachinePointerInfo::getJumpTable(),
2661 Chain = Addr.getValue(1);
2662 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2663 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2665 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2666 MachinePointerInfo::getJumpTable(), false, false, 0);
2667 Chain = Addr.getValue(1);
2668 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2672 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2673 DebugLoc dl = Op.getDebugLoc();
2676 switch (Op.getOpcode()) {
2678 assert(0 && "Invalid opcode!");
2679 case ISD::FP_TO_SINT:
2680 Opc = ARMISD::FTOSI;
2682 case ISD::FP_TO_UINT:
2683 Opc = ARMISD::FTOUI;
2686 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2687 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2690 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2691 EVT VT = Op.getValueType();
2692 DebugLoc dl = Op.getDebugLoc();
2695 switch (Op.getOpcode()) {
2697 assert(0 && "Invalid opcode!");
2698 case ISD::SINT_TO_FP:
2699 Opc = ARMISD::SITOF;
2701 case ISD::UINT_TO_FP:
2702 Opc = ARMISD::UITOF;
2706 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2707 return DAG.getNode(Opc, dl, VT, Op);
2710 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2711 // Implement fcopysign with a fabs and a conditional fneg.
2712 SDValue Tmp0 = Op.getOperand(0);
2713 SDValue Tmp1 = Op.getOperand(1);
2714 DebugLoc dl = Op.getDebugLoc();
2715 EVT VT = Op.getValueType();
2716 EVT SrcVT = Tmp1.getValueType();
2717 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2718 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2719 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2720 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2721 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2722 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2725 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2726 MachineFunction &MF = DAG.getMachineFunction();
2727 MachineFrameInfo *MFI = MF.getFrameInfo();
2728 MFI->setReturnAddressIsTaken(true);
2730 EVT VT = Op.getValueType();
2731 DebugLoc dl = Op.getDebugLoc();
2732 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2734 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2735 SDValue Offset = DAG.getConstant(4, MVT::i32);
2736 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2737 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2738 MachinePointerInfo(), false, false, 0);
2741 // Return LR, which contains the return address. Mark it an implicit live-in.
2742 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2743 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2746 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2747 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2748 MFI->setFrameAddressIsTaken(true);
2750 EVT VT = Op.getValueType();
2751 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2752 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2753 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2754 ? ARM::R7 : ARM::R11;
2755 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2757 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2758 MachinePointerInfo(),
2763 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2764 /// expand a bit convert where either the source or destination type is i64 to
2765 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2766 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2767 /// vectors), since the legalizer won't know what to do with that.
2768 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2770 DebugLoc dl = N->getDebugLoc();
2771 SDValue Op = N->getOperand(0);
2773 // This function is only supposed to be called for i64 types, either as the
2774 // source or destination of the bit convert.
2775 EVT SrcVT = Op.getValueType();
2776 EVT DstVT = N->getValueType(0);
2777 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2778 "ExpandBIT_CONVERT called for non-i64 type");
2780 // Turn i64->f64 into VMOVDRR.
2781 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2782 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2783 DAG.getConstant(0, MVT::i32));
2784 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2785 DAG.getConstant(1, MVT::i32));
2786 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2787 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2790 // Turn f64->i64 into VMOVRRD.
2791 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2792 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2793 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2794 // Merge the pieces into a single i64 value.
2795 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2801 /// getZeroVector - Returns a vector of specified type with all zero elements.
2802 /// Zero vectors are used to represent vector negation and in those cases
2803 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2804 /// not support i64 elements, so sometimes the zero vectors will need to be
2805 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2807 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2808 assert(VT.isVector() && "Expected a vector type");
2809 // The canonical modified immediate encoding of a zero vector is....0!
2810 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2811 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2812 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2813 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2816 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2817 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2818 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2819 SelectionDAG &DAG) const {
2820 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2821 EVT VT = Op.getValueType();
2822 unsigned VTBits = VT.getSizeInBits();
2823 DebugLoc dl = Op.getDebugLoc();
2824 SDValue ShOpLo = Op.getOperand(0);
2825 SDValue ShOpHi = Op.getOperand(1);
2826 SDValue ShAmt = Op.getOperand(2);
2828 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2830 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2832 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2833 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2834 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2835 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2836 DAG.getConstant(VTBits, MVT::i32));
2837 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2838 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2839 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2841 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2842 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2844 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2845 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2848 SDValue Ops[2] = { Lo, Hi };
2849 return DAG.getMergeValues(Ops, 2, dl);
2852 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2853 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2854 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2855 SelectionDAG &DAG) const {
2856 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2857 EVT VT = Op.getValueType();
2858 unsigned VTBits = VT.getSizeInBits();
2859 DebugLoc dl = Op.getDebugLoc();
2860 SDValue ShOpLo = Op.getOperand(0);
2861 SDValue ShOpHi = Op.getOperand(1);
2862 SDValue ShAmt = Op.getOperand(2);
2865 assert(Op.getOpcode() == ISD::SHL_PARTS);
2866 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2867 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2868 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2869 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2870 DAG.getConstant(VTBits, MVT::i32));
2871 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2872 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2874 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2875 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2876 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2878 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2879 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2882 SDValue Ops[2] = { Lo, Hi };
2883 return DAG.getMergeValues(Ops, 2, dl);
2886 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2887 SelectionDAG &DAG) const {
2888 // The rounding mode is in bits 23:22 of the FPSCR.
2889 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2890 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2891 // so that the shift + and get folded into a bitfield extract.
2892 DebugLoc dl = Op.getDebugLoc();
2893 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2894 DAG.getConstant(Intrinsic::arm_get_fpscr,
2896 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2897 DAG.getConstant(1U << 22, MVT::i32));
2898 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2899 DAG.getConstant(22, MVT::i32));
2900 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2901 DAG.getConstant(3, MVT::i32));
2904 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2905 const ARMSubtarget *ST) {
2906 EVT VT = N->getValueType(0);
2907 DebugLoc dl = N->getDebugLoc();
2909 if (!ST->hasV6T2Ops())
2912 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2913 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2916 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2917 const ARMSubtarget *ST) {
2918 EVT VT = N->getValueType(0);
2919 DebugLoc dl = N->getDebugLoc();
2921 // Lower vector shifts on NEON to use VSHL.
2922 if (VT.isVector()) {
2923 assert(ST->hasNEON() && "unexpected vector shift");
2925 // Left shifts translate directly to the vshiftu intrinsic.
2926 if (N->getOpcode() == ISD::SHL)
2927 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2928 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2929 N->getOperand(0), N->getOperand(1));
2931 assert((N->getOpcode() == ISD::SRA ||
2932 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2934 // NEON uses the same intrinsics for both left and right shifts. For
2935 // right shifts, the shift amounts are negative, so negate the vector of
2937 EVT ShiftVT = N->getOperand(1).getValueType();
2938 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2939 getZeroVector(ShiftVT, DAG, dl),
2941 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2942 Intrinsic::arm_neon_vshifts :
2943 Intrinsic::arm_neon_vshiftu);
2944 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2945 DAG.getConstant(vshiftInt, MVT::i32),
2946 N->getOperand(0), NegatedCount);
2949 // We can get here for a node like i32 = ISD::SHL i32, i64
2953 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2954 "Unknown shift to lower!");
2956 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2957 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2958 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2961 // If we are in thumb mode, we don't have RRX.
2962 if (ST->isThumb1Only()) return SDValue();
2964 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2965 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2966 DAG.getConstant(0, MVT::i32));
2967 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2968 DAG.getConstant(1, MVT::i32));
2970 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2971 // captures the result into a carry flag.
2972 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2973 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2975 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2976 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2978 // Merge the pieces into a single i64 value.
2979 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2982 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2983 SDValue TmpOp0, TmpOp1;
2984 bool Invert = false;
2988 SDValue Op0 = Op.getOperand(0);
2989 SDValue Op1 = Op.getOperand(1);
2990 SDValue CC = Op.getOperand(2);
2991 EVT VT = Op.getValueType();
2992 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2993 DebugLoc dl = Op.getDebugLoc();
2995 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2996 switch (SetCCOpcode) {
2997 default: llvm_unreachable("Illegal FP comparison"); break;
2999 case ISD::SETNE: Invert = true; // Fallthrough
3001 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3003 case ISD::SETLT: Swap = true; // Fallthrough
3005 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3007 case ISD::SETLE: Swap = true; // Fallthrough
3009 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3010 case ISD::SETUGE: Swap = true; // Fallthrough
3011 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3012 case ISD::SETUGT: Swap = true; // Fallthrough
3013 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3014 case ISD::SETUEQ: Invert = true; // Fallthrough
3016 // Expand this to (OLT | OGT).
3020 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3021 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3023 case ISD::SETUO: Invert = true; // Fallthrough
3025 // Expand this to (OLT | OGE).
3029 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3030 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3034 // Integer comparisons.
3035 switch (SetCCOpcode) {
3036 default: llvm_unreachable("Illegal integer comparison"); break;
3037 case ISD::SETNE: Invert = true;
3038 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3039 case ISD::SETLT: Swap = true;
3040 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3041 case ISD::SETLE: Swap = true;
3042 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3043 case ISD::SETULT: Swap = true;
3044 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3045 case ISD::SETULE: Swap = true;
3046 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3049 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3050 if (Opc == ARMISD::VCEQ) {
3053 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3055 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3058 // Ignore bitconvert.
3059 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3060 AndOp = AndOp.getOperand(0);
3062 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3064 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3065 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3072 std::swap(Op0, Op1);
3074 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3077 Result = DAG.getNOT(dl, Result, VT);
3082 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3083 /// valid vector constant for a NEON instruction with a "modified immediate"
3084 /// operand (e.g., VMOV). If so, return the encoded value.
3085 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3086 unsigned SplatBitSize, SelectionDAG &DAG,
3087 EVT &VT, bool is128Bits, bool isVMOV) {
3088 unsigned OpCmode, Imm;
3090 // SplatBitSize is set to the smallest size that splats the vector, so a
3091 // zero vector will always have SplatBitSize == 8. However, NEON modified
3092 // immediate instructions others than VMOV do not support the 8-bit encoding
3093 // of a zero vector, and the default encoding of zero is supposed to be the
3098 switch (SplatBitSize) {
3102 // Any 1-byte value is OK. Op=0, Cmode=1110.
3103 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3106 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3110 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3111 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3112 if ((SplatBits & ~0xff) == 0) {
3113 // Value = 0x00nn: Op=x, Cmode=100x.
3118 if ((SplatBits & ~0xff00) == 0) {
3119 // Value = 0xnn00: Op=x, Cmode=101x.
3121 Imm = SplatBits >> 8;
3127 // NEON's 32-bit VMOV supports splat values where:
3128 // * only one byte is nonzero, or
3129 // * the least significant byte is 0xff and the second byte is nonzero, or
3130 // * the least significant 2 bytes are 0xff and the third is nonzero.
3131 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3132 if ((SplatBits & ~0xff) == 0) {
3133 // Value = 0x000000nn: Op=x, Cmode=000x.
3138 if ((SplatBits & ~0xff00) == 0) {
3139 // Value = 0x0000nn00: Op=x, Cmode=001x.
3141 Imm = SplatBits >> 8;
3144 if ((SplatBits & ~0xff0000) == 0) {
3145 // Value = 0x00nn0000: Op=x, Cmode=010x.
3147 Imm = SplatBits >> 16;
3150 if ((SplatBits & ~0xff000000) == 0) {
3151 // Value = 0xnn000000: Op=x, Cmode=011x.
3153 Imm = SplatBits >> 24;
3157 if ((SplatBits & ~0xffff) == 0 &&
3158 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3159 // Value = 0x0000nnff: Op=x, Cmode=1100.
3161 Imm = SplatBits >> 8;
3166 if ((SplatBits & ~0xffffff) == 0 &&
3167 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3168 // Value = 0x00nnffff: Op=x, Cmode=1101.
3170 Imm = SplatBits >> 16;
3171 SplatBits |= 0xffff;
3175 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3176 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3177 // VMOV.I32. A (very) minor optimization would be to replicate the value
3178 // and fall through here to test for a valid 64-bit splat. But, then the
3179 // caller would also need to check and handle the change in size.
3185 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3186 uint64_t BitMask = 0xff;
3188 unsigned ImmMask = 1;
3190 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3191 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3194 } else if ((SplatBits & BitMask) != 0) {
3200 // Op=1, Cmode=1110.
3203 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3208 llvm_unreachable("unexpected size for isNEONModifiedImm");
3212 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3213 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3216 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3217 bool &ReverseVEXT, unsigned &Imm) {
3218 unsigned NumElts = VT.getVectorNumElements();
3219 ReverseVEXT = false;
3221 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3227 // If this is a VEXT shuffle, the immediate value is the index of the first
3228 // element. The other shuffle indices must be the successive elements after
3230 unsigned ExpectedElt = Imm;
3231 for (unsigned i = 1; i < NumElts; ++i) {
3232 // Increment the expected index. If it wraps around, it may still be
3233 // a VEXT but the source vectors must be swapped.
3235 if (ExpectedElt == NumElts * 2) {
3240 if (M[i] < 0) continue; // ignore UNDEF indices
3241 if (ExpectedElt != static_cast<unsigned>(M[i]))
3245 // Adjust the index value if the source operands will be swapped.
3252 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3253 /// instruction with the specified blocksize. (The order of the elements
3254 /// within each block of the vector is reversed.)
3255 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3256 unsigned BlockSize) {
3257 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3258 "Only possible block sizes for VREV are: 16, 32, 64");
3260 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3264 unsigned NumElts = VT.getVectorNumElements();
3265 unsigned BlockElts = M[0] + 1;
3266 // If the first shuffle index is UNDEF, be optimistic.
3268 BlockElts = BlockSize / EltSz;
3270 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3273 for (unsigned i = 0; i < NumElts; ++i) {
3274 if (M[i] < 0) continue; // ignore UNDEF indices
3275 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3282 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3283 unsigned &WhichResult) {
3284 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3288 unsigned NumElts = VT.getVectorNumElements();
3289 WhichResult = (M[0] == 0 ? 0 : 1);
3290 for (unsigned i = 0; i < NumElts; i += 2) {
3291 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3292 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3298 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3299 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3300 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3301 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3302 unsigned &WhichResult) {
3303 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3307 unsigned NumElts = VT.getVectorNumElements();
3308 WhichResult = (M[0] == 0 ? 0 : 1);
3309 for (unsigned i = 0; i < NumElts; i += 2) {
3310 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3311 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3317 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3318 unsigned &WhichResult) {
3319 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3323 unsigned NumElts = VT.getVectorNumElements();
3324 WhichResult = (M[0] == 0 ? 0 : 1);
3325 for (unsigned i = 0; i != NumElts; ++i) {
3326 if (M[i] < 0) continue; // ignore UNDEF indices
3327 if ((unsigned) M[i] != 2 * i + WhichResult)
3331 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3332 if (VT.is64BitVector() && EltSz == 32)
3338 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3339 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3340 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3341 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3342 unsigned &WhichResult) {
3343 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3347 unsigned Half = VT.getVectorNumElements() / 2;
3348 WhichResult = (M[0] == 0 ? 0 : 1);
3349 for (unsigned j = 0; j != 2; ++j) {
3350 unsigned Idx = WhichResult;
3351 for (unsigned i = 0; i != Half; ++i) {
3352 int MIdx = M[i + j * Half];
3353 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3359 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3360 if (VT.is64BitVector() && EltSz == 32)
3366 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3367 unsigned &WhichResult) {
3368 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3372 unsigned NumElts = VT.getVectorNumElements();
3373 WhichResult = (M[0] == 0 ? 0 : 1);
3374 unsigned Idx = WhichResult * NumElts / 2;
3375 for (unsigned i = 0; i != NumElts; i += 2) {
3376 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3377 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3382 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3383 if (VT.is64BitVector() && EltSz == 32)
3389 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3390 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3391 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3392 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3393 unsigned &WhichResult) {
3394 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3398 unsigned NumElts = VT.getVectorNumElements();
3399 WhichResult = (M[0] == 0 ? 0 : 1);
3400 unsigned Idx = WhichResult * NumElts / 2;
3401 for (unsigned i = 0; i != NumElts; i += 2) {
3402 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3403 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3408 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3409 if (VT.is64BitVector() && EltSz == 32)
3415 // If N is an integer constant that can be moved into a register in one
3416 // instruction, return an SDValue of such a constant (will become a MOV
3417 // instruction). Otherwise return null.
3418 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3419 const ARMSubtarget *ST, DebugLoc dl) {
3421 if (!isa<ConstantSDNode>(N))
3423 Val = cast<ConstantSDNode>(N)->getZExtValue();
3425 if (ST->isThumb1Only()) {
3426 if (Val <= 255 || ~Val <= 255)
3427 return DAG.getConstant(Val, MVT::i32);
3429 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3430 return DAG.getConstant(Val, MVT::i32);
3435 // If this is a case we can't handle, return null and let the default
3436 // expansion code take care of it.
3437 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3438 const ARMSubtarget *ST) {
3439 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3440 DebugLoc dl = Op.getDebugLoc();
3441 EVT VT = Op.getValueType();
3443 APInt SplatBits, SplatUndef;
3444 unsigned SplatBitSize;
3446 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3447 if (SplatBitSize <= 64) {
3448 // Check if an immediate VMOV works.
3450 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3451 SplatUndef.getZExtValue(), SplatBitSize,
3452 DAG, VmovVT, VT.is128BitVector(), true);
3453 if (Val.getNode()) {
3454 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3455 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3458 // Try an immediate VMVN.
3459 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3460 ((1LL << SplatBitSize) - 1));
3461 Val = isNEONModifiedImm(NegatedImm,
3462 SplatUndef.getZExtValue(), SplatBitSize,
3463 DAG, VmovVT, VT.is128BitVector(), false);
3464 if (Val.getNode()) {
3465 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3466 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3471 // Scan through the operands to see if only one value is used.
3472 unsigned NumElts = VT.getVectorNumElements();
3473 bool isOnlyLowElement = true;
3474 bool usesOnlyOneValue = true;
3475 bool isConstant = true;
3477 for (unsigned i = 0; i < NumElts; ++i) {
3478 SDValue V = Op.getOperand(i);
3479 if (V.getOpcode() == ISD::UNDEF)
3482 isOnlyLowElement = false;
3483 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3486 if (!Value.getNode())
3488 else if (V != Value)
3489 usesOnlyOneValue = false;
3492 if (!Value.getNode())
3493 return DAG.getUNDEF(VT);
3495 if (isOnlyLowElement)
3496 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3498 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3500 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3501 // i32 and try again.
3502 if (usesOnlyOneValue && EltSize <= 32) {
3504 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3505 if (VT.getVectorElementType().isFloatingPoint()) {
3506 SmallVector<SDValue, 8> Ops;
3507 for (unsigned i = 0; i < NumElts; ++i)
3508 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3510 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3512 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3514 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3516 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3518 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3521 // If all elements are constants and the case above didn't get hit, fall back
3522 // to the default expansion, which will generate a load from the constant
3527 // Vectors with 32- or 64-bit elements can be built by directly assigning
3528 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3529 // will be legalized.
3530 if (EltSize >= 32) {
3531 // Do the expansion with floating-point types, since that is what the VFP
3532 // registers are defined to use, and since i64 is not legal.
3533 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3534 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3535 SmallVector<SDValue, 8> Ops;
3536 for (unsigned i = 0; i < NumElts; ++i)
3537 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3538 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3539 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3545 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3546 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3547 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3548 /// are assumed to be legal.
3550 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3552 if (VT.getVectorNumElements() == 4 &&
3553 (VT.is128BitVector() || VT.is64BitVector())) {
3554 unsigned PFIndexes[4];
3555 for (unsigned i = 0; i != 4; ++i) {
3559 PFIndexes[i] = M[i];
3562 // Compute the index in the perfect shuffle table.
3563 unsigned PFTableIndex =
3564 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3565 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3566 unsigned Cost = (PFEntry >> 30);
3573 unsigned Imm, WhichResult;
3575 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3576 return (EltSize >= 32 ||
3577 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3578 isVREVMask(M, VT, 64) ||
3579 isVREVMask(M, VT, 32) ||
3580 isVREVMask(M, VT, 16) ||
3581 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3582 isVTRNMask(M, VT, WhichResult) ||
3583 isVUZPMask(M, VT, WhichResult) ||
3584 isVZIPMask(M, VT, WhichResult) ||
3585 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3586 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3587 isVZIP_v_undef_Mask(M, VT, WhichResult));
3590 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3591 /// the specified operations to build the shuffle.
3592 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3593 SDValue RHS, SelectionDAG &DAG,
3595 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3596 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3597 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3600 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3609 OP_VUZPL, // VUZP, left result
3610 OP_VUZPR, // VUZP, right result
3611 OP_VZIPL, // VZIP, left result
3612 OP_VZIPR, // VZIP, right result
3613 OP_VTRNL, // VTRN, left result
3614 OP_VTRNR // VTRN, right result
3617 if (OpNum == OP_COPY) {
3618 if (LHSID == (1*9+2)*9+3) return LHS;
3619 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3623 SDValue OpLHS, OpRHS;
3624 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3625 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3626 EVT VT = OpLHS.getValueType();
3629 default: llvm_unreachable("Unknown shuffle opcode!");
3631 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3636 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3637 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3641 return DAG.getNode(ARMISD::VEXT, dl, VT,
3643 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3646 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3647 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3650 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3651 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3654 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3655 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3659 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3660 SDValue V1 = Op.getOperand(0);
3661 SDValue V2 = Op.getOperand(1);
3662 DebugLoc dl = Op.getDebugLoc();
3663 EVT VT = Op.getValueType();
3664 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3665 SmallVector<int, 8> ShuffleMask;
3667 // Convert shuffles that are directly supported on NEON to target-specific
3668 // DAG nodes, instead of keeping them as shuffles and matching them again
3669 // during code selection. This is more efficient and avoids the possibility
3670 // of inconsistencies between legalization and selection.
3671 // FIXME: floating-point vectors should be canonicalized to integer vectors
3672 // of the same time so that they get CSEd properly.
3673 SVN->getMask(ShuffleMask);
3675 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3676 if (EltSize <= 32) {
3677 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3678 int Lane = SVN->getSplatIndex();
3679 // If this is undef splat, generate it via "just" vdup, if possible.
3680 if (Lane == -1) Lane = 0;
3682 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3683 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3685 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3686 DAG.getConstant(Lane, MVT::i32));
3691 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3694 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3695 DAG.getConstant(Imm, MVT::i32));
3698 if (isVREVMask(ShuffleMask, VT, 64))
3699 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3700 if (isVREVMask(ShuffleMask, VT, 32))
3701 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3702 if (isVREVMask(ShuffleMask, VT, 16))
3703 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3705 // Check for Neon shuffles that modify both input vectors in place.
3706 // If both results are used, i.e., if there are two shuffles with the same
3707 // source operands and with masks corresponding to both results of one of
3708 // these operations, DAG memoization will ensure that a single node is
3709 // used for both shuffles.
3710 unsigned WhichResult;
3711 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3712 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3713 V1, V2).getValue(WhichResult);
3714 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3715 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3716 V1, V2).getValue(WhichResult);
3717 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3718 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3719 V1, V2).getValue(WhichResult);
3721 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3722 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3723 V1, V1).getValue(WhichResult);
3724 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3725 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3726 V1, V1).getValue(WhichResult);
3727 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3728 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3729 V1, V1).getValue(WhichResult);
3732 // If the shuffle is not directly supported and it has 4 elements, use
3733 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3734 unsigned NumElts = VT.getVectorNumElements();
3736 unsigned PFIndexes[4];
3737 for (unsigned i = 0; i != 4; ++i) {
3738 if (ShuffleMask[i] < 0)
3741 PFIndexes[i] = ShuffleMask[i];
3744 // Compute the index in the perfect shuffle table.
3745 unsigned PFTableIndex =
3746 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3747 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3748 unsigned Cost = (PFEntry >> 30);
3751 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3754 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3755 if (EltSize >= 32) {
3756 // Do the expansion with floating-point types, since that is what the VFP
3757 // registers are defined to use, and since i64 is not legal.
3758 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3759 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3760 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3761 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3762 SmallVector<SDValue, 8> Ops;
3763 for (unsigned i = 0; i < NumElts; ++i) {
3764 if (ShuffleMask[i] < 0)
3765 Ops.push_back(DAG.getUNDEF(EltVT));
3767 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3768 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3769 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3772 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3773 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3779 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3780 EVT VT = Op.getValueType();
3781 DebugLoc dl = Op.getDebugLoc();
3782 SDValue Vec = Op.getOperand(0);
3783 SDValue Lane = Op.getOperand(1);
3784 assert(VT == MVT::i32 &&
3785 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3786 "unexpected type for custom-lowering vector extract");
3787 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3790 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3791 // The only time a CONCAT_VECTORS operation can have legal types is when
3792 // two 64-bit vectors are concatenated to a 128-bit vector.
3793 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3794 "unexpected CONCAT_VECTORS");
3795 DebugLoc dl = Op.getDebugLoc();
3796 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3797 SDValue Op0 = Op.getOperand(0);
3798 SDValue Op1 = Op.getOperand(1);
3799 if (Op0.getOpcode() != ISD::UNDEF)
3800 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3801 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3802 DAG.getIntPtrConstant(0));
3803 if (Op1.getOpcode() != ISD::UNDEF)
3804 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3805 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3806 DAG.getIntPtrConstant(1));
3807 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3810 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3811 /// an extending load, return the unextended value.
3812 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3813 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3814 return N->getOperand(0);
3815 LoadSDNode *LD = cast<LoadSDNode>(N);
3816 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3817 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3818 LD->isNonTemporal(), LD->getAlignment());
3821 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3822 // Multiplications are only custom-lowered for 128-bit vectors so that
3823 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3824 EVT VT = Op.getValueType();
3825 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3826 SDNode *N0 = Op.getOperand(0).getNode();
3827 SDNode *N1 = Op.getOperand(1).getNode();
3828 unsigned NewOpc = 0;
3829 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3830 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3831 NewOpc = ARMISD::VMULLs;
3832 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3833 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3834 NewOpc = ARMISD::VMULLu;
3835 } else if (VT == MVT::v2i64) {
3836 // Fall through to expand this. It is not legal.
3839 // Other vector multiplications are legal.
3843 // Legalize to a VMULL instruction.
3844 DebugLoc DL = Op.getDebugLoc();
3845 SDValue Op0 = SkipExtension(N0, DAG);
3846 SDValue Op1 = SkipExtension(N1, DAG);
3848 assert(Op0.getValueType().is64BitVector() &&
3849 Op1.getValueType().is64BitVector() &&
3850 "unexpected types for extended operands to VMULL");
3851 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3854 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3855 switch (Op.getOpcode()) {
3856 default: llvm_unreachable("Don't know how to custom lower this!");
3857 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3858 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3859 case ISD::GlobalAddress:
3860 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3861 LowerGlobalAddressELF(Op, DAG);
3862 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3863 case ISD::SELECT: return LowerSELECT(Op, DAG);
3864 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3865 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3866 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3867 case ISD::VASTART: return LowerVASTART(Op, DAG);
3868 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3869 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
3870 case ISD::SINT_TO_FP:
3871 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3872 case ISD::FP_TO_SINT:
3873 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3874 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3875 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3876 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3877 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3878 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3879 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3880 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
3881 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3883 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3886 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3887 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3888 case ISD::SRL_PARTS:
3889 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3890 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3891 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3892 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3893 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3894 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3895 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3896 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3897 case ISD::MUL: return LowerMUL(Op, DAG);
3902 /// ReplaceNodeResults - Replace the results of node with an illegal result
3903 /// type with new values built out of custom code.
3904 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3905 SmallVectorImpl<SDValue>&Results,
3906 SelectionDAG &DAG) const {
3908 switch (N->getOpcode()) {
3910 llvm_unreachable("Don't know how to custom expand this!");
3912 case ISD::BIT_CONVERT:
3913 Res = ExpandBIT_CONVERT(N, DAG);
3917 Res = LowerShift(N, DAG, Subtarget);
3921 Results.push_back(Res);
3924 //===----------------------------------------------------------------------===//
3925 // ARM Scheduler Hooks
3926 //===----------------------------------------------------------------------===//
3929 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3930 MachineBasicBlock *BB,
3931 unsigned Size) const {
3932 unsigned dest = MI->getOperand(0).getReg();
3933 unsigned ptr = MI->getOperand(1).getReg();
3934 unsigned oldval = MI->getOperand(2).getReg();
3935 unsigned newval = MI->getOperand(3).getReg();
3936 unsigned scratch = BB->getParent()->getRegInfo()
3937 .createVirtualRegister(ARM::GPRRegisterClass);
3938 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3939 DebugLoc dl = MI->getDebugLoc();
3940 bool isThumb2 = Subtarget->isThumb2();
3942 unsigned ldrOpc, strOpc;
3944 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3946 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3947 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3950 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3951 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3954 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3955 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3959 MachineFunction *MF = BB->getParent();
3960 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3961 MachineFunction::iterator It = BB;
3962 ++It; // insert the new blocks after the current block
3964 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3965 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3966 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3967 MF->insert(It, loop1MBB);
3968 MF->insert(It, loop2MBB);
3969 MF->insert(It, exitMBB);
3971 // Transfer the remainder of BB and its successor edges to exitMBB.
3972 exitMBB->splice(exitMBB->begin(), BB,
3973 llvm::next(MachineBasicBlock::iterator(MI)),
3975 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3979 // fallthrough --> loop1MBB
3980 BB->addSuccessor(loop1MBB);
3983 // ldrex dest, [ptr]
3987 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3988 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3989 .addReg(dest).addReg(oldval));
3990 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3991 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3992 BB->addSuccessor(loop2MBB);
3993 BB->addSuccessor(exitMBB);
3996 // strex scratch, newval, [ptr]
4000 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4002 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4003 .addReg(scratch).addImm(0));
4004 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4005 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4006 BB->addSuccessor(loop1MBB);
4007 BB->addSuccessor(exitMBB);
4013 MI->eraseFromParent(); // The instruction is gone now.
4019 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4020 unsigned Size, unsigned BinOpcode) const {
4021 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4022 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4024 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4025 MachineFunction *MF = BB->getParent();
4026 MachineFunction::iterator It = BB;
4029 unsigned dest = MI->getOperand(0).getReg();
4030 unsigned ptr = MI->getOperand(1).getReg();
4031 unsigned incr = MI->getOperand(2).getReg();
4032 DebugLoc dl = MI->getDebugLoc();
4034 bool isThumb2 = Subtarget->isThumb2();
4035 unsigned ldrOpc, strOpc;
4037 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4039 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4040 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4043 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4044 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4047 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4048 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4052 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4053 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4054 MF->insert(It, loopMBB);
4055 MF->insert(It, exitMBB);
4057 // Transfer the remainder of BB and its successor edges to exitMBB.
4058 exitMBB->splice(exitMBB->begin(), BB,
4059 llvm::next(MachineBasicBlock::iterator(MI)),
4061 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4063 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4064 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4065 unsigned scratch2 = (!BinOpcode) ? incr :
4066 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4070 // fallthrough --> loopMBB
4071 BB->addSuccessor(loopMBB);
4075 // <binop> scratch2, dest, incr
4076 // strex scratch, scratch2, ptr
4079 // fallthrough --> exitMBB
4081 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4083 // operand order needs to go the other way for NAND
4084 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4085 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4086 addReg(incr).addReg(dest)).addReg(0);
4088 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4089 addReg(dest).addReg(incr)).addReg(0);
4092 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4094 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4095 .addReg(scratch).addImm(0));
4096 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4097 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4099 BB->addSuccessor(loopMBB);
4100 BB->addSuccessor(exitMBB);
4106 MI->eraseFromParent(); // The instruction is gone now.
4112 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4113 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4114 E = MBB->succ_end(); I != E; ++I)
4117 llvm_unreachable("Expecting a BB with two successors!");
4121 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4122 MachineBasicBlock *BB) const {
4123 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4124 DebugLoc dl = MI->getDebugLoc();
4125 bool isThumb2 = Subtarget->isThumb2();
4126 switch (MI->getOpcode()) {
4129 llvm_unreachable("Unexpected instr type to insert");
4131 case ARM::ATOMIC_LOAD_ADD_I8:
4132 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4133 case ARM::ATOMIC_LOAD_ADD_I16:
4134 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4135 case ARM::ATOMIC_LOAD_ADD_I32:
4136 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4138 case ARM::ATOMIC_LOAD_AND_I8:
4139 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4140 case ARM::ATOMIC_LOAD_AND_I16:
4141 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4142 case ARM::ATOMIC_LOAD_AND_I32:
4143 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4145 case ARM::ATOMIC_LOAD_OR_I8:
4146 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4147 case ARM::ATOMIC_LOAD_OR_I16:
4148 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4149 case ARM::ATOMIC_LOAD_OR_I32:
4150 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4152 case ARM::ATOMIC_LOAD_XOR_I8:
4153 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4154 case ARM::ATOMIC_LOAD_XOR_I16:
4155 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4156 case ARM::ATOMIC_LOAD_XOR_I32:
4157 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4159 case ARM::ATOMIC_LOAD_NAND_I8:
4160 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4161 case ARM::ATOMIC_LOAD_NAND_I16:
4162 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4163 case ARM::ATOMIC_LOAD_NAND_I32:
4164 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4166 case ARM::ATOMIC_LOAD_SUB_I8:
4167 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4168 case ARM::ATOMIC_LOAD_SUB_I16:
4169 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4170 case ARM::ATOMIC_LOAD_SUB_I32:
4171 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4173 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4174 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4175 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4177 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4178 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4179 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4181 case ARM::tMOVCCr_pseudo: {
4182 // To "insert" a SELECT_CC instruction, we actually have to insert the
4183 // diamond control-flow pattern. The incoming instruction knows the
4184 // destination vreg to set, the condition code register to branch on, the
4185 // true/false values to select between, and a branch opcode to use.
4186 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4187 MachineFunction::iterator It = BB;
4193 // cmpTY ccX, r1, r2
4195 // fallthrough --> copy0MBB
4196 MachineBasicBlock *thisMBB = BB;
4197 MachineFunction *F = BB->getParent();
4198 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4199 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4200 F->insert(It, copy0MBB);
4201 F->insert(It, sinkMBB);
4203 // Transfer the remainder of BB and its successor edges to sinkMBB.
4204 sinkMBB->splice(sinkMBB->begin(), BB,
4205 llvm::next(MachineBasicBlock::iterator(MI)),
4207 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4209 BB->addSuccessor(copy0MBB);
4210 BB->addSuccessor(sinkMBB);
4212 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4213 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4216 // %FalseValue = ...
4217 // # fallthrough to sinkMBB
4220 // Update machine-CFG edges
4221 BB->addSuccessor(sinkMBB);
4224 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4227 BuildMI(*BB, BB->begin(), dl,
4228 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4229 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4230 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4232 MI->eraseFromParent(); // The pseudo instruction is gone now.
4237 case ARM::BCCZi64: {
4238 // Compare both parts that make up the double comparison separately for
4240 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4242 unsigned LHS1 = MI->getOperand(1).getReg();
4243 unsigned LHS2 = MI->getOperand(2).getReg();
4245 AddDefaultPred(BuildMI(BB, dl,
4246 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4247 .addReg(LHS1).addImm(0));
4248 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4249 .addReg(LHS2).addImm(0)
4250 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4252 unsigned RHS1 = MI->getOperand(3).getReg();
4253 unsigned RHS2 = MI->getOperand(4).getReg();
4254 AddDefaultPred(BuildMI(BB, dl,
4255 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4256 .addReg(LHS1).addReg(RHS1));
4257 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4258 .addReg(LHS2).addReg(RHS2)
4259 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4262 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4263 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4264 if (MI->getOperand(0).getImm() == ARMCC::NE)
4265 std::swap(destMBB, exitMBB);
4267 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4268 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4269 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4272 MI->eraseFromParent(); // The pseudo instruction is gone now.
4278 //===----------------------------------------------------------------------===//
4279 // ARM Optimization Hooks
4280 //===----------------------------------------------------------------------===//
4283 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4284 TargetLowering::DAGCombinerInfo &DCI) {
4285 SelectionDAG &DAG = DCI.DAG;
4286 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4287 EVT VT = N->getValueType(0);
4288 unsigned Opc = N->getOpcode();
4289 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4290 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4291 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4292 ISD::CondCode CC = ISD::SETCC_INVALID;
4295 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4297 SDValue CCOp = Slct.getOperand(0);
4298 if (CCOp.getOpcode() == ISD::SETCC)
4299 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4302 bool DoXform = false;
4304 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4307 if (LHS.getOpcode() == ISD::Constant &&
4308 cast<ConstantSDNode>(LHS)->isNullValue()) {
4310 } else if (CC != ISD::SETCC_INVALID &&
4311 RHS.getOpcode() == ISD::Constant &&
4312 cast<ConstantSDNode>(RHS)->isNullValue()) {
4313 std::swap(LHS, RHS);
4314 SDValue Op0 = Slct.getOperand(0);
4315 EVT OpVT = isSlctCC ? Op0.getValueType() :
4316 Op0.getOperand(0).getValueType();
4317 bool isInt = OpVT.isInteger();
4318 CC = ISD::getSetCCInverse(CC, isInt);
4320 if (!TLI.isCondCodeLegal(CC, OpVT))
4321 return SDValue(); // Inverse operator isn't legal.
4328 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4330 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4331 Slct.getOperand(0), Slct.getOperand(1), CC);
4332 SDValue CCOp = Slct.getOperand(0);
4334 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4335 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4336 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4337 CCOp, OtherOp, Result);
4342 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4343 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4344 /// called with the default operands, and if that fails, with commuted
4346 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4347 TargetLowering::DAGCombinerInfo &DCI) {
4348 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4349 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4350 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4351 if (Result.getNode()) return Result;
4356 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4358 static SDValue PerformADDCombine(SDNode *N,
4359 TargetLowering::DAGCombinerInfo &DCI) {
4360 SDValue N0 = N->getOperand(0);
4361 SDValue N1 = N->getOperand(1);
4363 // First try with the default operand order.
4364 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4365 if (Result.getNode())
4368 // If that didn't work, try again with the operands commuted.
4369 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4372 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4374 static SDValue PerformSUBCombine(SDNode *N,
4375 TargetLowering::DAGCombinerInfo &DCI) {
4376 SDValue N0 = N->getOperand(0);
4377 SDValue N1 = N->getOperand(1);
4379 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4380 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4381 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4382 if (Result.getNode()) return Result;
4388 static SDValue PerformMULCombine(SDNode *N,
4389 TargetLowering::DAGCombinerInfo &DCI,
4390 const ARMSubtarget *Subtarget) {
4391 SelectionDAG &DAG = DCI.DAG;
4393 if (Subtarget->isThumb1Only())
4396 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4399 EVT VT = N->getValueType(0);
4403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4407 uint64_t MulAmt = C->getZExtValue();
4408 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4409 ShiftAmt = ShiftAmt & (32 - 1);
4410 SDValue V = N->getOperand(0);
4411 DebugLoc DL = N->getDebugLoc();
4414 MulAmt >>= ShiftAmt;
4415 if (isPowerOf2_32(MulAmt - 1)) {
4416 // (mul x, 2^N + 1) => (add (shl x, N), x)
4417 Res = DAG.getNode(ISD::ADD, DL, VT,
4418 V, DAG.getNode(ISD::SHL, DL, VT,
4419 V, DAG.getConstant(Log2_32(MulAmt-1),
4421 } else if (isPowerOf2_32(MulAmt + 1)) {
4422 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4423 Res = DAG.getNode(ISD::SUB, DL, VT,
4424 DAG.getNode(ISD::SHL, DL, VT,
4425 V, DAG.getConstant(Log2_32(MulAmt+1),
4432 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4433 DAG.getConstant(ShiftAmt, MVT::i32));
4435 // Do not add new nodes to DAG combiner worklist.
4436 DCI.CombineTo(N, Res, false);
4440 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4441 static SDValue PerformORCombine(SDNode *N,
4442 TargetLowering::DAGCombinerInfo &DCI,
4443 const ARMSubtarget *Subtarget) {
4444 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4447 // BFI is only available on V6T2+
4448 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4451 SelectionDAG &DAG = DCI.DAG;
4452 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4453 DebugLoc DL = N->getDebugLoc();
4454 // 1) or (and A, mask), val => ARMbfi A, val, mask
4455 // iff (val & mask) == val
4457 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4458 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4459 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4460 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4461 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4462 // (i.e., copy a bitfield value into another bitfield of the same width)
4463 if (N0.getOpcode() != ISD::AND)
4466 EVT VT = N->getValueType(0);
4471 // The value and the mask need to be constants so we can verify this is
4472 // actually a bitfield set. If the mask is 0xffff, we can do better
4473 // via a movt instruction, so don't use BFI in that case.
4474 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4477 unsigned Mask = C->getZExtValue();
4481 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4482 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4483 unsigned Val = C->getZExtValue();
4484 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4486 Val >>= CountTrailingZeros_32(~Mask);
4488 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4489 DAG.getConstant(Val, MVT::i32),
4490 DAG.getConstant(Mask, MVT::i32));
4492 // Do not add new nodes to DAG combiner worklist.
4493 DCI.CombineTo(N, Res, false);
4494 } else if (N1.getOpcode() == ISD::AND) {
4495 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4496 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4499 unsigned Mask2 = C->getZExtValue();
4501 if (ARM::isBitFieldInvertedMask(Mask) &&
4502 ARM::isBitFieldInvertedMask(~Mask2) &&
4503 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4504 // The pack halfword instruction works better for masks that fit it,
4505 // so use that when it's available.
4506 if (Subtarget->hasT2ExtractPack() &&
4507 (Mask == 0xffff || Mask == 0xffff0000))
4510 unsigned lsb = CountTrailingZeros_32(Mask2);
4511 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4512 DAG.getConstant(lsb, MVT::i32));
4513 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4514 DAG.getConstant(Mask, MVT::i32));
4515 // Do not add new nodes to DAG combiner worklist.
4516 DCI.CombineTo(N, Res, false);
4517 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4518 ARM::isBitFieldInvertedMask(Mask2) &&
4519 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4520 // The pack halfword instruction works better for masks that fit it,
4521 // so use that when it's available.
4522 if (Subtarget->hasT2ExtractPack() &&
4523 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4526 unsigned lsb = CountTrailingZeros_32(Mask);
4527 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4528 DAG.getConstant(lsb, MVT::i32));
4529 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4530 DAG.getConstant(Mask2, MVT::i32));
4531 // Do not add new nodes to DAG combiner worklist.
4532 DCI.CombineTo(N, Res, false);
4539 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4540 /// ARMISD::VMOVRRD.
4541 static SDValue PerformVMOVRRDCombine(SDNode *N,
4542 TargetLowering::DAGCombinerInfo &DCI) {
4543 // vmovrrd(vmovdrr x, y) -> x,y
4544 SDValue InDouble = N->getOperand(0);
4545 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4546 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4550 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4551 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4552 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4553 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4554 SDValue Op0 = N->getOperand(0);
4555 SDValue Op1 = N->getOperand(1);
4556 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4557 Op0 = Op0.getOperand(0);
4558 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4559 Op1 = Op1.getOperand(0);
4560 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4561 Op0.getNode() == Op1.getNode() &&
4562 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4563 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4564 N->getValueType(0), Op0.getOperand(0));
4568 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4569 /// ISD::BUILD_VECTOR.
4570 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4571 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4572 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4573 // into a pair of GPRs, which is fine when the value is used as a scalar,
4574 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4575 if (N->getNumOperands() == 2)
4576 return PerformVMOVDRRCombine(N, DAG);
4581 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4582 /// ISD::VECTOR_SHUFFLE.
4583 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4584 // The LLVM shufflevector instruction does not require the shuffle mask
4585 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4586 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4587 // operands do not match the mask length, they are extended by concatenating
4588 // them with undef vectors. That is probably the right thing for other
4589 // targets, but for NEON it is better to concatenate two double-register
4590 // size vector operands into a single quad-register size vector. Do that
4591 // transformation here:
4592 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4593 // shuffle(concat(v1, v2), undef)
4594 SDValue Op0 = N->getOperand(0);
4595 SDValue Op1 = N->getOperand(1);
4596 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4597 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4598 Op0.getNumOperands() != 2 ||
4599 Op1.getNumOperands() != 2)
4601 SDValue Concat0Op1 = Op0.getOperand(1);
4602 SDValue Concat1Op1 = Op1.getOperand(1);
4603 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4604 Concat1Op1.getOpcode() != ISD::UNDEF)
4606 // Skip the transformation if any of the types are illegal.
4607 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4608 EVT VT = N->getValueType(0);
4609 if (!TLI.isTypeLegal(VT) ||
4610 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
4611 !TLI.isTypeLegal(Concat1Op1.getValueType()))
4614 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
4615 Op0.getOperand(0), Op1.getOperand(0));
4616 // Translate the shuffle mask.
4617 SmallVector<int, 16> NewMask;
4618 unsigned NumElts = VT.getVectorNumElements();
4619 unsigned HalfElts = NumElts/2;
4620 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4621 for (unsigned n = 0; n < NumElts; ++n) {
4622 int MaskElt = SVN->getMaskElt(n);
4624 if (MaskElt < (int)HalfElts)
4626 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
4627 NewElt = HalfElts + MaskElt - NumElts;
4628 NewMask.push_back(NewElt);
4630 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
4631 DAG.getUNDEF(VT), NewMask.data());
4634 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4635 /// ARMISD::VDUPLANE.
4636 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4637 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4639 SDValue Op = N->getOperand(0);
4640 EVT VT = N->getValueType(0);
4642 // Ignore bit_converts.
4643 while (Op.getOpcode() == ISD::BIT_CONVERT)
4644 Op = Op.getOperand(0);
4645 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4648 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4649 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4650 // The canonical VMOV for a zero vector uses a 32-bit element size.
4651 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4653 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4655 if (EltSize > VT.getVectorElementType().getSizeInBits())
4658 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4661 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4662 /// operand of a vector shift operation, where all the elements of the
4663 /// build_vector must have the same constant integer value.
4664 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4665 // Ignore bit_converts.
4666 while (Op.getOpcode() == ISD::BIT_CONVERT)
4667 Op = Op.getOperand(0);
4668 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4669 APInt SplatBits, SplatUndef;
4670 unsigned SplatBitSize;
4672 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4673 HasAnyUndefs, ElementBits) ||
4674 SplatBitSize > ElementBits)
4676 Cnt = SplatBits.getSExtValue();
4680 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4681 /// operand of a vector shift left operation. That value must be in the range:
4682 /// 0 <= Value < ElementBits for a left shift; or
4683 /// 0 <= Value <= ElementBits for a long left shift.
4684 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4685 assert(VT.isVector() && "vector shift count is not a vector type");
4686 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4687 if (! getVShiftImm(Op, ElementBits, Cnt))
4689 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4692 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4693 /// operand of a vector shift right operation. For a shift opcode, the value
4694 /// is positive, but for an intrinsic the value count must be negative. The
4695 /// absolute value must be in the range:
4696 /// 1 <= |Value| <= ElementBits for a right shift; or
4697 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4698 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4700 assert(VT.isVector() && "vector shift count is not a vector type");
4701 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4702 if (! getVShiftImm(Op, ElementBits, Cnt))
4706 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4709 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4710 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4711 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4714 // Don't do anything for most intrinsics.
4717 // Vector shifts: check for immediate versions and lower them.
4718 // Note: This is done during DAG combining instead of DAG legalizing because
4719 // the build_vectors for 64-bit vector element shift counts are generally
4720 // not legal, and it is hard to see their values after they get legalized to
4721 // loads from a constant pool.
4722 case Intrinsic::arm_neon_vshifts:
4723 case Intrinsic::arm_neon_vshiftu:
4724 case Intrinsic::arm_neon_vshiftls:
4725 case Intrinsic::arm_neon_vshiftlu:
4726 case Intrinsic::arm_neon_vshiftn:
4727 case Intrinsic::arm_neon_vrshifts:
4728 case Intrinsic::arm_neon_vrshiftu:
4729 case Intrinsic::arm_neon_vrshiftn:
4730 case Intrinsic::arm_neon_vqshifts:
4731 case Intrinsic::arm_neon_vqshiftu:
4732 case Intrinsic::arm_neon_vqshiftsu:
4733 case Intrinsic::arm_neon_vqshiftns:
4734 case Intrinsic::arm_neon_vqshiftnu:
4735 case Intrinsic::arm_neon_vqshiftnsu:
4736 case Intrinsic::arm_neon_vqrshiftns:
4737 case Intrinsic::arm_neon_vqrshiftnu:
4738 case Intrinsic::arm_neon_vqrshiftnsu: {
4739 EVT VT = N->getOperand(1).getValueType();
4741 unsigned VShiftOpc = 0;
4744 case Intrinsic::arm_neon_vshifts:
4745 case Intrinsic::arm_neon_vshiftu:
4746 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4747 VShiftOpc = ARMISD::VSHL;
4750 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4751 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4752 ARMISD::VSHRs : ARMISD::VSHRu);
4757 case Intrinsic::arm_neon_vshiftls:
4758 case Intrinsic::arm_neon_vshiftlu:
4759 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4761 llvm_unreachable("invalid shift count for vshll intrinsic");
4763 case Intrinsic::arm_neon_vrshifts:
4764 case Intrinsic::arm_neon_vrshiftu:
4765 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4769 case Intrinsic::arm_neon_vqshifts:
4770 case Intrinsic::arm_neon_vqshiftu:
4771 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4775 case Intrinsic::arm_neon_vqshiftsu:
4776 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4778 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4780 case Intrinsic::arm_neon_vshiftn:
4781 case Intrinsic::arm_neon_vrshiftn:
4782 case Intrinsic::arm_neon_vqshiftns:
4783 case Intrinsic::arm_neon_vqshiftnu:
4784 case Intrinsic::arm_neon_vqshiftnsu:
4785 case Intrinsic::arm_neon_vqrshiftns:
4786 case Intrinsic::arm_neon_vqrshiftnu:
4787 case Intrinsic::arm_neon_vqrshiftnsu:
4788 // Narrowing shifts require an immediate right shift.
4789 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4791 llvm_unreachable("invalid shift count for narrowing vector shift "
4795 llvm_unreachable("unhandled vector shift");
4799 case Intrinsic::arm_neon_vshifts:
4800 case Intrinsic::arm_neon_vshiftu:
4801 // Opcode already set above.
4803 case Intrinsic::arm_neon_vshiftls:
4804 case Intrinsic::arm_neon_vshiftlu:
4805 if (Cnt == VT.getVectorElementType().getSizeInBits())
4806 VShiftOpc = ARMISD::VSHLLi;
4808 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4809 ARMISD::VSHLLs : ARMISD::VSHLLu);
4811 case Intrinsic::arm_neon_vshiftn:
4812 VShiftOpc = ARMISD::VSHRN; break;
4813 case Intrinsic::arm_neon_vrshifts:
4814 VShiftOpc = ARMISD::VRSHRs; break;
4815 case Intrinsic::arm_neon_vrshiftu:
4816 VShiftOpc = ARMISD::VRSHRu; break;
4817 case Intrinsic::arm_neon_vrshiftn:
4818 VShiftOpc = ARMISD::VRSHRN; break;
4819 case Intrinsic::arm_neon_vqshifts:
4820 VShiftOpc = ARMISD::VQSHLs; break;
4821 case Intrinsic::arm_neon_vqshiftu:
4822 VShiftOpc = ARMISD::VQSHLu; break;
4823 case Intrinsic::arm_neon_vqshiftsu:
4824 VShiftOpc = ARMISD::VQSHLsu; break;
4825 case Intrinsic::arm_neon_vqshiftns:
4826 VShiftOpc = ARMISD::VQSHRNs; break;
4827 case Intrinsic::arm_neon_vqshiftnu:
4828 VShiftOpc = ARMISD::VQSHRNu; break;
4829 case Intrinsic::arm_neon_vqshiftnsu:
4830 VShiftOpc = ARMISD::VQSHRNsu; break;
4831 case Intrinsic::arm_neon_vqrshiftns:
4832 VShiftOpc = ARMISD::VQRSHRNs; break;
4833 case Intrinsic::arm_neon_vqrshiftnu:
4834 VShiftOpc = ARMISD::VQRSHRNu; break;
4835 case Intrinsic::arm_neon_vqrshiftnsu:
4836 VShiftOpc = ARMISD::VQRSHRNsu; break;
4839 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4840 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4843 case Intrinsic::arm_neon_vshiftins: {
4844 EVT VT = N->getOperand(1).getValueType();
4846 unsigned VShiftOpc = 0;
4848 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4849 VShiftOpc = ARMISD::VSLI;
4850 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4851 VShiftOpc = ARMISD::VSRI;
4853 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4856 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4857 N->getOperand(1), N->getOperand(2),
4858 DAG.getConstant(Cnt, MVT::i32));
4861 case Intrinsic::arm_neon_vqrshifts:
4862 case Intrinsic::arm_neon_vqrshiftu:
4863 // No immediate versions of these to check for.
4870 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4871 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4872 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4873 /// vector element shift counts are generally not legal, and it is hard to see
4874 /// their values after they get legalized to loads from a constant pool.
4875 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4876 const ARMSubtarget *ST) {
4877 EVT VT = N->getValueType(0);
4879 // Nothing to be done for scalar shifts.
4880 if (! VT.isVector())
4883 assert(ST->hasNEON() && "unexpected vector shift");
4886 switch (N->getOpcode()) {
4887 default: llvm_unreachable("unexpected shift opcode");
4890 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4891 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4892 DAG.getConstant(Cnt, MVT::i32));
4897 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4898 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4899 ARMISD::VSHRs : ARMISD::VSHRu);
4900 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4901 DAG.getConstant(Cnt, MVT::i32));
4907 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4908 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4909 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4910 const ARMSubtarget *ST) {
4911 SDValue N0 = N->getOperand(0);
4913 // Check for sign- and zero-extensions of vector extract operations of 8-
4914 // and 16-bit vector elements. NEON supports these directly. They are
4915 // handled during DAG combining because type legalization will promote them
4916 // to 32-bit types and it is messy to recognize the operations after that.
4917 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4918 SDValue Vec = N0.getOperand(0);
4919 SDValue Lane = N0.getOperand(1);
4920 EVT VT = N->getValueType(0);
4921 EVT EltVT = N0.getValueType();
4922 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4924 if (VT == MVT::i32 &&
4925 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4926 TLI.isTypeLegal(Vec.getValueType())) {
4929 switch (N->getOpcode()) {
4930 default: llvm_unreachable("unexpected opcode");
4931 case ISD::SIGN_EXTEND:
4932 Opc = ARMISD::VGETLANEs;
4934 case ISD::ZERO_EXTEND:
4935 case ISD::ANY_EXTEND:
4936 Opc = ARMISD::VGETLANEu;
4939 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4946 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4947 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4948 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4949 const ARMSubtarget *ST) {
4950 // If the target supports NEON, try to use vmax/vmin instructions for f32
4951 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4952 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4953 // a NaN; only do the transformation when it matches that behavior.
4955 // For now only do this when using NEON for FP operations; if using VFP, it
4956 // is not obvious that the benefit outweighs the cost of switching to the
4958 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4959 N->getValueType(0) != MVT::f32)
4962 SDValue CondLHS = N->getOperand(0);
4963 SDValue CondRHS = N->getOperand(1);
4964 SDValue LHS = N->getOperand(2);
4965 SDValue RHS = N->getOperand(3);
4966 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4968 unsigned Opcode = 0;
4970 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4971 IsReversed = false; // x CC y ? x : y
4972 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4973 IsReversed = true ; // x CC y ? y : x
4987 // If LHS is NaN, an ordered comparison will be false and the result will
4988 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4989 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4990 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4991 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4993 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4994 // will return -0, so vmin can only be used for unsafe math or if one of
4995 // the operands is known to be nonzero.
4996 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4998 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5000 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5009 // If LHS is NaN, an ordered comparison will be false and the result will
5010 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5011 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5012 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5013 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5015 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5016 // will return +0, so vmax can only be used for unsafe math or if one of
5017 // the operands is known to be nonzero.
5018 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5020 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5022 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5028 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5031 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5032 DAGCombinerInfo &DCI) const {
5033 switch (N->getOpcode()) {
5035 case ISD::ADD: return PerformADDCombine(N, DCI);
5036 case ISD::SUB: return PerformSUBCombine(N, DCI);
5037 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5038 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5039 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5040 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5041 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
5042 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5043 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
5044 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5047 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5048 case ISD::SIGN_EXTEND:
5049 case ISD::ZERO_EXTEND:
5050 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5051 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5056 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5057 if (!Subtarget->allowsUnalignedMem())
5060 switch (VT.getSimpleVT().SimpleTy) {
5067 // FIXME: VLD1 etc with standard alignment is legal.
5071 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5076 switch (VT.getSimpleVT().SimpleTy) {
5077 default: return false;
5092 if ((V & (Scale - 1)) != 0)
5095 return V == (V & ((1LL << 5) - 1));
5098 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5099 const ARMSubtarget *Subtarget) {
5106 switch (VT.getSimpleVT().SimpleTy) {
5107 default: return false;
5112 // + imm12 or - imm8
5114 return V == (V & ((1LL << 8) - 1));
5115 return V == (V & ((1LL << 12) - 1));
5118 // Same as ARM mode. FIXME: NEON?
5119 if (!Subtarget->hasVFP2())
5124 return V == (V & ((1LL << 8) - 1));
5128 /// isLegalAddressImmediate - Return true if the integer value can be used
5129 /// as the offset of the target addressing mode for load / store of the
5131 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5132 const ARMSubtarget *Subtarget) {
5139 if (Subtarget->isThumb1Only())
5140 return isLegalT1AddressImmediate(V, VT);
5141 else if (Subtarget->isThumb2())
5142 return isLegalT2AddressImmediate(V, VT, Subtarget);
5147 switch (VT.getSimpleVT().SimpleTy) {
5148 default: return false;
5153 return V == (V & ((1LL << 12) - 1));
5156 return V == (V & ((1LL << 8) - 1));
5159 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5164 return V == (V & ((1LL << 8) - 1));
5168 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5170 int Scale = AM.Scale;
5174 switch (VT.getSimpleVT().SimpleTy) {
5175 default: return false;
5184 return Scale == 2 || Scale == 4 || Scale == 8;
5187 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5191 // Note, we allow "void" uses (basically, uses that aren't loads or
5192 // stores), because arm allows folding a scale into many arithmetic
5193 // operations. This should be made more precise and revisited later.
5195 // Allow r << imm, but the imm has to be a multiple of two.
5196 if (Scale & 1) return false;
5197 return isPowerOf2_32(Scale);
5201 /// isLegalAddressingMode - Return true if the addressing mode represented
5202 /// by AM is legal for this target, for a load/store of the specified type.
5203 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5204 const Type *Ty) const {
5205 EVT VT = getValueType(Ty, true);
5206 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5209 // Can never fold addr of global into load/store.
5214 case 0: // no scale reg, must be "r+i" or "r", or "i".
5217 if (Subtarget->isThumb1Only())
5221 // ARM doesn't support any R+R*scale+imm addr modes.
5228 if (Subtarget->isThumb2())
5229 return isLegalT2ScaledAddressingMode(AM, VT);
5231 int Scale = AM.Scale;
5232 switch (VT.getSimpleVT().SimpleTy) {
5233 default: return false;
5237 if (Scale < 0) Scale = -Scale;
5241 return isPowerOf2_32(Scale & ~1);
5245 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5250 // Note, we allow "void" uses (basically, uses that aren't loads or
5251 // stores), because arm allows folding a scale into many arithmetic
5252 // operations. This should be made more precise and revisited later.
5254 // Allow r << imm, but the imm has to be a multiple of two.
5255 if (Scale & 1) return false;
5256 return isPowerOf2_32(Scale);
5263 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5264 /// icmp immediate, that is the target has icmp instructions which can compare
5265 /// a register against the immediate without having to materialize the
5266 /// immediate into a register.
5267 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5268 if (!Subtarget->isThumb())
5269 return ARM_AM::getSOImmVal(Imm) != -1;
5270 if (Subtarget->isThumb2())
5271 return ARM_AM::getT2SOImmVal(Imm) != -1;
5272 return Imm >= 0 && Imm <= 255;
5275 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5276 bool isSEXTLoad, SDValue &Base,
5277 SDValue &Offset, bool &isInc,
5278 SelectionDAG &DAG) {
5279 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5282 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5284 Base = Ptr->getOperand(0);
5285 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5286 int RHSC = (int)RHS->getZExtValue();
5287 if (RHSC < 0 && RHSC > -256) {
5288 assert(Ptr->getOpcode() == ISD::ADD);
5290 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5294 isInc = (Ptr->getOpcode() == ISD::ADD);
5295 Offset = Ptr->getOperand(1);
5297 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5299 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5300 int RHSC = (int)RHS->getZExtValue();
5301 if (RHSC < 0 && RHSC > -0x1000) {
5302 assert(Ptr->getOpcode() == ISD::ADD);
5304 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5305 Base = Ptr->getOperand(0);
5310 if (Ptr->getOpcode() == ISD::ADD) {
5312 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5313 if (ShOpcVal != ARM_AM::no_shift) {
5314 Base = Ptr->getOperand(1);
5315 Offset = Ptr->getOperand(0);
5317 Base = Ptr->getOperand(0);
5318 Offset = Ptr->getOperand(1);
5323 isInc = (Ptr->getOpcode() == ISD::ADD);
5324 Base = Ptr->getOperand(0);
5325 Offset = Ptr->getOperand(1);
5329 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5333 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5334 bool isSEXTLoad, SDValue &Base,
5335 SDValue &Offset, bool &isInc,
5336 SelectionDAG &DAG) {
5337 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5340 Base = Ptr->getOperand(0);
5341 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5342 int RHSC = (int)RHS->getZExtValue();
5343 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5344 assert(Ptr->getOpcode() == ISD::ADD);
5346 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5348 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5349 isInc = Ptr->getOpcode() == ISD::ADD;
5350 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5358 /// getPreIndexedAddressParts - returns true by value, base pointer and
5359 /// offset pointer and addressing mode by reference if the node's address
5360 /// can be legally represented as pre-indexed load / store address.
5362 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5364 ISD::MemIndexedMode &AM,
5365 SelectionDAG &DAG) const {
5366 if (Subtarget->isThumb1Only())
5371 bool isSEXTLoad = false;
5372 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5373 Ptr = LD->getBasePtr();
5374 VT = LD->getMemoryVT();
5375 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5376 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5377 Ptr = ST->getBasePtr();
5378 VT = ST->getMemoryVT();
5383 bool isLegal = false;
5384 if (Subtarget->isThumb2())
5385 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5386 Offset, isInc, DAG);
5388 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5389 Offset, isInc, DAG);
5393 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5397 /// getPostIndexedAddressParts - returns true by value, base pointer and
5398 /// offset pointer and addressing mode by reference if this node can be
5399 /// combined with a load / store to form a post-indexed load / store.
5400 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5403 ISD::MemIndexedMode &AM,
5404 SelectionDAG &DAG) const {
5405 if (Subtarget->isThumb1Only())
5410 bool isSEXTLoad = false;
5411 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5412 VT = LD->getMemoryVT();
5413 Ptr = LD->getBasePtr();
5414 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5415 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5416 VT = ST->getMemoryVT();
5417 Ptr = ST->getBasePtr();
5422 bool isLegal = false;
5423 if (Subtarget->isThumb2())
5424 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5427 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5433 // Swap base ptr and offset to catch more post-index load / store when
5434 // it's legal. In Thumb2 mode, offset must be an immediate.
5435 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5436 !Subtarget->isThumb2())
5437 std::swap(Base, Offset);
5439 // Post-indexed load / store update the base pointer.
5444 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5448 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5452 const SelectionDAG &DAG,
5453 unsigned Depth) const {
5454 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5455 switch (Op.getOpcode()) {
5457 case ARMISD::CMOV: {
5458 // Bits are known zero/one if known on the LHS and RHS.
5459 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5460 if (KnownZero == 0 && KnownOne == 0) return;
5462 APInt KnownZeroRHS, KnownOneRHS;
5463 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5464 KnownZeroRHS, KnownOneRHS, Depth+1);
5465 KnownZero &= KnownZeroRHS;
5466 KnownOne &= KnownOneRHS;
5472 //===----------------------------------------------------------------------===//
5473 // ARM Inline Assembly Support
5474 //===----------------------------------------------------------------------===//
5476 /// getConstraintType - Given a constraint letter, return the type of
5477 /// constraint it is for this target.
5478 ARMTargetLowering::ConstraintType
5479 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5480 if (Constraint.size() == 1) {
5481 switch (Constraint[0]) {
5483 case 'l': return C_RegisterClass;
5484 case 'w': return C_RegisterClass;
5487 return TargetLowering::getConstraintType(Constraint);
5490 /// Examine constraint type and operand type and determine a weight value.
5491 /// This object must already have been set up with the operand type
5492 /// and the current alternative constraint selected.
5493 TargetLowering::ConstraintWeight
5494 ARMTargetLowering::getSingleConstraintMatchWeight(
5495 AsmOperandInfo &info, const char *constraint) const {
5496 ConstraintWeight weight = CW_Invalid;
5497 Value *CallOperandVal = info.CallOperandVal;
5498 // If we don't have a value, we can't do a match,
5499 // but allow it at the lowest weight.
5500 if (CallOperandVal == NULL)
5502 const Type *type = CallOperandVal->getType();
5503 // Look at the constraint type.
5504 switch (*constraint) {
5506 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5509 if (type->isIntegerTy()) {
5510 if (Subtarget->isThumb())
5511 weight = CW_SpecificReg;
5513 weight = CW_Register;
5517 if (type->isFloatingPointTy())
5518 weight = CW_Register;
5524 std::pair<unsigned, const TargetRegisterClass*>
5525 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5527 if (Constraint.size() == 1) {
5528 // GCC ARM Constraint Letters
5529 switch (Constraint[0]) {
5531 if (Subtarget->isThumb())
5532 return std::make_pair(0U, ARM::tGPRRegisterClass);
5534 return std::make_pair(0U, ARM::GPRRegisterClass);
5536 return std::make_pair(0U, ARM::GPRRegisterClass);
5539 return std::make_pair(0U, ARM::SPRRegisterClass);
5540 if (VT.getSizeInBits() == 64)
5541 return std::make_pair(0U, ARM::DPRRegisterClass);
5542 if (VT.getSizeInBits() == 128)
5543 return std::make_pair(0U, ARM::QPRRegisterClass);
5547 if (StringRef("{cc}").equals_lower(Constraint))
5548 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5550 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5553 std::vector<unsigned> ARMTargetLowering::
5554 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5556 if (Constraint.size() != 1)
5557 return std::vector<unsigned>();
5559 switch (Constraint[0]) { // GCC ARM Constraint Letters
5562 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5563 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5566 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5567 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5568 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5569 ARM::R12, ARM::LR, 0);
5572 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5573 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5574 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5575 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5576 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5577 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5578 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5579 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5580 if (VT.getSizeInBits() == 64)
5581 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5582 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5583 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5584 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5585 if (VT.getSizeInBits() == 128)
5586 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5587 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5591 return std::vector<unsigned>();
5594 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5595 /// vector. If it is invalid, don't add anything to Ops.
5596 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5598 std::vector<SDValue>&Ops,
5599 SelectionDAG &DAG) const {
5600 SDValue Result(0, 0);
5602 switch (Constraint) {
5604 case 'I': case 'J': case 'K': case 'L':
5605 case 'M': case 'N': case 'O':
5606 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5610 int64_t CVal64 = C->getSExtValue();
5611 int CVal = (int) CVal64;
5612 // None of these constraints allow values larger than 32 bits. Check
5613 // that the value fits in an int.
5617 switch (Constraint) {
5619 if (Subtarget->isThumb1Only()) {
5620 // This must be a constant between 0 and 255, for ADD
5622 if (CVal >= 0 && CVal <= 255)
5624 } else if (Subtarget->isThumb2()) {
5625 // A constant that can be used as an immediate value in a
5626 // data-processing instruction.
5627 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5630 // A constant that can be used as an immediate value in a
5631 // data-processing instruction.
5632 if (ARM_AM::getSOImmVal(CVal) != -1)
5638 if (Subtarget->isThumb()) { // FIXME thumb2
5639 // This must be a constant between -255 and -1, for negated ADD
5640 // immediates. This can be used in GCC with an "n" modifier that
5641 // prints the negated value, for use with SUB instructions. It is
5642 // not useful otherwise but is implemented for compatibility.
5643 if (CVal >= -255 && CVal <= -1)
5646 // This must be a constant between -4095 and 4095. It is not clear
5647 // what this constraint is intended for. Implemented for
5648 // compatibility with GCC.
5649 if (CVal >= -4095 && CVal <= 4095)
5655 if (Subtarget->isThumb1Only()) {
5656 // A 32-bit value where only one byte has a nonzero value. Exclude
5657 // zero to match GCC. This constraint is used by GCC internally for
5658 // constants that can be loaded with a move/shift combination.
5659 // It is not useful otherwise but is implemented for compatibility.
5660 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5662 } else if (Subtarget->isThumb2()) {
5663 // A constant whose bitwise inverse can be used as an immediate
5664 // value in a data-processing instruction. This can be used in GCC
5665 // with a "B" modifier that prints the inverted value, for use with
5666 // BIC and MVN instructions. It is not useful otherwise but is
5667 // implemented for compatibility.
5668 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5671 // A constant whose bitwise inverse can be used as an immediate
5672 // value in a data-processing instruction. This can be used in GCC
5673 // with a "B" modifier that prints the inverted value, for use with
5674 // BIC and MVN instructions. It is not useful otherwise but is
5675 // implemented for compatibility.
5676 if (ARM_AM::getSOImmVal(~CVal) != -1)
5682 if (Subtarget->isThumb1Only()) {
5683 // This must be a constant between -7 and 7,
5684 // for 3-operand ADD/SUB immediate instructions.
5685 if (CVal >= -7 && CVal < 7)
5687 } else if (Subtarget->isThumb2()) {
5688 // A constant whose negation can be used as an immediate value in a
5689 // data-processing instruction. This can be used in GCC with an "n"
5690 // modifier that prints the negated value, for use with SUB
5691 // instructions. It is not useful otherwise but is implemented for
5693 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5696 // A constant whose negation can be used as an immediate value in a
5697 // data-processing instruction. This can be used in GCC with an "n"
5698 // modifier that prints the negated value, for use with SUB
5699 // instructions. It is not useful otherwise but is implemented for
5701 if (ARM_AM::getSOImmVal(-CVal) != -1)
5707 if (Subtarget->isThumb()) { // FIXME thumb2
5708 // This must be a multiple of 4 between 0 and 1020, for
5709 // ADD sp + immediate.
5710 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5713 // A power of two or a constant between 0 and 32. This is used in
5714 // GCC for the shift amount on shifted register operands, but it is
5715 // useful in general for any shift amounts.
5716 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5722 if (Subtarget->isThumb()) { // FIXME thumb2
5723 // This must be a constant between 0 and 31, for shift amounts.
5724 if (CVal >= 0 && CVal <= 31)
5730 if (Subtarget->isThumb()) { // FIXME thumb2
5731 // This must be a multiple of 4 between -508 and 508, for
5732 // ADD/SUB sp = sp + immediate.
5733 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5738 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5742 if (Result.getNode()) {
5743 Ops.push_back(Result);
5746 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5750 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5751 // The ARM target isn't yet aware of offsets.
5755 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5756 APInt Imm = FPImm.bitcastToAPInt();
5757 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5758 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5759 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5761 // We can handle 4 bits of mantissa.
5762 // mantissa = (16+UInt(e:f:g:h))/16.
5763 if (Mantissa & 0x7ffff)
5766 if ((Mantissa & 0xf) != Mantissa)
5769 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5770 if (Exp < -3 || Exp > 4)
5772 Exp = ((Exp+3) & 0x7) ^ 4;
5774 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5777 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5778 APInt Imm = FPImm.bitcastToAPInt();
5779 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5780 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5781 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5783 // We can handle 4 bits of mantissa.
5784 // mantissa = (16+UInt(e:f:g:h))/16.
5785 if (Mantissa & 0xffffffffffffLL)
5788 if ((Mantissa & 0xf) != Mantissa)
5791 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5792 if (Exp < -3 || Exp > 4)
5794 Exp = ((Exp+3) & 0x7) ^ 4;
5796 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5799 bool ARM::isBitFieldInvertedMask(unsigned v) {
5800 if (v == 0xffffffff)
5802 // there can be 1's on either or both "outsides", all the "inside"
5804 unsigned int lsb = 0, msb = 31;
5805 while (v & (1 << msb)) --msb;
5806 while (v & (1 << lsb)) ++lsb;
5807 for (unsigned int i = lsb; i <= msb; ++i) {
5814 /// isFPImmLegal - Returns true if the target can instruction select the
5815 /// specified FP immediate natively. If false, the legalizer will
5816 /// materialize the FP immediate as a load from a constant pool.
5817 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5818 if (!Subtarget->hasVFP3())
5821 return ARM::getVFPf32Imm(Imm) != -1;
5823 return ARM::getVFPf64Imm(Imm) != -1;
5827 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5828 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5829 /// specified in the intrinsic calls.
5830 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5832 unsigned Intrinsic) const {
5833 switch (Intrinsic) {
5834 case Intrinsic::arm_neon_vld1:
5835 case Intrinsic::arm_neon_vld2:
5836 case Intrinsic::arm_neon_vld3:
5837 case Intrinsic::arm_neon_vld4:
5838 case Intrinsic::arm_neon_vld2lane:
5839 case Intrinsic::arm_neon_vld3lane:
5840 case Intrinsic::arm_neon_vld4lane: {
5841 Info.opc = ISD::INTRINSIC_W_CHAIN;
5842 // Conservatively set memVT to the entire set of vectors loaded.
5843 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5844 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5845 Info.ptrVal = I.getArgOperand(0);
5847 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5848 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5849 Info.vol = false; // volatile loads with NEON intrinsics not supported
5850 Info.readMem = true;
5851 Info.writeMem = false;
5854 case Intrinsic::arm_neon_vst1:
5855 case Intrinsic::arm_neon_vst2:
5856 case Intrinsic::arm_neon_vst3:
5857 case Intrinsic::arm_neon_vst4:
5858 case Intrinsic::arm_neon_vst2lane:
5859 case Intrinsic::arm_neon_vst3lane:
5860 case Intrinsic::arm_neon_vst4lane: {
5861 Info.opc = ISD::INTRINSIC_VOID;
5862 // Conservatively set memVT to the entire set of vectors stored.
5863 unsigned NumElts = 0;
5864 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5865 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5866 if (!ArgTy->isVectorTy())
5868 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5870 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5871 Info.ptrVal = I.getArgOperand(0);
5873 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5874 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5875 Info.vol = false; // volatile stores with NEON intrinsics not supported
5876 Info.readMem = false;
5877 Info.writeMem = true;