1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
76 class ARMCCState : public CCState {
78 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
79 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
80 LLVMContext &C, ParmContext PC)
81 : CCState(CC, isVarArg, MF, TM, locs, C) {
82 assert(((PC == Call) || (PC == Prologue)) &&
83 "ARMCCState users must specify whether their context is call"
84 "or prologue generation.");
90 // The APCS parameter registers.
91 static const unsigned GPRArgRegs[] = {
92 ARM::R0, ARM::R1, ARM::R2, ARM::R3
95 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
96 EVT PromotedBitwiseVT) {
97 if (VT != PromotedLdStVT) {
98 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
99 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
100 PromotedLdStVT.getSimpleVT());
102 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
103 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
104 PromotedLdStVT.getSimpleVT());
107 EVT ElemTy = VT.getVectorElementType();
108 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
109 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
111 if (ElemTy != MVT::i32) {
112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
117 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
118 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
120 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
121 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
122 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
123 if (VT.isInteger()) {
124 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
125 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
126 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
128 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
129 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
130 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
131 setTruncStoreAction(VT.getSimpleVT(),
132 (MVT::SimpleValueType)InnerVT, Expand);
134 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
136 // Promote all bit-wise operations.
137 if (VT.isInteger() && VT != PromotedBitwiseVT) {
138 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
139 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
140 PromotedBitwiseVT.getSimpleVT());
141 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
142 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
143 PromotedBitwiseVT.getSimpleVT());
144 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
145 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
146 PromotedBitwiseVT.getSimpleVT());
149 // Neon does not support vector divide/remainder operations.
150 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
151 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
158 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
159 addRegisterClass(VT, ARM::DPRRegisterClass);
160 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
163 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
164 addRegisterClass(VT, ARM::QPRRegisterClass);
165 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
168 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
169 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
170 return new TargetLoweringObjectFileMachO();
172 return new ARMElfTargetObjectFile();
175 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
176 : TargetLowering(TM, createTLOF(TM)) {
177 Subtarget = &TM.getSubtarget<ARMSubtarget>();
178 RegInfo = TM.getRegisterInfo();
179 Itins = TM.getInstrItineraryData();
181 if (Subtarget->isTargetDarwin()) {
182 // Uses VFP for Thumb libfuncs if available.
183 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
184 // Single-precision floating-point arithmetic.
185 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
186 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
187 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
188 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
190 // Double-precision floating-point arithmetic.
191 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
192 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
193 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
194 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
196 // Single-precision comparisons.
197 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
198 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
199 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
200 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
201 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
202 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
203 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
204 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
206 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
215 // Double-precision comparisons.
216 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
217 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
218 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
219 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
220 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
221 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
222 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
223 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
225 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
234 // Floating-point to integer conversions.
235 // i64 conversions are done via library routines even when generating VFP
236 // instructions, so use the same ones.
237 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
238 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
239 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
240 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
242 // Conversions between floating types.
243 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
244 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
246 // Integer to floating-point conversions.
247 // i64 conversions are done via library routines even when generating VFP
248 // instructions, so use the same ones.
249 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
250 // e.g., __floatunsidf vs. __floatunssidfvfp.
251 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
252 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
253 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
254 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
258 // These libcalls are not available in 32-bit.
259 setLibcallName(RTLIB::SHL_I128, 0);
260 setLibcallName(RTLIB::SRL_I128, 0);
261 setLibcallName(RTLIB::SRA_I128, 0);
263 if (Subtarget->isAAPCS_ABI()) {
264 // Double-precision floating-point arithmetic helper functions
265 // RTABI chapter 4.1.2, Table 2
266 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
267 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
268 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
269 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
270 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
275 // Double-precision floating-point comparison helper functions
276 // RTABI chapter 4.1.2, Table 3
277 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
278 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
279 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
280 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
281 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
282 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
283 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
284 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
285 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
286 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
287 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
288 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
289 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
290 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
291 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
292 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
293 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
302 // Single-precision floating-point arithmetic helper functions
303 // RTABI chapter 4.1.2, Table 4
304 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
305 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
306 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
307 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
308 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
313 // Single-precision floating-point comparison helper functions
314 // RTABI chapter 4.1.2, Table 5
315 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
316 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
317 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
318 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
319 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
320 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
321 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
322 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
323 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
324 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
325 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
326 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
327 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
328 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
329 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
330 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
331 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
340 // Floating-point to integer conversions.
341 // RTABI chapter 4.1.2, Table 6
342 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
343 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
344 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
345 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
346 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
347 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
348 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
349 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
350 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
359 // Conversions between floating types.
360 // RTABI chapter 4.1.2, Table 7
361 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
362 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
363 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
366 // Integer to floating-point conversions.
367 // RTABI chapter 4.1.2, Table 8
368 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
369 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
370 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
371 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
372 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
373 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
374 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
375 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
376 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
385 // Long long helper functions
386 // RTABI chapter 4.2, Table 9
387 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
388 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
389 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
390 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
391 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
392 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
393 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
400 // Integer division functions
401 // RTABI chapter 4.3.1
402 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
403 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
404 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
405 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
406 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
407 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
408 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
416 // RTABI chapter 4.3.4
417 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
418 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
419 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
422 if (Subtarget->isThumb1Only())
423 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
425 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
426 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
427 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
428 if (!Subtarget->isFPOnlySP())
429 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
431 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
434 if (Subtarget->hasNEON()) {
435 addDRTypeForNEON(MVT::v2f32);
436 addDRTypeForNEON(MVT::v8i8);
437 addDRTypeForNEON(MVT::v4i16);
438 addDRTypeForNEON(MVT::v2i32);
439 addDRTypeForNEON(MVT::v1i64);
441 addQRTypeForNEON(MVT::v4f32);
442 addQRTypeForNEON(MVT::v2f64);
443 addQRTypeForNEON(MVT::v16i8);
444 addQRTypeForNEON(MVT::v8i16);
445 addQRTypeForNEON(MVT::v4i32);
446 addQRTypeForNEON(MVT::v2i64);
448 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
449 // neither Neon nor VFP support any arithmetic operations on it.
450 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
451 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
452 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
453 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
454 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
455 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
456 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
457 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
458 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
459 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
460 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
461 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
462 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
463 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
464 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
465 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
466 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
467 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
468 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
469 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
470 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
471 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
472 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
473 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
475 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
477 // Neon does not support some operations on v1i64 and v2i64 types.
478 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
479 // Custom handling for some quad-vector types to detect VMULL.
480 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
481 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
482 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
483 // Custom handling for some vector types to avoid expensive expansions
484 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
485 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
486 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
487 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
488 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
489 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
490 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
491 // a destination type that is wider than the source.
492 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
493 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
495 setTargetDAGCombine(ISD::INTRINSIC_VOID);
496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
497 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
498 setTargetDAGCombine(ISD::SHL);
499 setTargetDAGCombine(ISD::SRL);
500 setTargetDAGCombine(ISD::SRA);
501 setTargetDAGCombine(ISD::SIGN_EXTEND);
502 setTargetDAGCombine(ISD::ZERO_EXTEND);
503 setTargetDAGCombine(ISD::ANY_EXTEND);
504 setTargetDAGCombine(ISD::SELECT_CC);
505 setTargetDAGCombine(ISD::BUILD_VECTOR);
506 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
507 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
508 setTargetDAGCombine(ISD::STORE);
511 computeRegisterProperties();
513 // ARM does not have f32 extending load.
514 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
516 // ARM does not have i1 sign extending load.
517 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
519 // ARM supports all 4 flavors of integer indexed load / store.
520 if (!Subtarget->isThumb1Only()) {
521 for (unsigned im = (unsigned)ISD::PRE_INC;
522 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
523 setIndexedLoadAction(im, MVT::i1, Legal);
524 setIndexedLoadAction(im, MVT::i8, Legal);
525 setIndexedLoadAction(im, MVT::i16, Legal);
526 setIndexedLoadAction(im, MVT::i32, Legal);
527 setIndexedStoreAction(im, MVT::i1, Legal);
528 setIndexedStoreAction(im, MVT::i8, Legal);
529 setIndexedStoreAction(im, MVT::i16, Legal);
530 setIndexedStoreAction(im, MVT::i32, Legal);
534 // i64 operation support.
535 setOperationAction(ISD::MUL, MVT::i64, Expand);
536 setOperationAction(ISD::MULHU, MVT::i32, Expand);
537 if (Subtarget->isThumb1Only()) {
538 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
539 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
541 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops())
542 setOperationAction(ISD::MULHS, MVT::i32, Expand);
544 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
545 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
546 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
547 setOperationAction(ISD::SRL, MVT::i64, Custom);
548 setOperationAction(ISD::SRA, MVT::i64, Custom);
550 // ARM does not have ROTL.
551 setOperationAction(ISD::ROTL, MVT::i32, Expand);
552 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
553 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
554 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
555 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
557 // Only ARMv6 has BSWAP.
558 if (!Subtarget->hasV6Ops())
559 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
561 // These are expanded into libcalls.
562 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
563 // v7M has a hardware divider
564 setOperationAction(ISD::SDIV, MVT::i32, Expand);
565 setOperationAction(ISD::UDIV, MVT::i32, Expand);
567 setOperationAction(ISD::SREM, MVT::i32, Expand);
568 setOperationAction(ISD::UREM, MVT::i32, Expand);
569 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
570 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
572 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
573 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
574 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
576 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
578 setOperationAction(ISD::TRAP, MVT::Other, Legal);
580 // Use the default implementation.
581 setOperationAction(ISD::VASTART, MVT::Other, Custom);
582 setOperationAction(ISD::VAARG, MVT::Other, Expand);
583 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
584 setOperationAction(ISD::VAEND, MVT::Other, Expand);
585 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
586 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
587 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
588 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
589 setExceptionPointerRegister(ARM::R0);
590 setExceptionSelectorRegister(ARM::R1);
592 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
593 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
594 // the default expansion.
595 if (Subtarget->hasDataBarrier() ||
596 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
597 // membarrier needs custom lowering; the rest are legal and handled
599 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
601 // Set them all for expansion, which will force libcalls.
602 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
603 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
604 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
605 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
606 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
607 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
608 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
609 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
611 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
612 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
613 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
616 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
623 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
624 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
625 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
626 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
627 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i8, Expand);
628 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i16, Expand);
629 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
630 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i8, Expand);
631 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i16, Expand);
632 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
633 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i8, Expand);
634 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i16, Expand);
635 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
636 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i8, Expand);
637 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i16, Expand);
638 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
639 // Since the libcalls include locking, fold in the fences
640 setShouldFoldAtomicFences(true);
642 // 64-bit versions are always libcalls (for now)
643 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
644 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
645 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
646 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
647 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
648 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
649 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
650 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
652 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
654 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
655 if (!Subtarget->hasV6Ops()) {
656 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
657 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
659 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
661 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
662 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
663 // iff target supports vfp2.
664 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
665 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
668 // We want to custom lower some of our intrinsics.
669 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
670 if (Subtarget->isTargetDarwin()) {
671 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
672 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
673 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
674 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
677 setOperationAction(ISD::SETCC, MVT::i32, Expand);
678 setOperationAction(ISD::SETCC, MVT::f32, Expand);
679 setOperationAction(ISD::SETCC, MVT::f64, Expand);
680 setOperationAction(ISD::SELECT, MVT::i32, Custom);
681 setOperationAction(ISD::SELECT, MVT::f32, Custom);
682 setOperationAction(ISD::SELECT, MVT::f64, Custom);
683 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
684 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
685 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
687 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
688 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
689 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
690 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
691 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
693 // We don't support sin/cos/fmod/copysign/pow
694 setOperationAction(ISD::FSIN, MVT::f64, Expand);
695 setOperationAction(ISD::FSIN, MVT::f32, Expand);
696 setOperationAction(ISD::FCOS, MVT::f32, Expand);
697 setOperationAction(ISD::FCOS, MVT::f64, Expand);
698 setOperationAction(ISD::FREM, MVT::f64, Expand);
699 setOperationAction(ISD::FREM, MVT::f32, Expand);
700 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 setOperationAction(ISD::FPOW, MVT::f64, Expand);
705 setOperationAction(ISD::FPOW, MVT::f32, Expand);
707 // Various VFP goodness
708 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
709 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
710 if (Subtarget->hasVFP2()) {
711 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
712 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
713 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
714 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
716 // Special handling for half-precision FP.
717 if (!Subtarget->hasFP16()) {
718 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
719 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
723 // We have target-specific dag combine patterns for the following nodes:
724 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
725 setTargetDAGCombine(ISD::ADD);
726 setTargetDAGCombine(ISD::SUB);
727 setTargetDAGCombine(ISD::MUL);
729 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
730 setTargetDAGCombine(ISD::OR);
731 if (Subtarget->hasNEON())
732 setTargetDAGCombine(ISD::AND);
734 setStackPointerRegisterToSaveRestore(ARM::SP);
736 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
737 setSchedulingPreference(Sched::RegPressure);
739 setSchedulingPreference(Sched::Hybrid);
741 //// temporary - rewrite interface to use type
742 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
744 // On ARM arguments smaller than 4 bytes are extended, so all arguments
745 // are at least 4 bytes aligned.
746 setMinStackArgumentAlignment(4);
748 benefitFromCodePlacementOpt = true;
750 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
753 // FIXME: It might make sense to define the representative register class as the
754 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
755 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
756 // SPR's representative would be DPR_VFP2. This should work well if register
757 // pressure tracking were modified such that a register use would increment the
758 // pressure of the register class's representative and all of it's super
759 // classes' representatives transitively. We have not implemented this because
760 // of the difficulty prior to coalescing of modeling operand register classes
761 // due to the common occurrence of cross class copies and subregister insertions
763 std::pair<const TargetRegisterClass*, uint8_t>
764 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
765 const TargetRegisterClass *RRC = 0;
767 switch (VT.getSimpleVT().SimpleTy) {
769 return TargetLowering::findRepresentativeClass(VT);
770 // Use DPR as representative register class for all floating point
771 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
772 // the cost is 1 for both f32 and f64.
773 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
774 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
775 RRC = ARM::DPRRegisterClass;
776 // When NEON is used for SP, only half of the register file is available
777 // because operations that define both SP and DP results will be constrained
778 // to the VFP2 class (D0-D15). We currently model this constraint prior to
779 // coalescing by double-counting the SP regs. See the FIXME above.
780 if (Subtarget->useNEONForSinglePrecisionFP())
783 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
784 case MVT::v4f32: case MVT::v2f64:
785 RRC = ARM::DPRRegisterClass;
789 RRC = ARM::DPRRegisterClass;
793 RRC = ARM::DPRRegisterClass;
797 return std::make_pair(RRC, Cost);
800 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
803 case ARMISD::Wrapper: return "ARMISD::Wrapper";
804 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
805 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
806 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
807 case ARMISD::CALL: return "ARMISD::CALL";
808 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
809 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
810 case ARMISD::tCALL: return "ARMISD::tCALL";
811 case ARMISD::BRCOND: return "ARMISD::BRCOND";
812 case ARMISD::BR_JT: return "ARMISD::BR_JT";
813 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
814 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
815 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
816 case ARMISD::CMP: return "ARMISD::CMP";
817 case ARMISD::CMPZ: return "ARMISD::CMPZ";
818 case ARMISD::CMPFP: return "ARMISD::CMPFP";
819 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
820 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
821 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
822 case ARMISD::CMOV: return "ARMISD::CMOV";
824 case ARMISD::RBIT: return "ARMISD::RBIT";
826 case ARMISD::FTOSI: return "ARMISD::FTOSI";
827 case ARMISD::FTOUI: return "ARMISD::FTOUI";
828 case ARMISD::SITOF: return "ARMISD::SITOF";
829 case ARMISD::UITOF: return "ARMISD::UITOF";
831 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
832 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
833 case ARMISD::RRX: return "ARMISD::RRX";
835 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
836 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
838 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
839 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
840 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
842 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
844 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
846 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
848 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
849 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
851 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
853 case ARMISD::VCEQ: return "ARMISD::VCEQ";
854 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
855 case ARMISD::VCGE: return "ARMISD::VCGE";
856 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
857 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
858 case ARMISD::VCGEU: return "ARMISD::VCGEU";
859 case ARMISD::VCGT: return "ARMISD::VCGT";
860 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
861 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
862 case ARMISD::VCGTU: return "ARMISD::VCGTU";
863 case ARMISD::VTST: return "ARMISD::VTST";
865 case ARMISD::VSHL: return "ARMISD::VSHL";
866 case ARMISD::VSHRs: return "ARMISD::VSHRs";
867 case ARMISD::VSHRu: return "ARMISD::VSHRu";
868 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
869 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
870 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
871 case ARMISD::VSHRN: return "ARMISD::VSHRN";
872 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
873 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
874 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
875 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
876 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
877 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
878 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
879 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
880 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
881 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
882 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
883 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
884 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
885 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
886 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
887 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
888 case ARMISD::VDUP: return "ARMISD::VDUP";
889 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
890 case ARMISD::VEXT: return "ARMISD::VEXT";
891 case ARMISD::VREV64: return "ARMISD::VREV64";
892 case ARMISD::VREV32: return "ARMISD::VREV32";
893 case ARMISD::VREV16: return "ARMISD::VREV16";
894 case ARMISD::VZIP: return "ARMISD::VZIP";
895 case ARMISD::VUZP: return "ARMISD::VUZP";
896 case ARMISD::VTRN: return "ARMISD::VTRN";
897 case ARMISD::VTBL1: return "ARMISD::VTBL1";
898 case ARMISD::VTBL2: return "ARMISD::VTBL2";
899 case ARMISD::VMULLs: return "ARMISD::VMULLs";
900 case ARMISD::VMULLu: return "ARMISD::VMULLu";
901 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
902 case ARMISD::FMAX: return "ARMISD::FMAX";
903 case ARMISD::FMIN: return "ARMISD::FMIN";
904 case ARMISD::BFI: return "ARMISD::BFI";
905 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
906 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
907 case ARMISD::VBSL: return "ARMISD::VBSL";
908 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
909 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
910 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
911 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
912 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
913 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
914 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
915 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
916 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
917 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
918 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
919 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
920 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
921 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
922 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
923 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
924 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
925 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
926 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
927 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
931 /// getRegClassFor - Return the register class that should be used for the
932 /// specified value type.
933 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
934 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
935 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
936 // load / store 4 to 8 consecutive D registers.
937 if (Subtarget->hasNEON()) {
938 if (VT == MVT::v4i64)
939 return ARM::QQPRRegisterClass;
940 else if (VT == MVT::v8i64)
941 return ARM::QQQQPRRegisterClass;
943 return TargetLowering::getRegClassFor(VT);
946 // Create a fast isel object.
948 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
949 return ARM::createFastISel(funcInfo);
952 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
953 /// be used for loads / stores from the global.
954 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
955 return (Subtarget->isThumb1Only() ? 127 : 4095);
958 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
959 unsigned NumVals = N->getNumValues();
961 return Sched::RegPressure;
963 for (unsigned i = 0; i != NumVals; ++i) {
964 EVT VT = N->getValueType(i);
965 if (VT == MVT::Glue || VT == MVT::Other)
967 if (VT.isFloatingPoint() || VT.isVector())
968 return Sched::Latency;
971 if (!N->isMachineOpcode())
972 return Sched::RegPressure;
974 // Load are scheduled for latency even if there instruction itinerary
976 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
977 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
979 if (TID.getNumDefs() == 0)
980 return Sched::RegPressure;
981 if (!Itins->isEmpty() &&
982 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
983 return Sched::Latency;
985 return Sched::RegPressure;
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
992 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
993 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
995 default: llvm_unreachable("Unknown condition code!");
996 case ISD::SETNE: return ARMCC::NE;
997 case ISD::SETEQ: return ARMCC::EQ;
998 case ISD::SETGT: return ARMCC::GT;
999 case ISD::SETGE: return ARMCC::GE;
1000 case ISD::SETLT: return ARMCC::LT;
1001 case ISD::SETLE: return ARMCC::LE;
1002 case ISD::SETUGT: return ARMCC::HI;
1003 case ISD::SETUGE: return ARMCC::HS;
1004 case ISD::SETULT: return ARMCC::LO;
1005 case ISD::SETULE: return ARMCC::LS;
1009 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1010 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1011 ARMCC::CondCodes &CondCode2) {
1012 CondCode2 = ARMCC::AL;
1014 default: llvm_unreachable("Unknown FP condition!");
1016 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1018 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1020 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1021 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1022 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1023 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1024 case ISD::SETO: CondCode = ARMCC::VC; break;
1025 case ISD::SETUO: CondCode = ARMCC::VS; break;
1026 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1027 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1028 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1030 case ISD::SETULT: CondCode = ARMCC::LT; break;
1032 case ISD::SETULE: CondCode = ARMCC::LE; break;
1034 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1038 //===----------------------------------------------------------------------===//
1039 // Calling Convention Implementation
1040 //===----------------------------------------------------------------------===//
1042 #include "ARMGenCallingConv.inc"
1044 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1045 /// given CallingConvention value.
1046 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1048 bool isVarArg) const {
1051 llvm_unreachable("Unsupported calling convention");
1052 case CallingConv::Fast:
1053 if (Subtarget->hasVFP2() && !isVarArg) {
1054 if (!Subtarget->isAAPCS_ABI())
1055 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1056 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1057 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1060 case CallingConv::C: {
1061 // Use target triple & subtarget features to do actual dispatch.
1062 if (!Subtarget->isAAPCS_ABI())
1063 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1064 else if (Subtarget->hasVFP2() &&
1065 FloatABIType == FloatABI::Hard && !isVarArg)
1066 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1067 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1069 case CallingConv::ARM_AAPCS_VFP:
1070 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1071 case CallingConv::ARM_AAPCS:
1072 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1073 case CallingConv::ARM_APCS:
1074 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1078 /// LowerCallResult - Lower the result values of a call into the
1079 /// appropriate copies out of appropriate physical registers.
1081 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1082 CallingConv::ID CallConv, bool isVarArg,
1083 const SmallVectorImpl<ISD::InputArg> &Ins,
1084 DebugLoc dl, SelectionDAG &DAG,
1085 SmallVectorImpl<SDValue> &InVals) const {
1087 // Assign locations to each value returned by this call.
1088 SmallVector<CCValAssign, 16> RVLocs;
1089 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1090 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1091 CCInfo.AnalyzeCallResult(Ins,
1092 CCAssignFnForNode(CallConv, /* Return*/ true,
1095 // Copy all of the result registers out of their specified physreg.
1096 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1097 CCValAssign VA = RVLocs[i];
1100 if (VA.needsCustom()) {
1101 // Handle f64 or half of a v2f64.
1102 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1104 Chain = Lo.getValue(1);
1105 InFlag = Lo.getValue(2);
1106 VA = RVLocs[++i]; // skip ahead to next loc
1107 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1109 Chain = Hi.getValue(1);
1110 InFlag = Hi.getValue(2);
1111 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1113 if (VA.getLocVT() == MVT::v2f64) {
1114 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1115 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1116 DAG.getConstant(0, MVT::i32));
1118 VA = RVLocs[++i]; // skip ahead to next loc
1119 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1120 Chain = Lo.getValue(1);
1121 InFlag = Lo.getValue(2);
1122 VA = RVLocs[++i]; // skip ahead to next loc
1123 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1124 Chain = Hi.getValue(1);
1125 InFlag = Hi.getValue(2);
1126 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1127 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1128 DAG.getConstant(1, MVT::i32));
1131 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1133 Chain = Val.getValue(1);
1134 InFlag = Val.getValue(2);
1137 switch (VA.getLocInfo()) {
1138 default: llvm_unreachable("Unknown loc info!");
1139 case CCValAssign::Full: break;
1140 case CCValAssign::BCvt:
1141 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1145 InVals.push_back(Val);
1151 /// LowerMemOpCallTo - Store the argument to the stack.
1153 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1154 SDValue StackPtr, SDValue Arg,
1155 DebugLoc dl, SelectionDAG &DAG,
1156 const CCValAssign &VA,
1157 ISD::ArgFlagsTy Flags) const {
1158 unsigned LocMemOffset = VA.getLocMemOffset();
1159 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1160 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1161 return DAG.getStore(Chain, dl, Arg, PtrOff,
1162 MachinePointerInfo::getStack(LocMemOffset),
1166 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1167 SDValue Chain, SDValue &Arg,
1168 RegsToPassVector &RegsToPass,
1169 CCValAssign &VA, CCValAssign &NextVA,
1171 SmallVector<SDValue, 8> &MemOpChains,
1172 ISD::ArgFlagsTy Flags) const {
1174 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1175 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1176 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1178 if (NextVA.isRegLoc())
1179 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1181 assert(NextVA.isMemLoc());
1182 if (StackPtr.getNode() == 0)
1183 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1185 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1191 /// LowerCall - Lowering a call into a callseq_start <-
1192 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1195 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1196 CallingConv::ID CallConv, bool isVarArg,
1198 const SmallVectorImpl<ISD::OutputArg> &Outs,
1199 const SmallVectorImpl<SDValue> &OutVals,
1200 const SmallVectorImpl<ISD::InputArg> &Ins,
1201 DebugLoc dl, SelectionDAG &DAG,
1202 SmallVectorImpl<SDValue> &InVals) const {
1203 MachineFunction &MF = DAG.getMachineFunction();
1204 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1205 bool IsSibCall = false;
1206 // Temporarily disable tail calls so things don't break.
1207 if (!EnableARMTailCalls)
1210 // Check if it's really possible to do a tail call.
1211 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1212 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1213 Outs, OutVals, Ins, DAG);
1214 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1215 // detected sibcalls.
1222 // Analyze operands of the call, assigning locations to each operand.
1223 SmallVector<CCValAssign, 16> ArgLocs;
1224 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1225 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1226 CCInfo.AnalyzeCallOperands(Outs,
1227 CCAssignFnForNode(CallConv, /* Return*/ false,
1230 // Get a count of how many bytes are to be pushed on the stack.
1231 unsigned NumBytes = CCInfo.getNextStackOffset();
1233 // For tail calls, memory operands are available in our caller's stack.
1237 // Adjust the stack pointer for the new arguments...
1238 // These operations are automatically eliminated by the prolog/epilog pass
1240 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1242 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1244 RegsToPassVector RegsToPass;
1245 SmallVector<SDValue, 8> MemOpChains;
1247 // Walk the register/memloc assignments, inserting copies/loads. In the case
1248 // of tail call optimization, arguments are handled later.
1249 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1251 ++i, ++realArgIdx) {
1252 CCValAssign &VA = ArgLocs[i];
1253 SDValue Arg = OutVals[realArgIdx];
1254 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1255 bool isByVal = Flags.isByVal();
1257 // Promote the value if needed.
1258 switch (VA.getLocInfo()) {
1259 default: llvm_unreachable("Unknown loc info!");
1260 case CCValAssign::Full: break;
1261 case CCValAssign::SExt:
1262 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1264 case CCValAssign::ZExt:
1265 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1267 case CCValAssign::AExt:
1268 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1270 case CCValAssign::BCvt:
1271 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1275 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1276 if (VA.needsCustom()) {
1277 if (VA.getLocVT() == MVT::v2f64) {
1278 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1279 DAG.getConstant(0, MVT::i32));
1280 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1281 DAG.getConstant(1, MVT::i32));
1283 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1284 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1286 VA = ArgLocs[++i]; // skip ahead to next loc
1287 if (VA.isRegLoc()) {
1288 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1289 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1291 assert(VA.isMemLoc());
1293 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1294 dl, DAG, VA, Flags));
1297 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1298 StackPtr, MemOpChains, Flags);
1300 } else if (VA.isRegLoc()) {
1301 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1302 } else if (isByVal) {
1303 assert(VA.isMemLoc());
1304 unsigned offset = 0;
1306 // True if this byval aggregate will be split between registers
1308 if (CCInfo.isFirstByValRegValid()) {
1309 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1311 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1312 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1313 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1314 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1315 MachinePointerInfo(),
1317 MemOpChains.push_back(Load.getValue(1));
1318 RegsToPass.push_back(std::make_pair(j, Load));
1320 offset = ARM::R4 - CCInfo.getFirstByValReg();
1321 CCInfo.clearFirstByValReg();
1324 unsigned LocMemOffset = VA.getLocMemOffset();
1325 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1326 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1328 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1329 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1330 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1332 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1333 Flags.getByValAlign(),
1334 /*isVolatile=*/false,
1335 /*AlwaysInline=*/false,
1336 MachinePointerInfo(0),
1337 MachinePointerInfo(0)));
1339 } else if (!IsSibCall) {
1340 assert(VA.isMemLoc());
1342 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1343 dl, DAG, VA, Flags));
1347 if (!MemOpChains.empty())
1348 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1349 &MemOpChains[0], MemOpChains.size());
1351 // Build a sequence of copy-to-reg nodes chained together with token chain
1352 // and flag operands which copy the outgoing args into the appropriate regs.
1354 // Tail call byval lowering might overwrite argument registers so in case of
1355 // tail call optimization the copies to registers are lowered later.
1357 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1358 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1359 RegsToPass[i].second, InFlag);
1360 InFlag = Chain.getValue(1);
1363 // For tail calls lower the arguments to the 'real' stack slot.
1365 // Force all the incoming stack arguments to be loaded from the stack
1366 // before any new outgoing arguments are stored to the stack, because the
1367 // outgoing stack slots may alias the incoming argument stack slots, and
1368 // the alias isn't otherwise explicit. This is slightly more conservative
1369 // than necessary, because it means that each store effectively depends
1370 // on every argument instead of just those arguments it would clobber.
1372 // Do not flag preceding copytoreg stuff together with the following stuff.
1374 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1375 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1376 RegsToPass[i].second, InFlag);
1377 InFlag = Chain.getValue(1);
1382 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1383 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1384 // node so that legalize doesn't hack it.
1385 bool isDirect = false;
1386 bool isARMFunc = false;
1387 bool isLocalARMFunc = false;
1388 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1390 if (EnableARMLongCalls) {
1391 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1392 && "long-calls with non-static relocation model!");
1393 // Handle a global address or an external symbol. If it's not one of
1394 // those, the target's already in a register, so we don't need to do
1396 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1397 const GlobalValue *GV = G->getGlobal();
1398 // Create a constant pool entry for the callee address
1399 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1400 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1403 // Get the address of the callee into a register
1404 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1405 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1406 Callee = DAG.getLoad(getPointerTy(), dl,
1407 DAG.getEntryNode(), CPAddr,
1408 MachinePointerInfo::getConstantPool(),
1410 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1411 const char *Sym = S->getSymbol();
1413 // Create a constant pool entry for the callee address
1414 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1415 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1416 Sym, ARMPCLabelIndex, 0);
1417 // Get the address of the callee into a register
1418 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1419 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1420 Callee = DAG.getLoad(getPointerTy(), dl,
1421 DAG.getEntryNode(), CPAddr,
1422 MachinePointerInfo::getConstantPool(),
1425 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1426 const GlobalValue *GV = G->getGlobal();
1428 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1429 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1430 getTargetMachine().getRelocationModel() != Reloc::Static;
1431 isARMFunc = !Subtarget->isThumb() || isStub;
1432 // ARM call to a local ARM function is predicable.
1433 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1434 // tBX takes a register source operand.
1435 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1436 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1437 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1440 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1441 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1442 Callee = DAG.getLoad(getPointerTy(), dl,
1443 DAG.getEntryNode(), CPAddr,
1444 MachinePointerInfo::getConstantPool(),
1446 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1447 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1448 getPointerTy(), Callee, PICLabel);
1450 // On ELF targets for PIC code, direct calls should go through the PLT
1451 unsigned OpFlags = 0;
1452 if (Subtarget->isTargetELF() &&
1453 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1454 OpFlags = ARMII::MO_PLT;
1455 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1457 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1459 bool isStub = Subtarget->isTargetDarwin() &&
1460 getTargetMachine().getRelocationModel() != Reloc::Static;
1461 isARMFunc = !Subtarget->isThumb() || isStub;
1462 // tBX takes a register source operand.
1463 const char *Sym = S->getSymbol();
1464 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1465 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1466 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1467 Sym, ARMPCLabelIndex, 4);
1468 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1469 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1470 Callee = DAG.getLoad(getPointerTy(), dl,
1471 DAG.getEntryNode(), CPAddr,
1472 MachinePointerInfo::getConstantPool(),
1474 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1475 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1476 getPointerTy(), Callee, PICLabel);
1478 unsigned OpFlags = 0;
1479 // On ELF targets for PIC code, direct calls should go through the PLT
1480 if (Subtarget->isTargetELF() &&
1481 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1482 OpFlags = ARMII::MO_PLT;
1483 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1487 // FIXME: handle tail calls differently.
1489 if (Subtarget->isThumb()) {
1490 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1491 CallOpc = ARMISD::CALL_NOLINK;
1493 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1495 CallOpc = (isDirect || Subtarget->hasV5TOps())
1496 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1497 : ARMISD::CALL_NOLINK;
1500 std::vector<SDValue> Ops;
1501 Ops.push_back(Chain);
1502 Ops.push_back(Callee);
1504 // Add argument registers to the end of the list so that they are known live
1506 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1507 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1508 RegsToPass[i].second.getValueType()));
1510 if (InFlag.getNode())
1511 Ops.push_back(InFlag);
1513 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1515 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1517 // Returns a chain and a flag for retval copy to use.
1518 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1519 InFlag = Chain.getValue(1);
1521 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1522 DAG.getIntPtrConstant(0, true), InFlag);
1524 InFlag = Chain.getValue(1);
1526 // Handle result values, copying them out of physregs into vregs that we
1528 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1532 /// HandleByVal - Every parameter *after* a byval parameter is passed
1533 /// on the stack. Remember the next parameter register to allocate,
1534 /// and then confiscate the rest of the parameter registers to insure
1537 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1538 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1539 assert((State->getCallOrPrologue() == Prologue ||
1540 State->getCallOrPrologue() == Call) &&
1541 "unhandled ParmContext");
1542 if ((!State->isFirstByValRegValid()) &&
1543 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1544 State->setFirstByValReg(reg);
1545 // At a call site, a byval parameter that is split between
1546 // registers and memory needs its size truncated here. In a
1547 // function prologue, such byval parameters are reassembled in
1548 // memory, and are not truncated.
1549 if (State->getCallOrPrologue() == Call) {
1550 unsigned excess = 4 * (ARM::R4 - reg);
1551 assert(size >= excess && "expected larger existing stack allocation");
1555 // Confiscate any remaining parameter registers to preclude their
1556 // assignment to subsequent parameters.
1557 while (State->AllocateReg(GPRArgRegs, 4))
1561 /// MatchingStackOffset - Return true if the given stack call argument is
1562 /// already available in the same position (relatively) of the caller's
1563 /// incoming argument stack.
1565 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1566 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1567 const ARMInstrInfo *TII) {
1568 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1570 if (Arg.getOpcode() == ISD::CopyFromReg) {
1571 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1572 if (!TargetRegisterInfo::isVirtualRegister(VR))
1574 MachineInstr *Def = MRI->getVRegDef(VR);
1577 if (!Flags.isByVal()) {
1578 if (!TII->isLoadFromStackSlot(Def, FI))
1583 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1584 if (Flags.isByVal())
1585 // ByVal argument is passed in as a pointer but it's now being
1586 // dereferenced. e.g.
1587 // define @foo(%struct.X* %A) {
1588 // tail call @bar(%struct.X* byval %A)
1591 SDValue Ptr = Ld->getBasePtr();
1592 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1595 FI = FINode->getIndex();
1599 assert(FI != INT_MAX);
1600 if (!MFI->isFixedObjectIndex(FI))
1602 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1605 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1606 /// for tail call optimization. Targets which want to do tail call
1607 /// optimization should implement this function.
1609 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1610 CallingConv::ID CalleeCC,
1612 bool isCalleeStructRet,
1613 bool isCallerStructRet,
1614 const SmallVectorImpl<ISD::OutputArg> &Outs,
1615 const SmallVectorImpl<SDValue> &OutVals,
1616 const SmallVectorImpl<ISD::InputArg> &Ins,
1617 SelectionDAG& DAG) const {
1618 const Function *CallerF = DAG.getMachineFunction().getFunction();
1619 CallingConv::ID CallerCC = CallerF->getCallingConv();
1620 bool CCMatch = CallerCC == CalleeCC;
1622 // Look for obvious safe cases to perform tail call optimization that do not
1623 // require ABI changes. This is what gcc calls sibcall.
1625 // Do not sibcall optimize vararg calls unless the call site is not passing
1627 if (isVarArg && !Outs.empty())
1630 // Also avoid sibcall optimization if either caller or callee uses struct
1631 // return semantics.
1632 if (isCalleeStructRet || isCallerStructRet)
1635 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1636 // emitEpilogue is not ready for them.
1637 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1638 // LR. This means if we need to reload LR, it takes an extra instructions,
1639 // which outweighs the value of the tail call; but here we don't know yet
1640 // whether LR is going to be used. Probably the right approach is to
1641 // generate the tail call here and turn it back into CALL/RET in
1642 // emitEpilogue if LR is used.
1644 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1645 // but we need to make sure there are enough registers; the only valid
1646 // registers are the 4 used for parameters. We don't currently do this
1648 if (Subtarget->isThumb1Only())
1651 // If the calling conventions do not match, then we'd better make sure the
1652 // results are returned in the same way as what the caller expects.
1654 SmallVector<CCValAssign, 16> RVLocs1;
1655 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1656 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1657 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1659 SmallVector<CCValAssign, 16> RVLocs2;
1660 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1661 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1662 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1664 if (RVLocs1.size() != RVLocs2.size())
1666 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1667 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1669 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1671 if (RVLocs1[i].isRegLoc()) {
1672 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1675 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1681 // If the callee takes no arguments then go on to check the results of the
1683 if (!Outs.empty()) {
1684 // Check if stack adjustment is needed. For now, do not do this if any
1685 // argument is passed on the stack.
1686 SmallVector<CCValAssign, 16> ArgLocs;
1687 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1688 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1689 CCInfo.AnalyzeCallOperands(Outs,
1690 CCAssignFnForNode(CalleeCC, false, isVarArg));
1691 if (CCInfo.getNextStackOffset()) {
1692 MachineFunction &MF = DAG.getMachineFunction();
1694 // Check if the arguments are already laid out in the right way as
1695 // the caller's fixed stack objects.
1696 MachineFrameInfo *MFI = MF.getFrameInfo();
1697 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1698 const ARMInstrInfo *TII =
1699 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1700 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1702 ++i, ++realArgIdx) {
1703 CCValAssign &VA = ArgLocs[i];
1704 EVT RegVT = VA.getLocVT();
1705 SDValue Arg = OutVals[realArgIdx];
1706 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1707 if (VA.getLocInfo() == CCValAssign::Indirect)
1709 if (VA.needsCustom()) {
1710 // f64 and vector types are split into multiple registers or
1711 // register/stack-slot combinations. The types will not match
1712 // the registers; give up on memory f64 refs until we figure
1713 // out what to do about this.
1716 if (!ArgLocs[++i].isRegLoc())
1718 if (RegVT == MVT::v2f64) {
1719 if (!ArgLocs[++i].isRegLoc())
1721 if (!ArgLocs[++i].isRegLoc())
1724 } else if (!VA.isRegLoc()) {
1725 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1737 ARMTargetLowering::LowerReturn(SDValue Chain,
1738 CallingConv::ID CallConv, bool isVarArg,
1739 const SmallVectorImpl<ISD::OutputArg> &Outs,
1740 const SmallVectorImpl<SDValue> &OutVals,
1741 DebugLoc dl, SelectionDAG &DAG) const {
1743 // CCValAssign - represent the assignment of the return value to a location.
1744 SmallVector<CCValAssign, 16> RVLocs;
1746 // CCState - Info about the registers and stack slots.
1747 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1748 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1750 // Analyze outgoing return values.
1751 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1754 // If this is the first return lowered for this function, add
1755 // the regs to the liveout set for the function.
1756 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1757 for (unsigned i = 0; i != RVLocs.size(); ++i)
1758 if (RVLocs[i].isRegLoc())
1759 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1764 // Copy the result values into the output registers.
1765 for (unsigned i = 0, realRVLocIdx = 0;
1767 ++i, ++realRVLocIdx) {
1768 CCValAssign &VA = RVLocs[i];
1769 assert(VA.isRegLoc() && "Can only return in registers!");
1771 SDValue Arg = OutVals[realRVLocIdx];
1773 switch (VA.getLocInfo()) {
1774 default: llvm_unreachable("Unknown loc info!");
1775 case CCValAssign::Full: break;
1776 case CCValAssign::BCvt:
1777 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1781 if (VA.needsCustom()) {
1782 if (VA.getLocVT() == MVT::v2f64) {
1783 // Extract the first half and return it in two registers.
1784 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1785 DAG.getConstant(0, MVT::i32));
1786 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1787 DAG.getVTList(MVT::i32, MVT::i32), Half);
1789 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1790 Flag = Chain.getValue(1);
1791 VA = RVLocs[++i]; // skip ahead to next loc
1792 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1793 HalfGPRs.getValue(1), Flag);
1794 Flag = Chain.getValue(1);
1795 VA = RVLocs[++i]; // skip ahead to next loc
1797 // Extract the 2nd half and fall through to handle it as an f64 value.
1798 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1799 DAG.getConstant(1, MVT::i32));
1801 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1803 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1804 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1805 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1806 Flag = Chain.getValue(1);
1807 VA = RVLocs[++i]; // skip ahead to next loc
1808 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1811 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1813 // Guarantee that all emitted copies are
1814 // stuck together, avoiding something bad.
1815 Flag = Chain.getValue(1);
1820 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1822 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1827 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1828 if (N->getNumValues() != 1)
1830 if (!N->hasNUsesOfValue(1, 0))
1833 unsigned NumCopies = 0;
1835 SDNode *Use = *N->use_begin();
1836 if (Use->getOpcode() == ISD::CopyToReg) {
1837 Copies[NumCopies++] = Use;
1838 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1839 // f64 returned in a pair of GPRs.
1840 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1842 if (UI->getOpcode() != ISD::CopyToReg)
1844 Copies[UI.getUse().getResNo()] = *UI;
1847 } else if (Use->getOpcode() == ISD::BITCAST) {
1848 // f32 returned in a single GPR.
1849 if (!Use->hasNUsesOfValue(1, 0))
1851 Use = *Use->use_begin();
1852 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1854 Copies[NumCopies++] = Use;
1859 if (NumCopies != 1 && NumCopies != 2)
1862 bool HasRet = false;
1863 for (unsigned i = 0; i < NumCopies; ++i) {
1864 SDNode *Copy = Copies[i];
1865 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1867 if (UI->getOpcode() == ISD::CopyToReg) {
1869 if (Use == Copies[0] || Use == Copies[1])
1873 if (UI->getOpcode() != ARMISD::RET_FLAG)
1882 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1883 if (!EnableARMTailCalls)
1886 if (!CI->isTailCall())
1889 return !Subtarget->isThumb1Only();
1892 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1893 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1894 // one of the above mentioned nodes. It has to be wrapped because otherwise
1895 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1896 // be used to form addressing mode. These wrapped nodes will be selected
1898 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1899 EVT PtrVT = Op.getValueType();
1900 // FIXME there is no actual debug info here
1901 DebugLoc dl = Op.getDebugLoc();
1902 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1904 if (CP->isMachineConstantPoolEntry())
1905 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1906 CP->getAlignment());
1908 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1909 CP->getAlignment());
1910 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1913 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1914 return MachineJumpTableInfo::EK_Inline;
1917 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1918 SelectionDAG &DAG) const {
1919 MachineFunction &MF = DAG.getMachineFunction();
1920 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1921 unsigned ARMPCLabelIndex = 0;
1922 DebugLoc DL = Op.getDebugLoc();
1923 EVT PtrVT = getPointerTy();
1924 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1925 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1927 if (RelocM == Reloc::Static) {
1928 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1930 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1931 ARMPCLabelIndex = AFI->createPICLabelUId();
1932 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1933 ARMCP::CPBlockAddress,
1935 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1937 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1938 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1939 MachinePointerInfo::getConstantPool(),
1941 if (RelocM == Reloc::Static)
1943 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1944 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1947 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1949 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1950 SelectionDAG &DAG) const {
1951 DebugLoc dl = GA->getDebugLoc();
1952 EVT PtrVT = getPointerTy();
1953 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1954 MachineFunction &MF = DAG.getMachineFunction();
1955 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1956 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1957 ARMConstantPoolValue *CPV =
1958 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1959 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1960 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1961 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1962 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1963 MachinePointerInfo::getConstantPool(),
1965 SDValue Chain = Argument.getValue(1);
1967 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1968 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1970 // call __tls_get_addr.
1973 Entry.Node = Argument;
1974 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1975 Args.push_back(Entry);
1976 // FIXME: is there useful debug info available here?
1977 std::pair<SDValue, SDValue> CallResult =
1978 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1979 false, false, false, false,
1980 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1981 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1982 return CallResult.first;
1985 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1986 // "local exec" model.
1988 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1989 SelectionDAG &DAG) const {
1990 const GlobalValue *GV = GA->getGlobal();
1991 DebugLoc dl = GA->getDebugLoc();
1993 SDValue Chain = DAG.getEntryNode();
1994 EVT PtrVT = getPointerTy();
1995 // Get the Thread Pointer
1996 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1998 if (GV->isDeclaration()) {
1999 MachineFunction &MF = DAG.getMachineFunction();
2000 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2001 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2002 // Initial exec model.
2003 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2004 ARMConstantPoolValue *CPV =
2005 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
2006 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
2007 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2008 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2009 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2010 MachinePointerInfo::getConstantPool(),
2012 Chain = Offset.getValue(1);
2014 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2015 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2017 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2018 MachinePointerInfo::getConstantPool(),
2022 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
2023 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2024 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2025 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2026 MachinePointerInfo::getConstantPool(),
2030 // The address of the thread local variable is the add of the thread
2031 // pointer with the offset of the variable.
2032 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2036 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2037 // TODO: implement the "local dynamic" model
2038 assert(Subtarget->isTargetELF() &&
2039 "TLS not implemented for non-ELF targets");
2040 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2041 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2042 // otherwise use the "Local Exec" TLS Model
2043 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2044 return LowerToTLSGeneralDynamicModel(GA, DAG);
2046 return LowerToTLSExecModels(GA, DAG);
2049 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2050 SelectionDAG &DAG) const {
2051 EVT PtrVT = getPointerTy();
2052 DebugLoc dl = Op.getDebugLoc();
2053 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2054 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2055 if (RelocM == Reloc::PIC_) {
2056 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2057 ARMConstantPoolValue *CPV =
2058 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2059 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2060 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2061 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2063 MachinePointerInfo::getConstantPool(),
2065 SDValue Chain = Result.getValue(1);
2066 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2067 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2069 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2070 MachinePointerInfo::getGOT(), false, false, 0);
2074 // If we have T2 ops, we can materialize the address directly via movt/movw
2075 // pair. This is always cheaper.
2076 if (Subtarget->useMovt()) {
2078 // FIXME: Once remat is capable of dealing with instructions with register
2079 // operands, expand this into two nodes.
2080 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2081 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2083 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2084 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2085 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2086 MachinePointerInfo::getConstantPool(),
2091 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2092 SelectionDAG &DAG) const {
2093 EVT PtrVT = getPointerTy();
2094 DebugLoc dl = Op.getDebugLoc();
2095 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2096 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2097 MachineFunction &MF = DAG.getMachineFunction();
2098 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2100 // FIXME: Enable this for static codegen when tool issues are fixed.
2101 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2103 // FIXME: Once remat is capable of dealing with instructions with register
2104 // operands, expand this into two nodes.
2105 if (RelocM == Reloc::Static)
2106 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2107 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2109 unsigned Wrapper = (RelocM == Reloc::PIC_)
2110 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2111 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2112 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2113 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2114 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2115 MachinePointerInfo::getGOT(), false, false, 0);
2119 unsigned ARMPCLabelIndex = 0;
2121 if (RelocM == Reloc::Static) {
2122 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2124 ARMPCLabelIndex = AFI->createPICLabelUId();
2125 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2126 ARMConstantPoolValue *CPV =
2127 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2128 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2130 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2132 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2133 MachinePointerInfo::getConstantPool(),
2135 SDValue Chain = Result.getValue(1);
2137 if (RelocM == Reloc::PIC_) {
2138 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2139 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2142 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2143 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2149 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2150 SelectionDAG &DAG) const {
2151 assert(Subtarget->isTargetELF() &&
2152 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2153 MachineFunction &MF = DAG.getMachineFunction();
2154 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2155 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2156 EVT PtrVT = getPointerTy();
2157 DebugLoc dl = Op.getDebugLoc();
2158 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2159 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2160 "_GLOBAL_OFFSET_TABLE_",
2161 ARMPCLabelIndex, PCAdj);
2162 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2163 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2164 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2165 MachinePointerInfo::getConstantPool(),
2167 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2168 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2172 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2174 DebugLoc dl = Op.getDebugLoc();
2175 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2176 Op.getOperand(0), Op.getOperand(1));
2180 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2181 DebugLoc dl = Op.getDebugLoc();
2182 SDValue Val = DAG.getConstant(0, MVT::i32);
2183 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2184 Op.getOperand(1), Val);
2188 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2189 DebugLoc dl = Op.getDebugLoc();
2190 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2191 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2195 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2196 const ARMSubtarget *Subtarget) const {
2197 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2198 DebugLoc dl = Op.getDebugLoc();
2200 default: return SDValue(); // Don't custom lower most intrinsics.
2201 case Intrinsic::arm_thread_pointer: {
2202 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2203 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2205 case Intrinsic::eh_sjlj_lsda: {
2206 MachineFunction &MF = DAG.getMachineFunction();
2207 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2208 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2209 EVT PtrVT = getPointerTy();
2210 DebugLoc dl = Op.getDebugLoc();
2211 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2213 unsigned PCAdj = (RelocM != Reloc::PIC_)
2214 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2215 ARMConstantPoolValue *CPV =
2216 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2217 ARMCP::CPLSDA, PCAdj);
2218 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2219 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2221 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2222 MachinePointerInfo::getConstantPool(),
2225 if (RelocM == Reloc::PIC_) {
2226 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2227 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2231 case Intrinsic::arm_neon_vmulls:
2232 case Intrinsic::arm_neon_vmullu: {
2233 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2234 ? ARMISD::VMULLs : ARMISD::VMULLu;
2235 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2236 Op.getOperand(1), Op.getOperand(2));
2241 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2242 const ARMSubtarget *Subtarget) {
2243 DebugLoc dl = Op.getDebugLoc();
2244 if (!Subtarget->hasDataBarrier()) {
2245 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2246 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2248 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2249 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2250 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2251 DAG.getConstant(0, MVT::i32));
2254 SDValue Op5 = Op.getOperand(5);
2255 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2256 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2257 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2258 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2260 ARM_MB::MemBOpt DMBOpt;
2261 if (isDeviceBarrier)
2262 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2264 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2265 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2266 DAG.getConstant(DMBOpt, MVT::i32));
2269 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2270 const ARMSubtarget *Subtarget) {
2271 // ARM pre v5TE and Thumb1 does not have preload instructions.
2272 if (!(Subtarget->isThumb2() ||
2273 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2274 // Just preserve the chain.
2275 return Op.getOperand(0);
2277 DebugLoc dl = Op.getDebugLoc();
2278 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2280 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2281 // ARMv7 with MP extension has PLDW.
2282 return Op.getOperand(0);
2284 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2285 if (Subtarget->isThumb()) {
2287 isRead = ~isRead & 1;
2288 isData = ~isData & 1;
2291 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2292 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2293 DAG.getConstant(isData, MVT::i32));
2296 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2297 MachineFunction &MF = DAG.getMachineFunction();
2298 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2300 // vastart just stores the address of the VarArgsFrameIndex slot into the
2301 // memory location argument.
2302 DebugLoc dl = Op.getDebugLoc();
2303 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2304 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2305 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2306 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2307 MachinePointerInfo(SV), false, false, 0);
2311 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2312 SDValue &Root, SelectionDAG &DAG,
2313 DebugLoc dl) const {
2314 MachineFunction &MF = DAG.getMachineFunction();
2315 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2317 TargetRegisterClass *RC;
2318 if (AFI->isThumb1OnlyFunction())
2319 RC = ARM::tGPRRegisterClass;
2321 RC = ARM::GPRRegisterClass;
2323 // Transform the arguments stored in physical registers into virtual ones.
2324 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2325 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2328 if (NextVA.isMemLoc()) {
2329 MachineFrameInfo *MFI = MF.getFrameInfo();
2330 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2332 // Create load node to retrieve arguments from the stack.
2333 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2334 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2335 MachinePointerInfo::getFixedStack(FI),
2338 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2339 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2342 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2346 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2347 unsigned &VARegSize, unsigned &VARegSaveSize)
2350 if (CCInfo.isFirstByValRegValid())
2351 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2353 unsigned int firstUnalloced;
2354 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2355 sizeof(GPRArgRegs) /
2356 sizeof(GPRArgRegs[0]));
2357 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2360 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2361 VARegSize = NumGPRs * 4;
2362 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2365 // The remaining GPRs hold either the beginning of variable-argument
2366 // data, or the beginning of an aggregate passed by value (usuall
2367 // byval). Either way, we allocate stack slots adjacent to the data
2368 // provided by our caller, and store the unallocated registers there.
2369 // If this is a variadic function, the va_list pointer will begin with
2370 // these values; otherwise, this reassembles a (byval) structure that
2371 // was split between registers and memory.
2373 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2374 DebugLoc dl, SDValue &Chain,
2375 unsigned ArgOffset) const {
2376 MachineFunction &MF = DAG.getMachineFunction();
2377 MachineFrameInfo *MFI = MF.getFrameInfo();
2378 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2379 unsigned firstRegToSaveIndex;
2380 if (CCInfo.isFirstByValRegValid())
2381 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2383 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2384 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2387 unsigned VARegSize, VARegSaveSize;
2388 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2389 if (VARegSaveSize) {
2390 // If this function is vararg, store any remaining integer argument regs
2391 // to their spots on the stack so that they may be loaded by deferencing
2392 // the result of va_next.
2393 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2394 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2395 ArgOffset + VARegSaveSize
2398 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2401 SmallVector<SDValue, 4> MemOps;
2402 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2403 TargetRegisterClass *RC;
2404 if (AFI->isThumb1OnlyFunction())
2405 RC = ARM::tGPRRegisterClass;
2407 RC = ARM::GPRRegisterClass;
2409 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2410 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2412 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2413 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2415 MemOps.push_back(Store);
2416 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2417 DAG.getConstant(4, getPointerTy()));
2419 if (!MemOps.empty())
2420 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2421 &MemOps[0], MemOps.size());
2423 // This will point to the next argument passed via stack.
2424 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2428 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2429 CallingConv::ID CallConv, bool isVarArg,
2430 const SmallVectorImpl<ISD::InputArg>
2432 DebugLoc dl, SelectionDAG &DAG,
2433 SmallVectorImpl<SDValue> &InVals)
2435 MachineFunction &MF = DAG.getMachineFunction();
2436 MachineFrameInfo *MFI = MF.getFrameInfo();
2438 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2440 // Assign locations to all of the incoming arguments.
2441 SmallVector<CCValAssign, 16> ArgLocs;
2442 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2443 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2444 CCInfo.AnalyzeFormalArguments(Ins,
2445 CCAssignFnForNode(CallConv, /* Return*/ false,
2448 SmallVector<SDValue, 16> ArgValues;
2449 int lastInsIndex = -1;
2452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2453 CCValAssign &VA = ArgLocs[i];
2455 // Arguments stored in registers.
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2459 if (VA.needsCustom()) {
2460 // f64 and vector types are split up into multiple registers or
2461 // combinations of registers and stack slots.
2462 if (VA.getLocVT() == MVT::v2f64) {
2463 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2465 VA = ArgLocs[++i]; // skip ahead to next loc
2467 if (VA.isMemLoc()) {
2468 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2469 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2470 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2471 MachinePointerInfo::getFixedStack(FI),
2474 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2477 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2478 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2479 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2480 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2481 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2483 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2486 TargetRegisterClass *RC;
2488 if (RegVT == MVT::f32)
2489 RC = ARM::SPRRegisterClass;
2490 else if (RegVT == MVT::f64)
2491 RC = ARM::DPRRegisterClass;
2492 else if (RegVT == MVT::v2f64)
2493 RC = ARM::QPRRegisterClass;
2494 else if (RegVT == MVT::i32)
2495 RC = (AFI->isThumb1OnlyFunction() ?
2496 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2498 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2500 // Transform the arguments in physical registers into virtual ones.
2501 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2502 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2505 // If this is an 8 or 16-bit value, it is really passed promoted
2506 // to 32 bits. Insert an assert[sz]ext to capture this, then
2507 // truncate to the right size.
2508 switch (VA.getLocInfo()) {
2509 default: llvm_unreachable("Unknown loc info!");
2510 case CCValAssign::Full: break;
2511 case CCValAssign::BCvt:
2512 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2514 case CCValAssign::SExt:
2515 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2516 DAG.getValueType(VA.getValVT()));
2517 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2519 case CCValAssign::ZExt:
2520 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2521 DAG.getValueType(VA.getValVT()));
2522 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2526 InVals.push_back(ArgValue);
2528 } else { // VA.isRegLoc()
2531 assert(VA.isMemLoc());
2532 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2534 int index = ArgLocs[i].getValNo();
2536 // Some Ins[] entries become multiple ArgLoc[] entries.
2537 // Process them only once.
2538 if (index != lastInsIndex)
2540 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2541 // FIXME: For now, all byval parameter objects are marked mutable.
2542 // This can be changed with more analysis.
2543 // In case of tail call optimization mark all arguments mutable.
2544 // Since they could be overwritten by lowering of arguments in case of
2546 if (Flags.isByVal()) {
2547 unsigned VARegSize, VARegSaveSize;
2548 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2549 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2550 unsigned Bytes = Flags.getByValSize() - VARegSize;
2551 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2552 int FI = MFI->CreateFixedObject(Bytes,
2553 VA.getLocMemOffset(), false);
2554 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2556 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2557 VA.getLocMemOffset(), true);
2559 // Create load nodes to retrieve arguments from the stack.
2560 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2561 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2562 MachinePointerInfo::getFixedStack(FI),
2565 lastInsIndex = index;
2572 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2577 /// isFloatingPointZero - Return true if this is +0.0.
2578 static bool isFloatingPointZero(SDValue Op) {
2579 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2580 return CFP->getValueAPF().isPosZero();
2581 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2582 // Maybe this has already been legalized into the constant pool?
2583 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2584 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2585 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2586 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2587 return CFP->getValueAPF().isPosZero();
2593 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2594 /// the given operands.
2596 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2597 SDValue &ARMcc, SelectionDAG &DAG,
2598 DebugLoc dl) const {
2599 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2600 unsigned C = RHSC->getZExtValue();
2601 if (!isLegalICmpImmediate(C)) {
2602 // Constant does not fit, try adjusting it by one?
2607 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2608 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2609 RHS = DAG.getConstant(C-1, MVT::i32);
2614 if (C != 0 && isLegalICmpImmediate(C-1)) {
2615 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2616 RHS = DAG.getConstant(C-1, MVT::i32);
2621 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2622 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2623 RHS = DAG.getConstant(C+1, MVT::i32);
2628 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2629 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2630 RHS = DAG.getConstant(C+1, MVT::i32);
2637 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2638 ARMISD::NodeType CompareType;
2641 CompareType = ARMISD::CMP;
2646 CompareType = ARMISD::CMPZ;
2649 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2650 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2653 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2655 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2656 DebugLoc dl) const {
2658 if (!isFloatingPointZero(RHS))
2659 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2661 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2662 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2665 /// duplicateCmp - Glue values can have only one use, so this function
2666 /// duplicates a comparison node.
2668 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2669 unsigned Opc = Cmp.getOpcode();
2670 DebugLoc DL = Cmp.getDebugLoc();
2671 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2672 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2674 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2675 Cmp = Cmp.getOperand(0);
2676 Opc = Cmp.getOpcode();
2677 if (Opc == ARMISD::CMPFP)
2678 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2680 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2681 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2683 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2686 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2687 SDValue Cond = Op.getOperand(0);
2688 SDValue SelectTrue = Op.getOperand(1);
2689 SDValue SelectFalse = Op.getOperand(2);
2690 DebugLoc dl = Op.getDebugLoc();
2694 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2695 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2697 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2698 const ConstantSDNode *CMOVTrue =
2699 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2700 const ConstantSDNode *CMOVFalse =
2701 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2703 if (CMOVTrue && CMOVFalse) {
2704 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2705 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2709 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2711 False = SelectFalse;
2712 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2717 if (True.getNode() && False.getNode()) {
2718 EVT VT = Op.getValueType();
2719 SDValue ARMcc = Cond.getOperand(2);
2720 SDValue CCR = Cond.getOperand(3);
2721 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2722 assert(True.getValueType() == VT);
2723 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2728 return DAG.getSelectCC(dl, Cond,
2729 DAG.getConstant(0, Cond.getValueType()),
2730 SelectTrue, SelectFalse, ISD::SETNE);
2733 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2734 EVT VT = Op.getValueType();
2735 SDValue LHS = Op.getOperand(0);
2736 SDValue RHS = Op.getOperand(1);
2737 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2738 SDValue TrueVal = Op.getOperand(2);
2739 SDValue FalseVal = Op.getOperand(3);
2740 DebugLoc dl = Op.getDebugLoc();
2742 if (LHS.getValueType() == MVT::i32) {
2744 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2745 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2746 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2749 ARMCC::CondCodes CondCode, CondCode2;
2750 FPCCToARMCC(CC, CondCode, CondCode2);
2752 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2753 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2754 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2755 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2757 if (CondCode2 != ARMCC::AL) {
2758 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2759 // FIXME: Needs another CMP because flag can have but one use.
2760 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2761 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2762 Result, TrueVal, ARMcc2, CCR, Cmp2);
2767 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2768 /// to morph to an integer compare sequence.
2769 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2770 const ARMSubtarget *Subtarget) {
2771 SDNode *N = Op.getNode();
2772 if (!N->hasOneUse())
2773 // Otherwise it requires moving the value from fp to integer registers.
2775 if (!N->getNumValues())
2777 EVT VT = Op.getValueType();
2778 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2779 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2780 // vmrs are very slow, e.g. cortex-a8.
2783 if (isFloatingPointZero(Op)) {
2787 return ISD::isNormalLoad(N);
2790 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2791 if (isFloatingPointZero(Op))
2792 return DAG.getConstant(0, MVT::i32);
2794 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2795 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2796 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2797 Ld->isVolatile(), Ld->isNonTemporal(),
2798 Ld->getAlignment());
2800 llvm_unreachable("Unknown VFP cmp argument!");
2803 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2804 SDValue &RetVal1, SDValue &RetVal2) {
2805 if (isFloatingPointZero(Op)) {
2806 RetVal1 = DAG.getConstant(0, MVT::i32);
2807 RetVal2 = DAG.getConstant(0, MVT::i32);
2811 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2812 SDValue Ptr = Ld->getBasePtr();
2813 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2814 Ld->getChain(), Ptr,
2815 Ld->getPointerInfo(),
2816 Ld->isVolatile(), Ld->isNonTemporal(),
2817 Ld->getAlignment());
2819 EVT PtrType = Ptr.getValueType();
2820 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2821 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2822 PtrType, Ptr, DAG.getConstant(4, PtrType));
2823 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2824 Ld->getChain(), NewPtr,
2825 Ld->getPointerInfo().getWithOffset(4),
2826 Ld->isVolatile(), Ld->isNonTemporal(),
2831 llvm_unreachable("Unknown VFP cmp argument!");
2834 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2835 /// f32 and even f64 comparisons to integer ones.
2837 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2838 SDValue Chain = Op.getOperand(0);
2839 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2840 SDValue LHS = Op.getOperand(2);
2841 SDValue RHS = Op.getOperand(3);
2842 SDValue Dest = Op.getOperand(4);
2843 DebugLoc dl = Op.getDebugLoc();
2845 bool SeenZero = false;
2846 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2847 canChangeToInt(RHS, SeenZero, Subtarget) &&
2848 // If one of the operand is zero, it's safe to ignore the NaN case since
2849 // we only care about equality comparisons.
2850 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2851 // If unsafe fp math optimization is enabled and there are no other uses of
2852 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2853 // to an integer comparison.
2854 if (CC == ISD::SETOEQ)
2856 else if (CC == ISD::SETUNE)
2860 if (LHS.getValueType() == MVT::f32) {
2861 LHS = bitcastf32Toi32(LHS, DAG);
2862 RHS = bitcastf32Toi32(RHS, DAG);
2863 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2864 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2865 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2866 Chain, Dest, ARMcc, CCR, Cmp);
2871 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2872 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2873 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2874 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2875 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2876 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2877 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2883 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2884 SDValue Chain = Op.getOperand(0);
2885 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2886 SDValue LHS = Op.getOperand(2);
2887 SDValue RHS = Op.getOperand(3);
2888 SDValue Dest = Op.getOperand(4);
2889 DebugLoc dl = Op.getDebugLoc();
2891 if (LHS.getValueType() == MVT::i32) {
2893 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2894 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2895 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2896 Chain, Dest, ARMcc, CCR, Cmp);
2899 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2902 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2903 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2904 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2905 if (Result.getNode())
2909 ARMCC::CondCodes CondCode, CondCode2;
2910 FPCCToARMCC(CC, CondCode, CondCode2);
2912 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2913 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2914 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2915 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2916 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2917 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2918 if (CondCode2 != ARMCC::AL) {
2919 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2920 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2921 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2926 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2927 SDValue Chain = Op.getOperand(0);
2928 SDValue Table = Op.getOperand(1);
2929 SDValue Index = Op.getOperand(2);
2930 DebugLoc dl = Op.getDebugLoc();
2932 EVT PTy = getPointerTy();
2933 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2934 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2935 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2936 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2937 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2938 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2939 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2940 if (Subtarget->isThumb2()) {
2941 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2942 // which does another jump to the destination. This also makes it easier
2943 // to translate it to TBB / TBH later.
2944 // FIXME: This might not work if the function is extremely large.
2945 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2946 Addr, Op.getOperand(2), JTI, UId);
2948 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2949 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2950 MachinePointerInfo::getJumpTable(),
2952 Chain = Addr.getValue(1);
2953 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2954 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2956 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2957 MachinePointerInfo::getJumpTable(), false, false, 0);
2958 Chain = Addr.getValue(1);
2959 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2963 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2964 DebugLoc dl = Op.getDebugLoc();
2967 switch (Op.getOpcode()) {
2969 assert(0 && "Invalid opcode!");
2970 case ISD::FP_TO_SINT:
2971 Opc = ARMISD::FTOSI;
2973 case ISD::FP_TO_UINT:
2974 Opc = ARMISD::FTOUI;
2977 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2978 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2981 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2982 EVT VT = Op.getValueType();
2983 DebugLoc dl = Op.getDebugLoc();
2985 EVT OperandVT = Op.getOperand(0).getValueType();
2986 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2987 if (VT != MVT::v4f32)
2988 return DAG.UnrollVectorOp(Op.getNode());
2992 switch (Op.getOpcode()) {
2994 assert(0 && "Invalid opcode!");
2995 case ISD::SINT_TO_FP:
2996 CastOpc = ISD::SIGN_EXTEND;
2997 Opc = ISD::SINT_TO_FP;
2999 case ISD::UINT_TO_FP:
3000 CastOpc = ISD::ZERO_EXTEND;
3001 Opc = ISD::UINT_TO_FP;
3005 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3006 return DAG.getNode(Opc, dl, VT, Op);
3009 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3010 EVT VT = Op.getValueType();
3012 return LowerVectorINT_TO_FP(Op, DAG);
3014 DebugLoc dl = Op.getDebugLoc();
3017 switch (Op.getOpcode()) {
3019 assert(0 && "Invalid opcode!");
3020 case ISD::SINT_TO_FP:
3021 Opc = ARMISD::SITOF;
3023 case ISD::UINT_TO_FP:
3024 Opc = ARMISD::UITOF;
3028 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3029 return DAG.getNode(Opc, dl, VT, Op);
3032 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3033 // Implement fcopysign with a fabs and a conditional fneg.
3034 SDValue Tmp0 = Op.getOperand(0);
3035 SDValue Tmp1 = Op.getOperand(1);
3036 DebugLoc dl = Op.getDebugLoc();
3037 EVT VT = Op.getValueType();
3038 EVT SrcVT = Tmp1.getValueType();
3039 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3040 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3041 bool UseNEON = !InGPR && Subtarget->hasNEON();
3044 // Use VBSL to copy the sign bit.
3045 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3046 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3047 DAG.getTargetConstant(EncodedVal, MVT::i32));
3048 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3050 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3051 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3052 DAG.getConstant(32, MVT::i32));
3053 else /*if (VT == MVT::f32)*/
3054 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3055 if (SrcVT == MVT::f32) {
3056 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3058 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3059 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3060 DAG.getConstant(32, MVT::i32));
3061 } else if (VT == MVT::f32)
3062 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3063 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3064 DAG.getConstant(32, MVT::i32));
3065 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3066 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3068 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3070 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3071 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3072 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3074 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3075 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3076 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3077 if (VT == MVT::f32) {
3078 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3079 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3080 DAG.getConstant(0, MVT::i32));
3082 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3088 // Bitcast operand 1 to i32.
3089 if (SrcVT == MVT::f64)
3090 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3091 &Tmp1, 1).getValue(1);
3092 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3094 // Or in the signbit with integer operations.
3095 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3096 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3097 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3098 if (VT == MVT::f32) {
3099 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3100 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3101 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3102 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3105 // f64: Or the high part with signbit and then combine two parts.
3106 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3108 SDValue Lo = Tmp0.getValue(0);
3109 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3110 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3111 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3114 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3115 MachineFunction &MF = DAG.getMachineFunction();
3116 MachineFrameInfo *MFI = MF.getFrameInfo();
3117 MFI->setReturnAddressIsTaken(true);
3119 EVT VT = Op.getValueType();
3120 DebugLoc dl = Op.getDebugLoc();
3121 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3123 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3124 SDValue Offset = DAG.getConstant(4, MVT::i32);
3125 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3126 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3127 MachinePointerInfo(), false, false, 0);
3130 // Return LR, which contains the return address. Mark it an implicit live-in.
3131 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3132 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3135 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3136 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3137 MFI->setFrameAddressIsTaken(true);
3139 EVT VT = Op.getValueType();
3140 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3141 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3142 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3143 ? ARM::R7 : ARM::R11;
3144 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3146 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3147 MachinePointerInfo(),
3152 /// ExpandBITCAST - If the target supports VFP, this function is called to
3153 /// expand a bit convert where either the source or destination type is i64 to
3154 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3155 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3156 /// vectors), since the legalizer won't know what to do with that.
3157 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3158 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3159 DebugLoc dl = N->getDebugLoc();
3160 SDValue Op = N->getOperand(0);
3162 // This function is only supposed to be called for i64 types, either as the
3163 // source or destination of the bit convert.
3164 EVT SrcVT = Op.getValueType();
3165 EVT DstVT = N->getValueType(0);
3166 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3167 "ExpandBITCAST called for non-i64 type");
3169 // Turn i64->f64 into VMOVDRR.
3170 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3171 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3172 DAG.getConstant(0, MVT::i32));
3173 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3174 DAG.getConstant(1, MVT::i32));
3175 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3176 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3179 // Turn f64->i64 into VMOVRRD.
3180 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3181 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3182 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3183 // Merge the pieces into a single i64 value.
3184 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3190 /// getZeroVector - Returns a vector of specified type with all zero elements.
3191 /// Zero vectors are used to represent vector negation and in those cases
3192 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3193 /// not support i64 elements, so sometimes the zero vectors will need to be
3194 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3196 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3197 assert(VT.isVector() && "Expected a vector type");
3198 // The canonical modified immediate encoding of a zero vector is....0!
3199 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3200 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3201 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3202 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3205 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3206 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3207 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3208 SelectionDAG &DAG) const {
3209 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3210 EVT VT = Op.getValueType();
3211 unsigned VTBits = VT.getSizeInBits();
3212 DebugLoc dl = Op.getDebugLoc();
3213 SDValue ShOpLo = Op.getOperand(0);
3214 SDValue ShOpHi = Op.getOperand(1);
3215 SDValue ShAmt = Op.getOperand(2);
3217 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3219 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3221 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3222 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3223 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3224 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3225 DAG.getConstant(VTBits, MVT::i32));
3226 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3227 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3228 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3230 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3231 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3233 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3234 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3237 SDValue Ops[2] = { Lo, Hi };
3238 return DAG.getMergeValues(Ops, 2, dl);
3241 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3242 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3243 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3244 SelectionDAG &DAG) const {
3245 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3246 EVT VT = Op.getValueType();
3247 unsigned VTBits = VT.getSizeInBits();
3248 DebugLoc dl = Op.getDebugLoc();
3249 SDValue ShOpLo = Op.getOperand(0);
3250 SDValue ShOpHi = Op.getOperand(1);
3251 SDValue ShAmt = Op.getOperand(2);
3254 assert(Op.getOpcode() == ISD::SHL_PARTS);
3255 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3256 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3257 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3258 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3259 DAG.getConstant(VTBits, MVT::i32));
3260 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3261 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3263 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3264 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3265 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3267 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3268 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3271 SDValue Ops[2] = { Lo, Hi };
3272 return DAG.getMergeValues(Ops, 2, dl);
3275 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3276 SelectionDAG &DAG) const {
3277 // The rounding mode is in bits 23:22 of the FPSCR.
3278 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3279 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3280 // so that the shift + and get folded into a bitfield extract.
3281 DebugLoc dl = Op.getDebugLoc();
3282 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3283 DAG.getConstant(Intrinsic::arm_get_fpscr,
3285 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3286 DAG.getConstant(1U << 22, MVT::i32));
3287 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3288 DAG.getConstant(22, MVT::i32));
3289 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3290 DAG.getConstant(3, MVT::i32));
3293 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3294 const ARMSubtarget *ST) {
3295 EVT VT = N->getValueType(0);
3296 DebugLoc dl = N->getDebugLoc();
3298 if (!ST->hasV6T2Ops())
3301 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3302 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3305 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3306 const ARMSubtarget *ST) {
3307 EVT VT = N->getValueType(0);
3308 DebugLoc dl = N->getDebugLoc();
3313 // Lower vector shifts on NEON to use VSHL.
3314 assert(ST->hasNEON() && "unexpected vector shift");
3316 // Left shifts translate directly to the vshiftu intrinsic.
3317 if (N->getOpcode() == ISD::SHL)
3318 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3319 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3320 N->getOperand(0), N->getOperand(1));
3322 assert((N->getOpcode() == ISD::SRA ||
3323 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3325 // NEON uses the same intrinsics for both left and right shifts. For
3326 // right shifts, the shift amounts are negative, so negate the vector of
3328 EVT ShiftVT = N->getOperand(1).getValueType();
3329 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3330 getZeroVector(ShiftVT, DAG, dl),
3332 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3333 Intrinsic::arm_neon_vshifts :
3334 Intrinsic::arm_neon_vshiftu);
3335 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3336 DAG.getConstant(vshiftInt, MVT::i32),
3337 N->getOperand(0), NegatedCount);
3340 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3341 const ARMSubtarget *ST) {
3342 EVT VT = N->getValueType(0);
3343 DebugLoc dl = N->getDebugLoc();
3345 // We can get here for a node like i32 = ISD::SHL i32, i64
3349 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3350 "Unknown shift to lower!");
3352 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3353 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3354 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3357 // If we are in thumb mode, we don't have RRX.
3358 if (ST->isThumb1Only()) return SDValue();
3360 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3361 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3362 DAG.getConstant(0, MVT::i32));
3363 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3364 DAG.getConstant(1, MVT::i32));
3366 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3367 // captures the result into a carry flag.
3368 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3369 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3371 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3372 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3374 // Merge the pieces into a single i64 value.
3375 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3378 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3379 SDValue TmpOp0, TmpOp1;
3380 bool Invert = false;
3384 SDValue Op0 = Op.getOperand(0);
3385 SDValue Op1 = Op.getOperand(1);
3386 SDValue CC = Op.getOperand(2);
3387 EVT VT = Op.getValueType();
3388 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3389 DebugLoc dl = Op.getDebugLoc();
3391 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3392 switch (SetCCOpcode) {
3393 default: llvm_unreachable("Illegal FP comparison"); break;
3395 case ISD::SETNE: Invert = true; // Fallthrough
3397 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3399 case ISD::SETLT: Swap = true; // Fallthrough
3401 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3403 case ISD::SETLE: Swap = true; // Fallthrough
3405 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3406 case ISD::SETUGE: Swap = true; // Fallthrough
3407 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3408 case ISD::SETUGT: Swap = true; // Fallthrough
3409 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3410 case ISD::SETUEQ: Invert = true; // Fallthrough
3412 // Expand this to (OLT | OGT).
3416 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3417 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3419 case ISD::SETUO: Invert = true; // Fallthrough
3421 // Expand this to (OLT | OGE).
3425 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3426 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3430 // Integer comparisons.
3431 switch (SetCCOpcode) {
3432 default: llvm_unreachable("Illegal integer comparison"); break;
3433 case ISD::SETNE: Invert = true;
3434 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3435 case ISD::SETLT: Swap = true;
3436 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3437 case ISD::SETLE: Swap = true;
3438 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3439 case ISD::SETULT: Swap = true;
3440 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3441 case ISD::SETULE: Swap = true;
3442 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3445 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3446 if (Opc == ARMISD::VCEQ) {
3449 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3451 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3454 // Ignore bitconvert.
3455 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3456 AndOp = AndOp.getOperand(0);
3458 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3460 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3461 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3468 std::swap(Op0, Op1);
3470 // If one of the operands is a constant vector zero, attempt to fold the
3471 // comparison to a specialized compare-against-zero form.
3473 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3475 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3476 if (Opc == ARMISD::VCGE)
3477 Opc = ARMISD::VCLEZ;
3478 else if (Opc == ARMISD::VCGT)
3479 Opc = ARMISD::VCLTZ;
3484 if (SingleOp.getNode()) {
3487 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3489 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3491 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3493 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3495 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3497 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3500 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3504 Result = DAG.getNOT(dl, Result, VT);
3509 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3510 /// valid vector constant for a NEON instruction with a "modified immediate"
3511 /// operand (e.g., VMOV). If so, return the encoded value.
3512 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3513 unsigned SplatBitSize, SelectionDAG &DAG,
3514 EVT &VT, bool is128Bits, NEONModImmType type) {
3515 unsigned OpCmode, Imm;
3517 // SplatBitSize is set to the smallest size that splats the vector, so a
3518 // zero vector will always have SplatBitSize == 8. However, NEON modified
3519 // immediate instructions others than VMOV do not support the 8-bit encoding
3520 // of a zero vector, and the default encoding of zero is supposed to be the
3525 switch (SplatBitSize) {
3527 if (type != VMOVModImm)
3529 // Any 1-byte value is OK. Op=0, Cmode=1110.
3530 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3533 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3537 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3538 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3539 if ((SplatBits & ~0xff) == 0) {
3540 // Value = 0x00nn: Op=x, Cmode=100x.
3545 if ((SplatBits & ~0xff00) == 0) {
3546 // Value = 0xnn00: Op=x, Cmode=101x.
3548 Imm = SplatBits >> 8;
3554 // NEON's 32-bit VMOV supports splat values where:
3555 // * only one byte is nonzero, or
3556 // * the least significant byte is 0xff and the second byte is nonzero, or
3557 // * the least significant 2 bytes are 0xff and the third is nonzero.
3558 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3559 if ((SplatBits & ~0xff) == 0) {
3560 // Value = 0x000000nn: Op=x, Cmode=000x.
3565 if ((SplatBits & ~0xff00) == 0) {
3566 // Value = 0x0000nn00: Op=x, Cmode=001x.
3568 Imm = SplatBits >> 8;
3571 if ((SplatBits & ~0xff0000) == 0) {
3572 // Value = 0x00nn0000: Op=x, Cmode=010x.
3574 Imm = SplatBits >> 16;
3577 if ((SplatBits & ~0xff000000) == 0) {
3578 // Value = 0xnn000000: Op=x, Cmode=011x.
3580 Imm = SplatBits >> 24;
3584 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3585 if (type == OtherModImm) return SDValue();
3587 if ((SplatBits & ~0xffff) == 0 &&
3588 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3589 // Value = 0x0000nnff: Op=x, Cmode=1100.
3591 Imm = SplatBits >> 8;
3596 if ((SplatBits & ~0xffffff) == 0 &&
3597 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3598 // Value = 0x00nnffff: Op=x, Cmode=1101.
3600 Imm = SplatBits >> 16;
3601 SplatBits |= 0xffff;
3605 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3606 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3607 // VMOV.I32. A (very) minor optimization would be to replicate the value
3608 // and fall through here to test for a valid 64-bit splat. But, then the
3609 // caller would also need to check and handle the change in size.
3613 if (type != VMOVModImm)
3615 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3616 uint64_t BitMask = 0xff;
3618 unsigned ImmMask = 1;
3620 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3621 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3624 } else if ((SplatBits & BitMask) != 0) {
3630 // Op=1, Cmode=1110.
3633 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3638 llvm_unreachable("unexpected size for isNEONModifiedImm");
3642 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3643 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3646 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3647 bool &ReverseVEXT, unsigned &Imm) {
3648 unsigned NumElts = VT.getVectorNumElements();
3649 ReverseVEXT = false;
3651 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3657 // If this is a VEXT shuffle, the immediate value is the index of the first
3658 // element. The other shuffle indices must be the successive elements after
3660 unsigned ExpectedElt = Imm;
3661 for (unsigned i = 1; i < NumElts; ++i) {
3662 // Increment the expected index. If it wraps around, it may still be
3663 // a VEXT but the source vectors must be swapped.
3665 if (ExpectedElt == NumElts * 2) {
3670 if (M[i] < 0) continue; // ignore UNDEF indices
3671 if (ExpectedElt != static_cast<unsigned>(M[i]))
3675 // Adjust the index value if the source operands will be swapped.
3682 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3683 /// instruction with the specified blocksize. (The order of the elements
3684 /// within each block of the vector is reversed.)
3685 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3686 unsigned BlockSize) {
3687 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3688 "Only possible block sizes for VREV are: 16, 32, 64");
3690 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3694 unsigned NumElts = VT.getVectorNumElements();
3695 unsigned BlockElts = M[0] + 1;
3696 // If the first shuffle index is UNDEF, be optimistic.
3698 BlockElts = BlockSize / EltSz;
3700 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3703 for (unsigned i = 0; i < NumElts; ++i) {
3704 if (M[i] < 0) continue; // ignore UNDEF indices
3705 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3712 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3713 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3714 // range, then 0 is placed into the resulting vector. So pretty much any mask
3715 // of 8 elements can work here.
3716 return VT == MVT::v8i8 && M.size() == 8;
3719 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3720 unsigned &WhichResult) {
3721 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3725 unsigned NumElts = VT.getVectorNumElements();
3726 WhichResult = (M[0] == 0 ? 0 : 1);
3727 for (unsigned i = 0; i < NumElts; i += 2) {
3728 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3729 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3735 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3736 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3737 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3738 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3739 unsigned &WhichResult) {
3740 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3744 unsigned NumElts = VT.getVectorNumElements();
3745 WhichResult = (M[0] == 0 ? 0 : 1);
3746 for (unsigned i = 0; i < NumElts; i += 2) {
3747 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3748 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3754 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3755 unsigned &WhichResult) {
3756 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3760 unsigned NumElts = VT.getVectorNumElements();
3761 WhichResult = (M[0] == 0 ? 0 : 1);
3762 for (unsigned i = 0; i != NumElts; ++i) {
3763 if (M[i] < 0) continue; // ignore UNDEF indices
3764 if ((unsigned) M[i] != 2 * i + WhichResult)
3768 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3769 if (VT.is64BitVector() && EltSz == 32)
3775 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3776 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3777 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3778 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3779 unsigned &WhichResult) {
3780 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3784 unsigned Half = VT.getVectorNumElements() / 2;
3785 WhichResult = (M[0] == 0 ? 0 : 1);
3786 for (unsigned j = 0; j != 2; ++j) {
3787 unsigned Idx = WhichResult;
3788 for (unsigned i = 0; i != Half; ++i) {
3789 int MIdx = M[i + j * Half];
3790 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3796 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3797 if (VT.is64BitVector() && EltSz == 32)
3803 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3804 unsigned &WhichResult) {
3805 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3809 unsigned NumElts = VT.getVectorNumElements();
3810 WhichResult = (M[0] == 0 ? 0 : 1);
3811 unsigned Idx = WhichResult * NumElts / 2;
3812 for (unsigned i = 0; i != NumElts; i += 2) {
3813 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3814 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3819 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3820 if (VT.is64BitVector() && EltSz == 32)
3826 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3827 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3828 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3829 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3830 unsigned &WhichResult) {
3831 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3835 unsigned NumElts = VT.getVectorNumElements();
3836 WhichResult = (M[0] == 0 ? 0 : 1);
3837 unsigned Idx = WhichResult * NumElts / 2;
3838 for (unsigned i = 0; i != NumElts; i += 2) {
3839 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3840 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3845 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3846 if (VT.is64BitVector() && EltSz == 32)
3852 // If N is an integer constant that can be moved into a register in one
3853 // instruction, return an SDValue of such a constant (will become a MOV
3854 // instruction). Otherwise return null.
3855 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3856 const ARMSubtarget *ST, DebugLoc dl) {
3858 if (!isa<ConstantSDNode>(N))
3860 Val = cast<ConstantSDNode>(N)->getZExtValue();
3862 if (ST->isThumb1Only()) {
3863 if (Val <= 255 || ~Val <= 255)
3864 return DAG.getConstant(Val, MVT::i32);
3866 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3867 return DAG.getConstant(Val, MVT::i32);
3872 // If this is a case we can't handle, return null and let the default
3873 // expansion code take care of it.
3874 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3875 const ARMSubtarget *ST) const {
3876 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3877 DebugLoc dl = Op.getDebugLoc();
3878 EVT VT = Op.getValueType();
3880 APInt SplatBits, SplatUndef;
3881 unsigned SplatBitSize;
3883 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3884 if (SplatBitSize <= 64) {
3885 // Check if an immediate VMOV works.
3887 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3888 SplatUndef.getZExtValue(), SplatBitSize,
3889 DAG, VmovVT, VT.is128BitVector(),
3891 if (Val.getNode()) {
3892 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3893 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3896 // Try an immediate VMVN.
3897 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3898 ((1LL << SplatBitSize) - 1));
3899 Val = isNEONModifiedImm(NegatedImm,
3900 SplatUndef.getZExtValue(), SplatBitSize,
3901 DAG, VmovVT, VT.is128BitVector(),
3903 if (Val.getNode()) {
3904 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3905 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3910 // Scan through the operands to see if only one value is used.
3911 unsigned NumElts = VT.getVectorNumElements();
3912 bool isOnlyLowElement = true;
3913 bool usesOnlyOneValue = true;
3914 bool isConstant = true;
3916 for (unsigned i = 0; i < NumElts; ++i) {
3917 SDValue V = Op.getOperand(i);
3918 if (V.getOpcode() == ISD::UNDEF)
3921 isOnlyLowElement = false;
3922 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3925 if (!Value.getNode())
3927 else if (V != Value)
3928 usesOnlyOneValue = false;
3931 if (!Value.getNode())
3932 return DAG.getUNDEF(VT);
3934 if (isOnlyLowElement)
3935 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3937 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3939 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3940 // i32 and try again.
3941 if (usesOnlyOneValue && EltSize <= 32) {
3943 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3944 if (VT.getVectorElementType().isFloatingPoint()) {
3945 SmallVector<SDValue, 8> Ops;
3946 for (unsigned i = 0; i < NumElts; ++i)
3947 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3949 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3950 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3951 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3953 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3955 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3957 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3960 // If all elements are constants and the case above didn't get hit, fall back
3961 // to the default expansion, which will generate a load from the constant
3966 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3968 SDValue shuffle = ReconstructShuffle(Op, DAG);
3969 if (shuffle != SDValue())
3973 // Vectors with 32- or 64-bit elements can be built by directly assigning
3974 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3975 // will be legalized.
3976 if (EltSize >= 32) {
3977 // Do the expansion with floating-point types, since that is what the VFP
3978 // registers are defined to use, and since i64 is not legal.
3979 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3980 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3981 SmallVector<SDValue, 8> Ops;
3982 for (unsigned i = 0; i < NumElts; ++i)
3983 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3984 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3985 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3991 // Gather data to see if the operation can be modelled as a
3992 // shuffle in combination with VEXTs.
3993 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3994 SelectionDAG &DAG) const {
3995 DebugLoc dl = Op.getDebugLoc();
3996 EVT VT = Op.getValueType();
3997 unsigned NumElts = VT.getVectorNumElements();
3999 SmallVector<SDValue, 2> SourceVecs;
4000 SmallVector<unsigned, 2> MinElts;
4001 SmallVector<unsigned, 2> MaxElts;
4003 for (unsigned i = 0; i < NumElts; ++i) {
4004 SDValue V = Op.getOperand(i);
4005 if (V.getOpcode() == ISD::UNDEF)
4007 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4008 // A shuffle can only come from building a vector from various
4009 // elements of other vectors.
4013 // Record this extraction against the appropriate vector if possible...
4014 SDValue SourceVec = V.getOperand(0);
4015 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4016 bool FoundSource = false;
4017 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4018 if (SourceVecs[j] == SourceVec) {
4019 if (MinElts[j] > EltNo)
4021 if (MaxElts[j] < EltNo)
4028 // Or record a new source if not...
4030 SourceVecs.push_back(SourceVec);
4031 MinElts.push_back(EltNo);
4032 MaxElts.push_back(EltNo);
4036 // Currently only do something sane when at most two source vectors
4038 if (SourceVecs.size() > 2)
4041 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4042 int VEXTOffsets[2] = {0, 0};
4044 // This loop extracts the usage patterns of the source vectors
4045 // and prepares appropriate SDValues for a shuffle if possible.
4046 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4047 if (SourceVecs[i].getValueType() == VT) {
4048 // No VEXT necessary
4049 ShuffleSrcs[i] = SourceVecs[i];
4052 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4053 // It probably isn't worth padding out a smaller vector just to
4054 // break it down again in a shuffle.
4058 // Since only 64-bit and 128-bit vectors are legal on ARM and
4059 // we've eliminated the other cases...
4060 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4061 "unexpected vector sizes in ReconstructShuffle");
4063 if (MaxElts[i] - MinElts[i] >= NumElts) {
4064 // Span too large for a VEXT to cope
4068 if (MinElts[i] >= NumElts) {
4069 // The extraction can just take the second half
4070 VEXTOffsets[i] = NumElts;
4071 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4073 DAG.getIntPtrConstant(NumElts));
4074 } else if (MaxElts[i] < NumElts) {
4075 // The extraction can just take the first half
4077 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4079 DAG.getIntPtrConstant(0));
4081 // An actual VEXT is needed
4082 VEXTOffsets[i] = MinElts[i];
4083 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4085 DAG.getIntPtrConstant(0));
4086 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4088 DAG.getIntPtrConstant(NumElts));
4089 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4090 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4094 SmallVector<int, 8> Mask;
4096 for (unsigned i = 0; i < NumElts; ++i) {
4097 SDValue Entry = Op.getOperand(i);
4098 if (Entry.getOpcode() == ISD::UNDEF) {
4103 SDValue ExtractVec = Entry.getOperand(0);
4104 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4105 .getOperand(1))->getSExtValue();
4106 if (ExtractVec == SourceVecs[0]) {
4107 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4109 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4113 // Final check before we try to produce nonsense...
4114 if (isShuffleMaskLegal(Mask, VT))
4115 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4121 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4122 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4123 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4124 /// are assumed to be legal.
4126 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4128 if (VT.getVectorNumElements() == 4 &&
4129 (VT.is128BitVector() || VT.is64BitVector())) {
4130 unsigned PFIndexes[4];
4131 for (unsigned i = 0; i != 4; ++i) {
4135 PFIndexes[i] = M[i];
4138 // Compute the index in the perfect shuffle table.
4139 unsigned PFTableIndex =
4140 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4141 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4142 unsigned Cost = (PFEntry >> 30);
4149 unsigned Imm, WhichResult;
4151 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4152 return (EltSize >= 32 ||
4153 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4154 isVREVMask(M, VT, 64) ||
4155 isVREVMask(M, VT, 32) ||
4156 isVREVMask(M, VT, 16) ||
4157 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4158 isVTBLMask(M, VT) ||
4159 isVTRNMask(M, VT, WhichResult) ||
4160 isVUZPMask(M, VT, WhichResult) ||
4161 isVZIPMask(M, VT, WhichResult) ||
4162 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4163 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4164 isVZIP_v_undef_Mask(M, VT, WhichResult));
4167 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4168 /// the specified operations to build the shuffle.
4169 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4170 SDValue RHS, SelectionDAG &DAG,
4172 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4173 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4174 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4177 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4186 OP_VUZPL, // VUZP, left result
4187 OP_VUZPR, // VUZP, right result
4188 OP_VZIPL, // VZIP, left result
4189 OP_VZIPR, // VZIP, right result
4190 OP_VTRNL, // VTRN, left result
4191 OP_VTRNR // VTRN, right result
4194 if (OpNum == OP_COPY) {
4195 if (LHSID == (1*9+2)*9+3) return LHS;
4196 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4200 SDValue OpLHS, OpRHS;
4201 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4202 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4203 EVT VT = OpLHS.getValueType();
4206 default: llvm_unreachable("Unknown shuffle opcode!");
4208 // VREV divides the vector in half and swaps within the half.
4209 if (VT.getVectorElementType() == MVT::i32 ||
4210 VT.getVectorElementType() == MVT::f32)
4211 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4212 // vrev <4 x i16> -> VREV32
4213 if (VT.getVectorElementType() == MVT::i16)
4214 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4215 // vrev <4 x i8> -> VREV16
4216 assert(VT.getVectorElementType() == MVT::i8);
4217 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4222 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4223 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4227 return DAG.getNode(ARMISD::VEXT, dl, VT,
4229 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4232 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4233 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4236 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4237 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4240 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4241 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4245 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4246 SmallVectorImpl<int> &ShuffleMask,
4247 SelectionDAG &DAG) {
4248 // Check to see if we can use the VTBL instruction.
4249 SDValue V1 = Op.getOperand(0);
4250 SDValue V2 = Op.getOperand(1);
4251 DebugLoc DL = Op.getDebugLoc();
4253 SmallVector<SDValue, 8> VTBLMask;
4254 for (SmallVectorImpl<int>::iterator
4255 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4256 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4258 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4259 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4260 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4263 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4264 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4268 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4269 SDValue V1 = Op.getOperand(0);
4270 SDValue V2 = Op.getOperand(1);
4271 DebugLoc dl = Op.getDebugLoc();
4272 EVT VT = Op.getValueType();
4273 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4274 SmallVector<int, 8> ShuffleMask;
4276 // Convert shuffles that are directly supported on NEON to target-specific
4277 // DAG nodes, instead of keeping them as shuffles and matching them again
4278 // during code selection. This is more efficient and avoids the possibility
4279 // of inconsistencies between legalization and selection.
4280 // FIXME: floating-point vectors should be canonicalized to integer vectors
4281 // of the same time so that they get CSEd properly.
4282 SVN->getMask(ShuffleMask);
4284 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4285 if (EltSize <= 32) {
4286 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4287 int Lane = SVN->getSplatIndex();
4288 // If this is undef splat, generate it via "just" vdup, if possible.
4289 if (Lane == -1) Lane = 0;
4291 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4292 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4294 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4295 DAG.getConstant(Lane, MVT::i32));
4300 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4303 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4304 DAG.getConstant(Imm, MVT::i32));
4307 if (isVREVMask(ShuffleMask, VT, 64))
4308 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4309 if (isVREVMask(ShuffleMask, VT, 32))
4310 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4311 if (isVREVMask(ShuffleMask, VT, 16))
4312 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4314 // Check for Neon shuffles that modify both input vectors in place.
4315 // If both results are used, i.e., if there are two shuffles with the same
4316 // source operands and with masks corresponding to both results of one of
4317 // these operations, DAG memoization will ensure that a single node is
4318 // used for both shuffles.
4319 unsigned WhichResult;
4320 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4321 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4322 V1, V2).getValue(WhichResult);
4323 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4324 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4325 V1, V2).getValue(WhichResult);
4326 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4327 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4328 V1, V2).getValue(WhichResult);
4330 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4331 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4332 V1, V1).getValue(WhichResult);
4333 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4334 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4335 V1, V1).getValue(WhichResult);
4336 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4337 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4338 V1, V1).getValue(WhichResult);
4341 // If the shuffle is not directly supported and it has 4 elements, use
4342 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4343 unsigned NumElts = VT.getVectorNumElements();
4345 unsigned PFIndexes[4];
4346 for (unsigned i = 0; i != 4; ++i) {
4347 if (ShuffleMask[i] < 0)
4350 PFIndexes[i] = ShuffleMask[i];
4353 // Compute the index in the perfect shuffle table.
4354 unsigned PFTableIndex =
4355 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4356 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4357 unsigned Cost = (PFEntry >> 30);
4360 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4363 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4364 if (EltSize >= 32) {
4365 // Do the expansion with floating-point types, since that is what the VFP
4366 // registers are defined to use, and since i64 is not legal.
4367 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4368 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4369 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4370 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4371 SmallVector<SDValue, 8> Ops;
4372 for (unsigned i = 0; i < NumElts; ++i) {
4373 if (ShuffleMask[i] < 0)
4374 Ops.push_back(DAG.getUNDEF(EltVT));
4376 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4377 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4378 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4381 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4382 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4385 if (VT == MVT::v8i8) {
4386 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4387 if (NewOp.getNode())
4394 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4395 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4396 SDValue Lane = Op.getOperand(1);
4397 if (!isa<ConstantSDNode>(Lane))
4400 SDValue Vec = Op.getOperand(0);
4401 if (Op.getValueType() == MVT::i32 &&
4402 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4403 DebugLoc dl = Op.getDebugLoc();
4404 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4410 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4411 // The only time a CONCAT_VECTORS operation can have legal types is when
4412 // two 64-bit vectors are concatenated to a 128-bit vector.
4413 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4414 "unexpected CONCAT_VECTORS");
4415 DebugLoc dl = Op.getDebugLoc();
4416 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4417 SDValue Op0 = Op.getOperand(0);
4418 SDValue Op1 = Op.getOperand(1);
4419 if (Op0.getOpcode() != ISD::UNDEF)
4420 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4421 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4422 DAG.getIntPtrConstant(0));
4423 if (Op1.getOpcode() != ISD::UNDEF)
4424 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4425 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4426 DAG.getIntPtrConstant(1));
4427 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4430 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4431 /// element has been zero/sign-extended, depending on the isSigned parameter,
4432 /// from an integer type half its size.
4433 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4435 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4436 EVT VT = N->getValueType(0);
4437 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4438 SDNode *BVN = N->getOperand(0).getNode();
4439 if (BVN->getValueType(0) != MVT::v4i32 ||
4440 BVN->getOpcode() != ISD::BUILD_VECTOR)
4442 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4443 unsigned HiElt = 1 - LoElt;
4444 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4445 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4446 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4447 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4448 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4451 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4452 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4455 if (Hi0->isNullValue() && Hi1->isNullValue())
4461 if (N->getOpcode() != ISD::BUILD_VECTOR)
4464 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4465 SDNode *Elt = N->getOperand(i).getNode();
4466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4467 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4468 unsigned HalfSize = EltSize / 2;
4470 int64_t SExtVal = C->getSExtValue();
4471 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4474 if ((C->getZExtValue() >> HalfSize) != 0)
4485 /// isSignExtended - Check if a node is a vector value that is sign-extended
4486 /// or a constant BUILD_VECTOR with sign-extended elements.
4487 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4488 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4490 if (isExtendedBUILD_VECTOR(N, DAG, true))
4495 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4496 /// or a constant BUILD_VECTOR with zero-extended elements.
4497 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4498 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4500 if (isExtendedBUILD_VECTOR(N, DAG, false))
4505 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4506 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4507 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4508 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4509 return N->getOperand(0);
4510 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4511 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4512 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4513 LD->isNonTemporal(), LD->getAlignment());
4514 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4515 // have been legalized as a BITCAST from v4i32.
4516 if (N->getOpcode() == ISD::BITCAST) {
4517 SDNode *BVN = N->getOperand(0).getNode();
4518 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4519 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4520 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4521 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4522 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4524 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4525 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4526 EVT VT = N->getValueType(0);
4527 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4528 unsigned NumElts = VT.getVectorNumElements();
4529 MVT TruncVT = MVT::getIntegerVT(EltSize);
4530 SmallVector<SDValue, 8> Ops;
4531 for (unsigned i = 0; i != NumElts; ++i) {
4532 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4533 const APInt &CInt = C->getAPIntValue();
4534 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4536 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4537 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4540 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4541 unsigned Opcode = N->getOpcode();
4542 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4543 SDNode *N0 = N->getOperand(0).getNode();
4544 SDNode *N1 = N->getOperand(1).getNode();
4545 return N0->hasOneUse() && N1->hasOneUse() &&
4546 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4551 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4552 unsigned Opcode = N->getOpcode();
4553 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4554 SDNode *N0 = N->getOperand(0).getNode();
4555 SDNode *N1 = N->getOperand(1).getNode();
4556 return N0->hasOneUse() && N1->hasOneUse() &&
4557 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4562 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4563 // Multiplications are only custom-lowered for 128-bit vectors so that
4564 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4565 EVT VT = Op.getValueType();
4566 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4567 SDNode *N0 = Op.getOperand(0).getNode();
4568 SDNode *N1 = Op.getOperand(1).getNode();
4569 unsigned NewOpc = 0;
4571 bool isN0SExt = isSignExtended(N0, DAG);
4572 bool isN1SExt = isSignExtended(N1, DAG);
4573 if (isN0SExt && isN1SExt)
4574 NewOpc = ARMISD::VMULLs;
4576 bool isN0ZExt = isZeroExtended(N0, DAG);
4577 bool isN1ZExt = isZeroExtended(N1, DAG);
4578 if (isN0ZExt && isN1ZExt)
4579 NewOpc = ARMISD::VMULLu;
4580 else if (isN1SExt || isN1ZExt) {
4581 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4582 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4583 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4584 NewOpc = ARMISD::VMULLs;
4586 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4587 NewOpc = ARMISD::VMULLu;
4589 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4591 NewOpc = ARMISD::VMULLu;
4597 if (VT == MVT::v2i64)
4598 // Fall through to expand this. It is not legal.
4601 // Other vector multiplications are legal.
4606 // Legalize to a VMULL instruction.
4607 DebugLoc DL = Op.getDebugLoc();
4609 SDValue Op1 = SkipExtension(N1, DAG);
4611 Op0 = SkipExtension(N0, DAG);
4612 assert(Op0.getValueType().is64BitVector() &&
4613 Op1.getValueType().is64BitVector() &&
4614 "unexpected types for extended operands to VMULL");
4615 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4618 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4619 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4626 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4627 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4628 EVT Op1VT = Op1.getValueType();
4629 return DAG.getNode(N0->getOpcode(), DL, VT,
4630 DAG.getNode(NewOpc, DL, VT,
4631 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4632 DAG.getNode(NewOpc, DL, VT,
4633 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4637 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4639 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4640 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4641 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4642 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4643 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4644 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4645 // Get reciprocal estimate.
4646 // float4 recip = vrecpeq_f32(yf);
4647 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4648 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4649 // Because char has a smaller range than uchar, we can actually get away
4650 // without any newton steps. This requires that we use a weird bias
4651 // of 0xb000, however (again, this has been exhaustively tested).
4652 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4653 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4654 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4655 Y = DAG.getConstant(0xb000, MVT::i32);
4656 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4657 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4658 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4659 // Convert back to short.
4660 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4661 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4666 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4668 // Convert to float.
4669 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4670 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4671 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4672 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4673 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4674 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4676 // Use reciprocal estimate and one refinement step.
4677 // float4 recip = vrecpeq_f32(yf);
4678 // recip *= vrecpsq_f32(yf, recip);
4679 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4680 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4681 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4682 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4684 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4685 // Because short has a smaller range than ushort, we can actually get away
4686 // with only a single newton step. This requires that we use a weird bias
4687 // of 89, however (again, this has been exhaustively tested).
4688 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4689 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4690 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4691 N1 = DAG.getConstant(0x89, MVT::i32);
4692 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4693 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4694 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4695 // Convert back to integer and return.
4696 // return vmovn_s32(vcvt_s32_f32(result));
4697 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4698 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4702 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4703 EVT VT = Op.getValueType();
4704 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4705 "unexpected type for custom-lowering ISD::SDIV");
4707 DebugLoc dl = Op.getDebugLoc();
4708 SDValue N0 = Op.getOperand(0);
4709 SDValue N1 = Op.getOperand(1);
4712 if (VT == MVT::v8i8) {
4713 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4714 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4716 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4717 DAG.getIntPtrConstant(4));
4718 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4719 DAG.getIntPtrConstant(4));
4720 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4721 DAG.getIntPtrConstant(0));
4722 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4723 DAG.getIntPtrConstant(0));
4725 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4726 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4728 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4729 N0 = LowerCONCAT_VECTORS(N0, DAG);
4731 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4734 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4737 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4738 EVT VT = Op.getValueType();
4739 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4740 "unexpected type for custom-lowering ISD::UDIV");
4742 DebugLoc dl = Op.getDebugLoc();
4743 SDValue N0 = Op.getOperand(0);
4744 SDValue N1 = Op.getOperand(1);
4747 if (VT == MVT::v8i8) {
4748 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4749 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4751 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4752 DAG.getIntPtrConstant(4));
4753 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4754 DAG.getIntPtrConstant(4));
4755 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4756 DAG.getIntPtrConstant(0));
4757 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4758 DAG.getIntPtrConstant(0));
4760 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4761 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4763 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4764 N0 = LowerCONCAT_VECTORS(N0, DAG);
4766 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4767 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4772 // v4i16 sdiv ... Convert to float.
4773 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4774 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4775 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4776 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4777 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4778 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4780 // Use reciprocal estimate and two refinement steps.
4781 // float4 recip = vrecpeq_f32(yf);
4782 // recip *= vrecpsq_f32(yf, recip);
4783 // recip *= vrecpsq_f32(yf, recip);
4784 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4785 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4786 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4787 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4789 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4790 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4791 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4793 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4794 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4795 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4796 // and that it will never cause us to return an answer too large).
4797 // float4 result = as_float4(as_int4(xf*recip) + 2);
4798 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4799 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4800 N1 = DAG.getConstant(2, MVT::i32);
4801 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4802 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4803 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4804 // Convert back to integer and return.
4805 // return vmovn_u32(vcvt_s32_f32(result));
4806 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4807 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4811 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4812 switch (Op.getOpcode()) {
4813 default: llvm_unreachable("Don't know how to custom lower this!");
4814 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4815 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4816 case ISD::GlobalAddress:
4817 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4818 LowerGlobalAddressELF(Op, DAG);
4819 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4820 case ISD::SELECT: return LowerSELECT(Op, DAG);
4821 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4822 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4823 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4824 case ISD::VASTART: return LowerVASTART(Op, DAG);
4825 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4826 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4827 case ISD::SINT_TO_FP:
4828 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4829 case ISD::FP_TO_SINT:
4830 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4831 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4832 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4833 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4834 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4835 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4836 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4837 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4838 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4840 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4843 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4844 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4845 case ISD::SRL_PARTS:
4846 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4847 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4848 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4849 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4850 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4851 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4852 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4853 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4854 case ISD::MUL: return LowerMUL(Op, DAG);
4855 case ISD::SDIV: return LowerSDIV(Op, DAG);
4856 case ISD::UDIV: return LowerUDIV(Op, DAG);
4861 /// ReplaceNodeResults - Replace the results of node with an illegal result
4862 /// type with new values built out of custom code.
4863 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4864 SmallVectorImpl<SDValue>&Results,
4865 SelectionDAG &DAG) const {
4867 switch (N->getOpcode()) {
4869 llvm_unreachable("Don't know how to custom expand this!");
4872 Res = ExpandBITCAST(N, DAG);
4876 Res = Expand64BitShift(N, DAG, Subtarget);
4880 Results.push_back(Res);
4883 //===----------------------------------------------------------------------===//
4884 // ARM Scheduler Hooks
4885 //===----------------------------------------------------------------------===//
4888 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4889 MachineBasicBlock *BB,
4890 unsigned Size) const {
4891 unsigned dest = MI->getOperand(0).getReg();
4892 unsigned ptr = MI->getOperand(1).getReg();
4893 unsigned oldval = MI->getOperand(2).getReg();
4894 unsigned newval = MI->getOperand(3).getReg();
4895 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4896 DebugLoc dl = MI->getDebugLoc();
4897 bool isThumb2 = Subtarget->isThumb2();
4899 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4901 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
4902 : ARM::GPRRegisterClass);
4905 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
4906 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
4907 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
4910 unsigned ldrOpc, strOpc;
4912 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4914 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4915 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4918 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4919 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4922 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4923 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4927 MachineFunction *MF = BB->getParent();
4928 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4929 MachineFunction::iterator It = BB;
4930 ++It; // insert the new blocks after the current block
4932 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4933 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4934 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4935 MF->insert(It, loop1MBB);
4936 MF->insert(It, loop2MBB);
4937 MF->insert(It, exitMBB);
4939 // Transfer the remainder of BB and its successor edges to exitMBB.
4940 exitMBB->splice(exitMBB->begin(), BB,
4941 llvm::next(MachineBasicBlock::iterator(MI)),
4943 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4947 // fallthrough --> loop1MBB
4948 BB->addSuccessor(loop1MBB);
4951 // ldrex dest, [ptr]
4955 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4956 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4957 .addReg(dest).addReg(oldval));
4958 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4959 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4960 BB->addSuccessor(loop2MBB);
4961 BB->addSuccessor(exitMBB);
4964 // strex scratch, newval, [ptr]
4968 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4970 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4971 .addReg(scratch).addImm(0));
4972 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4973 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4974 BB->addSuccessor(loop1MBB);
4975 BB->addSuccessor(exitMBB);
4981 MI->eraseFromParent(); // The instruction is gone now.
4987 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4988 unsigned Size, unsigned BinOpcode) const {
4989 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4990 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4992 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4993 MachineFunction *MF = BB->getParent();
4994 MachineFunction::iterator It = BB;
4997 unsigned dest = MI->getOperand(0).getReg();
4998 unsigned ptr = MI->getOperand(1).getReg();
4999 unsigned incr = MI->getOperand(2).getReg();
5000 DebugLoc dl = MI->getDebugLoc();
5001 bool isThumb2 = Subtarget->isThumb2();
5003 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5005 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5006 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5009 unsigned ldrOpc, strOpc;
5011 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5013 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5014 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5017 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5018 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5021 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5022 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5026 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5027 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5028 MF->insert(It, loopMBB);
5029 MF->insert(It, exitMBB);
5031 // Transfer the remainder of BB and its successor edges to exitMBB.
5032 exitMBB->splice(exitMBB->begin(), BB,
5033 llvm::next(MachineBasicBlock::iterator(MI)),
5035 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5037 TargetRegisterClass *TRC =
5038 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5039 unsigned scratch = MRI.createVirtualRegister(TRC);
5040 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5044 // fallthrough --> loopMBB
5045 BB->addSuccessor(loopMBB);
5049 // <binop> scratch2, dest, incr
5050 // strex scratch, scratch2, ptr
5053 // fallthrough --> exitMBB
5055 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5057 // operand order needs to go the other way for NAND
5058 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5059 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5060 addReg(incr).addReg(dest)).addReg(0);
5062 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5063 addReg(dest).addReg(incr)).addReg(0);
5066 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5068 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5069 .addReg(scratch).addImm(0));
5070 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5071 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5073 BB->addSuccessor(loopMBB);
5074 BB->addSuccessor(exitMBB);
5080 MI->eraseFromParent(); // The instruction is gone now.
5086 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5087 MachineBasicBlock *BB,
5090 ARMCC::CondCodes Cond) const {
5091 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5093 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5094 MachineFunction *MF = BB->getParent();
5095 MachineFunction::iterator It = BB;
5098 unsigned dest = MI->getOperand(0).getReg();
5099 unsigned ptr = MI->getOperand(1).getReg();
5100 unsigned incr = MI->getOperand(2).getReg();
5101 unsigned oldval = dest;
5102 DebugLoc dl = MI->getDebugLoc();
5103 bool isThumb2 = Subtarget->isThumb2();
5105 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5107 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5108 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5111 unsigned ldrOpc, strOpc, extendOpc;
5113 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5115 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5116 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5117 extendOpc = isThumb2 ? ARM::t2SXTBr : ARM::SXTBr;
5120 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5121 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5122 extendOpc = isThumb2 ? ARM::t2SXTHr : ARM::SXTHr;
5125 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5126 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5131 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5132 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5133 MF->insert(It, loopMBB);
5134 MF->insert(It, exitMBB);
5136 // Transfer the remainder of BB and its successor edges to exitMBB.
5137 exitMBB->splice(exitMBB->begin(), BB,
5138 llvm::next(MachineBasicBlock::iterator(MI)),
5140 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5142 TargetRegisterClass *TRC =
5143 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5144 unsigned scratch = MRI.createVirtualRegister(TRC);
5145 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5149 // fallthrough --> loopMBB
5150 BB->addSuccessor(loopMBB);
5154 // (sign extend dest, if required)
5156 // cmov.cond scratch2, dest, incr
5157 // strex scratch, scratch2, ptr
5160 // fallthrough --> exitMBB
5162 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5164 // Sign extend the value, if necessary.
5165 if (signExtend && extendOpc) {
5166 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5167 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest));
5170 // Build compare and cmov instructions.
5171 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5172 .addReg(oldval).addReg(incr));
5173 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5174 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5176 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5178 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5179 .addReg(scratch).addImm(0));
5180 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5181 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5183 BB->addSuccessor(loopMBB);
5184 BB->addSuccessor(exitMBB);
5190 MI->eraseFromParent(); // The instruction is gone now.
5196 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5197 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5198 E = MBB->succ_end(); I != E; ++I)
5201 llvm_unreachable("Expecting a BB with two successors!");
5204 // FIXME: This opcode table should obviously be expressed in the target
5205 // description. We probably just need a "machine opcode" value in the pseudo
5206 // instruction. But the ideal solution maybe to simply remove the "S" version
5207 // of the opcode altogether.
5208 struct AddSubFlagsOpcodePair {
5210 unsigned MachineOpc;
5213 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
5214 {ARM::ADCSri, ARM::ADCri},
5215 {ARM::ADCSrr, ARM::ADCrr},
5216 {ARM::ADCSrs, ARM::ADCrs},
5217 {ARM::SBCSri, ARM::SBCri},
5218 {ARM::SBCSrr, ARM::SBCrr},
5219 {ARM::SBCSrs, ARM::SBCrs},
5220 {ARM::RSBSri, ARM::RSBri},
5221 {ARM::RSBSrr, ARM::RSBrr},
5222 {ARM::RSBSrs, ARM::RSBrs},
5223 {ARM::RSCSri, ARM::RSCri},
5224 {ARM::RSCSrs, ARM::RSCrs},
5225 {ARM::t2ADCSri, ARM::t2ADCri},
5226 {ARM::t2ADCSrr, ARM::t2ADCrr},
5227 {ARM::t2ADCSrs, ARM::t2ADCrs},
5228 {ARM::t2SBCSri, ARM::t2SBCri},
5229 {ARM::t2SBCSrr, ARM::t2SBCrr},
5230 {ARM::t2SBCSrs, ARM::t2SBCrs},
5231 {ARM::t2RSBSri, ARM::t2RSBri},
5232 {ARM::t2RSBSrs, ARM::t2RSBrs},
5235 // Convert and Add or Subtract with Carry and Flags to a generic opcode with
5236 // CPSR<def> operand. e.g. ADCS (...) -> ADC (... CPSR<def>).
5238 // FIXME: Somewhere we should assert that CPSR<def> is in the correct
5239 // position to be recognized by the target descrition as the 'S' bit.
5240 bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
5241 MachineBasicBlock *BB) const {
5242 unsigned OldOpc = MI->getOpcode();
5243 unsigned NewOpc = 0;
5245 // This is only called for instructions that need remapping, so iterating over
5246 // the tiny opcode table is not costly.
5247 static const int NPairs =
5248 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
5249 for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
5250 *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
5251 if (OldOpc == Pair->PseudoOpc) {
5252 NewOpc = Pair->MachineOpc;
5259 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5260 DebugLoc dl = MI->getDebugLoc();
5261 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5262 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5263 MIB.addOperand(MI->getOperand(i));
5264 AddDefaultPred(MIB);
5265 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5266 MI->eraseFromParent();
5271 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5272 MachineBasicBlock *BB) const {
5273 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5274 DebugLoc dl = MI->getDebugLoc();
5275 bool isThumb2 = Subtarget->isThumb2();
5276 switch (MI->getOpcode()) {
5278 if (RemapAddSubWithFlags(MI, BB))
5282 llvm_unreachable("Unexpected instr type to insert");
5284 case ARM::ATOMIC_LOAD_ADD_I8:
5285 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5286 case ARM::ATOMIC_LOAD_ADD_I16:
5287 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5288 case ARM::ATOMIC_LOAD_ADD_I32:
5289 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5291 case ARM::ATOMIC_LOAD_AND_I8:
5292 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5293 case ARM::ATOMIC_LOAD_AND_I16:
5294 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5295 case ARM::ATOMIC_LOAD_AND_I32:
5296 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5298 case ARM::ATOMIC_LOAD_OR_I8:
5299 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5300 case ARM::ATOMIC_LOAD_OR_I16:
5301 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5302 case ARM::ATOMIC_LOAD_OR_I32:
5303 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5305 case ARM::ATOMIC_LOAD_XOR_I8:
5306 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5307 case ARM::ATOMIC_LOAD_XOR_I16:
5308 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5309 case ARM::ATOMIC_LOAD_XOR_I32:
5310 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5312 case ARM::ATOMIC_LOAD_NAND_I8:
5313 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5314 case ARM::ATOMIC_LOAD_NAND_I16:
5315 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5316 case ARM::ATOMIC_LOAD_NAND_I32:
5317 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5319 case ARM::ATOMIC_LOAD_SUB_I8:
5320 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5321 case ARM::ATOMIC_LOAD_SUB_I16:
5322 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5323 case ARM::ATOMIC_LOAD_SUB_I32:
5324 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5326 case ARM::ATOMIC_LOAD_MIN_I8:
5327 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
5328 case ARM::ATOMIC_LOAD_MIN_I16:
5329 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
5330 case ARM::ATOMIC_LOAD_MIN_I32:
5331 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
5333 case ARM::ATOMIC_LOAD_MAX_I8:
5334 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
5335 case ARM::ATOMIC_LOAD_MAX_I16:
5336 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
5337 case ARM::ATOMIC_LOAD_MAX_I32:
5338 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
5340 case ARM::ATOMIC_LOAD_UMIN_I8:
5341 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
5342 case ARM::ATOMIC_LOAD_UMIN_I16:
5343 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
5344 case ARM::ATOMIC_LOAD_UMIN_I32:
5345 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
5347 case ARM::ATOMIC_LOAD_UMAX_I8:
5348 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
5349 case ARM::ATOMIC_LOAD_UMAX_I16:
5350 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
5351 case ARM::ATOMIC_LOAD_UMAX_I32:
5352 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
5354 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5355 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5356 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5358 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5359 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5360 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5362 case ARM::tMOVCCr_pseudo: {
5363 // To "insert" a SELECT_CC instruction, we actually have to insert the
5364 // diamond control-flow pattern. The incoming instruction knows the
5365 // destination vreg to set, the condition code register to branch on, the
5366 // true/false values to select between, and a branch opcode to use.
5367 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5368 MachineFunction::iterator It = BB;
5374 // cmpTY ccX, r1, r2
5376 // fallthrough --> copy0MBB
5377 MachineBasicBlock *thisMBB = BB;
5378 MachineFunction *F = BB->getParent();
5379 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5380 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5381 F->insert(It, copy0MBB);
5382 F->insert(It, sinkMBB);
5384 // Transfer the remainder of BB and its successor edges to sinkMBB.
5385 sinkMBB->splice(sinkMBB->begin(), BB,
5386 llvm::next(MachineBasicBlock::iterator(MI)),
5388 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5390 BB->addSuccessor(copy0MBB);
5391 BB->addSuccessor(sinkMBB);
5393 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5394 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5397 // %FalseValue = ...
5398 // # fallthrough to sinkMBB
5401 // Update machine-CFG edges
5402 BB->addSuccessor(sinkMBB);
5405 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5408 BuildMI(*BB, BB->begin(), dl,
5409 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5410 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5411 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5413 MI->eraseFromParent(); // The pseudo instruction is gone now.
5418 case ARM::BCCZi64: {
5419 // If there is an unconditional branch to the other successor, remove it.
5420 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5422 // Compare both parts that make up the double comparison separately for
5424 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5426 unsigned LHS1 = MI->getOperand(1).getReg();
5427 unsigned LHS2 = MI->getOperand(2).getReg();
5429 AddDefaultPred(BuildMI(BB, dl,
5430 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5431 .addReg(LHS1).addImm(0));
5432 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5433 .addReg(LHS2).addImm(0)
5434 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5436 unsigned RHS1 = MI->getOperand(3).getReg();
5437 unsigned RHS2 = MI->getOperand(4).getReg();
5438 AddDefaultPred(BuildMI(BB, dl,
5439 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5440 .addReg(LHS1).addReg(RHS1));
5441 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5442 .addReg(LHS2).addReg(RHS2)
5443 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5446 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5447 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5448 if (MI->getOperand(0).getImm() == ARMCC::NE)
5449 std::swap(destMBB, exitMBB);
5451 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5452 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5453 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5456 MI->eraseFromParent(); // The pseudo instruction is gone now.
5462 //===----------------------------------------------------------------------===//
5463 // ARM Optimization Hooks
5464 //===----------------------------------------------------------------------===//
5467 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5468 TargetLowering::DAGCombinerInfo &DCI) {
5469 SelectionDAG &DAG = DCI.DAG;
5470 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5471 EVT VT = N->getValueType(0);
5472 unsigned Opc = N->getOpcode();
5473 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5474 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5475 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5476 ISD::CondCode CC = ISD::SETCC_INVALID;
5479 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5481 SDValue CCOp = Slct.getOperand(0);
5482 if (CCOp.getOpcode() == ISD::SETCC)
5483 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5486 bool DoXform = false;
5488 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5491 if (LHS.getOpcode() == ISD::Constant &&
5492 cast<ConstantSDNode>(LHS)->isNullValue()) {
5494 } else if (CC != ISD::SETCC_INVALID &&
5495 RHS.getOpcode() == ISD::Constant &&
5496 cast<ConstantSDNode>(RHS)->isNullValue()) {
5497 std::swap(LHS, RHS);
5498 SDValue Op0 = Slct.getOperand(0);
5499 EVT OpVT = isSlctCC ? Op0.getValueType() :
5500 Op0.getOperand(0).getValueType();
5501 bool isInt = OpVT.isInteger();
5502 CC = ISD::getSetCCInverse(CC, isInt);
5504 if (!TLI.isCondCodeLegal(CC, OpVT))
5505 return SDValue(); // Inverse operator isn't legal.
5512 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5514 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5515 Slct.getOperand(0), Slct.getOperand(1), CC);
5516 SDValue CCOp = Slct.getOperand(0);
5518 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5519 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5520 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5521 CCOp, OtherOp, Result);
5526 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
5527 // (only after legalization).
5528 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
5529 TargetLowering::DAGCombinerInfo &DCI,
5530 const ARMSubtarget *Subtarget) {
5532 // Only perform optimization if after legalize, and if NEON is available. We
5533 // also expected both operands to be BUILD_VECTORs.
5534 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
5535 || N0.getOpcode() != ISD::BUILD_VECTOR
5536 || N1.getOpcode() != ISD::BUILD_VECTOR)
5539 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
5540 EVT VT = N->getValueType(0);
5541 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
5544 // Check that the vector operands are of the right form.
5545 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
5546 // operands, where N is the size of the formed vector.
5547 // Each EXTRACT_VECTOR should have the same input vector and odd or even
5548 // index such that we have a pair wise add pattern.
5550 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
5551 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5553 SDValue Vec = N0->getOperand(0)->getOperand(0);
5554 SDNode *V = Vec.getNode();
5555 unsigned nextIndex = 0;
5557 // For each operands to the ADD which are BUILD_VECTORs,
5558 // check to see if each of their operands are an EXTRACT_VECTOR with
5559 // the same vector and appropriate index.
5560 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
5561 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
5562 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5564 SDValue ExtVec0 = N0->getOperand(i);
5565 SDValue ExtVec1 = N1->getOperand(i);
5567 // First operand is the vector, verify its the same.
5568 if (V != ExtVec0->getOperand(0).getNode() ||
5569 V != ExtVec1->getOperand(0).getNode())
5572 // Second is the constant, verify its correct.
5573 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
5574 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
5576 // For the constant, we want to see all the even or all the odd.
5577 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
5578 || C1->getZExtValue() != nextIndex+1)
5587 // Create VPADDL node.
5588 SelectionDAG &DAG = DCI.DAG;
5589 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5590 DebugLoc DL = N->getDebugLoc();
5592 // Build operand list.
5593 SmallVector<SDValue, 8> Ops;
5594 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
5595 TLI.getPointerTy()));
5597 // Input is the vector.
5600 // Get widened type and narrowed type.
5602 unsigned numElem = VT.getVectorNumElements();
5603 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
5604 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
5605 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
5606 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
5608 assert(0 && "Invalid vector element type for padd optimization.");
5611 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
5612 widenType, &Ops[0], Ops.size());
5613 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
5616 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5617 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5618 /// called with the default operands, and if that fails, with commuted
5620 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5621 TargetLowering::DAGCombinerInfo &DCI,
5622 const ARMSubtarget *Subtarget){
5624 // Attempt to create vpaddl for this add.
5625 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
5626 if (Result.getNode())
5629 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5630 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5631 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5632 if (Result.getNode()) return Result;
5637 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5639 static SDValue PerformADDCombine(SDNode *N,
5640 TargetLowering::DAGCombinerInfo &DCI,
5641 const ARMSubtarget *Subtarget) {
5642 SDValue N0 = N->getOperand(0);
5643 SDValue N1 = N->getOperand(1);
5645 // First try with the default operand order.
5646 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
5647 if (Result.getNode())
5650 // If that didn't work, try again with the operands commuted.
5651 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
5654 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5656 static SDValue PerformSUBCombine(SDNode *N,
5657 TargetLowering::DAGCombinerInfo &DCI) {
5658 SDValue N0 = N->getOperand(0);
5659 SDValue N1 = N->getOperand(1);
5661 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5662 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5663 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5664 if (Result.getNode()) return Result;
5670 /// PerformVMULCombine
5671 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5672 /// special multiplier accumulator forwarding.
5678 static SDValue PerformVMULCombine(SDNode *N,
5679 TargetLowering::DAGCombinerInfo &DCI,
5680 const ARMSubtarget *Subtarget) {
5681 if (!Subtarget->hasVMLxForwarding())
5684 SelectionDAG &DAG = DCI.DAG;
5685 SDValue N0 = N->getOperand(0);
5686 SDValue N1 = N->getOperand(1);
5687 unsigned Opcode = N0.getOpcode();
5688 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5689 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5690 Opcode = N1.getOpcode();
5691 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5692 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5697 EVT VT = N->getValueType(0);
5698 DebugLoc DL = N->getDebugLoc();
5699 SDValue N00 = N0->getOperand(0);
5700 SDValue N01 = N0->getOperand(1);
5701 return DAG.getNode(Opcode, DL, VT,
5702 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5703 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5706 static SDValue PerformMULCombine(SDNode *N,
5707 TargetLowering::DAGCombinerInfo &DCI,
5708 const ARMSubtarget *Subtarget) {
5709 SelectionDAG &DAG = DCI.DAG;
5711 if (Subtarget->isThumb1Only())
5714 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5717 EVT VT = N->getValueType(0);
5718 if (VT.is64BitVector() || VT.is128BitVector())
5719 return PerformVMULCombine(N, DCI, Subtarget);
5723 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5727 uint64_t MulAmt = C->getZExtValue();
5728 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5729 ShiftAmt = ShiftAmt & (32 - 1);
5730 SDValue V = N->getOperand(0);
5731 DebugLoc DL = N->getDebugLoc();
5734 MulAmt >>= ShiftAmt;
5735 if (isPowerOf2_32(MulAmt - 1)) {
5736 // (mul x, 2^N + 1) => (add (shl x, N), x)
5737 Res = DAG.getNode(ISD::ADD, DL, VT,
5738 V, DAG.getNode(ISD::SHL, DL, VT,
5739 V, DAG.getConstant(Log2_32(MulAmt-1),
5741 } else if (isPowerOf2_32(MulAmt + 1)) {
5742 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5743 Res = DAG.getNode(ISD::SUB, DL, VT,
5744 DAG.getNode(ISD::SHL, DL, VT,
5745 V, DAG.getConstant(Log2_32(MulAmt+1),
5752 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5753 DAG.getConstant(ShiftAmt, MVT::i32));
5755 // Do not add new nodes to DAG combiner worklist.
5756 DCI.CombineTo(N, Res, false);
5760 static SDValue PerformANDCombine(SDNode *N,
5761 TargetLowering::DAGCombinerInfo &DCI) {
5763 // Attempt to use immediate-form VBIC
5764 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5765 DebugLoc dl = N->getDebugLoc();
5766 EVT VT = N->getValueType(0);
5767 SelectionDAG &DAG = DCI.DAG;
5769 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5772 APInt SplatBits, SplatUndef;
5773 unsigned SplatBitSize;
5776 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5777 if (SplatBitSize <= 64) {
5779 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5780 SplatUndef.getZExtValue(), SplatBitSize,
5781 DAG, VbicVT, VT.is128BitVector(),
5783 if (Val.getNode()) {
5785 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5786 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5787 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5795 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5796 static SDValue PerformORCombine(SDNode *N,
5797 TargetLowering::DAGCombinerInfo &DCI,
5798 const ARMSubtarget *Subtarget) {
5799 // Attempt to use immediate-form VORR
5800 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5801 DebugLoc dl = N->getDebugLoc();
5802 EVT VT = N->getValueType(0);
5803 SelectionDAG &DAG = DCI.DAG;
5805 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5808 APInt SplatBits, SplatUndef;
5809 unsigned SplatBitSize;
5811 if (BVN && Subtarget->hasNEON() &&
5812 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5813 if (SplatBitSize <= 64) {
5815 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5816 SplatUndef.getZExtValue(), SplatBitSize,
5817 DAG, VorrVT, VT.is128BitVector(),
5819 if (Val.getNode()) {
5821 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5822 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5823 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5828 SDValue N0 = N->getOperand(0);
5829 if (N0.getOpcode() != ISD::AND)
5831 SDValue N1 = N->getOperand(1);
5833 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5834 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5835 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5837 unsigned SplatBitSize;
5840 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5842 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5843 HasAnyUndefs) && !HasAnyUndefs) {
5844 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5846 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5847 HasAnyUndefs) && !HasAnyUndefs &&
5848 SplatBits0 == ~SplatBits1) {
5849 // Canonicalize the vector type to make instruction selection simpler.
5850 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5851 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5852 N0->getOperand(1), N0->getOperand(0),
5854 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5859 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5862 // BFI is only available on V6T2+
5863 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5866 DebugLoc DL = N->getDebugLoc();
5867 // 1) or (and A, mask), val => ARMbfi A, val, mask
5868 // iff (val & mask) == val
5870 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5871 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5872 // && mask == ~mask2
5873 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5874 // && ~mask == mask2
5875 // (i.e., copy a bitfield value into another bitfield of the same width)
5880 SDValue N00 = N0.getOperand(0);
5882 // The value and the mask need to be constants so we can verify this is
5883 // actually a bitfield set. If the mask is 0xffff, we can do better
5884 // via a movt instruction, so don't use BFI in that case.
5885 SDValue MaskOp = N0.getOperand(1);
5886 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5889 unsigned Mask = MaskC->getZExtValue();
5893 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5894 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5896 unsigned Val = N1C->getZExtValue();
5897 if ((Val & ~Mask) != Val)
5900 if (ARM::isBitFieldInvertedMask(Mask)) {
5901 Val >>= CountTrailingZeros_32(~Mask);
5903 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5904 DAG.getConstant(Val, MVT::i32),
5905 DAG.getConstant(Mask, MVT::i32));
5907 // Do not add new nodes to DAG combiner worklist.
5908 DCI.CombineTo(N, Res, false);
5911 } else if (N1.getOpcode() == ISD::AND) {
5912 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5913 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5916 unsigned Mask2 = N11C->getZExtValue();
5918 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5920 if (ARM::isBitFieldInvertedMask(Mask) &&
5922 // The pack halfword instruction works better for masks that fit it,
5923 // so use that when it's available.
5924 if (Subtarget->hasT2ExtractPack() &&
5925 (Mask == 0xffff || Mask == 0xffff0000))
5928 unsigned amt = CountTrailingZeros_32(Mask2);
5929 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5930 DAG.getConstant(amt, MVT::i32));
5931 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5932 DAG.getConstant(Mask, MVT::i32));
5933 // Do not add new nodes to DAG combiner worklist.
5934 DCI.CombineTo(N, Res, false);
5936 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5938 // The pack halfword instruction works better for masks that fit it,
5939 // so use that when it's available.
5940 if (Subtarget->hasT2ExtractPack() &&
5941 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5944 unsigned lsb = CountTrailingZeros_32(Mask);
5945 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5946 DAG.getConstant(lsb, MVT::i32));
5947 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5948 DAG.getConstant(Mask2, MVT::i32));
5949 // Do not add new nodes to DAG combiner worklist.
5950 DCI.CombineTo(N, Res, false);
5955 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5956 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5957 ARM::isBitFieldInvertedMask(~Mask)) {
5958 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5959 // where lsb(mask) == #shamt and masked bits of B are known zero.
5960 SDValue ShAmt = N00.getOperand(1);
5961 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5962 unsigned LSB = CountTrailingZeros_32(Mask);
5966 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5967 DAG.getConstant(~Mask, MVT::i32));
5969 // Do not add new nodes to DAG combiner worklist.
5970 DCI.CombineTo(N, Res, false);
5976 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
5977 /// the bits being cleared by the AND are not demanded by the BFI.
5978 static SDValue PerformBFICombine(SDNode *N,
5979 TargetLowering::DAGCombinerInfo &DCI) {
5980 SDValue N1 = N->getOperand(1);
5981 if (N1.getOpcode() == ISD::AND) {
5982 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5985 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5986 unsigned LSB = CountTrailingZeros_32(~InvMask);
5987 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
5988 unsigned Mask = (1 << Width)-1;
5989 unsigned Mask2 = N11C->getZExtValue();
5990 if ((Mask & (~Mask2)) == 0)
5991 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5992 N->getOperand(0), N1.getOperand(0),
5998 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5999 /// ARMISD::VMOVRRD.
6000 static SDValue PerformVMOVRRDCombine(SDNode *N,
6001 TargetLowering::DAGCombinerInfo &DCI) {
6002 // vmovrrd(vmovdrr x, y) -> x,y
6003 SDValue InDouble = N->getOperand(0);
6004 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
6005 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
6007 // vmovrrd(load f64) -> (load i32), (load i32)
6008 SDNode *InNode = InDouble.getNode();
6009 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
6010 InNode->getValueType(0) == MVT::f64 &&
6011 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
6012 !cast<LoadSDNode>(InNode)->isVolatile()) {
6013 // TODO: Should this be done for non-FrameIndex operands?
6014 LoadSDNode *LD = cast<LoadSDNode>(InNode);
6016 SelectionDAG &DAG = DCI.DAG;
6017 DebugLoc DL = LD->getDebugLoc();
6018 SDValue BasePtr = LD->getBasePtr();
6019 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
6020 LD->getPointerInfo(), LD->isVolatile(),
6021 LD->isNonTemporal(), LD->getAlignment());
6023 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6024 DAG.getConstant(4, MVT::i32));
6025 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
6026 LD->getPointerInfo(), LD->isVolatile(),
6027 LD->isNonTemporal(),
6028 std::min(4U, LD->getAlignment() / 2));
6030 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
6031 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
6032 DCI.RemoveFromWorklist(LD);
6040 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
6041 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
6042 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
6043 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
6044 SDValue Op0 = N->getOperand(0);
6045 SDValue Op1 = N->getOperand(1);
6046 if (Op0.getOpcode() == ISD::BITCAST)
6047 Op0 = Op0.getOperand(0);
6048 if (Op1.getOpcode() == ISD::BITCAST)
6049 Op1 = Op1.getOperand(0);
6050 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
6051 Op0.getNode() == Op1.getNode() &&
6052 Op0.getResNo() == 0 && Op1.getResNo() == 1)
6053 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6054 N->getValueType(0), Op0.getOperand(0));
6058 /// PerformSTORECombine - Target-specific dag combine xforms for
6060 static SDValue PerformSTORECombine(SDNode *N,
6061 TargetLowering::DAGCombinerInfo &DCI) {
6062 // Bitcast an i64 store extracted from a vector to f64.
6063 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6064 StoreSDNode *St = cast<StoreSDNode>(N);
6065 SDValue StVal = St->getValue();
6066 if (!ISD::isNormalStore(St) || St->isVolatile())
6069 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
6070 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
6071 SelectionDAG &DAG = DCI.DAG;
6072 DebugLoc DL = St->getDebugLoc();
6073 SDValue BasePtr = St->getBasePtr();
6074 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
6075 StVal.getNode()->getOperand(0), BasePtr,
6076 St->getPointerInfo(), St->isVolatile(),
6077 St->isNonTemporal(), St->getAlignment());
6079 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6080 DAG.getConstant(4, MVT::i32));
6081 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
6082 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
6083 St->isNonTemporal(),
6084 std::min(4U, St->getAlignment() / 2));
6087 if (StVal.getValueType() != MVT::i64 ||
6088 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6091 SelectionDAG &DAG = DCI.DAG;
6092 DebugLoc dl = StVal.getDebugLoc();
6093 SDValue IntVec = StVal.getOperand(0);
6094 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6095 IntVec.getValueType().getVectorNumElements());
6096 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
6097 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6098 Vec, StVal.getOperand(1));
6099 dl = N->getDebugLoc();
6100 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
6101 // Make the DAGCombiner fold the bitcasts.
6102 DCI.AddToWorklist(Vec.getNode());
6103 DCI.AddToWorklist(ExtElt.getNode());
6104 DCI.AddToWorklist(V.getNode());
6105 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
6106 St->getPointerInfo(), St->isVolatile(),
6107 St->isNonTemporal(), St->getAlignment(),
6111 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
6112 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
6113 /// i64 vector to have f64 elements, since the value can then be loaded
6114 /// directly into a VFP register.
6115 static bool hasNormalLoadOperand(SDNode *N) {
6116 unsigned NumElts = N->getValueType(0).getVectorNumElements();
6117 for (unsigned i = 0; i < NumElts; ++i) {
6118 SDNode *Elt = N->getOperand(i).getNode();
6119 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
6125 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
6126 /// ISD::BUILD_VECTOR.
6127 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
6128 TargetLowering::DAGCombinerInfo &DCI){
6129 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6130 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6131 // into a pair of GPRs, which is fine when the value is used as a scalar,
6132 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
6133 SelectionDAG &DAG = DCI.DAG;
6134 if (N->getNumOperands() == 2) {
6135 SDValue RV = PerformVMOVDRRCombine(N, DAG);
6140 // Load i64 elements as f64 values so that type legalization does not split
6141 // them up into i32 values.
6142 EVT VT = N->getValueType(0);
6143 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
6145 DebugLoc dl = N->getDebugLoc();
6146 SmallVector<SDValue, 8> Ops;
6147 unsigned NumElts = VT.getVectorNumElements();
6148 for (unsigned i = 0; i < NumElts; ++i) {
6149 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
6151 // Make the DAGCombiner fold the bitcast.
6152 DCI.AddToWorklist(V.getNode());
6154 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
6155 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
6156 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
6159 /// PerformInsertEltCombine - Target-specific dag combine xforms for
6160 /// ISD::INSERT_VECTOR_ELT.
6161 static SDValue PerformInsertEltCombine(SDNode *N,
6162 TargetLowering::DAGCombinerInfo &DCI) {
6163 // Bitcast an i64 load inserted into a vector to f64.
6164 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6165 EVT VT = N->getValueType(0);
6166 SDNode *Elt = N->getOperand(1).getNode();
6167 if (VT.getVectorElementType() != MVT::i64 ||
6168 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
6171 SelectionDAG &DAG = DCI.DAG;
6172 DebugLoc dl = N->getDebugLoc();
6173 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6174 VT.getVectorNumElements());
6175 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
6176 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
6177 // Make the DAGCombiner fold the bitcasts.
6178 DCI.AddToWorklist(Vec.getNode());
6179 DCI.AddToWorklist(V.getNode());
6180 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
6181 Vec, V, N->getOperand(2));
6182 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
6185 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
6186 /// ISD::VECTOR_SHUFFLE.
6187 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
6188 // The LLVM shufflevector instruction does not require the shuffle mask
6189 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
6190 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
6191 // operands do not match the mask length, they are extended by concatenating
6192 // them with undef vectors. That is probably the right thing for other
6193 // targets, but for NEON it is better to concatenate two double-register
6194 // size vector operands into a single quad-register size vector. Do that
6195 // transformation here:
6196 // shuffle(concat(v1, undef), concat(v2, undef)) ->
6197 // shuffle(concat(v1, v2), undef)
6198 SDValue Op0 = N->getOperand(0);
6199 SDValue Op1 = N->getOperand(1);
6200 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
6201 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
6202 Op0.getNumOperands() != 2 ||
6203 Op1.getNumOperands() != 2)
6205 SDValue Concat0Op1 = Op0.getOperand(1);
6206 SDValue Concat1Op1 = Op1.getOperand(1);
6207 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
6208 Concat1Op1.getOpcode() != ISD::UNDEF)
6210 // Skip the transformation if any of the types are illegal.
6211 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6212 EVT VT = N->getValueType(0);
6213 if (!TLI.isTypeLegal(VT) ||
6214 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
6215 !TLI.isTypeLegal(Concat1Op1.getValueType()))
6218 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
6219 Op0.getOperand(0), Op1.getOperand(0));
6220 // Translate the shuffle mask.
6221 SmallVector<int, 16> NewMask;
6222 unsigned NumElts = VT.getVectorNumElements();
6223 unsigned HalfElts = NumElts/2;
6224 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6225 for (unsigned n = 0; n < NumElts; ++n) {
6226 int MaskElt = SVN->getMaskElt(n);
6228 if (MaskElt < (int)HalfElts)
6230 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
6231 NewElt = HalfElts + MaskElt - NumElts;
6232 NewMask.push_back(NewElt);
6234 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
6235 DAG.getUNDEF(VT), NewMask.data());
6238 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
6239 /// NEON load/store intrinsics to merge base address updates.
6240 static SDValue CombineBaseUpdate(SDNode *N,
6241 TargetLowering::DAGCombinerInfo &DCI) {
6242 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6245 SelectionDAG &DAG = DCI.DAG;
6246 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
6247 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
6248 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
6249 SDValue Addr = N->getOperand(AddrOpIdx);
6251 // Search for a use of the address operand that is an increment.
6252 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
6253 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
6255 if (User->getOpcode() != ISD::ADD ||
6256 UI.getUse().getResNo() != Addr.getResNo())
6259 // Check that the add is independent of the load/store. Otherwise, folding
6260 // it would create a cycle.
6261 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
6264 // Find the new opcode for the updating load/store.
6266 bool isLaneOp = false;
6267 unsigned NewOpc = 0;
6268 unsigned NumVecs = 0;
6270 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6272 default: assert(0 && "unexpected intrinsic for Neon base update");
6273 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
6275 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
6277 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
6279 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
6281 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
6282 NumVecs = 2; isLaneOp = true; break;
6283 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
6284 NumVecs = 3; isLaneOp = true; break;
6285 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
6286 NumVecs = 4; isLaneOp = true; break;
6287 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
6288 NumVecs = 1; isLoad = false; break;
6289 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
6290 NumVecs = 2; isLoad = false; break;
6291 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
6292 NumVecs = 3; isLoad = false; break;
6293 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
6294 NumVecs = 4; isLoad = false; break;
6295 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
6296 NumVecs = 2; isLoad = false; isLaneOp = true; break;
6297 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6298 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6299 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6300 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6304 switch (N->getOpcode()) {
6305 default: assert(0 && "unexpected opcode for Neon base update");
6306 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6307 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6308 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6312 // Find the size of memory referenced by the load/store.
6315 VecTy = N->getValueType(0);
6317 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6318 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6320 NumBytes /= VecTy.getVectorNumElements();
6322 // If the increment is a constant, it must match the memory ref size.
6323 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6324 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6325 uint64_t IncVal = CInc->getZExtValue();
6326 if (IncVal != NumBytes)
6328 } else if (NumBytes >= 3 * 16) {
6329 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6330 // separate instructions that make it harder to use a non-constant update.
6334 // Create the new updating load/store node.
6336 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6338 for (n = 0; n < NumResultVecs; ++n)
6340 Tys[n++] = MVT::i32;
6341 Tys[n] = MVT::Other;
6342 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6343 SmallVector<SDValue, 8> Ops;
6344 Ops.push_back(N->getOperand(0)); // incoming chain
6345 Ops.push_back(N->getOperand(AddrOpIdx));
6347 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6348 Ops.push_back(N->getOperand(i));
6350 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6351 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6352 Ops.data(), Ops.size(),
6353 MemInt->getMemoryVT(),
6354 MemInt->getMemOperand());
6357 std::vector<SDValue> NewResults;
6358 for (unsigned i = 0; i < NumResultVecs; ++i) {
6359 NewResults.push_back(SDValue(UpdN.getNode(), i));
6361 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6362 DCI.CombineTo(N, NewResults);
6363 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6370 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6371 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6372 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6374 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6375 SelectionDAG &DAG = DCI.DAG;
6376 EVT VT = N->getValueType(0);
6377 // vldN-dup instructions only support 64-bit vectors for N > 1.
6378 if (!VT.is64BitVector())
6381 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6382 SDNode *VLD = N->getOperand(0).getNode();
6383 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6385 unsigned NumVecs = 0;
6386 unsigned NewOpc = 0;
6387 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
6388 if (IntNo == Intrinsic::arm_neon_vld2lane) {
6390 NewOpc = ARMISD::VLD2DUP;
6391 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
6393 NewOpc = ARMISD::VLD3DUP;
6394 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
6396 NewOpc = ARMISD::VLD4DUP;
6401 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6402 // numbers match the load.
6403 unsigned VLDLaneNo =
6404 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6405 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6407 // Ignore uses of the chain result.
6408 if (UI.getUse().getResNo() == NumVecs)
6411 if (User->getOpcode() != ARMISD::VDUPLANE ||
6412 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6416 // Create the vldN-dup node.
6419 for (n = 0; n < NumVecs; ++n)
6421 Tys[n] = MVT::Other;
6422 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6423 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6424 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6425 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6426 Ops, 2, VLDMemInt->getMemoryVT(),
6427 VLDMemInt->getMemOperand());
6430 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6432 unsigned ResNo = UI.getUse().getResNo();
6433 // Ignore uses of the chain result.
6434 if (ResNo == NumVecs)
6437 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6440 // Now the vldN-lane intrinsic is dead except for its chain result.
6441 // Update uses of the chain.
6442 std::vector<SDValue> VLDDupResults;
6443 for (unsigned n = 0; n < NumVecs; ++n)
6444 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6445 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6446 DCI.CombineTo(VLD, VLDDupResults);
6451 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6452 /// ARMISD::VDUPLANE.
6453 static SDValue PerformVDUPLANECombine(SDNode *N,
6454 TargetLowering::DAGCombinerInfo &DCI) {
6455 SDValue Op = N->getOperand(0);
6457 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6458 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6459 if (CombineVLDDUP(N, DCI))
6460 return SDValue(N, 0);
6462 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6463 // redundant. Ignore bit_converts for now; element sizes are checked below.
6464 while (Op.getOpcode() == ISD::BITCAST)
6465 Op = Op.getOperand(0);
6466 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6469 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6470 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6471 // The canonical VMOV for a zero vector uses a 32-bit element size.
6472 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6474 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6476 EVT VT = N->getValueType(0);
6477 if (EltSize > VT.getVectorElementType().getSizeInBits())
6480 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6483 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6484 /// operand of a vector shift operation, where all the elements of the
6485 /// build_vector must have the same constant integer value.
6486 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6487 // Ignore bit_converts.
6488 while (Op.getOpcode() == ISD::BITCAST)
6489 Op = Op.getOperand(0);
6490 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6491 APInt SplatBits, SplatUndef;
6492 unsigned SplatBitSize;
6494 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6495 HasAnyUndefs, ElementBits) ||
6496 SplatBitSize > ElementBits)
6498 Cnt = SplatBits.getSExtValue();
6502 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6503 /// operand of a vector shift left operation. That value must be in the range:
6504 /// 0 <= Value < ElementBits for a left shift; or
6505 /// 0 <= Value <= ElementBits for a long left shift.
6506 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6507 assert(VT.isVector() && "vector shift count is not a vector type");
6508 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6509 if (! getVShiftImm(Op, ElementBits, Cnt))
6511 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6514 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6515 /// operand of a vector shift right operation. For a shift opcode, the value
6516 /// is positive, but for an intrinsic the value count must be negative. The
6517 /// absolute value must be in the range:
6518 /// 1 <= |Value| <= ElementBits for a right shift; or
6519 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6520 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6522 assert(VT.isVector() && "vector shift count is not a vector type");
6523 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6524 if (! getVShiftImm(Op, ElementBits, Cnt))
6528 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6531 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6532 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6533 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6536 // Don't do anything for most intrinsics.
6539 // Vector shifts: check for immediate versions and lower them.
6540 // Note: This is done during DAG combining instead of DAG legalizing because
6541 // the build_vectors for 64-bit vector element shift counts are generally
6542 // not legal, and it is hard to see their values after they get legalized to
6543 // loads from a constant pool.
6544 case Intrinsic::arm_neon_vshifts:
6545 case Intrinsic::arm_neon_vshiftu:
6546 case Intrinsic::arm_neon_vshiftls:
6547 case Intrinsic::arm_neon_vshiftlu:
6548 case Intrinsic::arm_neon_vshiftn:
6549 case Intrinsic::arm_neon_vrshifts:
6550 case Intrinsic::arm_neon_vrshiftu:
6551 case Intrinsic::arm_neon_vrshiftn:
6552 case Intrinsic::arm_neon_vqshifts:
6553 case Intrinsic::arm_neon_vqshiftu:
6554 case Intrinsic::arm_neon_vqshiftsu:
6555 case Intrinsic::arm_neon_vqshiftns:
6556 case Intrinsic::arm_neon_vqshiftnu:
6557 case Intrinsic::arm_neon_vqshiftnsu:
6558 case Intrinsic::arm_neon_vqrshiftns:
6559 case Intrinsic::arm_neon_vqrshiftnu:
6560 case Intrinsic::arm_neon_vqrshiftnsu: {
6561 EVT VT = N->getOperand(1).getValueType();
6563 unsigned VShiftOpc = 0;
6566 case Intrinsic::arm_neon_vshifts:
6567 case Intrinsic::arm_neon_vshiftu:
6568 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6569 VShiftOpc = ARMISD::VSHL;
6572 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6573 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6574 ARMISD::VSHRs : ARMISD::VSHRu);
6579 case Intrinsic::arm_neon_vshiftls:
6580 case Intrinsic::arm_neon_vshiftlu:
6581 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6583 llvm_unreachable("invalid shift count for vshll intrinsic");
6585 case Intrinsic::arm_neon_vrshifts:
6586 case Intrinsic::arm_neon_vrshiftu:
6587 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6591 case Intrinsic::arm_neon_vqshifts:
6592 case Intrinsic::arm_neon_vqshiftu:
6593 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6597 case Intrinsic::arm_neon_vqshiftsu:
6598 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6600 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6602 case Intrinsic::arm_neon_vshiftn:
6603 case Intrinsic::arm_neon_vrshiftn:
6604 case Intrinsic::arm_neon_vqshiftns:
6605 case Intrinsic::arm_neon_vqshiftnu:
6606 case Intrinsic::arm_neon_vqshiftnsu:
6607 case Intrinsic::arm_neon_vqrshiftns:
6608 case Intrinsic::arm_neon_vqrshiftnu:
6609 case Intrinsic::arm_neon_vqrshiftnsu:
6610 // Narrowing shifts require an immediate right shift.
6611 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6613 llvm_unreachable("invalid shift count for narrowing vector shift "
6617 llvm_unreachable("unhandled vector shift");
6621 case Intrinsic::arm_neon_vshifts:
6622 case Intrinsic::arm_neon_vshiftu:
6623 // Opcode already set above.
6625 case Intrinsic::arm_neon_vshiftls:
6626 case Intrinsic::arm_neon_vshiftlu:
6627 if (Cnt == VT.getVectorElementType().getSizeInBits())
6628 VShiftOpc = ARMISD::VSHLLi;
6630 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6631 ARMISD::VSHLLs : ARMISD::VSHLLu);
6633 case Intrinsic::arm_neon_vshiftn:
6634 VShiftOpc = ARMISD::VSHRN; break;
6635 case Intrinsic::arm_neon_vrshifts:
6636 VShiftOpc = ARMISD::VRSHRs; break;
6637 case Intrinsic::arm_neon_vrshiftu:
6638 VShiftOpc = ARMISD::VRSHRu; break;
6639 case Intrinsic::arm_neon_vrshiftn:
6640 VShiftOpc = ARMISD::VRSHRN; break;
6641 case Intrinsic::arm_neon_vqshifts:
6642 VShiftOpc = ARMISD::VQSHLs; break;
6643 case Intrinsic::arm_neon_vqshiftu:
6644 VShiftOpc = ARMISD::VQSHLu; break;
6645 case Intrinsic::arm_neon_vqshiftsu:
6646 VShiftOpc = ARMISD::VQSHLsu; break;
6647 case Intrinsic::arm_neon_vqshiftns:
6648 VShiftOpc = ARMISD::VQSHRNs; break;
6649 case Intrinsic::arm_neon_vqshiftnu:
6650 VShiftOpc = ARMISD::VQSHRNu; break;
6651 case Intrinsic::arm_neon_vqshiftnsu:
6652 VShiftOpc = ARMISD::VQSHRNsu; break;
6653 case Intrinsic::arm_neon_vqrshiftns:
6654 VShiftOpc = ARMISD::VQRSHRNs; break;
6655 case Intrinsic::arm_neon_vqrshiftnu:
6656 VShiftOpc = ARMISD::VQRSHRNu; break;
6657 case Intrinsic::arm_neon_vqrshiftnsu:
6658 VShiftOpc = ARMISD::VQRSHRNsu; break;
6661 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6662 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6665 case Intrinsic::arm_neon_vshiftins: {
6666 EVT VT = N->getOperand(1).getValueType();
6668 unsigned VShiftOpc = 0;
6670 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6671 VShiftOpc = ARMISD::VSLI;
6672 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6673 VShiftOpc = ARMISD::VSRI;
6675 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6678 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6679 N->getOperand(1), N->getOperand(2),
6680 DAG.getConstant(Cnt, MVT::i32));
6683 case Intrinsic::arm_neon_vqrshifts:
6684 case Intrinsic::arm_neon_vqrshiftu:
6685 // No immediate versions of these to check for.
6692 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6693 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6694 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6695 /// vector element shift counts are generally not legal, and it is hard to see
6696 /// their values after they get legalized to loads from a constant pool.
6697 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6698 const ARMSubtarget *ST) {
6699 EVT VT = N->getValueType(0);
6701 // Nothing to be done for scalar shifts.
6702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6703 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6706 assert(ST->hasNEON() && "unexpected vector shift");
6709 switch (N->getOpcode()) {
6710 default: llvm_unreachable("unexpected shift opcode");
6713 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6714 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6715 DAG.getConstant(Cnt, MVT::i32));
6720 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6721 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6722 ARMISD::VSHRs : ARMISD::VSHRu);
6723 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6724 DAG.getConstant(Cnt, MVT::i32));
6730 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6731 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6732 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6733 const ARMSubtarget *ST) {
6734 SDValue N0 = N->getOperand(0);
6736 // Check for sign- and zero-extensions of vector extract operations of 8-
6737 // and 16-bit vector elements. NEON supports these directly. They are
6738 // handled during DAG combining because type legalization will promote them
6739 // to 32-bit types and it is messy to recognize the operations after that.
6740 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6741 SDValue Vec = N0.getOperand(0);
6742 SDValue Lane = N0.getOperand(1);
6743 EVT VT = N->getValueType(0);
6744 EVT EltVT = N0.getValueType();
6745 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6747 if (VT == MVT::i32 &&
6748 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6749 TLI.isTypeLegal(Vec.getValueType()) &&
6750 isa<ConstantSDNode>(Lane)) {
6753 switch (N->getOpcode()) {
6754 default: llvm_unreachable("unexpected opcode");
6755 case ISD::SIGN_EXTEND:
6756 Opc = ARMISD::VGETLANEs;
6758 case ISD::ZERO_EXTEND:
6759 case ISD::ANY_EXTEND:
6760 Opc = ARMISD::VGETLANEu;
6763 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6770 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6771 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6772 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6773 const ARMSubtarget *ST) {
6774 // If the target supports NEON, try to use vmax/vmin instructions for f32
6775 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6776 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6777 // a NaN; only do the transformation when it matches that behavior.
6779 // For now only do this when using NEON for FP operations; if using VFP, it
6780 // is not obvious that the benefit outweighs the cost of switching to the
6782 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6783 N->getValueType(0) != MVT::f32)
6786 SDValue CondLHS = N->getOperand(0);
6787 SDValue CondRHS = N->getOperand(1);
6788 SDValue LHS = N->getOperand(2);
6789 SDValue RHS = N->getOperand(3);
6790 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6792 unsigned Opcode = 0;
6794 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6795 IsReversed = false; // x CC y ? x : y
6796 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6797 IsReversed = true ; // x CC y ? y : x
6811 // If LHS is NaN, an ordered comparison will be false and the result will
6812 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6813 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6814 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6815 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6817 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6818 // will return -0, so vmin can only be used for unsafe math or if one of
6819 // the operands is known to be nonzero.
6820 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6822 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6824 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6833 // If LHS is NaN, an ordered comparison will be false and the result will
6834 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6835 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6836 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6837 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6839 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6840 // will return +0, so vmax can only be used for unsafe math or if one of
6841 // the operands is known to be nonzero.
6842 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6844 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6846 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6852 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6855 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6856 DAGCombinerInfo &DCI) const {
6857 switch (N->getOpcode()) {
6859 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
6860 case ISD::SUB: return PerformSUBCombine(N, DCI);
6861 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6862 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6863 case ISD::AND: return PerformANDCombine(N, DCI);
6864 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6865 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6866 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6867 case ISD::STORE: return PerformSTORECombine(N, DCI);
6868 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6869 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6870 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6871 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6872 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6875 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6876 case ISD::SIGN_EXTEND:
6877 case ISD::ZERO_EXTEND:
6878 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6879 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6880 case ARMISD::VLD2DUP:
6881 case ARMISD::VLD3DUP:
6882 case ARMISD::VLD4DUP:
6883 return CombineBaseUpdate(N, DCI);
6884 case ISD::INTRINSIC_VOID:
6885 case ISD::INTRINSIC_W_CHAIN:
6886 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6887 case Intrinsic::arm_neon_vld1:
6888 case Intrinsic::arm_neon_vld2:
6889 case Intrinsic::arm_neon_vld3:
6890 case Intrinsic::arm_neon_vld4:
6891 case Intrinsic::arm_neon_vld2lane:
6892 case Intrinsic::arm_neon_vld3lane:
6893 case Intrinsic::arm_neon_vld4lane:
6894 case Intrinsic::arm_neon_vst1:
6895 case Intrinsic::arm_neon_vst2:
6896 case Intrinsic::arm_neon_vst3:
6897 case Intrinsic::arm_neon_vst4:
6898 case Intrinsic::arm_neon_vst2lane:
6899 case Intrinsic::arm_neon_vst3lane:
6900 case Intrinsic::arm_neon_vst4lane:
6901 return CombineBaseUpdate(N, DCI);
6909 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6911 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6914 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6915 if (!Subtarget->allowsUnalignedMem())
6918 switch (VT.getSimpleVT().SimpleTy) {
6925 // FIXME: VLD1 etc with standard alignment is legal.
6929 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6934 switch (VT.getSimpleVT().SimpleTy) {
6935 default: return false;
6950 if ((V & (Scale - 1)) != 0)
6953 return V == (V & ((1LL << 5) - 1));
6956 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6957 const ARMSubtarget *Subtarget) {
6964 switch (VT.getSimpleVT().SimpleTy) {
6965 default: return false;
6970 // + imm12 or - imm8
6972 return V == (V & ((1LL << 8) - 1));
6973 return V == (V & ((1LL << 12) - 1));
6976 // Same as ARM mode. FIXME: NEON?
6977 if (!Subtarget->hasVFP2())
6982 return V == (V & ((1LL << 8) - 1));
6986 /// isLegalAddressImmediate - Return true if the integer value can be used
6987 /// as the offset of the target addressing mode for load / store of the
6989 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6990 const ARMSubtarget *Subtarget) {
6997 if (Subtarget->isThumb1Only())
6998 return isLegalT1AddressImmediate(V, VT);
6999 else if (Subtarget->isThumb2())
7000 return isLegalT2AddressImmediate(V, VT, Subtarget);
7005 switch (VT.getSimpleVT().SimpleTy) {
7006 default: return false;
7011 return V == (V & ((1LL << 12) - 1));
7014 return V == (V & ((1LL << 8) - 1));
7017 if (!Subtarget->hasVFP2()) // FIXME: NEON?
7022 return V == (V & ((1LL << 8) - 1));
7026 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
7028 int Scale = AM.Scale;
7032 switch (VT.getSimpleVT().SimpleTy) {
7033 default: return false;
7042 return Scale == 2 || Scale == 4 || Scale == 8;
7045 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7049 // Note, we allow "void" uses (basically, uses that aren't loads or
7050 // stores), because arm allows folding a scale into many arithmetic
7051 // operations. This should be made more precise and revisited later.
7053 // Allow r << imm, but the imm has to be a multiple of two.
7054 if (Scale & 1) return false;
7055 return isPowerOf2_32(Scale);
7059 /// isLegalAddressingMode - Return true if the addressing mode represented
7060 /// by AM is legal for this target, for a load/store of the specified type.
7061 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7062 const Type *Ty) const {
7063 EVT VT = getValueType(Ty, true);
7064 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
7067 // Can never fold addr of global into load/store.
7072 case 0: // no scale reg, must be "r+i" or "r", or "i".
7075 if (Subtarget->isThumb1Only())
7079 // ARM doesn't support any R+R*scale+imm addr modes.
7086 if (Subtarget->isThumb2())
7087 return isLegalT2ScaledAddressingMode(AM, VT);
7089 int Scale = AM.Scale;
7090 switch (VT.getSimpleVT().SimpleTy) {
7091 default: return false;
7095 if (Scale < 0) Scale = -Scale;
7099 return isPowerOf2_32(Scale & ~1);
7103 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7108 // Note, we allow "void" uses (basically, uses that aren't loads or
7109 // stores), because arm allows folding a scale into many arithmetic
7110 // operations. This should be made more precise and revisited later.
7112 // Allow r << imm, but the imm has to be a multiple of two.
7113 if (Scale & 1) return false;
7114 return isPowerOf2_32(Scale);
7121 /// isLegalICmpImmediate - Return true if the specified immediate is legal
7122 /// icmp immediate, that is the target has icmp instructions which can compare
7123 /// a register against the immediate without having to materialize the
7124 /// immediate into a register.
7125 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
7126 if (!Subtarget->isThumb())
7127 return ARM_AM::getSOImmVal(Imm) != -1;
7128 if (Subtarget->isThumb2())
7129 return ARM_AM::getT2SOImmVal(Imm) != -1;
7130 return Imm >= 0 && Imm <= 255;
7133 /// isLegalAddImmediate - Return true if the specified immediate is legal
7134 /// add immediate, that is the target has add instructions which can add
7135 /// a register with the immediate without having to materialize the
7136 /// immediate into a register.
7137 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
7138 return ARM_AM::getSOImmVal(Imm) != -1;
7141 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
7142 bool isSEXTLoad, SDValue &Base,
7143 SDValue &Offset, bool &isInc,
7144 SelectionDAG &DAG) {
7145 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7148 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
7150 Base = Ptr->getOperand(0);
7151 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7152 int RHSC = (int)RHS->getZExtValue();
7153 if (RHSC < 0 && RHSC > -256) {
7154 assert(Ptr->getOpcode() == ISD::ADD);
7156 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7160 isInc = (Ptr->getOpcode() == ISD::ADD);
7161 Offset = Ptr->getOperand(1);
7163 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
7165 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7166 int RHSC = (int)RHS->getZExtValue();
7167 if (RHSC < 0 && RHSC > -0x1000) {
7168 assert(Ptr->getOpcode() == ISD::ADD);
7170 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7171 Base = Ptr->getOperand(0);
7176 if (Ptr->getOpcode() == ISD::ADD) {
7178 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
7179 if (ShOpcVal != ARM_AM::no_shift) {
7180 Base = Ptr->getOperand(1);
7181 Offset = Ptr->getOperand(0);
7183 Base = Ptr->getOperand(0);
7184 Offset = Ptr->getOperand(1);
7189 isInc = (Ptr->getOpcode() == ISD::ADD);
7190 Base = Ptr->getOperand(0);
7191 Offset = Ptr->getOperand(1);
7195 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
7199 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
7200 bool isSEXTLoad, SDValue &Base,
7201 SDValue &Offset, bool &isInc,
7202 SelectionDAG &DAG) {
7203 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7206 Base = Ptr->getOperand(0);
7207 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7208 int RHSC = (int)RHS->getZExtValue();
7209 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
7210 assert(Ptr->getOpcode() == ISD::ADD);
7212 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7214 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
7215 isInc = Ptr->getOpcode() == ISD::ADD;
7216 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
7224 /// getPreIndexedAddressParts - returns true by value, base pointer and
7225 /// offset pointer and addressing mode by reference if the node's address
7226 /// can be legally represented as pre-indexed load / store address.
7228 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7230 ISD::MemIndexedMode &AM,
7231 SelectionDAG &DAG) const {
7232 if (Subtarget->isThumb1Only())
7237 bool isSEXTLoad = false;
7238 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7239 Ptr = LD->getBasePtr();
7240 VT = LD->getMemoryVT();
7241 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7242 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7243 Ptr = ST->getBasePtr();
7244 VT = ST->getMemoryVT();
7249 bool isLegal = false;
7250 if (Subtarget->isThumb2())
7251 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7252 Offset, isInc, DAG);
7254 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7255 Offset, isInc, DAG);
7259 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
7263 /// getPostIndexedAddressParts - returns true by value, base pointer and
7264 /// offset pointer and addressing mode by reference if this node can be
7265 /// combined with a load / store to form a post-indexed load / store.
7266 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
7269 ISD::MemIndexedMode &AM,
7270 SelectionDAG &DAG) const {
7271 if (Subtarget->isThumb1Only())
7276 bool isSEXTLoad = false;
7277 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7278 VT = LD->getMemoryVT();
7279 Ptr = LD->getBasePtr();
7280 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7281 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7282 VT = ST->getMemoryVT();
7283 Ptr = ST->getBasePtr();
7288 bool isLegal = false;
7289 if (Subtarget->isThumb2())
7290 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7293 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7299 // Swap base ptr and offset to catch more post-index load / store when
7300 // it's legal. In Thumb2 mode, offset must be an immediate.
7301 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
7302 !Subtarget->isThumb2())
7303 std::swap(Base, Offset);
7305 // Post-indexed load / store update the base pointer.
7310 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
7314 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7318 const SelectionDAG &DAG,
7319 unsigned Depth) const {
7320 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
7321 switch (Op.getOpcode()) {
7323 case ARMISD::CMOV: {
7324 // Bits are known zero/one if known on the LHS and RHS.
7325 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
7326 if (KnownZero == 0 && KnownOne == 0) return;
7328 APInt KnownZeroRHS, KnownOneRHS;
7329 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
7330 KnownZeroRHS, KnownOneRHS, Depth+1);
7331 KnownZero &= KnownZeroRHS;
7332 KnownOne &= KnownOneRHS;
7338 //===----------------------------------------------------------------------===//
7339 // ARM Inline Assembly Support
7340 //===----------------------------------------------------------------------===//
7342 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
7343 // Looking for "rev" which is V6+.
7344 if (!Subtarget->hasV6Ops())
7347 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
7348 std::string AsmStr = IA->getAsmString();
7349 SmallVector<StringRef, 4> AsmPieces;
7350 SplitString(AsmStr, AsmPieces, ";\n");
7352 switch (AsmPieces.size()) {
7353 default: return false;
7355 AsmStr = AsmPieces[0];
7357 SplitString(AsmStr, AsmPieces, " \t,");
7360 if (AsmPieces.size() == 3 &&
7361 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
7362 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
7363 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
7364 if (Ty && Ty->getBitWidth() == 32)
7365 return IntrinsicLowering::LowerToByteSwap(CI);
7373 /// getConstraintType - Given a constraint letter, return the type of
7374 /// constraint it is for this target.
7375 ARMTargetLowering::ConstraintType
7376 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
7377 if (Constraint.size() == 1) {
7378 switch (Constraint[0]) {
7380 case 'l': return C_RegisterClass;
7381 case 'w': return C_RegisterClass;
7384 if (Constraint == "Uv")
7387 return TargetLowering::getConstraintType(Constraint);
7390 /// Examine constraint type and operand type and determine a weight value.
7391 /// This object must already have been set up with the operand type
7392 /// and the current alternative constraint selected.
7393 TargetLowering::ConstraintWeight
7394 ARMTargetLowering::getSingleConstraintMatchWeight(
7395 AsmOperandInfo &info, const char *constraint) const {
7396 ConstraintWeight weight = CW_Invalid;
7397 Value *CallOperandVal = info.CallOperandVal;
7398 // If we don't have a value, we can't do a match,
7399 // but allow it at the lowest weight.
7400 if (CallOperandVal == NULL)
7402 const Type *type = CallOperandVal->getType();
7403 // Look at the constraint type.
7404 switch (*constraint) {
7406 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7409 if (type->isIntegerTy()) {
7410 if (Subtarget->isThumb())
7411 weight = CW_SpecificReg;
7413 weight = CW_Register;
7417 if (type->isFloatingPointTy())
7418 weight = CW_Register;
7424 std::pair<unsigned, const TargetRegisterClass*>
7425 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7427 if (Constraint.size() == 1) {
7428 // GCC ARM Constraint Letters
7429 switch (Constraint[0]) {
7431 if (Subtarget->isThumb())
7432 return std::make_pair(0U, ARM::tGPRRegisterClass);
7434 return std::make_pair(0U, ARM::GPRRegisterClass);
7436 return std::make_pair(0U, ARM::GPRRegisterClass);
7439 return std::make_pair(0U, ARM::SPRRegisterClass);
7440 if (VT.getSizeInBits() == 64)
7441 return std::make_pair(0U, ARM::DPRRegisterClass);
7442 if (VT.getSizeInBits() == 128)
7443 return std::make_pair(0U, ARM::QPRRegisterClass);
7447 if (StringRef("{cc}").equals_lower(Constraint))
7448 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7450 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7453 std::vector<unsigned> ARMTargetLowering::
7454 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7456 if (Constraint.size() != 1)
7457 return std::vector<unsigned>();
7459 switch (Constraint[0]) { // GCC ARM Constraint Letters
7462 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7463 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7466 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7467 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7468 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
7469 ARM::R12, ARM::LR, 0);
7472 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
7473 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
7474 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
7475 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
7476 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
7477 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
7478 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
7479 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
7480 if (VT.getSizeInBits() == 64)
7481 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
7482 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
7483 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
7484 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
7485 if (VT.getSizeInBits() == 128)
7486 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
7487 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
7491 return std::vector<unsigned>();
7494 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7495 /// vector. If it is invalid, don't add anything to Ops.
7496 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7497 std::string &Constraint,
7498 std::vector<SDValue>&Ops,
7499 SelectionDAG &DAG) const {
7500 SDValue Result(0, 0);
7502 // Currently only support length 1 constraints.
7503 if (Constraint.length() != 1) return;
7505 char ConstraintLetter = Constraint[0];
7506 switch (ConstraintLetter) {
7508 case 'I': case 'J': case 'K': case 'L':
7509 case 'M': case 'N': case 'O':
7510 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7514 int64_t CVal64 = C->getSExtValue();
7515 int CVal = (int) CVal64;
7516 // None of these constraints allow values larger than 32 bits. Check
7517 // that the value fits in an int.
7521 switch (ConstraintLetter) {
7523 if (Subtarget->isThumb1Only()) {
7524 // This must be a constant between 0 and 255, for ADD
7526 if (CVal >= 0 && CVal <= 255)
7528 } else if (Subtarget->isThumb2()) {
7529 // A constant that can be used as an immediate value in a
7530 // data-processing instruction.
7531 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7534 // A constant that can be used as an immediate value in a
7535 // data-processing instruction.
7536 if (ARM_AM::getSOImmVal(CVal) != -1)
7542 if (Subtarget->isThumb()) { // FIXME thumb2
7543 // This must be a constant between -255 and -1, for negated ADD
7544 // immediates. This can be used in GCC with an "n" modifier that
7545 // prints the negated value, for use with SUB instructions. It is
7546 // not useful otherwise but is implemented for compatibility.
7547 if (CVal >= -255 && CVal <= -1)
7550 // This must be a constant between -4095 and 4095. It is not clear
7551 // what this constraint is intended for. Implemented for
7552 // compatibility with GCC.
7553 if (CVal >= -4095 && CVal <= 4095)
7559 if (Subtarget->isThumb1Only()) {
7560 // A 32-bit value where only one byte has a nonzero value. Exclude
7561 // zero to match GCC. This constraint is used by GCC internally for
7562 // constants that can be loaded with a move/shift combination.
7563 // It is not useful otherwise but is implemented for compatibility.
7564 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7566 } else if (Subtarget->isThumb2()) {
7567 // A constant whose bitwise inverse can be used as an immediate
7568 // value in a data-processing instruction. This can be used in GCC
7569 // with a "B" modifier that prints the inverted value, for use with
7570 // BIC and MVN instructions. It is not useful otherwise but is
7571 // implemented for compatibility.
7572 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7575 // A constant whose bitwise inverse can be used as an immediate
7576 // value in a data-processing instruction. This can be used in GCC
7577 // with a "B" modifier that prints the inverted value, for use with
7578 // BIC and MVN instructions. It is not useful otherwise but is
7579 // implemented for compatibility.
7580 if (ARM_AM::getSOImmVal(~CVal) != -1)
7586 if (Subtarget->isThumb1Only()) {
7587 // This must be a constant between -7 and 7,
7588 // for 3-operand ADD/SUB immediate instructions.
7589 if (CVal >= -7 && CVal < 7)
7591 } else if (Subtarget->isThumb2()) {
7592 // A constant whose negation can be used as an immediate value in a
7593 // data-processing instruction. This can be used in GCC with an "n"
7594 // modifier that prints the negated value, for use with SUB
7595 // instructions. It is not useful otherwise but is implemented for
7597 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7600 // A constant whose negation can be used as an immediate value in a
7601 // data-processing instruction. This can be used in GCC with an "n"
7602 // modifier that prints the negated value, for use with SUB
7603 // instructions. It is not useful otherwise but is implemented for
7605 if (ARM_AM::getSOImmVal(-CVal) != -1)
7611 if (Subtarget->isThumb()) { // FIXME thumb2
7612 // This must be a multiple of 4 between 0 and 1020, for
7613 // ADD sp + immediate.
7614 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7617 // A power of two or a constant between 0 and 32. This is used in
7618 // GCC for the shift amount on shifted register operands, but it is
7619 // useful in general for any shift amounts.
7620 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7626 if (Subtarget->isThumb()) { // FIXME thumb2
7627 // This must be a constant between 0 and 31, for shift amounts.
7628 if (CVal >= 0 && CVal <= 31)
7634 if (Subtarget->isThumb()) { // FIXME thumb2
7635 // This must be a multiple of 4 between -508 and 508, for
7636 // ADD/SUB sp = sp + immediate.
7637 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7642 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7646 if (Result.getNode()) {
7647 Ops.push_back(Result);
7650 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7654 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7655 // The ARM target isn't yet aware of offsets.
7659 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7660 APInt Imm = FPImm.bitcastToAPInt();
7661 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7662 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7663 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7665 // We can handle 4 bits of mantissa.
7666 // mantissa = (16+UInt(e:f:g:h))/16.
7667 if (Mantissa & 0x7ffff)
7670 if ((Mantissa & 0xf) != Mantissa)
7673 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7674 if (Exp < -3 || Exp > 4)
7676 Exp = ((Exp+3) & 0x7) ^ 4;
7678 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7681 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7682 APInt Imm = FPImm.bitcastToAPInt();
7683 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7684 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7685 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7687 // We can handle 4 bits of mantissa.
7688 // mantissa = (16+UInt(e:f:g:h))/16.
7689 if (Mantissa & 0xffffffffffffLL)
7692 if ((Mantissa & 0xf) != Mantissa)
7695 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7696 if (Exp < -3 || Exp > 4)
7698 Exp = ((Exp+3) & 0x7) ^ 4;
7700 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7703 bool ARM::isBitFieldInvertedMask(unsigned v) {
7704 if (v == 0xffffffff)
7706 // there can be 1's on either or both "outsides", all the "inside"
7708 unsigned int lsb = 0, msb = 31;
7709 while (v & (1 << msb)) --msb;
7710 while (v & (1 << lsb)) ++lsb;
7711 for (unsigned int i = lsb; i <= msb; ++i) {
7718 /// isFPImmLegal - Returns true if the target can instruction select the
7719 /// specified FP immediate natively. If false, the legalizer will
7720 /// materialize the FP immediate as a load from a constant pool.
7721 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7722 if (!Subtarget->hasVFP3())
7725 return ARM::getVFPf32Imm(Imm) != -1;
7727 return ARM::getVFPf64Imm(Imm) != -1;
7731 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7732 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7733 /// specified in the intrinsic calls.
7734 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7736 unsigned Intrinsic) const {
7737 switch (Intrinsic) {
7738 case Intrinsic::arm_neon_vld1:
7739 case Intrinsic::arm_neon_vld2:
7740 case Intrinsic::arm_neon_vld3:
7741 case Intrinsic::arm_neon_vld4:
7742 case Intrinsic::arm_neon_vld2lane:
7743 case Intrinsic::arm_neon_vld3lane:
7744 case Intrinsic::arm_neon_vld4lane: {
7745 Info.opc = ISD::INTRINSIC_W_CHAIN;
7746 // Conservatively set memVT to the entire set of vectors loaded.
7747 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7748 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7749 Info.ptrVal = I.getArgOperand(0);
7751 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7752 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7753 Info.vol = false; // volatile loads with NEON intrinsics not supported
7754 Info.readMem = true;
7755 Info.writeMem = false;
7758 case Intrinsic::arm_neon_vst1:
7759 case Intrinsic::arm_neon_vst2:
7760 case Intrinsic::arm_neon_vst3:
7761 case Intrinsic::arm_neon_vst4:
7762 case Intrinsic::arm_neon_vst2lane:
7763 case Intrinsic::arm_neon_vst3lane:
7764 case Intrinsic::arm_neon_vst4lane: {
7765 Info.opc = ISD::INTRINSIC_VOID;
7766 // Conservatively set memVT to the entire set of vectors stored.
7767 unsigned NumElts = 0;
7768 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7769 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7770 if (!ArgTy->isVectorTy())
7772 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7774 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7775 Info.ptrVal = I.getArgOperand(0);
7777 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7778 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7779 Info.vol = false; // volatile stores with NEON intrinsics not supported
7780 Info.readMem = false;
7781 Info.writeMem = true;
7784 case Intrinsic::arm_strexd: {
7785 Info.opc = ISD::INTRINSIC_W_CHAIN;
7786 Info.memVT = MVT::i64;
7787 Info.ptrVal = I.getArgOperand(2);
7791 Info.readMem = false;
7792 Info.writeMem = true;
7795 case Intrinsic::arm_ldrexd: {
7796 Info.opc = ISD::INTRINSIC_W_CHAIN;
7797 Info.memVT = MVT::i64;
7798 Info.ptrVal = I.getArgOperand(0);
7802 Info.readMem = true;
7803 Info.writeMem = false;