1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
76 EVT PromotedBitwiseVT) {
77 if (VT != PromotedLdStVT) {
78 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
79 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
80 PromotedLdStVT.getSimpleVT());
82 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
83 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
84 PromotedLdStVT.getSimpleVT());
87 EVT ElemTy = VT.getVectorElementType();
88 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
89 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
91 if (ElemTy != MVT::i32) {
92 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
97 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
98 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
99 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
100 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
101 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
103 if (VT.isInteger()) {
104 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
105 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
107 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
108 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
109 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
110 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
111 setTruncStoreAction(VT.getSimpleVT(),
112 (MVT::SimpleValueType)InnerVT, Expand);
114 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
116 // Promote all bit-wise operations.
117 if (VT.isInteger() && VT != PromotedBitwiseVT) {
118 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
124 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
125 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
126 PromotedBitwiseVT.getSimpleVT());
129 // Neon does not support vector divide/remainder operations.
130 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
134 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
138 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
139 addRegisterClass(VT, ARM::DPRRegisterClass);
140 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
143 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::QPRRegisterClass);
145 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
148 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
149 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
150 return new TargetLoweringObjectFileMachO();
152 return new ARMElfTargetObjectFile();
155 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<ARMSubtarget>();
158 RegInfo = TM.getRegisterInfo();
159 Itins = TM.getInstrItineraryData();
161 if (Subtarget->isTargetDarwin()) {
162 // Uses VFP for Thumb libfuncs if available.
163 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
164 // Single-precision floating-point arithmetic.
165 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
166 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
167 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
168 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
170 // Double-precision floating-point arithmetic.
171 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
172 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
173 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
174 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
176 // Single-precision comparisons.
177 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
178 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
179 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
180 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
181 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
182 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
183 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
184 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
186 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
195 // Double-precision comparisons.
196 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
197 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
198 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
199 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
200 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
201 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
202 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
203 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
205 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
214 // Floating-point to integer conversions.
215 // i64 conversions are done via library routines even when generating VFP
216 // instructions, so use the same ones.
217 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
218 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
219 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
220 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
222 // Conversions between floating types.
223 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
224 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
226 // Integer to floating-point conversions.
227 // i64 conversions are done via library routines even when generating VFP
228 // instructions, so use the same ones.
229 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
230 // e.g., __floatunsidf vs. __floatunssidfvfp.
231 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
232 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
233 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
234 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
238 // These libcalls are not available in 32-bit.
239 setLibcallName(RTLIB::SHL_I128, 0);
240 setLibcallName(RTLIB::SRL_I128, 0);
241 setLibcallName(RTLIB::SRA_I128, 0);
243 if (Subtarget->isAAPCS_ABI()) {
244 // Double-precision floating-point arithmetic helper functions
245 // RTABI chapter 4.1.2, Table 2
246 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
247 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
248 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
249 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
250 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
251 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
252 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
253 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
255 // Double-precision floating-point comparison helper functions
256 // RTABI chapter 4.1.2, Table 3
257 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
258 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
259 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
260 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
261 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
262 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
263 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
264 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
265 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
266 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
267 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
268 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
269 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
270 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
271 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
272 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
273 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
282 // Single-precision floating-point arithmetic helper functions
283 // RTABI chapter 4.1.2, Table 4
284 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
285 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
286 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
287 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
288 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
289 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
293 // Single-precision floating-point comparison helper functions
294 // RTABI chapter 4.1.2, Table 5
295 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
296 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
297 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
298 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
299 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
300 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
301 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
302 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
303 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
304 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
305 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
306 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
307 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
308 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
309 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
310 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
311 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
320 // Floating-point to integer conversions.
321 // RTABI chapter 4.1.2, Table 6
322 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
323 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
324 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
325 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
326 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
327 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
328 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
329 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
330 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
339 // Conversions between floating types.
340 // RTABI chapter 4.1.2, Table 7
341 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
342 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
343 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
344 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
346 // Integer to floating-point conversions.
347 // RTABI chapter 4.1.2, Table 8
348 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
349 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
350 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
351 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
352 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
353 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
354 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
355 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
356 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
365 // Long long helper functions
366 // RTABI chapter 4.2, Table 9
367 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
368 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
369 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
370 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
371 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
372 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
373 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
380 // Integer division functions
381 // RTABI chapter 4.3.1
382 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
383 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
384 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
385 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
386 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
387 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
388 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
396 if (Subtarget->isThumb1Only())
397 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
399 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
400 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
401 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
402 if (!Subtarget->isFPOnlySP())
403 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
405 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
408 if (Subtarget->hasNEON()) {
409 addDRTypeForNEON(MVT::v2f32);
410 addDRTypeForNEON(MVT::v8i8);
411 addDRTypeForNEON(MVT::v4i16);
412 addDRTypeForNEON(MVT::v2i32);
413 addDRTypeForNEON(MVT::v1i64);
415 addQRTypeForNEON(MVT::v4f32);
416 addQRTypeForNEON(MVT::v2f64);
417 addQRTypeForNEON(MVT::v16i8);
418 addQRTypeForNEON(MVT::v8i16);
419 addQRTypeForNEON(MVT::v4i32);
420 addQRTypeForNEON(MVT::v2i64);
422 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
423 // neither Neon nor VFP support any arithmetic operations on it.
424 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
425 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
426 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
427 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
428 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
429 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
430 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
431 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
432 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
434 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
435 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
436 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
437 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
438 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
439 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
441 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
442 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
443 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
444 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
445 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
446 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
447 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
449 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
451 // Neon does not support some operations on v1i64 and v2i64 types.
452 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
453 // Custom handling for some quad-vector types to detect VMULL.
454 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
455 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
456 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
457 // Custom handling for some vector types to avoid expensive expansions
458 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
459 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
460 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
461 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
462 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
463 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
465 setTargetDAGCombine(ISD::INTRINSIC_VOID);
466 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
467 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
468 setTargetDAGCombine(ISD::SHL);
469 setTargetDAGCombine(ISD::SRL);
470 setTargetDAGCombine(ISD::SRA);
471 setTargetDAGCombine(ISD::SIGN_EXTEND);
472 setTargetDAGCombine(ISD::ZERO_EXTEND);
473 setTargetDAGCombine(ISD::ANY_EXTEND);
474 setTargetDAGCombine(ISD::SELECT_CC);
475 setTargetDAGCombine(ISD::BUILD_VECTOR);
476 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
477 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
478 setTargetDAGCombine(ISD::STORE);
481 computeRegisterProperties();
483 // ARM does not have f32 extending load.
484 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
486 // ARM does not have i1 sign extending load.
487 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
489 // ARM supports all 4 flavors of integer indexed load / store.
490 if (!Subtarget->isThumb1Only()) {
491 for (unsigned im = (unsigned)ISD::PRE_INC;
492 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
493 setIndexedLoadAction(im, MVT::i1, Legal);
494 setIndexedLoadAction(im, MVT::i8, Legal);
495 setIndexedLoadAction(im, MVT::i16, Legal);
496 setIndexedLoadAction(im, MVT::i32, Legal);
497 setIndexedStoreAction(im, MVT::i1, Legal);
498 setIndexedStoreAction(im, MVT::i8, Legal);
499 setIndexedStoreAction(im, MVT::i16, Legal);
500 setIndexedStoreAction(im, MVT::i32, Legal);
504 // i64 operation support.
505 if (Subtarget->isThumb1Only()) {
506 setOperationAction(ISD::MUL, MVT::i64, Expand);
507 setOperationAction(ISD::MULHU, MVT::i32, Expand);
508 setOperationAction(ISD::MULHS, MVT::i32, Expand);
509 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
510 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
512 setOperationAction(ISD::MUL, MVT::i64, Expand);
513 setOperationAction(ISD::MULHU, MVT::i32, Expand);
514 if (!Subtarget->hasV6Ops())
515 setOperationAction(ISD::MULHS, MVT::i32, Expand);
517 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
518 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
519 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
520 setOperationAction(ISD::SRL, MVT::i64, Custom);
521 setOperationAction(ISD::SRA, MVT::i64, Custom);
523 // ARM does not have ROTL.
524 setOperationAction(ISD::ROTL, MVT::i32, Expand);
525 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
526 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
527 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
528 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
530 // Only ARMv6 has BSWAP.
531 if (!Subtarget->hasV6Ops())
532 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
534 // These are expanded into libcalls.
535 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
536 // v7M has a hardware divider
537 setOperationAction(ISD::SDIV, MVT::i32, Expand);
538 setOperationAction(ISD::UDIV, MVT::i32, Expand);
540 setOperationAction(ISD::SREM, MVT::i32, Expand);
541 setOperationAction(ISD::UREM, MVT::i32, Expand);
542 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
543 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
545 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
546 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
547 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
548 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
549 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
551 setOperationAction(ISD::TRAP, MVT::Other, Legal);
553 // Use the default implementation.
554 setOperationAction(ISD::VASTART, MVT::Other, Custom);
555 setOperationAction(ISD::VAARG, MVT::Other, Expand);
556 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
557 setOperationAction(ISD::VAEND, MVT::Other, Expand);
558 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
559 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
560 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
561 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
562 setExceptionPointerRegister(ARM::R0);
563 setExceptionSelectorRegister(ARM::R1);
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
566 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
567 // the default expansion.
568 if (Subtarget->hasDataBarrier() ||
569 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
570 // membarrier needs custom lowering; the rest are legal and handled
572 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
574 // Set them all for expansion, which will force libcalls.
575 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
576 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
577 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
578 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
579 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
580 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
581 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
588 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
589 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
590 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
591 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
592 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
600 // Since the libcalls include locking, fold in the fences
601 setShouldFoldAtomicFences(true);
603 // 64-bit versions are always libcalls (for now)
604 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
606 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
608 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
609 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
611 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
613 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
615 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
616 if (!Subtarget->hasV6Ops()) {
617 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
618 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
620 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
622 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
623 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
624 // iff target supports vfp2.
625 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
626 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
629 // We want to custom lower some of our intrinsics.
630 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
631 if (Subtarget->isTargetDarwin()) {
632 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
633 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
634 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
637 setOperationAction(ISD::SETCC, MVT::i32, Expand);
638 setOperationAction(ISD::SETCC, MVT::f32, Expand);
639 setOperationAction(ISD::SETCC, MVT::f64, Expand);
640 setOperationAction(ISD::SELECT, MVT::i32, Custom);
641 setOperationAction(ISD::SELECT, MVT::f32, Custom);
642 setOperationAction(ISD::SELECT, MVT::f64, Custom);
643 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
644 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
645 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
647 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
648 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
649 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
650 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
651 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
653 // We don't support sin/cos/fmod/copysign/pow
654 setOperationAction(ISD::FSIN, MVT::f64, Expand);
655 setOperationAction(ISD::FSIN, MVT::f32, Expand);
656 setOperationAction(ISD::FCOS, MVT::f32, Expand);
657 setOperationAction(ISD::FCOS, MVT::f64, Expand);
658 setOperationAction(ISD::FREM, MVT::f64, Expand);
659 setOperationAction(ISD::FREM, MVT::f32, Expand);
660 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 setOperationAction(ISD::FPOW, MVT::f64, Expand);
665 setOperationAction(ISD::FPOW, MVT::f32, Expand);
667 // Various VFP goodness
668 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
669 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
670 if (Subtarget->hasVFP2()) {
671 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
672 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
673 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
674 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
676 // Special handling for half-precision FP.
677 if (!Subtarget->hasFP16()) {
678 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
679 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
683 // We have target-specific dag combine patterns for the following nodes:
684 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
685 setTargetDAGCombine(ISD::ADD);
686 setTargetDAGCombine(ISD::SUB);
687 setTargetDAGCombine(ISD::MUL);
689 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
690 setTargetDAGCombine(ISD::OR);
691 if (Subtarget->hasNEON())
692 setTargetDAGCombine(ISD::AND);
694 setStackPointerRegisterToSaveRestore(ARM::SP);
696 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
697 setSchedulingPreference(Sched::RegPressure);
699 setSchedulingPreference(Sched::Hybrid);
701 //// temporary - rewrite interface to use type
702 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
704 // On ARM arguments smaller than 4 bytes are extended, so all arguments
705 // are at least 4 bytes aligned.
706 setMinStackArgumentAlignment(4);
708 benefitFromCodePlacementOpt = true;
711 // FIXME: It might make sense to define the representative register class as the
712 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
713 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
714 // SPR's representative would be DPR_VFP2. This should work well if register
715 // pressure tracking were modified such that a register use would increment the
716 // pressure of the register class's representative and all of it's super
717 // classes' representatives transitively. We have not implemented this because
718 // of the difficulty prior to coalescing of modeling operand register classes
719 // due to the common occurence of cross class copies and subregister insertions
721 std::pair<const TargetRegisterClass*, uint8_t>
722 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
723 const TargetRegisterClass *RRC = 0;
725 switch (VT.getSimpleVT().SimpleTy) {
727 return TargetLowering::findRepresentativeClass(VT);
728 // Use DPR as representative register class for all floating point
729 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
730 // the cost is 1 for both f32 and f64.
731 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
732 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
733 RRC = ARM::DPRRegisterClass;
734 // When NEON is used for SP, only half of the register file is available
735 // because operations that define both SP and DP results will be constrained
736 // to the VFP2 class (D0-D15). We currently model this constraint prior to
737 // coalescing by double-counting the SP regs. See the FIXME above.
738 if (Subtarget->useNEONForSinglePrecisionFP())
741 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
742 case MVT::v4f32: case MVT::v2f64:
743 RRC = ARM::DPRRegisterClass;
747 RRC = ARM::DPRRegisterClass;
751 RRC = ARM::DPRRegisterClass;
755 return std::make_pair(RRC, Cost);
758 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
761 case ARMISD::Wrapper: return "ARMISD::Wrapper";
762 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
763 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
764 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
765 case ARMISD::CALL: return "ARMISD::CALL";
766 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
767 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
768 case ARMISD::tCALL: return "ARMISD::tCALL";
769 case ARMISD::BRCOND: return "ARMISD::BRCOND";
770 case ARMISD::BR_JT: return "ARMISD::BR_JT";
771 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
772 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
773 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
774 case ARMISD::CMP: return "ARMISD::CMP";
775 case ARMISD::CMPZ: return "ARMISD::CMPZ";
776 case ARMISD::CMPFP: return "ARMISD::CMPFP";
777 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
778 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
779 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
780 case ARMISD::CMOV: return "ARMISD::CMOV";
782 case ARMISD::RBIT: return "ARMISD::RBIT";
784 case ARMISD::FTOSI: return "ARMISD::FTOSI";
785 case ARMISD::FTOUI: return "ARMISD::FTOUI";
786 case ARMISD::SITOF: return "ARMISD::SITOF";
787 case ARMISD::UITOF: return "ARMISD::UITOF";
789 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
790 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
791 case ARMISD::RRX: return "ARMISD::RRX";
793 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
794 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
796 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
797 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
798 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
800 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
802 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
804 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
806 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
807 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
809 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
811 case ARMISD::VCEQ: return "ARMISD::VCEQ";
812 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
813 case ARMISD::VCGE: return "ARMISD::VCGE";
814 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
815 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
816 case ARMISD::VCGEU: return "ARMISD::VCGEU";
817 case ARMISD::VCGT: return "ARMISD::VCGT";
818 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
819 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
820 case ARMISD::VCGTU: return "ARMISD::VCGTU";
821 case ARMISD::VTST: return "ARMISD::VTST";
823 case ARMISD::VSHL: return "ARMISD::VSHL";
824 case ARMISD::VSHRs: return "ARMISD::VSHRs";
825 case ARMISD::VSHRu: return "ARMISD::VSHRu";
826 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
827 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
828 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
829 case ARMISD::VSHRN: return "ARMISD::VSHRN";
830 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
831 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
832 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
833 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
834 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
835 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
836 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
837 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
838 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
839 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
840 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
841 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
842 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
843 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
844 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
845 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
846 case ARMISD::VDUP: return "ARMISD::VDUP";
847 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
848 case ARMISD::VEXT: return "ARMISD::VEXT";
849 case ARMISD::VREV64: return "ARMISD::VREV64";
850 case ARMISD::VREV32: return "ARMISD::VREV32";
851 case ARMISD::VREV16: return "ARMISD::VREV16";
852 case ARMISD::VZIP: return "ARMISD::VZIP";
853 case ARMISD::VUZP: return "ARMISD::VUZP";
854 case ARMISD::VTRN: return "ARMISD::VTRN";
855 case ARMISD::VTBL1: return "ARMISD::VTBL1";
856 case ARMISD::VTBL2: return "ARMISD::VTBL2";
857 case ARMISD::VTBL3: return "ARMISD::VTBL3";
858 case ARMISD::VTBL4: return "ARMISD::VTBL4";
859 case ARMISD::VMULLs: return "ARMISD::VMULLs";
860 case ARMISD::VMULLu: return "ARMISD::VMULLu";
861 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
862 case ARMISD::FMAX: return "ARMISD::FMAX";
863 case ARMISD::FMIN: return "ARMISD::FMIN";
864 case ARMISD::BFI: return "ARMISD::BFI";
865 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
866 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
867 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
868 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
869 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
870 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
871 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
872 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
873 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
874 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
875 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
876 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
877 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
878 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
879 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
880 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
881 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
882 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
883 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
884 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
885 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
886 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
890 /// getRegClassFor - Return the register class that should be used for the
891 /// specified value type.
892 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
893 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
894 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
895 // load / store 4 to 8 consecutive D registers.
896 if (Subtarget->hasNEON()) {
897 if (VT == MVT::v4i64)
898 return ARM::QQPRRegisterClass;
899 else if (VT == MVT::v8i64)
900 return ARM::QQQQPRRegisterClass;
902 return TargetLowering::getRegClassFor(VT);
905 // Create a fast isel object.
907 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
908 return ARM::createFastISel(funcInfo);
911 /// getFunctionAlignment - Return the Log2 alignment of this function.
912 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
913 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
916 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
917 /// be used for loads / stores from the global.
918 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
919 return (Subtarget->isThumb1Only() ? 127 : 4095);
922 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
923 unsigned NumVals = N->getNumValues();
925 return Sched::RegPressure;
927 for (unsigned i = 0; i != NumVals; ++i) {
928 EVT VT = N->getValueType(i);
929 if (VT == MVT::Glue || VT == MVT::Other)
931 if (VT.isFloatingPoint() || VT.isVector())
932 return Sched::Latency;
935 if (!N->isMachineOpcode())
936 return Sched::RegPressure;
938 // Load are scheduled for latency even if there instruction itinerary
940 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
941 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
943 if (TID.getNumDefs() == 0)
944 return Sched::RegPressure;
945 if (!Itins->isEmpty() &&
946 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
947 return Sched::Latency;
949 return Sched::RegPressure;
952 //===----------------------------------------------------------------------===//
954 //===----------------------------------------------------------------------===//
956 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
957 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
959 default: llvm_unreachable("Unknown condition code!");
960 case ISD::SETNE: return ARMCC::NE;
961 case ISD::SETEQ: return ARMCC::EQ;
962 case ISD::SETGT: return ARMCC::GT;
963 case ISD::SETGE: return ARMCC::GE;
964 case ISD::SETLT: return ARMCC::LT;
965 case ISD::SETLE: return ARMCC::LE;
966 case ISD::SETUGT: return ARMCC::HI;
967 case ISD::SETUGE: return ARMCC::HS;
968 case ISD::SETULT: return ARMCC::LO;
969 case ISD::SETULE: return ARMCC::LS;
973 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
974 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
975 ARMCC::CondCodes &CondCode2) {
976 CondCode2 = ARMCC::AL;
978 default: llvm_unreachable("Unknown FP condition!");
980 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
982 case ISD::SETOGT: CondCode = ARMCC::GT; break;
984 case ISD::SETOGE: CondCode = ARMCC::GE; break;
985 case ISD::SETOLT: CondCode = ARMCC::MI; break;
986 case ISD::SETOLE: CondCode = ARMCC::LS; break;
987 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
988 case ISD::SETO: CondCode = ARMCC::VC; break;
989 case ISD::SETUO: CondCode = ARMCC::VS; break;
990 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
991 case ISD::SETUGT: CondCode = ARMCC::HI; break;
992 case ISD::SETUGE: CondCode = ARMCC::PL; break;
994 case ISD::SETULT: CondCode = ARMCC::LT; break;
996 case ISD::SETULE: CondCode = ARMCC::LE; break;
998 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1002 //===----------------------------------------------------------------------===//
1003 // Calling Convention Implementation
1004 //===----------------------------------------------------------------------===//
1006 #include "ARMGenCallingConv.inc"
1008 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1009 /// given CallingConvention value.
1010 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1012 bool isVarArg) const {
1015 llvm_unreachable("Unsupported calling convention");
1016 case CallingConv::Fast:
1017 if (Subtarget->hasVFP2() && !isVarArg) {
1018 if (!Subtarget->isAAPCS_ABI())
1019 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1020 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1021 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1024 case CallingConv::C: {
1025 // Use target triple & subtarget features to do actual dispatch.
1026 if (!Subtarget->isAAPCS_ABI())
1027 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1028 else if (Subtarget->hasVFP2() &&
1029 FloatABIType == FloatABI::Hard && !isVarArg)
1030 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1031 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1033 case CallingConv::ARM_AAPCS_VFP:
1034 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1035 case CallingConv::ARM_AAPCS:
1036 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1037 case CallingConv::ARM_APCS:
1038 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1042 /// LowerCallResult - Lower the result values of a call into the
1043 /// appropriate copies out of appropriate physical registers.
1045 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1046 CallingConv::ID CallConv, bool isVarArg,
1047 const SmallVectorImpl<ISD::InputArg> &Ins,
1048 DebugLoc dl, SelectionDAG &DAG,
1049 SmallVectorImpl<SDValue> &InVals) const {
1051 // Assign locations to each value returned by this call.
1052 SmallVector<CCValAssign, 16> RVLocs;
1053 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1054 RVLocs, *DAG.getContext());
1055 CCInfo.AnalyzeCallResult(Ins,
1056 CCAssignFnForNode(CallConv, /* Return*/ true,
1059 // Copy all of the result registers out of their specified physreg.
1060 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1061 CCValAssign VA = RVLocs[i];
1064 if (VA.needsCustom()) {
1065 // Handle f64 or half of a v2f64.
1066 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1068 Chain = Lo.getValue(1);
1069 InFlag = Lo.getValue(2);
1070 VA = RVLocs[++i]; // skip ahead to next loc
1071 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1073 Chain = Hi.getValue(1);
1074 InFlag = Hi.getValue(2);
1075 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1077 if (VA.getLocVT() == MVT::v2f64) {
1078 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1079 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1080 DAG.getConstant(0, MVT::i32));
1082 VA = RVLocs[++i]; // skip ahead to next loc
1083 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1084 Chain = Lo.getValue(1);
1085 InFlag = Lo.getValue(2);
1086 VA = RVLocs[++i]; // skip ahead to next loc
1087 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1088 Chain = Hi.getValue(1);
1089 InFlag = Hi.getValue(2);
1090 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1091 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1092 DAG.getConstant(1, MVT::i32));
1095 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1097 Chain = Val.getValue(1);
1098 InFlag = Val.getValue(2);
1101 switch (VA.getLocInfo()) {
1102 default: llvm_unreachable("Unknown loc info!");
1103 case CCValAssign::Full: break;
1104 case CCValAssign::BCvt:
1105 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1109 InVals.push_back(Val);
1115 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1116 /// by "Src" to address "Dst" of size "Size". Alignment information is
1117 /// specified by the specific parameter attribute. The copy will be passed as
1118 /// a byval function parameter.
1119 /// Sometimes what we are copying is the end of a larger object, the part that
1120 /// does not fit in registers.
1122 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1123 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1125 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1126 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1127 /*isVolatile=*/false, /*AlwaysInline=*/false,
1128 MachinePointerInfo(0), MachinePointerInfo(0));
1131 /// LowerMemOpCallTo - Store the argument to the stack.
1133 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1134 SDValue StackPtr, SDValue Arg,
1135 DebugLoc dl, SelectionDAG &DAG,
1136 const CCValAssign &VA,
1137 ISD::ArgFlagsTy Flags) const {
1138 unsigned LocMemOffset = VA.getLocMemOffset();
1139 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1140 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1141 if (Flags.isByVal())
1142 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1144 return DAG.getStore(Chain, dl, Arg, PtrOff,
1145 MachinePointerInfo::getStack(LocMemOffset),
1149 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1150 SDValue Chain, SDValue &Arg,
1151 RegsToPassVector &RegsToPass,
1152 CCValAssign &VA, CCValAssign &NextVA,
1154 SmallVector<SDValue, 8> &MemOpChains,
1155 ISD::ArgFlagsTy Flags) const {
1157 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1158 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1159 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1161 if (NextVA.isRegLoc())
1162 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1164 assert(NextVA.isMemLoc());
1165 if (StackPtr.getNode() == 0)
1166 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1168 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1174 /// LowerCall - Lowering a call into a callseq_start <-
1175 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1178 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1179 CallingConv::ID CallConv, bool isVarArg,
1181 const SmallVectorImpl<ISD::OutputArg> &Outs,
1182 const SmallVectorImpl<SDValue> &OutVals,
1183 const SmallVectorImpl<ISD::InputArg> &Ins,
1184 DebugLoc dl, SelectionDAG &DAG,
1185 SmallVectorImpl<SDValue> &InVals) const {
1186 MachineFunction &MF = DAG.getMachineFunction();
1187 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1188 bool IsSibCall = false;
1189 // Temporarily disable tail calls so things don't break.
1190 if (!EnableARMTailCalls)
1193 // Check if it's really possible to do a tail call.
1194 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1195 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1196 Outs, OutVals, Ins, DAG);
1197 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1198 // detected sibcalls.
1205 // Analyze operands of the call, assigning locations to each operand.
1206 SmallVector<CCValAssign, 16> ArgLocs;
1207 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1209 CCInfo.AnalyzeCallOperands(Outs,
1210 CCAssignFnForNode(CallConv, /* Return*/ false,
1213 // Get a count of how many bytes are to be pushed on the stack.
1214 unsigned NumBytes = CCInfo.getNextStackOffset();
1216 // For tail calls, memory operands are available in our caller's stack.
1220 // Adjust the stack pointer for the new arguments...
1221 // These operations are automatically eliminated by the prolog/epilog pass
1223 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1225 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1227 RegsToPassVector RegsToPass;
1228 SmallVector<SDValue, 8> MemOpChains;
1230 // Walk the register/memloc assignments, inserting copies/loads. In the case
1231 // of tail call optimization, arguments are handled later.
1232 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1234 ++i, ++realArgIdx) {
1235 CCValAssign &VA = ArgLocs[i];
1236 SDValue Arg = OutVals[realArgIdx];
1237 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1238 bool isByVal = Flags.isByVal();
1240 // Promote the value if needed.
1241 switch (VA.getLocInfo()) {
1242 default: llvm_unreachable("Unknown loc info!");
1243 case CCValAssign::Full: break;
1244 case CCValAssign::SExt:
1245 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1247 case CCValAssign::ZExt:
1248 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1250 case CCValAssign::AExt:
1251 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1253 case CCValAssign::BCvt:
1254 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1258 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1259 if (VA.needsCustom()) {
1260 if (VA.getLocVT() == MVT::v2f64) {
1261 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1262 DAG.getConstant(0, MVT::i32));
1263 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1264 DAG.getConstant(1, MVT::i32));
1266 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1267 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1269 VA = ArgLocs[++i]; // skip ahead to next loc
1270 if (VA.isRegLoc()) {
1271 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1272 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1274 assert(VA.isMemLoc());
1276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1277 dl, DAG, VA, Flags));
1280 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1281 StackPtr, MemOpChains, Flags);
1283 } else if (VA.isRegLoc()) {
1284 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1285 } else if (!IsSibCall || isByVal) {
1286 assert(VA.isMemLoc());
1288 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1289 dl, DAG, VA, Flags));
1293 if (!MemOpChains.empty())
1294 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1295 &MemOpChains[0], MemOpChains.size());
1297 // Build a sequence of copy-to-reg nodes chained together with token chain
1298 // and flag operands which copy the outgoing args into the appropriate regs.
1300 // Tail call byval lowering might overwrite argument registers so in case of
1301 // tail call optimization the copies to registers are lowered later.
1303 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1304 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1305 RegsToPass[i].second, InFlag);
1306 InFlag = Chain.getValue(1);
1309 // For tail calls lower the arguments to the 'real' stack slot.
1311 // Force all the incoming stack arguments to be loaded from the stack
1312 // before any new outgoing arguments are stored to the stack, because the
1313 // outgoing stack slots may alias the incoming argument stack slots, and
1314 // the alias isn't otherwise explicit. This is slightly more conservative
1315 // than necessary, because it means that each store effectively depends
1316 // on every argument instead of just those arguments it would clobber.
1318 // Do not flag preceeding copytoreg stuff together with the following stuff.
1320 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1321 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1322 RegsToPass[i].second, InFlag);
1323 InFlag = Chain.getValue(1);
1328 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1329 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1330 // node so that legalize doesn't hack it.
1331 bool isDirect = false;
1332 bool isARMFunc = false;
1333 bool isLocalARMFunc = false;
1334 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1336 if (EnableARMLongCalls) {
1337 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1338 && "long-calls with non-static relocation model!");
1339 // Handle a global address or an external symbol. If it's not one of
1340 // those, the target's already in a register, so we don't need to do
1342 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1343 const GlobalValue *GV = G->getGlobal();
1344 // Create a constant pool entry for the callee address
1345 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1346 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1349 // Get the address of the callee into a register
1350 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1351 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1352 Callee = DAG.getLoad(getPointerTy(), dl,
1353 DAG.getEntryNode(), CPAddr,
1354 MachinePointerInfo::getConstantPool(),
1356 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1357 const char *Sym = S->getSymbol();
1359 // Create a constant pool entry for the callee address
1360 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1361 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1362 Sym, ARMPCLabelIndex, 0);
1363 // Get the address of the callee into a register
1364 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1365 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1366 Callee = DAG.getLoad(getPointerTy(), dl,
1367 DAG.getEntryNode(), CPAddr,
1368 MachinePointerInfo::getConstantPool(),
1371 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1372 const GlobalValue *GV = G->getGlobal();
1374 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1375 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1376 getTargetMachine().getRelocationModel() != Reloc::Static;
1377 isARMFunc = !Subtarget->isThumb() || isStub;
1378 // ARM call to a local ARM function is predicable.
1379 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1380 // tBX takes a register source operand.
1381 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1382 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1383 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1386 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1387 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1388 Callee = DAG.getLoad(getPointerTy(), dl,
1389 DAG.getEntryNode(), CPAddr,
1390 MachinePointerInfo::getConstantPool(),
1392 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1393 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1394 getPointerTy(), Callee, PICLabel);
1396 // On ELF targets for PIC code, direct calls should go through the PLT
1397 unsigned OpFlags = 0;
1398 if (Subtarget->isTargetELF() &&
1399 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1400 OpFlags = ARMII::MO_PLT;
1401 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1403 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1405 bool isStub = Subtarget->isTargetDarwin() &&
1406 getTargetMachine().getRelocationModel() != Reloc::Static;
1407 isARMFunc = !Subtarget->isThumb() || isStub;
1408 // tBX takes a register source operand.
1409 const char *Sym = S->getSymbol();
1410 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1411 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1412 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1413 Sym, ARMPCLabelIndex, 4);
1414 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1415 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1416 Callee = DAG.getLoad(getPointerTy(), dl,
1417 DAG.getEntryNode(), CPAddr,
1418 MachinePointerInfo::getConstantPool(),
1420 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1421 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1422 getPointerTy(), Callee, PICLabel);
1424 unsigned OpFlags = 0;
1425 // On ELF targets for PIC code, direct calls should go through the PLT
1426 if (Subtarget->isTargetELF() &&
1427 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1428 OpFlags = ARMII::MO_PLT;
1429 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1433 // FIXME: handle tail calls differently.
1435 if (Subtarget->isThumb()) {
1436 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1437 CallOpc = ARMISD::CALL_NOLINK;
1439 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1441 CallOpc = (isDirect || Subtarget->hasV5TOps())
1442 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1443 : ARMISD::CALL_NOLINK;
1446 std::vector<SDValue> Ops;
1447 Ops.push_back(Chain);
1448 Ops.push_back(Callee);
1450 // Add argument registers to the end of the list so that they are known live
1452 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1453 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1454 RegsToPass[i].second.getValueType()));
1456 if (InFlag.getNode())
1457 Ops.push_back(InFlag);
1459 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1461 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1463 // Returns a chain and a flag for retval copy to use.
1464 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1465 InFlag = Chain.getValue(1);
1467 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1468 DAG.getIntPtrConstant(0, true), InFlag);
1470 InFlag = Chain.getValue(1);
1472 // Handle result values, copying them out of physregs into vregs that we
1474 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1478 /// HandleByVal - Every parameter *after* a byval parameter is passed
1479 /// on the stack. Confiscate all the parameter registers to insure
1482 llvm::ARMTargetLowering::HandleByVal(CCState *State) const {
1483 static const unsigned RegList1[] = {
1484 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1486 do {} while (State->AllocateReg(RegList1, 4));
1489 /// MatchingStackOffset - Return true if the given stack call argument is
1490 /// already available in the same position (relatively) of the caller's
1491 /// incoming argument stack.
1493 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1494 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1495 const ARMInstrInfo *TII) {
1496 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1498 if (Arg.getOpcode() == ISD::CopyFromReg) {
1499 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1500 if (!TargetRegisterInfo::isVirtualRegister(VR))
1502 MachineInstr *Def = MRI->getVRegDef(VR);
1505 if (!Flags.isByVal()) {
1506 if (!TII->isLoadFromStackSlot(Def, FI))
1511 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1512 if (Flags.isByVal())
1513 // ByVal argument is passed in as a pointer but it's now being
1514 // dereferenced. e.g.
1515 // define @foo(%struct.X* %A) {
1516 // tail call @bar(%struct.X* byval %A)
1519 SDValue Ptr = Ld->getBasePtr();
1520 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1523 FI = FINode->getIndex();
1527 assert(FI != INT_MAX);
1528 if (!MFI->isFixedObjectIndex(FI))
1530 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1533 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1534 /// for tail call optimization. Targets which want to do tail call
1535 /// optimization should implement this function.
1537 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1538 CallingConv::ID CalleeCC,
1540 bool isCalleeStructRet,
1541 bool isCallerStructRet,
1542 const SmallVectorImpl<ISD::OutputArg> &Outs,
1543 const SmallVectorImpl<SDValue> &OutVals,
1544 const SmallVectorImpl<ISD::InputArg> &Ins,
1545 SelectionDAG& DAG) const {
1546 const Function *CallerF = DAG.getMachineFunction().getFunction();
1547 CallingConv::ID CallerCC = CallerF->getCallingConv();
1548 bool CCMatch = CallerCC == CalleeCC;
1550 // Look for obvious safe cases to perform tail call optimization that do not
1551 // require ABI changes. This is what gcc calls sibcall.
1553 // Do not sibcall optimize vararg calls unless the call site is not passing
1555 if (isVarArg && !Outs.empty())
1558 // Also avoid sibcall optimization if either caller or callee uses struct
1559 // return semantics.
1560 if (isCalleeStructRet || isCallerStructRet)
1563 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1564 // emitEpilogue is not ready for them.
1565 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1566 // LR. This means if we need to reload LR, it takes an extra instructions,
1567 // which outweighs the value of the tail call; but here we don't know yet
1568 // whether LR is going to be used. Probably the right approach is to
1569 // generate the tail call here and turn it back into CALL/RET in
1570 // emitEpilogue if LR is used.
1572 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1573 // but we need to make sure there are enough registers; the only valid
1574 // registers are the 4 used for parameters. We don't currently do this
1576 if (Subtarget->isThumb1Only())
1579 // If the calling conventions do not match, then we'd better make sure the
1580 // results are returned in the same way as what the caller expects.
1582 SmallVector<CCValAssign, 16> RVLocs1;
1583 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1584 RVLocs1, *DAG.getContext());
1585 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1587 SmallVector<CCValAssign, 16> RVLocs2;
1588 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1589 RVLocs2, *DAG.getContext());
1590 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1592 if (RVLocs1.size() != RVLocs2.size())
1594 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1595 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1597 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1599 if (RVLocs1[i].isRegLoc()) {
1600 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1603 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1609 // If the callee takes no arguments then go on to check the results of the
1611 if (!Outs.empty()) {
1612 // Check if stack adjustment is needed. For now, do not do this if any
1613 // argument is passed on the stack.
1614 SmallVector<CCValAssign, 16> ArgLocs;
1615 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1616 ArgLocs, *DAG.getContext());
1617 CCInfo.AnalyzeCallOperands(Outs,
1618 CCAssignFnForNode(CalleeCC, false, isVarArg));
1619 if (CCInfo.getNextStackOffset()) {
1620 MachineFunction &MF = DAG.getMachineFunction();
1622 // Check if the arguments are already laid out in the right way as
1623 // the caller's fixed stack objects.
1624 MachineFrameInfo *MFI = MF.getFrameInfo();
1625 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1626 const ARMInstrInfo *TII =
1627 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1628 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1630 ++i, ++realArgIdx) {
1631 CCValAssign &VA = ArgLocs[i];
1632 EVT RegVT = VA.getLocVT();
1633 SDValue Arg = OutVals[realArgIdx];
1634 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1635 if (VA.getLocInfo() == CCValAssign::Indirect)
1637 if (VA.needsCustom()) {
1638 // f64 and vector types are split into multiple registers or
1639 // register/stack-slot combinations. The types will not match
1640 // the registers; give up on memory f64 refs until we figure
1641 // out what to do about this.
1644 if (!ArgLocs[++i].isRegLoc())
1646 if (RegVT == MVT::v2f64) {
1647 if (!ArgLocs[++i].isRegLoc())
1649 if (!ArgLocs[++i].isRegLoc())
1652 } else if (!VA.isRegLoc()) {
1653 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1665 ARMTargetLowering::LowerReturn(SDValue Chain,
1666 CallingConv::ID CallConv, bool isVarArg,
1667 const SmallVectorImpl<ISD::OutputArg> &Outs,
1668 const SmallVectorImpl<SDValue> &OutVals,
1669 DebugLoc dl, SelectionDAG &DAG) const {
1671 // CCValAssign - represent the assignment of the return value to a location.
1672 SmallVector<CCValAssign, 16> RVLocs;
1674 // CCState - Info about the registers and stack slots.
1675 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1678 // Analyze outgoing return values.
1679 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1682 // If this is the first return lowered for this function, add
1683 // the regs to the liveout set for the function.
1684 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1685 for (unsigned i = 0; i != RVLocs.size(); ++i)
1686 if (RVLocs[i].isRegLoc())
1687 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1692 // Copy the result values into the output registers.
1693 for (unsigned i = 0, realRVLocIdx = 0;
1695 ++i, ++realRVLocIdx) {
1696 CCValAssign &VA = RVLocs[i];
1697 assert(VA.isRegLoc() && "Can only return in registers!");
1699 SDValue Arg = OutVals[realRVLocIdx];
1701 switch (VA.getLocInfo()) {
1702 default: llvm_unreachable("Unknown loc info!");
1703 case CCValAssign::Full: break;
1704 case CCValAssign::BCvt:
1705 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1709 if (VA.needsCustom()) {
1710 if (VA.getLocVT() == MVT::v2f64) {
1711 // Extract the first half and return it in two registers.
1712 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1713 DAG.getConstant(0, MVT::i32));
1714 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1715 DAG.getVTList(MVT::i32, MVT::i32), Half);
1717 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1718 Flag = Chain.getValue(1);
1719 VA = RVLocs[++i]; // skip ahead to next loc
1720 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1721 HalfGPRs.getValue(1), Flag);
1722 Flag = Chain.getValue(1);
1723 VA = RVLocs[++i]; // skip ahead to next loc
1725 // Extract the 2nd half and fall through to handle it as an f64 value.
1726 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1727 DAG.getConstant(1, MVT::i32));
1729 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1731 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1732 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1733 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1734 Flag = Chain.getValue(1);
1735 VA = RVLocs[++i]; // skip ahead to next loc
1736 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1739 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1741 // Guarantee that all emitted copies are
1742 // stuck together, avoiding something bad.
1743 Flag = Chain.getValue(1);
1748 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1750 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1755 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1756 if (N->getNumValues() != 1)
1758 if (!N->hasNUsesOfValue(1, 0))
1761 unsigned NumCopies = 0;
1763 SDNode *Use = *N->use_begin();
1764 if (Use->getOpcode() == ISD::CopyToReg) {
1765 Copies[NumCopies++] = Use;
1766 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1767 // f64 returned in a pair of GPRs.
1768 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1770 if (UI->getOpcode() != ISD::CopyToReg)
1772 Copies[UI.getUse().getResNo()] = *UI;
1775 } else if (Use->getOpcode() == ISD::BITCAST) {
1776 // f32 returned in a single GPR.
1777 if (!Use->hasNUsesOfValue(1, 0))
1779 Use = *Use->use_begin();
1780 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1782 Copies[NumCopies++] = Use;
1787 if (NumCopies != 1 && NumCopies != 2)
1790 bool HasRet = false;
1791 for (unsigned i = 0; i < NumCopies; ++i) {
1792 SDNode *Copy = Copies[i];
1793 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1795 if (UI->getOpcode() == ISD::CopyToReg) {
1797 if (Use == Copies[0] || Use == Copies[1])
1801 if (UI->getOpcode() != ARMISD::RET_FLAG)
1810 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1811 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1812 // one of the above mentioned nodes. It has to be wrapped because otherwise
1813 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1814 // be used to form addressing mode. These wrapped nodes will be selected
1816 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1817 EVT PtrVT = Op.getValueType();
1818 // FIXME there is no actual debug info here
1819 DebugLoc dl = Op.getDebugLoc();
1820 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1822 if (CP->isMachineConstantPoolEntry())
1823 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1824 CP->getAlignment());
1826 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1827 CP->getAlignment());
1828 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1831 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1832 return MachineJumpTableInfo::EK_Inline;
1835 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1836 SelectionDAG &DAG) const {
1837 MachineFunction &MF = DAG.getMachineFunction();
1838 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1839 unsigned ARMPCLabelIndex = 0;
1840 DebugLoc DL = Op.getDebugLoc();
1841 EVT PtrVT = getPointerTy();
1842 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1843 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1845 if (RelocM == Reloc::Static) {
1846 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1848 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1849 ARMPCLabelIndex = AFI->createPICLabelUId();
1850 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1851 ARMCP::CPBlockAddress,
1853 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1855 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1856 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1857 MachinePointerInfo::getConstantPool(),
1859 if (RelocM == Reloc::Static)
1861 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1862 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1865 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1867 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1868 SelectionDAG &DAG) const {
1869 DebugLoc dl = GA->getDebugLoc();
1870 EVT PtrVT = getPointerTy();
1871 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1872 MachineFunction &MF = DAG.getMachineFunction();
1873 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1874 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1875 ARMConstantPoolValue *CPV =
1876 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1877 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1878 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1879 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1880 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1881 MachinePointerInfo::getConstantPool(),
1883 SDValue Chain = Argument.getValue(1);
1885 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1886 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1888 // call __tls_get_addr.
1891 Entry.Node = Argument;
1892 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1893 Args.push_back(Entry);
1894 // FIXME: is there useful debug info available here?
1895 std::pair<SDValue, SDValue> CallResult =
1896 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1897 false, false, false, false,
1898 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1899 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1900 return CallResult.first;
1903 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1904 // "local exec" model.
1906 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1907 SelectionDAG &DAG) const {
1908 const GlobalValue *GV = GA->getGlobal();
1909 DebugLoc dl = GA->getDebugLoc();
1911 SDValue Chain = DAG.getEntryNode();
1912 EVT PtrVT = getPointerTy();
1913 // Get the Thread Pointer
1914 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1916 if (GV->isDeclaration()) {
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1919 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1920 // Initial exec model.
1921 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1922 ARMConstantPoolValue *CPV =
1923 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1924 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1925 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1926 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1927 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1928 MachinePointerInfo::getConstantPool(),
1930 Chain = Offset.getValue(1);
1932 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1933 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1935 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1936 MachinePointerInfo::getConstantPool(),
1940 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1941 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1942 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1943 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1944 MachinePointerInfo::getConstantPool(),
1948 // The address of the thread local variable is the add of the thread
1949 // pointer with the offset of the variable.
1950 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1954 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1955 // TODO: implement the "local dynamic" model
1956 assert(Subtarget->isTargetELF() &&
1957 "TLS not implemented for non-ELF targets");
1958 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1959 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1960 // otherwise use the "Local Exec" TLS Model
1961 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1962 return LowerToTLSGeneralDynamicModel(GA, DAG);
1964 return LowerToTLSExecModels(GA, DAG);
1967 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1968 SelectionDAG &DAG) const {
1969 EVT PtrVT = getPointerTy();
1970 DebugLoc dl = Op.getDebugLoc();
1971 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1972 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1973 if (RelocM == Reloc::PIC_) {
1974 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1975 ARMConstantPoolValue *CPV =
1976 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1977 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1978 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1979 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1981 MachinePointerInfo::getConstantPool(),
1983 SDValue Chain = Result.getValue(1);
1984 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1985 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1987 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1988 MachinePointerInfo::getGOT(), false, false, 0);
1992 // If we have T2 ops, we can materialize the address directly via movt/movw
1993 // pair. This is always cheaper.
1994 if (Subtarget->useMovt()) {
1996 // FIXME: Once remat is capable of dealing with instructions with register
1997 // operands, expand this into two nodes.
1998 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1999 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2001 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2002 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2003 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2004 MachinePointerInfo::getConstantPool(),
2009 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2010 SelectionDAG &DAG) const {
2011 EVT PtrVT = getPointerTy();
2012 DebugLoc dl = Op.getDebugLoc();
2013 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2014 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2015 MachineFunction &MF = DAG.getMachineFunction();
2016 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2018 if (Subtarget->useMovt()) {
2020 // FIXME: Once remat is capable of dealing with instructions with register
2021 // operands, expand this into two nodes.
2022 if (RelocM == Reloc::Static)
2023 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2024 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2026 unsigned Wrapper = (RelocM == Reloc::PIC_)
2027 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2028 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2029 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2030 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2031 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2032 MachinePointerInfo::getGOT(), false, false, 0);
2036 unsigned ARMPCLabelIndex = 0;
2038 if (RelocM == Reloc::Static) {
2039 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2041 ARMPCLabelIndex = AFI->createPICLabelUId();
2042 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2043 ARMConstantPoolValue *CPV =
2044 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2045 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2047 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2049 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2050 MachinePointerInfo::getConstantPool(),
2052 SDValue Chain = Result.getValue(1);
2054 if (RelocM == Reloc::PIC_) {
2055 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2056 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2059 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2060 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2066 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2067 SelectionDAG &DAG) const {
2068 assert(Subtarget->isTargetELF() &&
2069 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2070 MachineFunction &MF = DAG.getMachineFunction();
2071 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2072 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2073 EVT PtrVT = getPointerTy();
2074 DebugLoc dl = Op.getDebugLoc();
2075 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2076 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2077 "_GLOBAL_OFFSET_TABLE_",
2078 ARMPCLabelIndex, PCAdj);
2079 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2080 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2081 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2082 MachinePointerInfo::getConstantPool(),
2084 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2085 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2089 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2091 DebugLoc dl = Op.getDebugLoc();
2092 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2093 Op.getOperand(0), Op.getOperand(1));
2097 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2098 DebugLoc dl = Op.getDebugLoc();
2099 SDValue Val = DAG.getConstant(0, MVT::i32);
2100 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2101 Op.getOperand(1), Val);
2105 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2106 DebugLoc dl = Op.getDebugLoc();
2107 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2108 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2112 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2113 const ARMSubtarget *Subtarget) const {
2114 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2115 DebugLoc dl = Op.getDebugLoc();
2117 default: return SDValue(); // Don't custom lower most intrinsics.
2118 case Intrinsic::arm_thread_pointer: {
2119 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2120 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2122 case Intrinsic::eh_sjlj_lsda: {
2123 MachineFunction &MF = DAG.getMachineFunction();
2124 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2125 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2126 EVT PtrVT = getPointerTy();
2127 DebugLoc dl = Op.getDebugLoc();
2128 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2130 unsigned PCAdj = (RelocM != Reloc::PIC_)
2131 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2132 ARMConstantPoolValue *CPV =
2133 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2134 ARMCP::CPLSDA, PCAdj);
2135 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2136 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2138 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2139 MachinePointerInfo::getConstantPool(),
2142 if (RelocM == Reloc::PIC_) {
2143 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2144 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2151 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2152 const ARMSubtarget *Subtarget) {
2153 DebugLoc dl = Op.getDebugLoc();
2154 if (!Subtarget->hasDataBarrier()) {
2155 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2156 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2158 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2159 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2160 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2161 DAG.getConstant(0, MVT::i32));
2164 SDValue Op5 = Op.getOperand(5);
2165 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2166 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2167 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2168 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2170 ARM_MB::MemBOpt DMBOpt;
2171 if (isDeviceBarrier)
2172 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2174 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2175 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2176 DAG.getConstant(DMBOpt, MVT::i32));
2179 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2180 const ARMSubtarget *Subtarget) {
2181 // ARM pre v5TE and Thumb1 does not have preload instructions.
2182 if (!(Subtarget->isThumb2() ||
2183 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2184 // Just preserve the chain.
2185 return Op.getOperand(0);
2187 DebugLoc dl = Op.getDebugLoc();
2188 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2190 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2191 // ARMv7 with MP extension has PLDW.
2192 return Op.getOperand(0);
2194 if (Subtarget->isThumb())
2196 isRead = ~isRead & 1;
2197 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2199 // Currently there is no intrinsic that matches pli.
2200 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2201 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2202 DAG.getConstant(isData, MVT::i32));
2205 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2206 MachineFunction &MF = DAG.getMachineFunction();
2207 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2209 // vastart just stores the address of the VarArgsFrameIndex slot into the
2210 // memory location argument.
2211 DebugLoc dl = Op.getDebugLoc();
2212 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2213 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2214 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2215 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2216 MachinePointerInfo(SV), false, false, 0);
2220 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2221 SDValue &Root, SelectionDAG &DAG,
2222 DebugLoc dl) const {
2223 MachineFunction &MF = DAG.getMachineFunction();
2224 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2226 TargetRegisterClass *RC;
2227 if (AFI->isThumb1OnlyFunction())
2228 RC = ARM::tGPRRegisterClass;
2230 RC = ARM::GPRRegisterClass;
2232 // Transform the arguments stored in physical registers into virtual ones.
2233 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2234 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2237 if (NextVA.isMemLoc()) {
2238 MachineFrameInfo *MFI = MF.getFrameInfo();
2239 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2241 // Create load node to retrieve arguments from the stack.
2242 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2243 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2244 MachinePointerInfo::getFixedStack(FI),
2247 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2248 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2251 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2255 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2256 CallingConv::ID CallConv, bool isVarArg,
2257 const SmallVectorImpl<ISD::InputArg>
2259 DebugLoc dl, SelectionDAG &DAG,
2260 SmallVectorImpl<SDValue> &InVals)
2263 MachineFunction &MF = DAG.getMachineFunction();
2264 MachineFrameInfo *MFI = MF.getFrameInfo();
2266 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2268 // Assign locations to all of the incoming arguments.
2269 SmallVector<CCValAssign, 16> ArgLocs;
2270 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2272 CCInfo.AnalyzeFormalArguments(Ins,
2273 CCAssignFnForNode(CallConv, /* Return*/ false,
2276 SmallVector<SDValue, 16> ArgValues;
2277 int lastInsIndex = -1;
2280 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2281 CCValAssign &VA = ArgLocs[i];
2283 // Arguments stored in registers.
2284 if (VA.isRegLoc()) {
2285 EVT RegVT = VA.getLocVT();
2287 if (VA.needsCustom()) {
2288 // f64 and vector types are split up into multiple registers or
2289 // combinations of registers and stack slots.
2290 if (VA.getLocVT() == MVT::v2f64) {
2291 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2293 VA = ArgLocs[++i]; // skip ahead to next loc
2295 if (VA.isMemLoc()) {
2296 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2297 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2298 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2299 MachinePointerInfo::getFixedStack(FI),
2302 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2305 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2306 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2307 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2308 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2309 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2311 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2314 TargetRegisterClass *RC;
2316 if (RegVT == MVT::f32)
2317 RC = ARM::SPRRegisterClass;
2318 else if (RegVT == MVT::f64)
2319 RC = ARM::DPRRegisterClass;
2320 else if (RegVT == MVT::v2f64)
2321 RC = ARM::QPRRegisterClass;
2322 else if (RegVT == MVT::i32)
2323 RC = (AFI->isThumb1OnlyFunction() ?
2324 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2326 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2328 // Transform the arguments in physical registers into virtual ones.
2329 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2330 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2333 // If this is an 8 or 16-bit value, it is really passed promoted
2334 // to 32 bits. Insert an assert[sz]ext to capture this, then
2335 // truncate to the right size.
2336 switch (VA.getLocInfo()) {
2337 default: llvm_unreachable("Unknown loc info!");
2338 case CCValAssign::Full: break;
2339 case CCValAssign::BCvt:
2340 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2342 case CCValAssign::SExt:
2343 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2344 DAG.getValueType(VA.getValVT()));
2345 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2347 case CCValAssign::ZExt:
2348 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2349 DAG.getValueType(VA.getValVT()));
2350 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2354 InVals.push_back(ArgValue);
2356 } else { // VA.isRegLoc()
2359 assert(VA.isMemLoc());
2360 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2362 int index = ArgLocs[i].getValNo();
2364 // Some Ins[] entries become multiple ArgLoc[] entries.
2365 // Process them only once.
2366 if (index != lastInsIndex)
2368 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2369 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2370 // changed with more analysis.
2371 // In case of tail call optimization mark all arguments mutable. Since they
2372 // could be overwritten by lowering of arguments in case of a tail call.
2373 if (Flags.isByVal()) {
2374 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
2375 VA.getLocMemOffset(), false);
2376 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2378 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2379 VA.getLocMemOffset(), true);
2381 // Create load nodes to retrieve arguments from the stack.
2382 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2383 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2384 MachinePointerInfo::getFixedStack(FI),
2387 lastInsIndex = index;
2394 static const unsigned GPRArgRegs[] = {
2395 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2398 unsigned NumGPRs = CCInfo.getFirstUnallocated
2399 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2401 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2402 unsigned VARegSize = (4 - NumGPRs) * 4;
2403 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2404 unsigned ArgOffset = CCInfo.getNextStackOffset();
2405 if (VARegSaveSize) {
2406 // If this function is vararg, store any remaining integer argument regs
2407 // to their spots on the stack so that they may be loaded by deferencing
2408 // the result of va_next.
2409 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2410 AFI->setVarArgsFrameIndex(
2411 MFI->CreateFixedObject(VARegSaveSize,
2412 ArgOffset + VARegSaveSize - VARegSize,
2414 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2417 SmallVector<SDValue, 4> MemOps;
2418 for (; NumGPRs < 4; ++NumGPRs) {
2419 TargetRegisterClass *RC;
2420 if (AFI->isThumb1OnlyFunction())
2421 RC = ARM::tGPRRegisterClass;
2423 RC = ARM::GPRRegisterClass;
2425 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2426 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2428 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2429 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2431 MemOps.push_back(Store);
2432 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2433 DAG.getConstant(4, getPointerTy()));
2435 if (!MemOps.empty())
2436 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2437 &MemOps[0], MemOps.size());
2439 // This will point to the next argument passed via stack.
2440 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2446 /// isFloatingPointZero - Return true if this is +0.0.
2447 static bool isFloatingPointZero(SDValue Op) {
2448 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2449 return CFP->getValueAPF().isPosZero();
2450 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2451 // Maybe this has already been legalized into the constant pool?
2452 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2453 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2454 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2455 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2456 return CFP->getValueAPF().isPosZero();
2462 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2463 /// the given operands.
2465 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2466 SDValue &ARMcc, SelectionDAG &DAG,
2467 DebugLoc dl) const {
2468 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2469 unsigned C = RHSC->getZExtValue();
2470 if (!isLegalICmpImmediate(C)) {
2471 // Constant does not fit, try adjusting it by one?
2476 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2477 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2478 RHS = DAG.getConstant(C-1, MVT::i32);
2483 if (C != 0 && isLegalICmpImmediate(C-1)) {
2484 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2485 RHS = DAG.getConstant(C-1, MVT::i32);
2490 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2491 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2492 RHS = DAG.getConstant(C+1, MVT::i32);
2497 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2498 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2499 RHS = DAG.getConstant(C+1, MVT::i32);
2506 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2507 ARMISD::NodeType CompareType;
2510 CompareType = ARMISD::CMP;
2515 CompareType = ARMISD::CMPZ;
2518 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2519 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2522 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2524 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2525 DebugLoc dl) const {
2527 if (!isFloatingPointZero(RHS))
2528 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2530 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2531 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2534 /// duplicateCmp - Glue values can have only one use, so this function
2535 /// duplicates a comparison node.
2537 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2538 unsigned Opc = Cmp.getOpcode();
2539 DebugLoc DL = Cmp.getDebugLoc();
2540 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2541 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2543 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2544 Cmp = Cmp.getOperand(0);
2545 Opc = Cmp.getOpcode();
2546 if (Opc == ARMISD::CMPFP)
2547 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2549 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2550 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2552 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2555 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2556 SDValue Cond = Op.getOperand(0);
2557 SDValue SelectTrue = Op.getOperand(1);
2558 SDValue SelectFalse = Op.getOperand(2);
2559 DebugLoc dl = Op.getDebugLoc();
2563 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2564 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2566 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2567 const ConstantSDNode *CMOVTrue =
2568 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2569 const ConstantSDNode *CMOVFalse =
2570 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2572 if (CMOVTrue && CMOVFalse) {
2573 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2574 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2578 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2580 False = SelectFalse;
2581 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2586 if (True.getNode() && False.getNode()) {
2587 EVT VT = Cond.getValueType();
2588 SDValue ARMcc = Cond.getOperand(2);
2589 SDValue CCR = Cond.getOperand(3);
2590 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2591 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2596 return DAG.getSelectCC(dl, Cond,
2597 DAG.getConstant(0, Cond.getValueType()),
2598 SelectTrue, SelectFalse, ISD::SETNE);
2601 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2602 EVT VT = Op.getValueType();
2603 SDValue LHS = Op.getOperand(0);
2604 SDValue RHS = Op.getOperand(1);
2605 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2606 SDValue TrueVal = Op.getOperand(2);
2607 SDValue FalseVal = Op.getOperand(3);
2608 DebugLoc dl = Op.getDebugLoc();
2610 if (LHS.getValueType() == MVT::i32) {
2612 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2613 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2614 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2617 ARMCC::CondCodes CondCode, CondCode2;
2618 FPCCToARMCC(CC, CondCode, CondCode2);
2620 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2621 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2622 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2623 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2625 if (CondCode2 != ARMCC::AL) {
2626 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2627 // FIXME: Needs another CMP because flag can have but one use.
2628 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2629 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2630 Result, TrueVal, ARMcc2, CCR, Cmp2);
2635 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2636 /// to morph to an integer compare sequence.
2637 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2638 const ARMSubtarget *Subtarget) {
2639 SDNode *N = Op.getNode();
2640 if (!N->hasOneUse())
2641 // Otherwise it requires moving the value from fp to integer registers.
2643 if (!N->getNumValues())
2645 EVT VT = Op.getValueType();
2646 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2647 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2648 // vmrs are very slow, e.g. cortex-a8.
2651 if (isFloatingPointZero(Op)) {
2655 return ISD::isNormalLoad(N);
2658 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2659 if (isFloatingPointZero(Op))
2660 return DAG.getConstant(0, MVT::i32);
2662 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2663 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2664 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2665 Ld->isVolatile(), Ld->isNonTemporal(),
2666 Ld->getAlignment());
2668 llvm_unreachable("Unknown VFP cmp argument!");
2671 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2672 SDValue &RetVal1, SDValue &RetVal2) {
2673 if (isFloatingPointZero(Op)) {
2674 RetVal1 = DAG.getConstant(0, MVT::i32);
2675 RetVal2 = DAG.getConstant(0, MVT::i32);
2679 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2680 SDValue Ptr = Ld->getBasePtr();
2681 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2682 Ld->getChain(), Ptr,
2683 Ld->getPointerInfo(),
2684 Ld->isVolatile(), Ld->isNonTemporal(),
2685 Ld->getAlignment());
2687 EVT PtrType = Ptr.getValueType();
2688 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2689 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2690 PtrType, Ptr, DAG.getConstant(4, PtrType));
2691 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2692 Ld->getChain(), NewPtr,
2693 Ld->getPointerInfo().getWithOffset(4),
2694 Ld->isVolatile(), Ld->isNonTemporal(),
2699 llvm_unreachable("Unknown VFP cmp argument!");
2702 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2703 /// f32 and even f64 comparisons to integer ones.
2705 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2706 SDValue Chain = Op.getOperand(0);
2707 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2708 SDValue LHS = Op.getOperand(2);
2709 SDValue RHS = Op.getOperand(3);
2710 SDValue Dest = Op.getOperand(4);
2711 DebugLoc dl = Op.getDebugLoc();
2713 bool SeenZero = false;
2714 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2715 canChangeToInt(RHS, SeenZero, Subtarget) &&
2716 // If one of the operand is zero, it's safe to ignore the NaN case since
2717 // we only care about equality comparisons.
2718 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2719 // If unsafe fp math optimization is enabled and there are no other uses of
2720 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2721 // to an integer comparison.
2722 if (CC == ISD::SETOEQ)
2724 else if (CC == ISD::SETUNE)
2728 if (LHS.getValueType() == MVT::f32) {
2729 LHS = bitcastf32Toi32(LHS, DAG);
2730 RHS = bitcastf32Toi32(RHS, DAG);
2731 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2732 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2733 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2734 Chain, Dest, ARMcc, CCR, Cmp);
2739 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2740 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2741 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2742 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2743 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2744 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2745 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2751 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2752 SDValue Chain = Op.getOperand(0);
2753 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2754 SDValue LHS = Op.getOperand(2);
2755 SDValue RHS = Op.getOperand(3);
2756 SDValue Dest = Op.getOperand(4);
2757 DebugLoc dl = Op.getDebugLoc();
2759 if (LHS.getValueType() == MVT::i32) {
2761 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2762 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2763 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2764 Chain, Dest, ARMcc, CCR, Cmp);
2767 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2770 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2771 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2772 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2773 if (Result.getNode())
2777 ARMCC::CondCodes CondCode, CondCode2;
2778 FPCCToARMCC(CC, CondCode, CondCode2);
2780 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2781 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2782 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2783 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2784 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2785 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2786 if (CondCode2 != ARMCC::AL) {
2787 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2788 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2789 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2794 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2795 SDValue Chain = Op.getOperand(0);
2796 SDValue Table = Op.getOperand(1);
2797 SDValue Index = Op.getOperand(2);
2798 DebugLoc dl = Op.getDebugLoc();
2800 EVT PTy = getPointerTy();
2801 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2802 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2803 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2804 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2805 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2806 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2807 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2808 if (Subtarget->isThumb2()) {
2809 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2810 // which does another jump to the destination. This also makes it easier
2811 // to translate it to TBB / TBH later.
2812 // FIXME: This might not work if the function is extremely large.
2813 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2814 Addr, Op.getOperand(2), JTI, UId);
2816 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2817 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2818 MachinePointerInfo::getJumpTable(),
2820 Chain = Addr.getValue(1);
2821 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2822 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2824 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2825 MachinePointerInfo::getJumpTable(), false, false, 0);
2826 Chain = Addr.getValue(1);
2827 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2831 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2832 DebugLoc dl = Op.getDebugLoc();
2835 switch (Op.getOpcode()) {
2837 assert(0 && "Invalid opcode!");
2838 case ISD::FP_TO_SINT:
2839 Opc = ARMISD::FTOSI;
2841 case ISD::FP_TO_UINT:
2842 Opc = ARMISD::FTOUI;
2845 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2846 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2849 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2850 EVT VT = Op.getValueType();
2851 DebugLoc dl = Op.getDebugLoc();
2854 switch (Op.getOpcode()) {
2856 assert(0 && "Invalid opcode!");
2857 case ISD::SINT_TO_FP:
2858 Opc = ARMISD::SITOF;
2860 case ISD::UINT_TO_FP:
2861 Opc = ARMISD::UITOF;
2865 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2866 return DAG.getNode(Opc, dl, VT, Op);
2869 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2870 // Implement fcopysign with a fabs and a conditional fneg.
2871 SDValue Tmp0 = Op.getOperand(0);
2872 SDValue Tmp1 = Op.getOperand(1);
2873 DebugLoc dl = Op.getDebugLoc();
2874 EVT VT = Op.getValueType();
2875 EVT SrcVT = Tmp1.getValueType();
2876 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
2877 Tmp0.getOpcode() == ARMISD::VMOVDRR;
2878 bool UseNEON = !InGPR && Subtarget->hasNEON();
2881 // Use VBSL to copy the sign bit.
2882 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
2883 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
2884 DAG.getTargetConstant(EncodedVal, MVT::i32));
2885 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
2887 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
2888 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
2889 DAG.getConstant(32, MVT::i32));
2890 else /*if (VT == MVT::f32)*/
2891 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
2892 if (SrcVT == MVT::f32) {
2893 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
2895 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
2896 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
2897 DAG.getConstant(32, MVT::i32));
2899 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
2900 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
2902 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
2904 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
2905 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
2906 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
2908 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
2909 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
2910 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
2911 if (VT == MVT::f32) {
2912 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
2913 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
2914 DAG.getConstant(0, MVT::i32));
2916 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
2922 // Bitcast operand 1 to i32.
2923 if (SrcVT == MVT::f64)
2924 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2925 &Tmp1, 1).getValue(1);
2926 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
2928 // Or in the signbit with integer operations.
2929 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
2930 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
2931 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
2932 if (VT == MVT::f32) {
2933 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
2934 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
2935 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
2936 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
2939 // f64: Or the high part with signbit and then combine two parts.
2940 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2942 SDValue Lo = Tmp0.getValue(0);
2943 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
2944 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
2945 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2948 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2949 MachineFunction &MF = DAG.getMachineFunction();
2950 MachineFrameInfo *MFI = MF.getFrameInfo();
2951 MFI->setReturnAddressIsTaken(true);
2953 EVT VT = Op.getValueType();
2954 DebugLoc dl = Op.getDebugLoc();
2955 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2957 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2958 SDValue Offset = DAG.getConstant(4, MVT::i32);
2959 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2960 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2961 MachinePointerInfo(), false, false, 0);
2964 // Return LR, which contains the return address. Mark it an implicit live-in.
2965 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2966 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2969 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2970 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2971 MFI->setFrameAddressIsTaken(true);
2973 EVT VT = Op.getValueType();
2974 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2975 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2976 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2977 ? ARM::R7 : ARM::R11;
2978 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2980 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2981 MachinePointerInfo(),
2986 /// ExpandBITCAST - If the target supports VFP, this function is called to
2987 /// expand a bit convert where either the source or destination type is i64 to
2988 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2989 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2990 /// vectors), since the legalizer won't know what to do with that.
2991 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
2992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2993 DebugLoc dl = N->getDebugLoc();
2994 SDValue Op = N->getOperand(0);
2996 // This function is only supposed to be called for i64 types, either as the
2997 // source or destination of the bit convert.
2998 EVT SrcVT = Op.getValueType();
2999 EVT DstVT = N->getValueType(0);
3000 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3001 "ExpandBITCAST called for non-i64 type");
3003 // Turn i64->f64 into VMOVDRR.
3004 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3005 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3006 DAG.getConstant(0, MVT::i32));
3007 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3008 DAG.getConstant(1, MVT::i32));
3009 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3010 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3013 // Turn f64->i64 into VMOVRRD.
3014 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3015 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3016 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3017 // Merge the pieces into a single i64 value.
3018 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3024 /// getZeroVector - Returns a vector of specified type with all zero elements.
3025 /// Zero vectors are used to represent vector negation and in those cases
3026 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3027 /// not support i64 elements, so sometimes the zero vectors will need to be
3028 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3030 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3031 assert(VT.isVector() && "Expected a vector type");
3032 // The canonical modified immediate encoding of a zero vector is....0!
3033 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3034 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3035 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3036 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3039 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3040 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3041 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3042 SelectionDAG &DAG) const {
3043 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3044 EVT VT = Op.getValueType();
3045 unsigned VTBits = VT.getSizeInBits();
3046 DebugLoc dl = Op.getDebugLoc();
3047 SDValue ShOpLo = Op.getOperand(0);
3048 SDValue ShOpHi = Op.getOperand(1);
3049 SDValue ShAmt = Op.getOperand(2);
3051 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3053 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3055 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3056 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3057 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3058 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3059 DAG.getConstant(VTBits, MVT::i32));
3060 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3061 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3062 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3064 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3065 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3067 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3068 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3071 SDValue Ops[2] = { Lo, Hi };
3072 return DAG.getMergeValues(Ops, 2, dl);
3075 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3076 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3077 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3078 SelectionDAG &DAG) const {
3079 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3080 EVT VT = Op.getValueType();
3081 unsigned VTBits = VT.getSizeInBits();
3082 DebugLoc dl = Op.getDebugLoc();
3083 SDValue ShOpLo = Op.getOperand(0);
3084 SDValue ShOpHi = Op.getOperand(1);
3085 SDValue ShAmt = Op.getOperand(2);
3088 assert(Op.getOpcode() == ISD::SHL_PARTS);
3089 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3090 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3091 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3092 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3093 DAG.getConstant(VTBits, MVT::i32));
3094 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3095 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3097 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3098 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3099 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3101 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3102 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3105 SDValue Ops[2] = { Lo, Hi };
3106 return DAG.getMergeValues(Ops, 2, dl);
3109 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3110 SelectionDAG &DAG) const {
3111 // The rounding mode is in bits 23:22 of the FPSCR.
3112 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3113 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3114 // so that the shift + and get folded into a bitfield extract.
3115 DebugLoc dl = Op.getDebugLoc();
3116 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3117 DAG.getConstant(Intrinsic::arm_get_fpscr,
3119 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3120 DAG.getConstant(1U << 22, MVT::i32));
3121 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3122 DAG.getConstant(22, MVT::i32));
3123 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3124 DAG.getConstant(3, MVT::i32));
3127 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3128 const ARMSubtarget *ST) {
3129 EVT VT = N->getValueType(0);
3130 DebugLoc dl = N->getDebugLoc();
3132 if (!ST->hasV6T2Ops())
3135 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3136 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3139 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3140 const ARMSubtarget *ST) {
3141 EVT VT = N->getValueType(0);
3142 DebugLoc dl = N->getDebugLoc();
3147 // Lower vector shifts on NEON to use VSHL.
3148 assert(ST->hasNEON() && "unexpected vector shift");
3150 // Left shifts translate directly to the vshiftu intrinsic.
3151 if (N->getOpcode() == ISD::SHL)
3152 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3153 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3154 N->getOperand(0), N->getOperand(1));
3156 assert((N->getOpcode() == ISD::SRA ||
3157 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3159 // NEON uses the same intrinsics for both left and right shifts. For
3160 // right shifts, the shift amounts are negative, so negate the vector of
3162 EVT ShiftVT = N->getOperand(1).getValueType();
3163 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3164 getZeroVector(ShiftVT, DAG, dl),
3166 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3167 Intrinsic::arm_neon_vshifts :
3168 Intrinsic::arm_neon_vshiftu);
3169 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3170 DAG.getConstant(vshiftInt, MVT::i32),
3171 N->getOperand(0), NegatedCount);
3174 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3175 const ARMSubtarget *ST) {
3176 EVT VT = N->getValueType(0);
3177 DebugLoc dl = N->getDebugLoc();
3179 // We can get here for a node like i32 = ISD::SHL i32, i64
3183 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3184 "Unknown shift to lower!");
3186 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3187 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3188 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3191 // If we are in thumb mode, we don't have RRX.
3192 if (ST->isThumb1Only()) return SDValue();
3194 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3195 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3196 DAG.getConstant(0, MVT::i32));
3197 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3198 DAG.getConstant(1, MVT::i32));
3200 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3201 // captures the result into a carry flag.
3202 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3203 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3205 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3206 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3208 // Merge the pieces into a single i64 value.
3209 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3212 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3213 SDValue TmpOp0, TmpOp1;
3214 bool Invert = false;
3218 SDValue Op0 = Op.getOperand(0);
3219 SDValue Op1 = Op.getOperand(1);
3220 SDValue CC = Op.getOperand(2);
3221 EVT VT = Op.getValueType();
3222 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3223 DebugLoc dl = Op.getDebugLoc();
3225 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3226 switch (SetCCOpcode) {
3227 default: llvm_unreachable("Illegal FP comparison"); break;
3229 case ISD::SETNE: Invert = true; // Fallthrough
3231 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3233 case ISD::SETLT: Swap = true; // Fallthrough
3235 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3237 case ISD::SETLE: Swap = true; // Fallthrough
3239 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3240 case ISD::SETUGE: Swap = true; // Fallthrough
3241 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3242 case ISD::SETUGT: Swap = true; // Fallthrough
3243 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3244 case ISD::SETUEQ: Invert = true; // Fallthrough
3246 // Expand this to (OLT | OGT).
3250 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3251 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3253 case ISD::SETUO: Invert = true; // Fallthrough
3255 // Expand this to (OLT | OGE).
3259 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3260 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3264 // Integer comparisons.
3265 switch (SetCCOpcode) {
3266 default: llvm_unreachable("Illegal integer comparison"); break;
3267 case ISD::SETNE: Invert = true;
3268 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3269 case ISD::SETLT: Swap = true;
3270 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3271 case ISD::SETLE: Swap = true;
3272 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3273 case ISD::SETULT: Swap = true;
3274 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3275 case ISD::SETULE: Swap = true;
3276 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3279 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3280 if (Opc == ARMISD::VCEQ) {
3283 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3285 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3288 // Ignore bitconvert.
3289 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3290 AndOp = AndOp.getOperand(0);
3292 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3294 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3295 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3302 std::swap(Op0, Op1);
3304 // If one of the operands is a constant vector zero, attempt to fold the
3305 // comparison to a specialized compare-against-zero form.
3307 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3309 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3310 if (Opc == ARMISD::VCGE)
3311 Opc = ARMISD::VCLEZ;
3312 else if (Opc == ARMISD::VCGT)
3313 Opc = ARMISD::VCLTZ;
3318 if (SingleOp.getNode()) {
3321 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3323 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3325 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3327 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3329 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3331 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3334 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3338 Result = DAG.getNOT(dl, Result, VT);
3343 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3344 /// valid vector constant for a NEON instruction with a "modified immediate"
3345 /// operand (e.g., VMOV). If so, return the encoded value.
3346 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3347 unsigned SplatBitSize, SelectionDAG &DAG,
3348 EVT &VT, bool is128Bits, NEONModImmType type) {
3349 unsigned OpCmode, Imm;
3351 // SplatBitSize is set to the smallest size that splats the vector, so a
3352 // zero vector will always have SplatBitSize == 8. However, NEON modified
3353 // immediate instructions others than VMOV do not support the 8-bit encoding
3354 // of a zero vector, and the default encoding of zero is supposed to be the
3359 switch (SplatBitSize) {
3361 if (type != VMOVModImm)
3363 // Any 1-byte value is OK. Op=0, Cmode=1110.
3364 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3367 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3371 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3372 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3373 if ((SplatBits & ~0xff) == 0) {
3374 // Value = 0x00nn: Op=x, Cmode=100x.
3379 if ((SplatBits & ~0xff00) == 0) {
3380 // Value = 0xnn00: Op=x, Cmode=101x.
3382 Imm = SplatBits >> 8;
3388 // NEON's 32-bit VMOV supports splat values where:
3389 // * only one byte is nonzero, or
3390 // * the least significant byte is 0xff and the second byte is nonzero, or
3391 // * the least significant 2 bytes are 0xff and the third is nonzero.
3392 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3393 if ((SplatBits & ~0xff) == 0) {
3394 // Value = 0x000000nn: Op=x, Cmode=000x.
3399 if ((SplatBits & ~0xff00) == 0) {
3400 // Value = 0x0000nn00: Op=x, Cmode=001x.
3402 Imm = SplatBits >> 8;
3405 if ((SplatBits & ~0xff0000) == 0) {
3406 // Value = 0x00nn0000: Op=x, Cmode=010x.
3408 Imm = SplatBits >> 16;
3411 if ((SplatBits & ~0xff000000) == 0) {
3412 // Value = 0xnn000000: Op=x, Cmode=011x.
3414 Imm = SplatBits >> 24;
3418 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3419 if (type == OtherModImm) return SDValue();
3421 if ((SplatBits & ~0xffff) == 0 &&
3422 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3423 // Value = 0x0000nnff: Op=x, Cmode=1100.
3425 Imm = SplatBits >> 8;
3430 if ((SplatBits & ~0xffffff) == 0 &&
3431 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3432 // Value = 0x00nnffff: Op=x, Cmode=1101.
3434 Imm = SplatBits >> 16;
3435 SplatBits |= 0xffff;
3439 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3440 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3441 // VMOV.I32. A (very) minor optimization would be to replicate the value
3442 // and fall through here to test for a valid 64-bit splat. But, then the
3443 // caller would also need to check and handle the change in size.
3447 if (type != VMOVModImm)
3449 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3450 uint64_t BitMask = 0xff;
3452 unsigned ImmMask = 1;
3454 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3455 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3458 } else if ((SplatBits & BitMask) != 0) {
3464 // Op=1, Cmode=1110.
3467 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3472 llvm_unreachable("unexpected size for isNEONModifiedImm");
3476 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3477 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3480 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3481 bool &ReverseVEXT, unsigned &Imm) {
3482 unsigned NumElts = VT.getVectorNumElements();
3483 ReverseVEXT = false;
3485 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3491 // If this is a VEXT shuffle, the immediate value is the index of the first
3492 // element. The other shuffle indices must be the successive elements after
3494 unsigned ExpectedElt = Imm;
3495 for (unsigned i = 1; i < NumElts; ++i) {
3496 // Increment the expected index. If it wraps around, it may still be
3497 // a VEXT but the source vectors must be swapped.
3499 if (ExpectedElt == NumElts * 2) {
3504 if (M[i] < 0) continue; // ignore UNDEF indices
3505 if (ExpectedElt != static_cast<unsigned>(M[i]))
3509 // Adjust the index value if the source operands will be swapped.
3516 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3517 /// instruction with the specified blocksize. (The order of the elements
3518 /// within each block of the vector is reversed.)
3519 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3520 unsigned BlockSize) {
3521 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3522 "Only possible block sizes for VREV are: 16, 32, 64");
3524 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3528 unsigned NumElts = VT.getVectorNumElements();
3529 unsigned BlockElts = M[0] + 1;
3530 // If the first shuffle index is UNDEF, be optimistic.
3532 BlockElts = BlockSize / EltSz;
3534 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3537 for (unsigned i = 0; i < NumElts; ++i) {
3538 if (M[i] < 0) continue; // ignore UNDEF indices
3539 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3546 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3547 unsigned &WhichResult) {
3548 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3552 unsigned NumElts = VT.getVectorNumElements();
3553 WhichResult = (M[0] == 0 ? 0 : 1);
3554 for (unsigned i = 0; i < NumElts; i += 2) {
3555 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3556 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3562 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3563 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3564 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3565 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3566 unsigned &WhichResult) {
3567 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3571 unsigned NumElts = VT.getVectorNumElements();
3572 WhichResult = (M[0] == 0 ? 0 : 1);
3573 for (unsigned i = 0; i < NumElts; i += 2) {
3574 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3575 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3581 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3582 unsigned &WhichResult) {
3583 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3587 unsigned NumElts = VT.getVectorNumElements();
3588 WhichResult = (M[0] == 0 ? 0 : 1);
3589 for (unsigned i = 0; i != NumElts; ++i) {
3590 if (M[i] < 0) continue; // ignore UNDEF indices
3591 if ((unsigned) M[i] != 2 * i + WhichResult)
3595 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3596 if (VT.is64BitVector() && EltSz == 32)
3602 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3603 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3604 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3605 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3606 unsigned &WhichResult) {
3607 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3611 unsigned Half = VT.getVectorNumElements() / 2;
3612 WhichResult = (M[0] == 0 ? 0 : 1);
3613 for (unsigned j = 0; j != 2; ++j) {
3614 unsigned Idx = WhichResult;
3615 for (unsigned i = 0; i != Half; ++i) {
3616 int MIdx = M[i + j * Half];
3617 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3623 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3624 if (VT.is64BitVector() && EltSz == 32)
3630 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3631 unsigned &WhichResult) {
3632 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3636 unsigned NumElts = VT.getVectorNumElements();
3637 WhichResult = (M[0] == 0 ? 0 : 1);
3638 unsigned Idx = WhichResult * NumElts / 2;
3639 for (unsigned i = 0; i != NumElts; i += 2) {
3640 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3641 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3646 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3647 if (VT.is64BitVector() && EltSz == 32)
3653 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3654 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3655 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3656 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3657 unsigned &WhichResult) {
3658 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3662 unsigned NumElts = VT.getVectorNumElements();
3663 WhichResult = (M[0] == 0 ? 0 : 1);
3664 unsigned Idx = WhichResult * NumElts / 2;
3665 for (unsigned i = 0; i != NumElts; i += 2) {
3666 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3667 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3672 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3673 if (VT.is64BitVector() && EltSz == 32)
3679 // If N is an integer constant that can be moved into a register in one
3680 // instruction, return an SDValue of such a constant (will become a MOV
3681 // instruction). Otherwise return null.
3682 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3683 const ARMSubtarget *ST, DebugLoc dl) {
3685 if (!isa<ConstantSDNode>(N))
3687 Val = cast<ConstantSDNode>(N)->getZExtValue();
3689 if (ST->isThumb1Only()) {
3690 if (Val <= 255 || ~Val <= 255)
3691 return DAG.getConstant(Val, MVT::i32);
3693 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3694 return DAG.getConstant(Val, MVT::i32);
3699 // If this is a case we can't handle, return null and let the default
3700 // expansion code take care of it.
3701 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3702 const ARMSubtarget *ST) const {
3703 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3704 DebugLoc dl = Op.getDebugLoc();
3705 EVT VT = Op.getValueType();
3707 APInt SplatBits, SplatUndef;
3708 unsigned SplatBitSize;
3710 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3711 if (SplatBitSize <= 64) {
3712 // Check if an immediate VMOV works.
3714 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3715 SplatUndef.getZExtValue(), SplatBitSize,
3716 DAG, VmovVT, VT.is128BitVector(),
3718 if (Val.getNode()) {
3719 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3720 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3723 // Try an immediate VMVN.
3724 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3725 ((1LL << SplatBitSize) - 1));
3726 Val = isNEONModifiedImm(NegatedImm,
3727 SplatUndef.getZExtValue(), SplatBitSize,
3728 DAG, VmovVT, VT.is128BitVector(),
3730 if (Val.getNode()) {
3731 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3732 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3737 // Scan through the operands to see if only one value is used.
3738 unsigned NumElts = VT.getVectorNumElements();
3739 bool isOnlyLowElement = true;
3740 bool usesOnlyOneValue = true;
3741 bool isConstant = true;
3743 for (unsigned i = 0; i < NumElts; ++i) {
3744 SDValue V = Op.getOperand(i);
3745 if (V.getOpcode() == ISD::UNDEF)
3748 isOnlyLowElement = false;
3749 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3752 if (!Value.getNode())
3754 else if (V != Value)
3755 usesOnlyOneValue = false;
3758 if (!Value.getNode())
3759 return DAG.getUNDEF(VT);
3761 if (isOnlyLowElement)
3762 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3764 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3766 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3767 // i32 and try again.
3768 if (usesOnlyOneValue && EltSize <= 32) {
3770 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3771 if (VT.getVectorElementType().isFloatingPoint()) {
3772 SmallVector<SDValue, 8> Ops;
3773 for (unsigned i = 0; i < NumElts; ++i)
3774 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3776 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3777 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3778 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3780 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3782 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3784 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3787 // If all elements are constants and the case above didn't get hit, fall back
3788 // to the default expansion, which will generate a load from the constant
3793 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3795 SDValue shuffle = ReconstructShuffle(Op, DAG);
3796 if (shuffle != SDValue())
3800 // Vectors with 32- or 64-bit elements can be built by directly assigning
3801 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3802 // will be legalized.
3803 if (EltSize >= 32) {
3804 // Do the expansion with floating-point types, since that is what the VFP
3805 // registers are defined to use, and since i64 is not legal.
3806 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3807 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3808 SmallVector<SDValue, 8> Ops;
3809 for (unsigned i = 0; i < NumElts; ++i)
3810 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3811 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3812 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3818 // Gather data to see if the operation can be modelled as a
3819 // shuffle in combination with VEXTs.
3820 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3821 SelectionDAG &DAG) const {
3822 DebugLoc dl = Op.getDebugLoc();
3823 EVT VT = Op.getValueType();
3824 unsigned NumElts = VT.getVectorNumElements();
3826 SmallVector<SDValue, 2> SourceVecs;
3827 SmallVector<unsigned, 2> MinElts;
3828 SmallVector<unsigned, 2> MaxElts;
3830 for (unsigned i = 0; i < NumElts; ++i) {
3831 SDValue V = Op.getOperand(i);
3832 if (V.getOpcode() == ISD::UNDEF)
3834 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3835 // A shuffle can only come from building a vector from various
3836 // elements of other vectors.
3840 // Record this extraction against the appropriate vector if possible...
3841 SDValue SourceVec = V.getOperand(0);
3842 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
3843 bool FoundSource = false;
3844 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
3845 if (SourceVecs[j] == SourceVec) {
3846 if (MinElts[j] > EltNo)
3848 if (MaxElts[j] < EltNo)
3855 // Or record a new source if not...
3857 SourceVecs.push_back(SourceVec);
3858 MinElts.push_back(EltNo);
3859 MaxElts.push_back(EltNo);
3863 // Currently only do something sane when at most two source vectors
3865 if (SourceVecs.size() > 2)
3868 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
3869 int VEXTOffsets[2] = {0, 0};
3871 // This loop extracts the usage patterns of the source vectors
3872 // and prepares appropriate SDValues for a shuffle if possible.
3873 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
3874 if (SourceVecs[i].getValueType() == VT) {
3875 // No VEXT necessary
3876 ShuffleSrcs[i] = SourceVecs[i];
3879 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
3880 // It probably isn't worth padding out a smaller vector just to
3881 // break it down again in a shuffle.
3885 // Since only 64-bit and 128-bit vectors are legal on ARM and
3886 // we've eliminated the other cases...
3887 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
3888 "unexpected vector sizes in ReconstructShuffle");
3890 if (MaxElts[i] - MinElts[i] >= NumElts) {
3891 // Span too large for a VEXT to cope
3895 if (MinElts[i] >= NumElts) {
3896 // The extraction can just take the second half
3897 VEXTOffsets[i] = NumElts;
3898 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3900 DAG.getIntPtrConstant(NumElts));
3901 } else if (MaxElts[i] < NumElts) {
3902 // The extraction can just take the first half
3904 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3906 DAG.getIntPtrConstant(0));
3908 // An actual VEXT is needed
3909 VEXTOffsets[i] = MinElts[i];
3910 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3912 DAG.getIntPtrConstant(0));
3913 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3915 DAG.getIntPtrConstant(NumElts));
3916 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
3917 DAG.getConstant(VEXTOffsets[i], MVT::i32));
3921 SmallVector<int, 8> Mask;
3923 for (unsigned i = 0; i < NumElts; ++i) {
3924 SDValue Entry = Op.getOperand(i);
3925 if (Entry.getOpcode() == ISD::UNDEF) {
3930 SDValue ExtractVec = Entry.getOperand(0);
3931 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
3932 .getOperand(1))->getSExtValue();
3933 if (ExtractVec == SourceVecs[0]) {
3934 Mask.push_back(ExtractElt - VEXTOffsets[0]);
3936 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
3940 // Final check before we try to produce nonsense...
3941 if (isShuffleMaskLegal(Mask, VT))
3942 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
3948 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3949 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3950 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3951 /// are assumed to be legal.
3953 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3955 if (VT.getVectorNumElements() == 4 &&
3956 (VT.is128BitVector() || VT.is64BitVector())) {
3957 unsigned PFIndexes[4];
3958 for (unsigned i = 0; i != 4; ++i) {
3962 PFIndexes[i] = M[i];
3965 // Compute the index in the perfect shuffle table.
3966 unsigned PFTableIndex =
3967 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3968 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3969 unsigned Cost = (PFEntry >> 30);
3976 unsigned Imm, WhichResult;
3978 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3979 return (EltSize >= 32 ||
3980 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3981 isVREVMask(M, VT, 64) ||
3982 isVREVMask(M, VT, 32) ||
3983 isVREVMask(M, VT, 16) ||
3984 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3985 isVTRNMask(M, VT, WhichResult) ||
3986 isVUZPMask(M, VT, WhichResult) ||
3987 isVZIPMask(M, VT, WhichResult) ||
3988 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3989 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3990 isVZIP_v_undef_Mask(M, VT, WhichResult));
3993 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3994 /// the specified operations to build the shuffle.
3995 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3996 SDValue RHS, SelectionDAG &DAG,
3998 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3999 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4000 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4003 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4012 OP_VUZPL, // VUZP, left result
4013 OP_VUZPR, // VUZP, right result
4014 OP_VZIPL, // VZIP, left result
4015 OP_VZIPR, // VZIP, right result
4016 OP_VTRNL, // VTRN, left result
4017 OP_VTRNR // VTRN, right result
4020 if (OpNum == OP_COPY) {
4021 if (LHSID == (1*9+2)*9+3) return LHS;
4022 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4026 SDValue OpLHS, OpRHS;
4027 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4028 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4029 EVT VT = OpLHS.getValueType();
4032 default: llvm_unreachable("Unknown shuffle opcode!");
4034 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4039 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4040 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4044 return DAG.getNode(ARMISD::VEXT, dl, VT,
4046 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4049 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4050 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4053 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4054 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4057 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4058 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4062 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4063 SmallVectorImpl<int> &ShuffleMask,
4064 SelectionDAG &DAG) {
4065 // Check to see if we can use the VTBL instruction.
4066 SDValue V1 = Op.getOperand(0);
4067 SDValue V2 = Op.getOperand(1);
4068 DebugLoc DL = Op.getDebugLoc();
4070 SmallVector<SDValue, 8> VTBLMask;
4071 for (SmallVectorImpl<int>::iterator
4072 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4073 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4075 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4076 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4077 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4080 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4081 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4085 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4086 SDValue V1 = Op.getOperand(0);
4087 SDValue V2 = Op.getOperand(1);
4088 DebugLoc dl = Op.getDebugLoc();
4089 EVT VT = Op.getValueType();
4090 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4091 SmallVector<int, 8> ShuffleMask;
4093 // Convert shuffles that are directly supported on NEON to target-specific
4094 // DAG nodes, instead of keeping them as shuffles and matching them again
4095 // during code selection. This is more efficient and avoids the possibility
4096 // of inconsistencies between legalization and selection.
4097 // FIXME: floating-point vectors should be canonicalized to integer vectors
4098 // of the same time so that they get CSEd properly.
4099 SVN->getMask(ShuffleMask);
4101 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4102 if (EltSize <= 32) {
4103 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4104 int Lane = SVN->getSplatIndex();
4105 // If this is undef splat, generate it via "just" vdup, if possible.
4106 if (Lane == -1) Lane = 0;
4108 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4109 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4111 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4112 DAG.getConstant(Lane, MVT::i32));
4117 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4120 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4121 DAG.getConstant(Imm, MVT::i32));
4124 if (isVREVMask(ShuffleMask, VT, 64))
4125 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4126 if (isVREVMask(ShuffleMask, VT, 32))
4127 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4128 if (isVREVMask(ShuffleMask, VT, 16))
4129 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4131 // Check for Neon shuffles that modify both input vectors in place.
4132 // If both results are used, i.e., if there are two shuffles with the same
4133 // source operands and with masks corresponding to both results of one of
4134 // these operations, DAG memoization will ensure that a single node is
4135 // used for both shuffles.
4136 unsigned WhichResult;
4137 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4138 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4139 V1, V2).getValue(WhichResult);
4140 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4141 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4142 V1, V2).getValue(WhichResult);
4143 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4144 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4145 V1, V2).getValue(WhichResult);
4147 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4148 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4149 V1, V1).getValue(WhichResult);
4150 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4151 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4152 V1, V1).getValue(WhichResult);
4153 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4154 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4155 V1, V1).getValue(WhichResult);
4158 // If the shuffle is not directly supported and it has 4 elements, use
4159 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4160 unsigned NumElts = VT.getVectorNumElements();
4162 unsigned PFIndexes[4];
4163 for (unsigned i = 0; i != 4; ++i) {
4164 if (ShuffleMask[i] < 0)
4167 PFIndexes[i] = ShuffleMask[i];
4170 // Compute the index in the perfect shuffle table.
4171 unsigned PFTableIndex =
4172 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4173 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4174 unsigned Cost = (PFEntry >> 30);
4177 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4180 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4181 if (EltSize >= 32) {
4182 // Do the expansion with floating-point types, since that is what the VFP
4183 // registers are defined to use, and since i64 is not legal.
4184 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4185 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4186 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4187 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4188 SmallVector<SDValue, 8> Ops;
4189 for (unsigned i = 0; i < NumElts; ++i) {
4190 if (ShuffleMask[i] < 0)
4191 Ops.push_back(DAG.getUNDEF(EltVT));
4193 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4194 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4195 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4198 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4199 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4202 if (VT == MVT::v8i8) {
4203 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4204 if (NewOp.getNode())
4211 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4212 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4213 SDValue Lane = Op.getOperand(1);
4214 if (!isa<ConstantSDNode>(Lane))
4217 SDValue Vec = Op.getOperand(0);
4218 if (Op.getValueType() == MVT::i32 &&
4219 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4220 DebugLoc dl = Op.getDebugLoc();
4221 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4227 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4228 // The only time a CONCAT_VECTORS operation can have legal types is when
4229 // two 64-bit vectors are concatenated to a 128-bit vector.
4230 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4231 "unexpected CONCAT_VECTORS");
4232 DebugLoc dl = Op.getDebugLoc();
4233 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4234 SDValue Op0 = Op.getOperand(0);
4235 SDValue Op1 = Op.getOperand(1);
4236 if (Op0.getOpcode() != ISD::UNDEF)
4237 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4238 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4239 DAG.getIntPtrConstant(0));
4240 if (Op1.getOpcode() != ISD::UNDEF)
4241 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4242 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4243 DAG.getIntPtrConstant(1));
4244 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4247 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4248 /// element has been zero/sign-extended, depending on the isSigned parameter,
4249 /// from an integer type half its size.
4250 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4252 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4253 EVT VT = N->getValueType(0);
4254 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4255 SDNode *BVN = N->getOperand(0).getNode();
4256 if (BVN->getValueType(0) != MVT::v4i32 ||
4257 BVN->getOpcode() != ISD::BUILD_VECTOR)
4259 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4260 unsigned HiElt = 1 - LoElt;
4261 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4262 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4263 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4264 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4265 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4268 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4269 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4272 if (Hi0->isNullValue() && Hi1->isNullValue())
4278 if (N->getOpcode() != ISD::BUILD_VECTOR)
4281 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4282 SDNode *Elt = N->getOperand(i).getNode();
4283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4284 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4285 unsigned HalfSize = EltSize / 2;
4287 int64_t SExtVal = C->getSExtValue();
4288 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4291 if ((C->getZExtValue() >> HalfSize) != 0)
4302 /// isSignExtended - Check if a node is a vector value that is sign-extended
4303 /// or a constant BUILD_VECTOR with sign-extended elements.
4304 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4305 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4307 if (isExtendedBUILD_VECTOR(N, DAG, true))
4312 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4313 /// or a constant BUILD_VECTOR with zero-extended elements.
4314 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4315 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4317 if (isExtendedBUILD_VECTOR(N, DAG, false))
4322 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4323 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4324 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4325 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4326 return N->getOperand(0);
4327 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4328 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4329 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4330 LD->isNonTemporal(), LD->getAlignment());
4331 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4332 // have been legalized as a BITCAST from v4i32.
4333 if (N->getOpcode() == ISD::BITCAST) {
4334 SDNode *BVN = N->getOperand(0).getNode();
4335 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4336 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4337 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4338 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4339 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4341 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4342 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4343 EVT VT = N->getValueType(0);
4344 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4345 unsigned NumElts = VT.getVectorNumElements();
4346 MVT TruncVT = MVT::getIntegerVT(EltSize);
4347 SmallVector<SDValue, 8> Ops;
4348 for (unsigned i = 0; i != NumElts; ++i) {
4349 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4350 const APInt &CInt = C->getAPIntValue();
4351 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4353 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4354 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4357 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4358 // Multiplications are only custom-lowered for 128-bit vectors so that
4359 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4360 EVT VT = Op.getValueType();
4361 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4362 SDNode *N0 = Op.getOperand(0).getNode();
4363 SDNode *N1 = Op.getOperand(1).getNode();
4364 unsigned NewOpc = 0;
4365 if (isSignExtended(N0, DAG) && isSignExtended(N1, DAG))
4366 NewOpc = ARMISD::VMULLs;
4367 else if (isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG))
4368 NewOpc = ARMISD::VMULLu;
4369 else if (VT == MVT::v2i64)
4370 // Fall through to expand this. It is not legal.
4373 // Other vector multiplications are legal.
4376 // Legalize to a VMULL instruction.
4377 DebugLoc DL = Op.getDebugLoc();
4378 SDValue Op0 = SkipExtension(N0, DAG);
4379 SDValue Op1 = SkipExtension(N1, DAG);
4381 assert(Op0.getValueType().is64BitVector() &&
4382 Op1.getValueType().is64BitVector() &&
4383 "unexpected types for extended operands to VMULL");
4384 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4388 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4390 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4391 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4392 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4393 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4394 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4395 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4396 // Get reciprocal estimate.
4397 // float4 recip = vrecpeq_f32(yf);
4398 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4399 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4400 // Because char has a smaller range than uchar, we can actually get away
4401 // without any newton steps. This requires that we use a weird bias
4402 // of 0xb000, however (again, this has been exhaustively tested).
4403 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4404 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4405 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4406 Y = DAG.getConstant(0xb000, MVT::i32);
4407 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4408 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4409 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4410 // Convert back to short.
4411 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4412 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4417 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4419 // Convert to float.
4420 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4421 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4422 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4423 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4424 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4425 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4427 // Use reciprocal estimate and one refinement step.
4428 // float4 recip = vrecpeq_f32(yf);
4429 // recip *= vrecpsq_f32(yf, recip);
4430 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4431 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4432 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4433 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4435 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4436 // Because short has a smaller range than ushort, we can actually get away
4437 // with only a single newton step. This requires that we use a weird bias
4438 // of 89, however (again, this has been exhaustively tested).
4439 // float4 result = as_float4(as_int4(xf*recip) + 89);
4440 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4441 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4442 N1 = DAG.getConstant(89, MVT::i32);
4443 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4444 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4445 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4446 // Convert back to integer and return.
4447 // return vmovn_s32(vcvt_s32_f32(result));
4448 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4449 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4453 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4454 EVT VT = Op.getValueType();
4455 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4456 "unexpected type for custom-lowering ISD::SDIV");
4458 DebugLoc dl = Op.getDebugLoc();
4459 SDValue N0 = Op.getOperand(0);
4460 SDValue N1 = Op.getOperand(1);
4463 if (VT == MVT::v8i8) {
4464 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4465 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4467 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4468 DAG.getIntPtrConstant(4));
4469 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4470 DAG.getIntPtrConstant(4));
4471 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4472 DAG.getIntPtrConstant(0));
4473 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4474 DAG.getIntPtrConstant(0));
4476 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4477 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4479 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4480 N0 = LowerCONCAT_VECTORS(N0, DAG);
4482 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4485 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4488 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4489 EVT VT = Op.getValueType();
4490 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4491 "unexpected type for custom-lowering ISD::UDIV");
4493 DebugLoc dl = Op.getDebugLoc();
4494 SDValue N0 = Op.getOperand(0);
4495 SDValue N1 = Op.getOperand(1);
4498 if (VT == MVT::v8i8) {
4499 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4500 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4502 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4503 DAG.getIntPtrConstant(4));
4504 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4505 DAG.getIntPtrConstant(4));
4506 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4507 DAG.getIntPtrConstant(0));
4508 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4509 DAG.getIntPtrConstant(0));
4511 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4512 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4514 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4515 N0 = LowerCONCAT_VECTORS(N0, DAG);
4517 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4518 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4523 // v4i16 sdiv ... Convert to float.
4524 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4525 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4526 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4527 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4528 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4529 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4531 // Use reciprocal estimate and two refinement steps.
4532 // float4 recip = vrecpeq_f32(yf);
4533 // recip *= vrecpsq_f32(yf, recip);
4534 // recip *= vrecpsq_f32(yf, recip);
4535 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4536 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4537 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4538 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4540 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4541 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4542 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4544 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4545 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4546 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4547 // and that it will never cause us to return an answer too large).
4548 // float4 result = as_float4(as_int4(xf*recip) + 89);
4549 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4550 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4551 N1 = DAG.getConstant(2, MVT::i32);
4552 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4553 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4554 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4555 // Convert back to integer and return.
4556 // return vmovn_u32(vcvt_s32_f32(result));
4557 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4558 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4562 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4563 switch (Op.getOpcode()) {
4564 default: llvm_unreachable("Don't know how to custom lower this!");
4565 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4566 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4567 case ISD::GlobalAddress:
4568 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4569 LowerGlobalAddressELF(Op, DAG);
4570 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4571 case ISD::SELECT: return LowerSELECT(Op, DAG);
4572 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4573 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4574 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4575 case ISD::VASTART: return LowerVASTART(Op, DAG);
4576 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4577 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4578 case ISD::SINT_TO_FP:
4579 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4580 case ISD::FP_TO_SINT:
4581 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4582 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4583 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4584 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4585 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4586 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4587 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4588 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4589 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4591 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4594 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4595 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4596 case ISD::SRL_PARTS:
4597 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4598 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4599 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4600 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4601 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4602 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4603 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4604 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4605 case ISD::MUL: return LowerMUL(Op, DAG);
4606 case ISD::SDIV: return LowerSDIV(Op, DAG);
4607 case ISD::UDIV: return LowerUDIV(Op, DAG);
4612 /// ReplaceNodeResults - Replace the results of node with an illegal result
4613 /// type with new values built out of custom code.
4614 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4615 SmallVectorImpl<SDValue>&Results,
4616 SelectionDAG &DAG) const {
4618 switch (N->getOpcode()) {
4620 llvm_unreachable("Don't know how to custom expand this!");
4623 Res = ExpandBITCAST(N, DAG);
4627 Res = Expand64BitShift(N, DAG, Subtarget);
4631 Results.push_back(Res);
4634 //===----------------------------------------------------------------------===//
4635 // ARM Scheduler Hooks
4636 //===----------------------------------------------------------------------===//
4639 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4640 MachineBasicBlock *BB,
4641 unsigned Size) const {
4642 unsigned dest = MI->getOperand(0).getReg();
4643 unsigned ptr = MI->getOperand(1).getReg();
4644 unsigned oldval = MI->getOperand(2).getReg();
4645 unsigned newval = MI->getOperand(3).getReg();
4646 unsigned scratch = BB->getParent()->getRegInfo()
4647 .createVirtualRegister(ARM::GPRRegisterClass);
4648 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4649 DebugLoc dl = MI->getDebugLoc();
4650 bool isThumb2 = Subtarget->isThumb2();
4652 unsigned ldrOpc, strOpc;
4654 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4656 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4657 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4660 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4661 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4664 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4665 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4669 MachineFunction *MF = BB->getParent();
4670 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4671 MachineFunction::iterator It = BB;
4672 ++It; // insert the new blocks after the current block
4674 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4675 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4676 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4677 MF->insert(It, loop1MBB);
4678 MF->insert(It, loop2MBB);
4679 MF->insert(It, exitMBB);
4681 // Transfer the remainder of BB and its successor edges to exitMBB.
4682 exitMBB->splice(exitMBB->begin(), BB,
4683 llvm::next(MachineBasicBlock::iterator(MI)),
4685 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4689 // fallthrough --> loop1MBB
4690 BB->addSuccessor(loop1MBB);
4693 // ldrex dest, [ptr]
4697 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4698 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4699 .addReg(dest).addReg(oldval));
4700 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4701 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4702 BB->addSuccessor(loop2MBB);
4703 BB->addSuccessor(exitMBB);
4706 // strex scratch, newval, [ptr]
4710 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4712 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4713 .addReg(scratch).addImm(0));
4714 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4715 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4716 BB->addSuccessor(loop1MBB);
4717 BB->addSuccessor(exitMBB);
4723 MI->eraseFromParent(); // The instruction is gone now.
4729 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4730 unsigned Size, unsigned BinOpcode) const {
4731 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4732 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4734 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4735 MachineFunction *MF = BB->getParent();
4736 MachineFunction::iterator It = BB;
4739 unsigned dest = MI->getOperand(0).getReg();
4740 unsigned ptr = MI->getOperand(1).getReg();
4741 unsigned incr = MI->getOperand(2).getReg();
4742 DebugLoc dl = MI->getDebugLoc();
4744 bool isThumb2 = Subtarget->isThumb2();
4745 unsigned ldrOpc, strOpc;
4747 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4749 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4750 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4753 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4754 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4757 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4758 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4762 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4763 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4764 MF->insert(It, loopMBB);
4765 MF->insert(It, exitMBB);
4767 // Transfer the remainder of BB and its successor edges to exitMBB.
4768 exitMBB->splice(exitMBB->begin(), BB,
4769 llvm::next(MachineBasicBlock::iterator(MI)),
4771 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4773 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4774 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4775 unsigned scratch2 = (!BinOpcode) ? incr :
4776 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4780 // fallthrough --> loopMBB
4781 BB->addSuccessor(loopMBB);
4785 // <binop> scratch2, dest, incr
4786 // strex scratch, scratch2, ptr
4789 // fallthrough --> exitMBB
4791 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4793 // operand order needs to go the other way for NAND
4794 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4795 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4796 addReg(incr).addReg(dest)).addReg(0);
4798 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4799 addReg(dest).addReg(incr)).addReg(0);
4802 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4804 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4805 .addReg(scratch).addImm(0));
4806 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4807 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4809 BB->addSuccessor(loopMBB);
4810 BB->addSuccessor(exitMBB);
4816 MI->eraseFromParent(); // The instruction is gone now.
4822 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4823 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4824 E = MBB->succ_end(); I != E; ++I)
4827 llvm_unreachable("Expecting a BB with two successors!");
4831 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4832 MachineBasicBlock *BB) const {
4833 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4834 DebugLoc dl = MI->getDebugLoc();
4835 bool isThumb2 = Subtarget->isThumb2();
4836 switch (MI->getOpcode()) {
4839 llvm_unreachable("Unexpected instr type to insert");
4841 case ARM::ATOMIC_LOAD_ADD_I8:
4842 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4843 case ARM::ATOMIC_LOAD_ADD_I16:
4844 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4845 case ARM::ATOMIC_LOAD_ADD_I32:
4846 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4848 case ARM::ATOMIC_LOAD_AND_I8:
4849 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4850 case ARM::ATOMIC_LOAD_AND_I16:
4851 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4852 case ARM::ATOMIC_LOAD_AND_I32:
4853 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4855 case ARM::ATOMIC_LOAD_OR_I8:
4856 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4857 case ARM::ATOMIC_LOAD_OR_I16:
4858 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4859 case ARM::ATOMIC_LOAD_OR_I32:
4860 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4862 case ARM::ATOMIC_LOAD_XOR_I8:
4863 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4864 case ARM::ATOMIC_LOAD_XOR_I16:
4865 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4866 case ARM::ATOMIC_LOAD_XOR_I32:
4867 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4869 case ARM::ATOMIC_LOAD_NAND_I8:
4870 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4871 case ARM::ATOMIC_LOAD_NAND_I16:
4872 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4873 case ARM::ATOMIC_LOAD_NAND_I32:
4874 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4876 case ARM::ATOMIC_LOAD_SUB_I8:
4877 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4878 case ARM::ATOMIC_LOAD_SUB_I16:
4879 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4880 case ARM::ATOMIC_LOAD_SUB_I32:
4881 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4883 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4884 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4885 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4887 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4888 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4889 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4891 case ARM::tMOVCCr_pseudo: {
4892 // To "insert" a SELECT_CC instruction, we actually have to insert the
4893 // diamond control-flow pattern. The incoming instruction knows the
4894 // destination vreg to set, the condition code register to branch on, the
4895 // true/false values to select between, and a branch opcode to use.
4896 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4897 MachineFunction::iterator It = BB;
4903 // cmpTY ccX, r1, r2
4905 // fallthrough --> copy0MBB
4906 MachineBasicBlock *thisMBB = BB;
4907 MachineFunction *F = BB->getParent();
4908 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4909 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4910 F->insert(It, copy0MBB);
4911 F->insert(It, sinkMBB);
4913 // Transfer the remainder of BB and its successor edges to sinkMBB.
4914 sinkMBB->splice(sinkMBB->begin(), BB,
4915 llvm::next(MachineBasicBlock::iterator(MI)),
4917 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4919 BB->addSuccessor(copy0MBB);
4920 BB->addSuccessor(sinkMBB);
4922 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4923 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4926 // %FalseValue = ...
4927 // # fallthrough to sinkMBB
4930 // Update machine-CFG edges
4931 BB->addSuccessor(sinkMBB);
4934 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4937 BuildMI(*BB, BB->begin(), dl,
4938 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4939 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4940 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4942 MI->eraseFromParent(); // The pseudo instruction is gone now.
4947 case ARM::BCCZi64: {
4948 // If there is an unconditional branch to the other successor, remove it.
4949 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
4951 // Compare both parts that make up the double comparison separately for
4953 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4955 unsigned LHS1 = MI->getOperand(1).getReg();
4956 unsigned LHS2 = MI->getOperand(2).getReg();
4958 AddDefaultPred(BuildMI(BB, dl,
4959 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4960 .addReg(LHS1).addImm(0));
4961 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4962 .addReg(LHS2).addImm(0)
4963 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4965 unsigned RHS1 = MI->getOperand(3).getReg();
4966 unsigned RHS2 = MI->getOperand(4).getReg();
4967 AddDefaultPred(BuildMI(BB, dl,
4968 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4969 .addReg(LHS1).addReg(RHS1));
4970 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4971 .addReg(LHS2).addReg(RHS2)
4972 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4975 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4976 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4977 if (MI->getOperand(0).getImm() == ARMCC::NE)
4978 std::swap(destMBB, exitMBB);
4980 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4981 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4982 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4985 MI->eraseFromParent(); // The pseudo instruction is gone now.
4991 //===----------------------------------------------------------------------===//
4992 // ARM Optimization Hooks
4993 //===----------------------------------------------------------------------===//
4996 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4997 TargetLowering::DAGCombinerInfo &DCI) {
4998 SelectionDAG &DAG = DCI.DAG;
4999 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5000 EVT VT = N->getValueType(0);
5001 unsigned Opc = N->getOpcode();
5002 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5003 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5004 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5005 ISD::CondCode CC = ISD::SETCC_INVALID;
5008 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5010 SDValue CCOp = Slct.getOperand(0);
5011 if (CCOp.getOpcode() == ISD::SETCC)
5012 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5015 bool DoXform = false;
5017 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5020 if (LHS.getOpcode() == ISD::Constant &&
5021 cast<ConstantSDNode>(LHS)->isNullValue()) {
5023 } else if (CC != ISD::SETCC_INVALID &&
5024 RHS.getOpcode() == ISD::Constant &&
5025 cast<ConstantSDNode>(RHS)->isNullValue()) {
5026 std::swap(LHS, RHS);
5027 SDValue Op0 = Slct.getOperand(0);
5028 EVT OpVT = isSlctCC ? Op0.getValueType() :
5029 Op0.getOperand(0).getValueType();
5030 bool isInt = OpVT.isInteger();
5031 CC = ISD::getSetCCInverse(CC, isInt);
5033 if (!TLI.isCondCodeLegal(CC, OpVT))
5034 return SDValue(); // Inverse operator isn't legal.
5041 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5043 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5044 Slct.getOperand(0), Slct.getOperand(1), CC);
5045 SDValue CCOp = Slct.getOperand(0);
5047 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5048 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5049 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5050 CCOp, OtherOp, Result);
5055 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5056 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5057 /// called with the default operands, and if that fails, with commuted
5059 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5060 TargetLowering::DAGCombinerInfo &DCI) {
5061 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5062 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5063 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5064 if (Result.getNode()) return Result;
5069 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5071 static SDValue PerformADDCombine(SDNode *N,
5072 TargetLowering::DAGCombinerInfo &DCI) {
5073 SDValue N0 = N->getOperand(0);
5074 SDValue N1 = N->getOperand(1);
5076 // First try with the default operand order.
5077 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
5078 if (Result.getNode())
5081 // If that didn't work, try again with the operands commuted.
5082 return PerformADDCombineWithOperands(N, N1, N0, DCI);
5085 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5087 static SDValue PerformSUBCombine(SDNode *N,
5088 TargetLowering::DAGCombinerInfo &DCI) {
5089 SDValue N0 = N->getOperand(0);
5090 SDValue N1 = N->getOperand(1);
5092 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5093 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5094 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5095 if (Result.getNode()) return Result;
5101 static SDValue PerformMULCombine(SDNode *N,
5102 TargetLowering::DAGCombinerInfo &DCI,
5103 const ARMSubtarget *Subtarget) {
5104 SelectionDAG &DAG = DCI.DAG;
5106 if (Subtarget->isThumb1Only())
5109 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5112 EVT VT = N->getValueType(0);
5116 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5120 uint64_t MulAmt = C->getZExtValue();
5121 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5122 ShiftAmt = ShiftAmt & (32 - 1);
5123 SDValue V = N->getOperand(0);
5124 DebugLoc DL = N->getDebugLoc();
5127 MulAmt >>= ShiftAmt;
5128 if (isPowerOf2_32(MulAmt - 1)) {
5129 // (mul x, 2^N + 1) => (add (shl x, N), x)
5130 Res = DAG.getNode(ISD::ADD, DL, VT,
5131 V, DAG.getNode(ISD::SHL, DL, VT,
5132 V, DAG.getConstant(Log2_32(MulAmt-1),
5134 } else if (isPowerOf2_32(MulAmt + 1)) {
5135 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5136 Res = DAG.getNode(ISD::SUB, DL, VT,
5137 DAG.getNode(ISD::SHL, DL, VT,
5138 V, DAG.getConstant(Log2_32(MulAmt+1),
5145 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5146 DAG.getConstant(ShiftAmt, MVT::i32));
5148 // Do not add new nodes to DAG combiner worklist.
5149 DCI.CombineTo(N, Res, false);
5153 static SDValue PerformANDCombine(SDNode *N,
5154 TargetLowering::DAGCombinerInfo &DCI) {
5155 // Attempt to use immediate-form VBIC
5156 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5157 DebugLoc dl = N->getDebugLoc();
5158 EVT VT = N->getValueType(0);
5159 SelectionDAG &DAG = DCI.DAG;
5161 APInt SplatBits, SplatUndef;
5162 unsigned SplatBitSize;
5165 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5166 if (SplatBitSize <= 64) {
5168 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5169 SplatUndef.getZExtValue(), SplatBitSize,
5170 DAG, VbicVT, VT.is128BitVector(),
5172 if (Val.getNode()) {
5174 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5175 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5176 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5184 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5185 static SDValue PerformORCombine(SDNode *N,
5186 TargetLowering::DAGCombinerInfo &DCI,
5187 const ARMSubtarget *Subtarget) {
5188 // Attempt to use immediate-form VORR
5189 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5190 DebugLoc dl = N->getDebugLoc();
5191 EVT VT = N->getValueType(0);
5192 SelectionDAG &DAG = DCI.DAG;
5194 APInt SplatBits, SplatUndef;
5195 unsigned SplatBitSize;
5197 if (BVN && Subtarget->hasNEON() &&
5198 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5199 if (SplatBitSize <= 64) {
5201 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5202 SplatUndef.getZExtValue(), SplatBitSize,
5203 DAG, VorrVT, VT.is128BitVector(),
5205 if (Val.getNode()) {
5207 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5208 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5209 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5214 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5217 // BFI is only available on V6T2+
5218 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5221 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
5222 DebugLoc DL = N->getDebugLoc();
5223 // 1) or (and A, mask), val => ARMbfi A, val, mask
5224 // iff (val & mask) == val
5226 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5227 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5228 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
5229 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5230 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
5231 // (i.e., copy a bitfield value into another bitfield of the same width)
5232 if (N0.getOpcode() != ISD::AND)
5238 SDValue N00 = N0.getOperand(0);
5240 // The value and the mask need to be constants so we can verify this is
5241 // actually a bitfield set. If the mask is 0xffff, we can do better
5242 // via a movt instruction, so don't use BFI in that case.
5243 SDValue MaskOp = N0.getOperand(1);
5244 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5247 unsigned Mask = MaskC->getZExtValue();
5251 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5252 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5254 unsigned Val = N1C->getZExtValue();
5255 if ((Val & ~Mask) != Val)
5258 if (ARM::isBitFieldInvertedMask(Mask)) {
5259 Val >>= CountTrailingZeros_32(~Mask);
5261 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5262 DAG.getConstant(Val, MVT::i32),
5263 DAG.getConstant(Mask, MVT::i32));
5265 // Do not add new nodes to DAG combiner worklist.
5266 DCI.CombineTo(N, Res, false);
5269 } else if (N1.getOpcode() == ISD::AND) {
5270 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5271 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5274 unsigned Mask2 = N11C->getZExtValue();
5276 if (ARM::isBitFieldInvertedMask(Mask) &&
5277 ARM::isBitFieldInvertedMask(~Mask2) &&
5278 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
5279 // The pack halfword instruction works better for masks that fit it,
5280 // so use that when it's available.
5281 if (Subtarget->hasT2ExtractPack() &&
5282 (Mask == 0xffff || Mask == 0xffff0000))
5285 unsigned lsb = CountTrailingZeros_32(Mask2);
5286 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5287 DAG.getConstant(lsb, MVT::i32));
5288 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5289 DAG.getConstant(Mask, MVT::i32));
5290 // Do not add new nodes to DAG combiner worklist.
5291 DCI.CombineTo(N, Res, false);
5293 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5294 ARM::isBitFieldInvertedMask(Mask2) &&
5295 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
5296 // The pack halfword instruction works better for masks that fit it,
5297 // so use that when it's available.
5298 if (Subtarget->hasT2ExtractPack() &&
5299 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5302 unsigned lsb = CountTrailingZeros_32(Mask);
5303 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5304 DAG.getConstant(lsb, MVT::i32));
5305 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5306 DAG.getConstant(Mask2, MVT::i32));
5307 // Do not add new nodes to DAG combiner worklist.
5308 DCI.CombineTo(N, Res, false);
5313 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5314 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5315 ARM::isBitFieldInvertedMask(~Mask)) {
5316 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5317 // where lsb(mask) == #shamt and masked bits of B are known zero.
5318 SDValue ShAmt = N00.getOperand(1);
5319 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5320 unsigned LSB = CountTrailingZeros_32(Mask);
5324 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5325 DAG.getConstant(~Mask, MVT::i32));
5327 // Do not add new nodes to DAG combiner worklist.
5328 DCI.CombineTo(N, Res, false);
5334 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5336 static SDValue PerformBFICombine(SDNode *N,
5337 TargetLowering::DAGCombinerInfo &DCI) {
5338 SDValue N1 = N->getOperand(1);
5339 if (N1.getOpcode() == ISD::AND) {
5340 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5343 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5344 unsigned Mask2 = N11C->getZExtValue();
5345 if ((Mask & Mask2) == Mask2)
5346 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5347 N->getOperand(0), N1.getOperand(0),
5353 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5354 /// ARMISD::VMOVRRD.
5355 static SDValue PerformVMOVRRDCombine(SDNode *N,
5356 TargetLowering::DAGCombinerInfo &DCI) {
5357 // vmovrrd(vmovdrr x, y) -> x,y
5358 SDValue InDouble = N->getOperand(0);
5359 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5360 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5364 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5365 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5366 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5367 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5368 SDValue Op0 = N->getOperand(0);
5369 SDValue Op1 = N->getOperand(1);
5370 if (Op0.getOpcode() == ISD::BITCAST)
5371 Op0 = Op0.getOperand(0);
5372 if (Op1.getOpcode() == ISD::BITCAST)
5373 Op1 = Op1.getOperand(0);
5374 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5375 Op0.getNode() == Op1.getNode() &&
5376 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5377 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5378 N->getValueType(0), Op0.getOperand(0));
5382 /// PerformSTORECombine - Target-specific dag combine xforms for
5384 static SDValue PerformSTORECombine(SDNode *N,
5385 TargetLowering::DAGCombinerInfo &DCI) {
5386 // Bitcast an i64 store extracted from a vector to f64.
5387 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5388 StoreSDNode *St = cast<StoreSDNode>(N);
5389 SDValue StVal = St->getValue();
5390 if (!ISD::isNormalStore(St) || St->isVolatile() ||
5391 StVal.getValueType() != MVT::i64 ||
5392 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5395 SelectionDAG &DAG = DCI.DAG;
5396 DebugLoc dl = StVal.getDebugLoc();
5397 SDValue IntVec = StVal.getOperand(0);
5398 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5399 IntVec.getValueType().getVectorNumElements());
5400 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5401 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5402 Vec, StVal.getOperand(1));
5403 dl = N->getDebugLoc();
5404 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5405 // Make the DAGCombiner fold the bitcasts.
5406 DCI.AddToWorklist(Vec.getNode());
5407 DCI.AddToWorklist(ExtElt.getNode());
5408 DCI.AddToWorklist(V.getNode());
5409 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5410 St->getPointerInfo(), St->isVolatile(),
5411 St->isNonTemporal(), St->getAlignment(),
5415 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5416 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5417 /// i64 vector to have f64 elements, since the value can then be loaded
5418 /// directly into a VFP register.
5419 static bool hasNormalLoadOperand(SDNode *N) {
5420 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5421 for (unsigned i = 0; i < NumElts; ++i) {
5422 SDNode *Elt = N->getOperand(i).getNode();
5423 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5429 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5430 /// ISD::BUILD_VECTOR.
5431 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5432 TargetLowering::DAGCombinerInfo &DCI){
5433 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
5434 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
5435 // into a pair of GPRs, which is fine when the value is used as a scalar,
5436 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
5437 SelectionDAG &DAG = DCI.DAG;
5438 if (N->getNumOperands() == 2) {
5439 SDValue RV = PerformVMOVDRRCombine(N, DAG);
5444 // Load i64 elements as f64 values so that type legalization does not split
5445 // them up into i32 values.
5446 EVT VT = N->getValueType(0);
5447 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
5449 DebugLoc dl = N->getDebugLoc();
5450 SmallVector<SDValue, 8> Ops;
5451 unsigned NumElts = VT.getVectorNumElements();
5452 for (unsigned i = 0; i < NumElts; ++i) {
5453 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
5455 // Make the DAGCombiner fold the bitcast.
5456 DCI.AddToWorklist(V.getNode());
5458 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
5459 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
5460 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
5463 /// PerformInsertEltCombine - Target-specific dag combine xforms for
5464 /// ISD::INSERT_VECTOR_ELT.
5465 static SDValue PerformInsertEltCombine(SDNode *N,
5466 TargetLowering::DAGCombinerInfo &DCI) {
5467 // Bitcast an i64 load inserted into a vector to f64.
5468 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5469 EVT VT = N->getValueType(0);
5470 SDNode *Elt = N->getOperand(1).getNode();
5471 if (VT.getVectorElementType() != MVT::i64 ||
5472 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
5475 SelectionDAG &DAG = DCI.DAG;
5476 DebugLoc dl = N->getDebugLoc();
5477 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5478 VT.getVectorNumElements());
5479 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
5480 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
5481 // Make the DAGCombiner fold the bitcasts.
5482 DCI.AddToWorklist(Vec.getNode());
5483 DCI.AddToWorklist(V.getNode());
5484 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
5485 Vec, V, N->getOperand(2));
5486 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
5489 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
5490 /// ISD::VECTOR_SHUFFLE.
5491 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
5492 // The LLVM shufflevector instruction does not require the shuffle mask
5493 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
5494 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
5495 // operands do not match the mask length, they are extended by concatenating
5496 // them with undef vectors. That is probably the right thing for other
5497 // targets, but for NEON it is better to concatenate two double-register
5498 // size vector operands into a single quad-register size vector. Do that
5499 // transformation here:
5500 // shuffle(concat(v1, undef), concat(v2, undef)) ->
5501 // shuffle(concat(v1, v2), undef)
5502 SDValue Op0 = N->getOperand(0);
5503 SDValue Op1 = N->getOperand(1);
5504 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
5505 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
5506 Op0.getNumOperands() != 2 ||
5507 Op1.getNumOperands() != 2)
5509 SDValue Concat0Op1 = Op0.getOperand(1);
5510 SDValue Concat1Op1 = Op1.getOperand(1);
5511 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
5512 Concat1Op1.getOpcode() != ISD::UNDEF)
5514 // Skip the transformation if any of the types are illegal.
5515 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5516 EVT VT = N->getValueType(0);
5517 if (!TLI.isTypeLegal(VT) ||
5518 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5519 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5522 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5523 Op0.getOperand(0), Op1.getOperand(0));
5524 // Translate the shuffle mask.
5525 SmallVector<int, 16> NewMask;
5526 unsigned NumElts = VT.getVectorNumElements();
5527 unsigned HalfElts = NumElts/2;
5528 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5529 for (unsigned n = 0; n < NumElts; ++n) {
5530 int MaskElt = SVN->getMaskElt(n);
5532 if (MaskElt < (int)HalfElts)
5534 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5535 NewElt = HalfElts + MaskElt - NumElts;
5536 NewMask.push_back(NewElt);
5538 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5539 DAG.getUNDEF(VT), NewMask.data());
5542 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
5543 /// NEON load/store intrinsics to merge base address updates.
5544 static SDValue CombineBaseUpdate(SDNode *N,
5545 TargetLowering::DAGCombinerInfo &DCI) {
5546 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5549 SelectionDAG &DAG = DCI.DAG;
5550 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
5551 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
5552 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
5553 SDValue Addr = N->getOperand(AddrOpIdx);
5555 // Search for a use of the address operand that is an increment.
5556 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
5557 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
5559 if (User->getOpcode() != ISD::ADD ||
5560 UI.getUse().getResNo() != Addr.getResNo())
5563 // Check that the add is independent of the load/store. Otherwise, folding
5564 // it would create a cycle.
5565 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
5568 // Find the new opcode for the updating load/store.
5570 bool isLaneOp = false;
5571 unsigned NewOpc = 0;
5572 unsigned NumVecs = 0;
5574 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
5576 default: assert(0 && "unexpected intrinsic for Neon base update");
5577 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
5579 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
5581 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
5583 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
5585 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
5586 NumVecs = 2; isLaneOp = true; break;
5587 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
5588 NumVecs = 3; isLaneOp = true; break;
5589 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
5590 NumVecs = 4; isLaneOp = true; break;
5591 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
5592 NumVecs = 1; isLoad = false; break;
5593 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
5594 NumVecs = 2; isLoad = false; break;
5595 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
5596 NumVecs = 3; isLoad = false; break;
5597 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
5598 NumVecs = 4; isLoad = false; break;
5599 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
5600 NumVecs = 2; isLoad = false; isLaneOp = true; break;
5601 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
5602 NumVecs = 3; isLoad = false; isLaneOp = true; break;
5603 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
5604 NumVecs = 4; isLoad = false; isLaneOp = true; break;
5608 switch (N->getOpcode()) {
5609 default: assert(0 && "unexpected opcode for Neon base update");
5610 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
5611 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
5612 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
5616 // Find the size of memory referenced by the load/store.
5619 VecTy = N->getValueType(0);
5621 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
5622 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
5624 NumBytes /= VecTy.getVectorNumElements();
5626 // If the increment is a constant, it must match the memory ref size.
5627 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
5628 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
5629 uint64_t IncVal = CInc->getZExtValue();
5630 if (IncVal != NumBytes)
5632 } else if (NumBytes >= 3 * 16) {
5633 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
5634 // separate instructions that make it harder to use a non-constant update.
5638 // Create the new updating load/store node.
5640 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
5642 for (n = 0; n < NumResultVecs; ++n)
5644 Tys[n++] = MVT::i32;
5645 Tys[n] = MVT::Other;
5646 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
5647 SmallVector<SDValue, 8> Ops;
5648 Ops.push_back(N->getOperand(0)); // incoming chain
5649 Ops.push_back(N->getOperand(AddrOpIdx));
5651 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
5652 Ops.push_back(N->getOperand(i));
5654 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
5655 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
5656 Ops.data(), Ops.size(),
5657 MemInt->getMemoryVT(),
5658 MemInt->getMemOperand());
5661 std::vector<SDValue> NewResults;
5662 for (unsigned i = 0; i < NumResultVecs; ++i) {
5663 NewResults.push_back(SDValue(UpdN.getNode(), i));
5665 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
5666 DCI.CombineTo(N, NewResults);
5667 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
5674 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
5675 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
5676 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
5678 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
5679 SelectionDAG &DAG = DCI.DAG;
5680 EVT VT = N->getValueType(0);
5681 // vldN-dup instructions only support 64-bit vectors for N > 1.
5682 if (!VT.is64BitVector())
5685 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
5686 SDNode *VLD = N->getOperand(0).getNode();
5687 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
5689 unsigned NumVecs = 0;
5690 unsigned NewOpc = 0;
5691 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
5692 if (IntNo == Intrinsic::arm_neon_vld2lane) {
5694 NewOpc = ARMISD::VLD2DUP;
5695 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
5697 NewOpc = ARMISD::VLD3DUP;
5698 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
5700 NewOpc = ARMISD::VLD4DUP;
5705 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
5706 // numbers match the load.
5707 unsigned VLDLaneNo =
5708 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
5709 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5711 // Ignore uses of the chain result.
5712 if (UI.getUse().getResNo() == NumVecs)
5715 if (User->getOpcode() != ARMISD::VDUPLANE ||
5716 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
5720 // Create the vldN-dup node.
5723 for (n = 0; n < NumVecs; ++n)
5725 Tys[n] = MVT::Other;
5726 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
5727 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
5728 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
5729 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
5730 Ops, 2, VLDMemInt->getMemoryVT(),
5731 VLDMemInt->getMemOperand());
5734 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5736 unsigned ResNo = UI.getUse().getResNo();
5737 // Ignore uses of the chain result.
5738 if (ResNo == NumVecs)
5741 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
5744 // Now the vldN-lane intrinsic is dead except for its chain result.
5745 // Update uses of the chain.
5746 std::vector<SDValue> VLDDupResults;
5747 for (unsigned n = 0; n < NumVecs; ++n)
5748 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
5749 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
5750 DCI.CombineTo(VLD, VLDDupResults);
5755 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
5756 /// ARMISD::VDUPLANE.
5757 static SDValue PerformVDUPLANECombine(SDNode *N,
5758 TargetLowering::DAGCombinerInfo &DCI) {
5759 SDValue Op = N->getOperand(0);
5761 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
5762 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
5763 if (CombineVLDDUP(N, DCI))
5764 return SDValue(N, 0);
5766 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
5767 // redundant. Ignore bit_converts for now; element sizes are checked below.
5768 while (Op.getOpcode() == ISD::BITCAST)
5769 Op = Op.getOperand(0);
5770 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
5773 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
5774 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
5775 // The canonical VMOV for a zero vector uses a 32-bit element size.
5776 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5778 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
5780 EVT VT = N->getValueType(0);
5781 if (EltSize > VT.getVectorElementType().getSizeInBits())
5784 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
5787 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5788 /// operand of a vector shift operation, where all the elements of the
5789 /// build_vector must have the same constant integer value.
5790 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5791 // Ignore bit_converts.
5792 while (Op.getOpcode() == ISD::BITCAST)
5793 Op = Op.getOperand(0);
5794 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5795 APInt SplatBits, SplatUndef;
5796 unsigned SplatBitSize;
5798 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5799 HasAnyUndefs, ElementBits) ||
5800 SplatBitSize > ElementBits)
5802 Cnt = SplatBits.getSExtValue();
5806 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5807 /// operand of a vector shift left operation. That value must be in the range:
5808 /// 0 <= Value < ElementBits for a left shift; or
5809 /// 0 <= Value <= ElementBits for a long left shift.
5810 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5811 assert(VT.isVector() && "vector shift count is not a vector type");
5812 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5813 if (! getVShiftImm(Op, ElementBits, Cnt))
5815 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
5818 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5819 /// operand of a vector shift right operation. For a shift opcode, the value
5820 /// is positive, but for an intrinsic the value count must be negative. The
5821 /// absolute value must be in the range:
5822 /// 1 <= |Value| <= ElementBits for a right shift; or
5823 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5824 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5826 assert(VT.isVector() && "vector shift count is not a vector type");
5827 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5828 if (! getVShiftImm(Op, ElementBits, Cnt))
5832 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
5835 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
5836 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
5837 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5840 // Don't do anything for most intrinsics.
5843 // Vector shifts: check for immediate versions and lower them.
5844 // Note: This is done during DAG combining instead of DAG legalizing because
5845 // the build_vectors for 64-bit vector element shift counts are generally
5846 // not legal, and it is hard to see their values after they get legalized to
5847 // loads from a constant pool.
5848 case Intrinsic::arm_neon_vshifts:
5849 case Intrinsic::arm_neon_vshiftu:
5850 case Intrinsic::arm_neon_vshiftls:
5851 case Intrinsic::arm_neon_vshiftlu:
5852 case Intrinsic::arm_neon_vshiftn:
5853 case Intrinsic::arm_neon_vrshifts:
5854 case Intrinsic::arm_neon_vrshiftu:
5855 case Intrinsic::arm_neon_vrshiftn:
5856 case Intrinsic::arm_neon_vqshifts:
5857 case Intrinsic::arm_neon_vqshiftu:
5858 case Intrinsic::arm_neon_vqshiftsu:
5859 case Intrinsic::arm_neon_vqshiftns:
5860 case Intrinsic::arm_neon_vqshiftnu:
5861 case Intrinsic::arm_neon_vqshiftnsu:
5862 case Intrinsic::arm_neon_vqrshiftns:
5863 case Intrinsic::arm_neon_vqrshiftnu:
5864 case Intrinsic::arm_neon_vqrshiftnsu: {
5865 EVT VT = N->getOperand(1).getValueType();
5867 unsigned VShiftOpc = 0;
5870 case Intrinsic::arm_neon_vshifts:
5871 case Intrinsic::arm_neon_vshiftu:
5872 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
5873 VShiftOpc = ARMISD::VSHL;
5876 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
5877 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
5878 ARMISD::VSHRs : ARMISD::VSHRu);
5883 case Intrinsic::arm_neon_vshiftls:
5884 case Intrinsic::arm_neon_vshiftlu:
5885 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
5887 llvm_unreachable("invalid shift count for vshll intrinsic");
5889 case Intrinsic::arm_neon_vrshifts:
5890 case Intrinsic::arm_neon_vrshiftu:
5891 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
5895 case Intrinsic::arm_neon_vqshifts:
5896 case Intrinsic::arm_neon_vqshiftu:
5897 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5901 case Intrinsic::arm_neon_vqshiftsu:
5902 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5904 llvm_unreachable("invalid shift count for vqshlu intrinsic");
5906 case Intrinsic::arm_neon_vshiftn:
5907 case Intrinsic::arm_neon_vrshiftn:
5908 case Intrinsic::arm_neon_vqshiftns:
5909 case Intrinsic::arm_neon_vqshiftnu:
5910 case Intrinsic::arm_neon_vqshiftnsu:
5911 case Intrinsic::arm_neon_vqrshiftns:
5912 case Intrinsic::arm_neon_vqrshiftnu:
5913 case Intrinsic::arm_neon_vqrshiftnsu:
5914 // Narrowing shifts require an immediate right shift.
5915 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
5917 llvm_unreachable("invalid shift count for narrowing vector shift "
5921 llvm_unreachable("unhandled vector shift");
5925 case Intrinsic::arm_neon_vshifts:
5926 case Intrinsic::arm_neon_vshiftu:
5927 // Opcode already set above.
5929 case Intrinsic::arm_neon_vshiftls:
5930 case Intrinsic::arm_neon_vshiftlu:
5931 if (Cnt == VT.getVectorElementType().getSizeInBits())
5932 VShiftOpc = ARMISD::VSHLLi;
5934 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
5935 ARMISD::VSHLLs : ARMISD::VSHLLu);
5937 case Intrinsic::arm_neon_vshiftn:
5938 VShiftOpc = ARMISD::VSHRN; break;
5939 case Intrinsic::arm_neon_vrshifts:
5940 VShiftOpc = ARMISD::VRSHRs; break;
5941 case Intrinsic::arm_neon_vrshiftu:
5942 VShiftOpc = ARMISD::VRSHRu; break;
5943 case Intrinsic::arm_neon_vrshiftn:
5944 VShiftOpc = ARMISD::VRSHRN; break;
5945 case Intrinsic::arm_neon_vqshifts:
5946 VShiftOpc = ARMISD::VQSHLs; break;
5947 case Intrinsic::arm_neon_vqshiftu:
5948 VShiftOpc = ARMISD::VQSHLu; break;
5949 case Intrinsic::arm_neon_vqshiftsu:
5950 VShiftOpc = ARMISD::VQSHLsu; break;
5951 case Intrinsic::arm_neon_vqshiftns:
5952 VShiftOpc = ARMISD::VQSHRNs; break;
5953 case Intrinsic::arm_neon_vqshiftnu:
5954 VShiftOpc = ARMISD::VQSHRNu; break;
5955 case Intrinsic::arm_neon_vqshiftnsu:
5956 VShiftOpc = ARMISD::VQSHRNsu; break;
5957 case Intrinsic::arm_neon_vqrshiftns:
5958 VShiftOpc = ARMISD::VQRSHRNs; break;
5959 case Intrinsic::arm_neon_vqrshiftnu:
5960 VShiftOpc = ARMISD::VQRSHRNu; break;
5961 case Intrinsic::arm_neon_vqrshiftnsu:
5962 VShiftOpc = ARMISD::VQRSHRNsu; break;
5965 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5966 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
5969 case Intrinsic::arm_neon_vshiftins: {
5970 EVT VT = N->getOperand(1).getValueType();
5972 unsigned VShiftOpc = 0;
5974 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
5975 VShiftOpc = ARMISD::VSLI;
5976 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
5977 VShiftOpc = ARMISD::VSRI;
5979 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
5982 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5983 N->getOperand(1), N->getOperand(2),
5984 DAG.getConstant(Cnt, MVT::i32));
5987 case Intrinsic::arm_neon_vqrshifts:
5988 case Intrinsic::arm_neon_vqrshiftu:
5989 // No immediate versions of these to check for.
5996 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
5997 /// lowers them. As with the vector shift intrinsics, this is done during DAG
5998 /// combining instead of DAG legalizing because the build_vectors for 64-bit
5999 /// vector element shift counts are generally not legal, and it is hard to see
6000 /// their values after they get legalized to loads from a constant pool.
6001 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6002 const ARMSubtarget *ST) {
6003 EVT VT = N->getValueType(0);
6005 // Nothing to be done for scalar shifts.
6006 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6007 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6010 assert(ST->hasNEON() && "unexpected vector shift");
6013 switch (N->getOpcode()) {
6014 default: llvm_unreachable("unexpected shift opcode");
6017 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6018 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6019 DAG.getConstant(Cnt, MVT::i32));
6024 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6025 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6026 ARMISD::VSHRs : ARMISD::VSHRu);
6027 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6028 DAG.getConstant(Cnt, MVT::i32));
6034 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6035 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6036 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6037 const ARMSubtarget *ST) {
6038 SDValue N0 = N->getOperand(0);
6040 // Check for sign- and zero-extensions of vector extract operations of 8-
6041 // and 16-bit vector elements. NEON supports these directly. They are
6042 // handled during DAG combining because type legalization will promote them
6043 // to 32-bit types and it is messy to recognize the operations after that.
6044 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6045 SDValue Vec = N0.getOperand(0);
6046 SDValue Lane = N0.getOperand(1);
6047 EVT VT = N->getValueType(0);
6048 EVT EltVT = N0.getValueType();
6049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6051 if (VT == MVT::i32 &&
6052 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6053 TLI.isTypeLegal(Vec.getValueType()) &&
6054 isa<ConstantSDNode>(Lane)) {
6057 switch (N->getOpcode()) {
6058 default: llvm_unreachable("unexpected opcode");
6059 case ISD::SIGN_EXTEND:
6060 Opc = ARMISD::VGETLANEs;
6062 case ISD::ZERO_EXTEND:
6063 case ISD::ANY_EXTEND:
6064 Opc = ARMISD::VGETLANEu;
6067 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6074 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6075 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6076 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6077 const ARMSubtarget *ST) {
6078 // If the target supports NEON, try to use vmax/vmin instructions for f32
6079 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6080 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6081 // a NaN; only do the transformation when it matches that behavior.
6083 // For now only do this when using NEON for FP operations; if using VFP, it
6084 // is not obvious that the benefit outweighs the cost of switching to the
6086 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6087 N->getValueType(0) != MVT::f32)
6090 SDValue CondLHS = N->getOperand(0);
6091 SDValue CondRHS = N->getOperand(1);
6092 SDValue LHS = N->getOperand(2);
6093 SDValue RHS = N->getOperand(3);
6094 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6096 unsigned Opcode = 0;
6098 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6099 IsReversed = false; // x CC y ? x : y
6100 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6101 IsReversed = true ; // x CC y ? y : x
6115 // If LHS is NaN, an ordered comparison will be false and the result will
6116 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6117 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6118 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6119 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6121 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6122 // will return -0, so vmin can only be used for unsafe math or if one of
6123 // the operands is known to be nonzero.
6124 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6126 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6128 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6137 // If LHS is NaN, an ordered comparison will be false and the result will
6138 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6139 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6140 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6141 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6143 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6144 // will return +0, so vmax can only be used for unsafe math or if one of
6145 // the operands is known to be nonzero.
6146 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6148 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6150 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6156 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6159 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6160 DAGCombinerInfo &DCI) const {
6161 switch (N->getOpcode()) {
6163 case ISD::ADD: return PerformADDCombine(N, DCI);
6164 case ISD::SUB: return PerformSUBCombine(N, DCI);
6165 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6166 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6167 case ISD::AND: return PerformANDCombine(N, DCI);
6168 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6169 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6170 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6171 case ISD::STORE: return PerformSTORECombine(N, DCI);
6172 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6173 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6174 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6175 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6176 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6179 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6180 case ISD::SIGN_EXTEND:
6181 case ISD::ZERO_EXTEND:
6182 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6183 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6184 case ARMISD::VLD2DUP:
6185 case ARMISD::VLD3DUP:
6186 case ARMISD::VLD4DUP:
6187 return CombineBaseUpdate(N, DCI);
6188 case ISD::INTRINSIC_VOID:
6189 case ISD::INTRINSIC_W_CHAIN:
6190 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6191 case Intrinsic::arm_neon_vld1:
6192 case Intrinsic::arm_neon_vld2:
6193 case Intrinsic::arm_neon_vld3:
6194 case Intrinsic::arm_neon_vld4:
6195 case Intrinsic::arm_neon_vld2lane:
6196 case Intrinsic::arm_neon_vld3lane:
6197 case Intrinsic::arm_neon_vld4lane:
6198 case Intrinsic::arm_neon_vst1:
6199 case Intrinsic::arm_neon_vst2:
6200 case Intrinsic::arm_neon_vst3:
6201 case Intrinsic::arm_neon_vst4:
6202 case Intrinsic::arm_neon_vst2lane:
6203 case Intrinsic::arm_neon_vst3lane:
6204 case Intrinsic::arm_neon_vst4lane:
6205 return CombineBaseUpdate(N, DCI);
6213 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6215 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6218 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6219 if (!Subtarget->allowsUnalignedMem())
6222 switch (VT.getSimpleVT().SimpleTy) {
6229 // FIXME: VLD1 etc with standard alignment is legal.
6233 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6238 switch (VT.getSimpleVT().SimpleTy) {
6239 default: return false;
6254 if ((V & (Scale - 1)) != 0)
6257 return V == (V & ((1LL << 5) - 1));
6260 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6261 const ARMSubtarget *Subtarget) {
6268 switch (VT.getSimpleVT().SimpleTy) {
6269 default: return false;
6274 // + imm12 or - imm8
6276 return V == (V & ((1LL << 8) - 1));
6277 return V == (V & ((1LL << 12) - 1));
6280 // Same as ARM mode. FIXME: NEON?
6281 if (!Subtarget->hasVFP2())
6286 return V == (V & ((1LL << 8) - 1));
6290 /// isLegalAddressImmediate - Return true if the integer value can be used
6291 /// as the offset of the target addressing mode for load / store of the
6293 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6294 const ARMSubtarget *Subtarget) {
6301 if (Subtarget->isThumb1Only())
6302 return isLegalT1AddressImmediate(V, VT);
6303 else if (Subtarget->isThumb2())
6304 return isLegalT2AddressImmediate(V, VT, Subtarget);
6309 switch (VT.getSimpleVT().SimpleTy) {
6310 default: return false;
6315 return V == (V & ((1LL << 12) - 1));
6318 return V == (V & ((1LL << 8) - 1));
6321 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6326 return V == (V & ((1LL << 8) - 1));
6330 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6332 int Scale = AM.Scale;
6336 switch (VT.getSimpleVT().SimpleTy) {
6337 default: return false;
6346 return Scale == 2 || Scale == 4 || Scale == 8;
6349 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6353 // Note, we allow "void" uses (basically, uses that aren't loads or
6354 // stores), because arm allows folding a scale into many arithmetic
6355 // operations. This should be made more precise and revisited later.
6357 // Allow r << imm, but the imm has to be a multiple of two.
6358 if (Scale & 1) return false;
6359 return isPowerOf2_32(Scale);
6363 /// isLegalAddressingMode - Return true if the addressing mode represented
6364 /// by AM is legal for this target, for a load/store of the specified type.
6365 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6366 const Type *Ty) const {
6367 EVT VT = getValueType(Ty, true);
6368 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6371 // Can never fold addr of global into load/store.
6376 case 0: // no scale reg, must be "r+i" or "r", or "i".
6379 if (Subtarget->isThumb1Only())
6383 // ARM doesn't support any R+R*scale+imm addr modes.
6390 if (Subtarget->isThumb2())
6391 return isLegalT2ScaledAddressingMode(AM, VT);
6393 int Scale = AM.Scale;
6394 switch (VT.getSimpleVT().SimpleTy) {
6395 default: return false;
6399 if (Scale < 0) Scale = -Scale;
6403 return isPowerOf2_32(Scale & ~1);
6407 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6412 // Note, we allow "void" uses (basically, uses that aren't loads or
6413 // stores), because arm allows folding a scale into many arithmetic
6414 // operations. This should be made more precise and revisited later.
6416 // Allow r << imm, but the imm has to be a multiple of two.
6417 if (Scale & 1) return false;
6418 return isPowerOf2_32(Scale);
6425 /// isLegalICmpImmediate - Return true if the specified immediate is legal
6426 /// icmp immediate, that is the target has icmp instructions which can compare
6427 /// a register against the immediate without having to materialize the
6428 /// immediate into a register.
6429 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
6430 if (!Subtarget->isThumb())
6431 return ARM_AM::getSOImmVal(Imm) != -1;
6432 if (Subtarget->isThumb2())
6433 return ARM_AM::getT2SOImmVal(Imm) != -1;
6434 return Imm >= 0 && Imm <= 255;
6437 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
6438 bool isSEXTLoad, SDValue &Base,
6439 SDValue &Offset, bool &isInc,
6440 SelectionDAG &DAG) {
6441 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6444 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
6446 Base = Ptr->getOperand(0);
6447 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6448 int RHSC = (int)RHS->getZExtValue();
6449 if (RHSC < 0 && RHSC > -256) {
6450 assert(Ptr->getOpcode() == ISD::ADD);
6452 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6456 isInc = (Ptr->getOpcode() == ISD::ADD);
6457 Offset = Ptr->getOperand(1);
6459 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
6461 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6462 int RHSC = (int)RHS->getZExtValue();
6463 if (RHSC < 0 && RHSC > -0x1000) {
6464 assert(Ptr->getOpcode() == ISD::ADD);
6466 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6467 Base = Ptr->getOperand(0);
6472 if (Ptr->getOpcode() == ISD::ADD) {
6474 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
6475 if (ShOpcVal != ARM_AM::no_shift) {
6476 Base = Ptr->getOperand(1);
6477 Offset = Ptr->getOperand(0);
6479 Base = Ptr->getOperand(0);
6480 Offset = Ptr->getOperand(1);
6485 isInc = (Ptr->getOpcode() == ISD::ADD);
6486 Base = Ptr->getOperand(0);
6487 Offset = Ptr->getOperand(1);
6491 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
6495 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
6496 bool isSEXTLoad, SDValue &Base,
6497 SDValue &Offset, bool &isInc,
6498 SelectionDAG &DAG) {
6499 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6502 Base = Ptr->getOperand(0);
6503 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6504 int RHSC = (int)RHS->getZExtValue();
6505 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
6506 assert(Ptr->getOpcode() == ISD::ADD);
6508 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6510 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
6511 isInc = Ptr->getOpcode() == ISD::ADD;
6512 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
6520 /// getPreIndexedAddressParts - returns true by value, base pointer and
6521 /// offset pointer and addressing mode by reference if the node's address
6522 /// can be legally represented as pre-indexed load / store address.
6524 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
6526 ISD::MemIndexedMode &AM,
6527 SelectionDAG &DAG) const {
6528 if (Subtarget->isThumb1Only())
6533 bool isSEXTLoad = false;
6534 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6535 Ptr = LD->getBasePtr();
6536 VT = LD->getMemoryVT();
6537 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6538 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6539 Ptr = ST->getBasePtr();
6540 VT = ST->getMemoryVT();
6545 bool isLegal = false;
6546 if (Subtarget->isThumb2())
6547 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6548 Offset, isInc, DAG);
6550 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6551 Offset, isInc, DAG);
6555 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
6559 /// getPostIndexedAddressParts - returns true by value, base pointer and
6560 /// offset pointer and addressing mode by reference if this node can be
6561 /// combined with a load / store to form a post-indexed load / store.
6562 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
6565 ISD::MemIndexedMode &AM,
6566 SelectionDAG &DAG) const {
6567 if (Subtarget->isThumb1Only())
6572 bool isSEXTLoad = false;
6573 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6574 VT = LD->getMemoryVT();
6575 Ptr = LD->getBasePtr();
6576 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6577 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6578 VT = ST->getMemoryVT();
6579 Ptr = ST->getBasePtr();
6584 bool isLegal = false;
6585 if (Subtarget->isThumb2())
6586 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6589 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6595 // Swap base ptr and offset to catch more post-index load / store when
6596 // it's legal. In Thumb2 mode, offset must be an immediate.
6597 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
6598 !Subtarget->isThumb2())
6599 std::swap(Base, Offset);
6601 // Post-indexed load / store update the base pointer.
6606 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
6610 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6614 const SelectionDAG &DAG,
6615 unsigned Depth) const {
6616 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
6617 switch (Op.getOpcode()) {
6619 case ARMISD::CMOV: {
6620 // Bits are known zero/one if known on the LHS and RHS.
6621 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
6622 if (KnownZero == 0 && KnownOne == 0) return;
6624 APInt KnownZeroRHS, KnownOneRHS;
6625 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
6626 KnownZeroRHS, KnownOneRHS, Depth+1);
6627 KnownZero &= KnownZeroRHS;
6628 KnownOne &= KnownOneRHS;
6634 //===----------------------------------------------------------------------===//
6635 // ARM Inline Assembly Support
6636 //===----------------------------------------------------------------------===//
6638 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
6639 // Looking for "rev" which is V6+.
6640 if (!Subtarget->hasV6Ops())
6643 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
6644 std::string AsmStr = IA->getAsmString();
6645 SmallVector<StringRef, 4> AsmPieces;
6646 SplitString(AsmStr, AsmPieces, ";\n");
6648 switch (AsmPieces.size()) {
6649 default: return false;
6651 AsmStr = AsmPieces[0];
6653 SplitString(AsmStr, AsmPieces, " \t,");
6656 if (AsmPieces.size() == 3 &&
6657 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
6658 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
6659 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
6660 if (Ty && Ty->getBitWidth() == 32)
6661 return IntrinsicLowering::LowerToByteSwap(CI);
6669 /// getConstraintType - Given a constraint letter, return the type of
6670 /// constraint it is for this target.
6671 ARMTargetLowering::ConstraintType
6672 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
6673 if (Constraint.size() == 1) {
6674 switch (Constraint[0]) {
6676 case 'l': return C_RegisterClass;
6677 case 'w': return C_RegisterClass;
6680 return TargetLowering::getConstraintType(Constraint);
6683 /// Examine constraint type and operand type and determine a weight value.
6684 /// This object must already have been set up with the operand type
6685 /// and the current alternative constraint selected.
6686 TargetLowering::ConstraintWeight
6687 ARMTargetLowering::getSingleConstraintMatchWeight(
6688 AsmOperandInfo &info, const char *constraint) const {
6689 ConstraintWeight weight = CW_Invalid;
6690 Value *CallOperandVal = info.CallOperandVal;
6691 // If we don't have a value, we can't do a match,
6692 // but allow it at the lowest weight.
6693 if (CallOperandVal == NULL)
6695 const Type *type = CallOperandVal->getType();
6696 // Look at the constraint type.
6697 switch (*constraint) {
6699 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6702 if (type->isIntegerTy()) {
6703 if (Subtarget->isThumb())
6704 weight = CW_SpecificReg;
6706 weight = CW_Register;
6710 if (type->isFloatingPointTy())
6711 weight = CW_Register;
6717 std::pair<unsigned, const TargetRegisterClass*>
6718 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6720 if (Constraint.size() == 1) {
6721 // GCC ARM Constraint Letters
6722 switch (Constraint[0]) {
6724 if (Subtarget->isThumb())
6725 return std::make_pair(0U, ARM::tGPRRegisterClass);
6727 return std::make_pair(0U, ARM::GPRRegisterClass);
6729 return std::make_pair(0U, ARM::GPRRegisterClass);
6732 return std::make_pair(0U, ARM::SPRRegisterClass);
6733 if (VT.getSizeInBits() == 64)
6734 return std::make_pair(0U, ARM::DPRRegisterClass);
6735 if (VT.getSizeInBits() == 128)
6736 return std::make_pair(0U, ARM::QPRRegisterClass);
6740 if (StringRef("{cc}").equals_lower(Constraint))
6741 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
6743 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6746 std::vector<unsigned> ARMTargetLowering::
6747 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6749 if (Constraint.size() != 1)
6750 return std::vector<unsigned>();
6752 switch (Constraint[0]) { // GCC ARM Constraint Letters
6755 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6756 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6759 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6760 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6761 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
6762 ARM::R12, ARM::LR, 0);
6765 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
6766 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
6767 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
6768 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
6769 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
6770 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
6771 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
6772 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
6773 if (VT.getSizeInBits() == 64)
6774 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
6775 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
6776 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
6777 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
6778 if (VT.getSizeInBits() == 128)
6779 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
6780 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
6784 return std::vector<unsigned>();
6787 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6788 /// vector. If it is invalid, don't add anything to Ops.
6789 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6791 std::vector<SDValue>&Ops,
6792 SelectionDAG &DAG) const {
6793 SDValue Result(0, 0);
6795 switch (Constraint) {
6797 case 'I': case 'J': case 'K': case 'L':
6798 case 'M': case 'N': case 'O':
6799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
6803 int64_t CVal64 = C->getSExtValue();
6804 int CVal = (int) CVal64;
6805 // None of these constraints allow values larger than 32 bits. Check
6806 // that the value fits in an int.
6810 switch (Constraint) {
6812 if (Subtarget->isThumb1Only()) {
6813 // This must be a constant between 0 and 255, for ADD
6815 if (CVal >= 0 && CVal <= 255)
6817 } else if (Subtarget->isThumb2()) {
6818 // A constant that can be used as an immediate value in a
6819 // data-processing instruction.
6820 if (ARM_AM::getT2SOImmVal(CVal) != -1)
6823 // A constant that can be used as an immediate value in a
6824 // data-processing instruction.
6825 if (ARM_AM::getSOImmVal(CVal) != -1)
6831 if (Subtarget->isThumb()) { // FIXME thumb2
6832 // This must be a constant between -255 and -1, for negated ADD
6833 // immediates. This can be used in GCC with an "n" modifier that
6834 // prints the negated value, for use with SUB instructions. It is
6835 // not useful otherwise but is implemented for compatibility.
6836 if (CVal >= -255 && CVal <= -1)
6839 // This must be a constant between -4095 and 4095. It is not clear
6840 // what this constraint is intended for. Implemented for
6841 // compatibility with GCC.
6842 if (CVal >= -4095 && CVal <= 4095)
6848 if (Subtarget->isThumb1Only()) {
6849 // A 32-bit value where only one byte has a nonzero value. Exclude
6850 // zero to match GCC. This constraint is used by GCC internally for
6851 // constants that can be loaded with a move/shift combination.
6852 // It is not useful otherwise but is implemented for compatibility.
6853 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
6855 } else if (Subtarget->isThumb2()) {
6856 // A constant whose bitwise inverse can be used as an immediate
6857 // value in a data-processing instruction. This can be used in GCC
6858 // with a "B" modifier that prints the inverted value, for use with
6859 // BIC and MVN instructions. It is not useful otherwise but is
6860 // implemented for compatibility.
6861 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
6864 // A constant whose bitwise inverse can be used as an immediate
6865 // value in a data-processing instruction. This can be used in GCC
6866 // with a "B" modifier that prints the inverted value, for use with
6867 // BIC and MVN instructions. It is not useful otherwise but is
6868 // implemented for compatibility.
6869 if (ARM_AM::getSOImmVal(~CVal) != -1)
6875 if (Subtarget->isThumb1Only()) {
6876 // This must be a constant between -7 and 7,
6877 // for 3-operand ADD/SUB immediate instructions.
6878 if (CVal >= -7 && CVal < 7)
6880 } else if (Subtarget->isThumb2()) {
6881 // A constant whose negation can be used as an immediate value in a
6882 // data-processing instruction. This can be used in GCC with an "n"
6883 // modifier that prints the negated value, for use with SUB
6884 // instructions. It is not useful otherwise but is implemented for
6886 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
6889 // A constant whose negation can be used as an immediate value in a
6890 // data-processing instruction. This can be used in GCC with an "n"
6891 // modifier that prints the negated value, for use with SUB
6892 // instructions. It is not useful otherwise but is implemented for
6894 if (ARM_AM::getSOImmVal(-CVal) != -1)
6900 if (Subtarget->isThumb()) { // FIXME thumb2
6901 // This must be a multiple of 4 between 0 and 1020, for
6902 // ADD sp + immediate.
6903 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
6906 // A power of two or a constant between 0 and 32. This is used in
6907 // GCC for the shift amount on shifted register operands, but it is
6908 // useful in general for any shift amounts.
6909 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
6915 if (Subtarget->isThumb()) { // FIXME thumb2
6916 // This must be a constant between 0 and 31, for shift amounts.
6917 if (CVal >= 0 && CVal <= 31)
6923 if (Subtarget->isThumb()) { // FIXME thumb2
6924 // This must be a multiple of 4 between -508 and 508, for
6925 // ADD/SUB sp = sp + immediate.
6926 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
6931 Result = DAG.getTargetConstant(CVal, Op.getValueType());
6935 if (Result.getNode()) {
6936 Ops.push_back(Result);
6939 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6943 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6944 // The ARM target isn't yet aware of offsets.
6948 int ARM::getVFPf32Imm(const APFloat &FPImm) {
6949 APInt Imm = FPImm.bitcastToAPInt();
6950 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
6951 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
6952 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
6954 // We can handle 4 bits of mantissa.
6955 // mantissa = (16+UInt(e:f:g:h))/16.
6956 if (Mantissa & 0x7ffff)
6959 if ((Mantissa & 0xf) != Mantissa)
6962 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6963 if (Exp < -3 || Exp > 4)
6965 Exp = ((Exp+3) & 0x7) ^ 4;
6967 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6970 int ARM::getVFPf64Imm(const APFloat &FPImm) {
6971 APInt Imm = FPImm.bitcastToAPInt();
6972 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
6973 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
6974 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
6976 // We can handle 4 bits of mantissa.
6977 // mantissa = (16+UInt(e:f:g:h))/16.
6978 if (Mantissa & 0xffffffffffffLL)
6981 if ((Mantissa & 0xf) != Mantissa)
6984 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6985 if (Exp < -3 || Exp > 4)
6987 Exp = ((Exp+3) & 0x7) ^ 4;
6989 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6992 bool ARM::isBitFieldInvertedMask(unsigned v) {
6993 if (v == 0xffffffff)
6995 // there can be 1's on either or both "outsides", all the "inside"
6997 unsigned int lsb = 0, msb = 31;
6998 while (v & (1 << msb)) --msb;
6999 while (v & (1 << lsb)) ++lsb;
7000 for (unsigned int i = lsb; i <= msb; ++i) {
7007 /// isFPImmLegal - Returns true if the target can instruction select the
7008 /// specified FP immediate natively. If false, the legalizer will
7009 /// materialize the FP immediate as a load from a constant pool.
7010 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7011 if (!Subtarget->hasVFP3())
7014 return ARM::getVFPf32Imm(Imm) != -1;
7016 return ARM::getVFPf64Imm(Imm) != -1;
7020 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7021 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7022 /// specified in the intrinsic calls.
7023 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7025 unsigned Intrinsic) const {
7026 switch (Intrinsic) {
7027 case Intrinsic::arm_neon_vld1:
7028 case Intrinsic::arm_neon_vld2:
7029 case Intrinsic::arm_neon_vld3:
7030 case Intrinsic::arm_neon_vld4:
7031 case Intrinsic::arm_neon_vld2lane:
7032 case Intrinsic::arm_neon_vld3lane:
7033 case Intrinsic::arm_neon_vld4lane: {
7034 Info.opc = ISD::INTRINSIC_W_CHAIN;
7035 // Conservatively set memVT to the entire set of vectors loaded.
7036 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7037 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7038 Info.ptrVal = I.getArgOperand(0);
7040 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7041 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7042 Info.vol = false; // volatile loads with NEON intrinsics not supported
7043 Info.readMem = true;
7044 Info.writeMem = false;
7047 case Intrinsic::arm_neon_vst1:
7048 case Intrinsic::arm_neon_vst2:
7049 case Intrinsic::arm_neon_vst3:
7050 case Intrinsic::arm_neon_vst4:
7051 case Intrinsic::arm_neon_vst2lane:
7052 case Intrinsic::arm_neon_vst3lane:
7053 case Intrinsic::arm_neon_vst4lane: {
7054 Info.opc = ISD::INTRINSIC_VOID;
7055 // Conservatively set memVT to the entire set of vectors stored.
7056 unsigned NumElts = 0;
7057 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7058 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7059 if (!ArgTy->isVectorTy())
7061 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7063 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7064 Info.ptrVal = I.getArgOperand(0);
7066 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7067 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7068 Info.vol = false; // volatile stores with NEON intrinsics not supported
7069 Info.readMem = false;
7070 Info.writeMem = true;