1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instruction.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/VectorExtras.h"
39 #include "llvm/Support/MathExtras.h"
42 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 CCValAssign::LocInfo &LocInfo,
44 ISD::ArgFlagsTy &ArgFlags,
46 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
54 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
55 CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags,
59 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
60 : TargetLowering(TM), ARMPCLabelIndex(0) {
61 Subtarget = &TM.getSubtarget<ARMSubtarget>();
63 if (Subtarget->isTargetDarwin()) {
64 // Uses VFP for Thumb libfuncs if available.
65 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
66 // Single-precision floating-point arithmetic.
67 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
68 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
69 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
70 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
72 // Double-precision floating-point arithmetic.
73 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
74 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
75 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
76 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
78 // Single-precision comparisons.
79 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
80 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
81 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
82 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
83 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
84 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
85 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
86 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
88 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
89 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
97 // Double-precision comparisons.
98 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
99 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
100 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
101 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
102 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
103 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
104 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
105 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
107 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
108 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
109 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
110 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
111 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
112 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
113 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
114 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
116 // Floating-point to integer conversions.
117 // i64 conversions are done via library routines even when generating VFP
118 // instructions, so use the same ones.
119 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
120 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
121 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
122 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
124 // Conversions between floating types.
125 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
126 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
128 // Integer to floating-point conversions.
129 // i64 conversions are done via library routines even when generating VFP
130 // instructions, so use the same ones.
131 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
132 // e.g., __floatunsidf vs. __floatunssidfvfp.
133 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
134 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
135 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
136 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
140 if (Subtarget->isThumb())
141 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
143 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
144 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
145 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
146 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
148 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
150 computeRegisterProperties();
152 // ARM does not have f32 extending load.
153 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
155 // ARM does not have i1 sign extending load.
156 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
158 // ARM supports all 4 flavors of integer indexed load / store.
159 for (unsigned im = (unsigned)ISD::PRE_INC;
160 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
161 setIndexedLoadAction(im, MVT::i1, Legal);
162 setIndexedLoadAction(im, MVT::i8, Legal);
163 setIndexedLoadAction(im, MVT::i16, Legal);
164 setIndexedLoadAction(im, MVT::i32, Legal);
165 setIndexedStoreAction(im, MVT::i1, Legal);
166 setIndexedStoreAction(im, MVT::i8, Legal);
167 setIndexedStoreAction(im, MVT::i16, Legal);
168 setIndexedStoreAction(im, MVT::i32, Legal);
171 // i64 operation support.
172 if (Subtarget->isThumb()) {
173 setOperationAction(ISD::MUL, MVT::i64, Expand);
174 setOperationAction(ISD::MULHU, MVT::i32, Expand);
175 setOperationAction(ISD::MULHS, MVT::i32, Expand);
176 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
177 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
179 setOperationAction(ISD::MUL, MVT::i64, Expand);
180 setOperationAction(ISD::MULHU, MVT::i32, Expand);
181 if (!Subtarget->hasV6Ops())
182 setOperationAction(ISD::MULHS, MVT::i32, Expand);
184 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
185 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
186 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
187 setOperationAction(ISD::SRL, MVT::i64, Custom);
188 setOperationAction(ISD::SRA, MVT::i64, Custom);
190 // ARM does not have ROTL.
191 setOperationAction(ISD::ROTL, MVT::i32, Expand);
192 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
193 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
194 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
195 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
197 // Only ARMv6 has BSWAP.
198 if (!Subtarget->hasV6Ops())
199 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
201 // These are expanded into libcalls.
202 setOperationAction(ISD::SDIV, MVT::i32, Expand);
203 setOperationAction(ISD::UDIV, MVT::i32, Expand);
204 setOperationAction(ISD::SREM, MVT::i32, Expand);
205 setOperationAction(ISD::UREM, MVT::i32, Expand);
206 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
207 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
209 // Support label based line numbers.
210 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
211 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
213 setOperationAction(ISD::RET, MVT::Other, Custom);
214 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
216 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
217 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
219 // Use the default implementation.
220 setOperationAction(ISD::VASTART, MVT::Other, Custom);
221 setOperationAction(ISD::VAARG, MVT::Other, Expand);
222 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
223 setOperationAction(ISD::VAEND, MVT::Other, Expand);
224 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
225 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
227 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
229 if (!Subtarget->hasV6Ops()) {
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
235 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
236 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
237 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
239 // We want to custom lower some of our intrinsics.
240 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
242 setOperationAction(ISD::SETCC, MVT::i32, Expand);
243 setOperationAction(ISD::SETCC, MVT::f32, Expand);
244 setOperationAction(ISD::SETCC, MVT::f64, Expand);
245 setOperationAction(ISD::SELECT, MVT::i32, Expand);
246 setOperationAction(ISD::SELECT, MVT::f32, Expand);
247 setOperationAction(ISD::SELECT, MVT::f64, Expand);
248 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
249 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
252 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
253 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
254 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
255 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
256 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
258 // We don't support sin/cos/fmod/copysign/pow
259 setOperationAction(ISD::FSIN, MVT::f64, Expand);
260 setOperationAction(ISD::FSIN, MVT::f32, Expand);
261 setOperationAction(ISD::FCOS, MVT::f32, Expand);
262 setOperationAction(ISD::FCOS, MVT::f64, Expand);
263 setOperationAction(ISD::FREM, MVT::f64, Expand);
264 setOperationAction(ISD::FREM, MVT::f32, Expand);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
266 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
267 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
269 setOperationAction(ISD::FPOW, MVT::f64, Expand);
270 setOperationAction(ISD::FPOW, MVT::f32, Expand);
272 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
273 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
274 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
275 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
276 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
280 // We have target-specific dag combine patterns for the following nodes:
281 // ARMISD::FMRRD - No need to call setTargetDAGCombine
282 setTargetDAGCombine(ISD::ADD);
283 setTargetDAGCombine(ISD::SUB);
285 setStackPointerRegisterToSaveRestore(ARM::SP);
286 setSchedulingPreference(SchedulingForRegPressure);
287 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
288 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
290 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
293 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
296 case ARMISD::Wrapper: return "ARMISD::Wrapper";
297 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
298 case ARMISD::CALL: return "ARMISD::CALL";
299 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
300 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
301 case ARMISD::tCALL: return "ARMISD::tCALL";
302 case ARMISD::BRCOND: return "ARMISD::BRCOND";
303 case ARMISD::BR_JT: return "ARMISD::BR_JT";
304 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
305 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
306 case ARMISD::CMP: return "ARMISD::CMP";
307 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
308 case ARMISD::CMPFP: return "ARMISD::CMPFP";
309 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
310 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
311 case ARMISD::CMOV: return "ARMISD::CMOV";
312 case ARMISD::CNEG: return "ARMISD::CNEG";
314 case ARMISD::FTOSI: return "ARMISD::FTOSI";
315 case ARMISD::FTOUI: return "ARMISD::FTOUI";
316 case ARMISD::SITOF: return "ARMISD::SITOF";
317 case ARMISD::UITOF: return "ARMISD::UITOF";
319 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
320 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
321 case ARMISD::RRX: return "ARMISD::RRX";
323 case ARMISD::FMRRD: return "ARMISD::FMRRD";
324 case ARMISD::FMDRR: return "ARMISD::FMDRR";
326 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
330 //===----------------------------------------------------------------------===//
332 //===----------------------------------------------------------------------===//
334 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
335 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
337 default: assert(0 && "Unknown condition code!");
338 case ISD::SETNE: return ARMCC::NE;
339 case ISD::SETEQ: return ARMCC::EQ;
340 case ISD::SETGT: return ARMCC::GT;
341 case ISD::SETGE: return ARMCC::GE;
342 case ISD::SETLT: return ARMCC::LT;
343 case ISD::SETLE: return ARMCC::LE;
344 case ISD::SETUGT: return ARMCC::HI;
345 case ISD::SETUGE: return ARMCC::HS;
346 case ISD::SETULT: return ARMCC::LO;
347 case ISD::SETULE: return ARMCC::LS;
351 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
352 /// returns true if the operands should be inverted to form the proper
354 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
355 ARMCC::CondCodes &CondCode2) {
357 CondCode2 = ARMCC::AL;
359 default: assert(0 && "Unknown FP condition!");
361 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
363 case ISD::SETOGT: CondCode = ARMCC::GT; break;
365 case ISD::SETOGE: CondCode = ARMCC::GE; break;
366 case ISD::SETOLT: CondCode = ARMCC::MI; break;
367 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
368 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
369 case ISD::SETO: CondCode = ARMCC::VC; break;
370 case ISD::SETUO: CondCode = ARMCC::VS; break;
371 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
372 case ISD::SETUGT: CondCode = ARMCC::HI; break;
373 case ISD::SETUGE: CondCode = ARMCC::PL; break;
375 case ISD::SETULT: CondCode = ARMCC::LT; break;
377 case ISD::SETULE: CondCode = ARMCC::LE; break;
379 case ISD::SETUNE: CondCode = ARMCC::NE; break;
384 //===----------------------------------------------------------------------===//
385 // Calling Convention Implementation
387 // The lower operations present on calling convention works on this order:
388 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
389 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
390 // LowerRET (virt regs --> phys regs)
391 // LowerCALL (phys regs --> virt regs)
393 //===----------------------------------------------------------------------===//
395 #include "ARMGenCallingConv.inc"
397 // APCS f64 is in register pairs, possibly split to stack
398 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
399 CCValAssign::LocInfo &LocInfo,
400 ISD::ArgFlagsTy &ArgFlags,
402 static const unsigned HiRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
403 static const unsigned LoRegList[] = { ARM::R1,
408 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4);
410 return false; // we didn't handle it
413 for (i = 0; i < 4; ++i)
414 if (HiRegList[i] == Reg)
417 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
418 if (LoRegList[i] != ARM::NoRegister)
419 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
422 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
423 State.AllocateStack(4, 4),
425 return true; // we handled it
428 // AAPCS f64 is in aligned register pairs
429 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
430 CCValAssign::LocInfo &LocInfo,
431 ISD::ArgFlagsTy &ArgFlags,
433 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
434 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
436 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
438 return false; // we didn't handle it
441 for (i = 0; i < 2; ++i)
442 if (HiRegList[i] == Reg)
445 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
446 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
448 return true; // we handled it
451 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
452 CCValAssign::LocInfo &LocInfo,
453 ISD::ArgFlagsTy &ArgFlags,
455 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
456 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
458 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
460 return false; // we didn't handle it
463 for (i = 0; i < 2; ++i)
464 if (HiRegList[i] == Reg)
467 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
468 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
470 return true; // we handled it
473 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
474 CCValAssign::LocInfo &LocInfo,
475 ISD::ArgFlagsTy &ArgFlags,
477 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
481 /// LowerCallResult - Lower the result values of an ISD::CALL into the
482 /// appropriate copies out of appropriate physical registers. This assumes that
483 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
484 /// being lowered. The returns a SDNode with the same number of values as the
486 SDNode *ARMTargetLowering::
487 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
488 unsigned CallingConv, SelectionDAG &DAG) {
490 DebugLoc dl = TheCall->getDebugLoc();
491 // Assign locations to each value returned by this call.
492 SmallVector<CCValAssign, 16> RVLocs;
493 bool isVarArg = TheCall->isVarArg();
494 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
495 CCInfo.AnalyzeCallResult(TheCall, RetCC_ARM);
497 SmallVector<SDValue, 8> ResultVals;
499 // Copy all of the result registers out of their specified physreg.
500 for (unsigned i = 0; i != RVLocs.size(); ++i) {
501 CCValAssign VA = RVLocs[i];
504 if (VA.needsCustom()) {
505 // Handle f64 as custom.
506 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
508 Chain = Lo.getValue(1);
509 InFlag = Lo.getValue(2);
510 VA = RVLocs[++i]; // skip ahead to next loc
511 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
513 Chain = Hi.getValue(1);
514 InFlag = Hi.getValue(2);
515 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
517 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
519 Chain = Val.getValue(1);
520 InFlag = Val.getValue(2);
523 switch (VA.getLocInfo()) {
524 default: assert(0 && "Unknown loc info!");
525 case CCValAssign::Full: break;
526 case CCValAssign::BCvt:
527 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
531 ResultVals.push_back(Val);
534 // Merge everything together with a MERGE_VALUES node.
535 ResultVals.push_back(Chain);
536 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
537 &ResultVals[0], ResultVals.size()).getNode();
540 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
541 /// by "Src" to address "Dst" of size "Size". Alignment information is
542 /// specified by the specific parameter attribute. The copy will be passed as
543 /// a byval function parameter.
544 /// Sometimes what we are copying is the end of a larger object, the part that
545 /// does not fit in registers.
547 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
548 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
550 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
551 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
552 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
555 /// LowerMemOpCallTo - Store the argument to the stack.
557 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
558 const SDValue &StackPtr,
559 const CCValAssign &VA, SDValue Chain,
560 SDValue Arg, ISD::ArgFlagsTy Flags) {
561 DebugLoc dl = TheCall->getDebugLoc();
562 unsigned LocMemOffset = VA.getLocMemOffset();
563 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
564 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
565 if (Flags.isByVal()) {
566 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
568 return DAG.getStore(Chain, dl, Arg, PtrOff,
569 PseudoSourceValue::getStack(), LocMemOffset);
572 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
573 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
575 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
576 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
577 MVT RetVT = TheCall->getRetValType(0);
578 SDValue Chain = TheCall->getChain();
579 unsigned CC = TheCall->getCallingConv();
580 assert((CC == CallingConv::C ||
581 CC == CallingConv::Fast) && "unknown calling convention");
582 bool isVarArg = TheCall->isVarArg();
583 SDValue Callee = TheCall->getCallee();
584 DebugLoc dl = TheCall->getDebugLoc();
586 // Analyze operands of the call, assigning locations to each operand.
587 SmallVector<CCValAssign, 16> ArgLocs;
588 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
589 CCInfo.AnalyzeCallOperands(TheCall, CC_ARM);
591 // Get a count of how many bytes are to be pushed on the stack.
592 unsigned NumBytes = CCInfo.getNextStackOffset();
594 // Adjust the stack pointer for the new arguments...
595 // These operations are automatically eliminated by the prolog/epilog pass
596 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
598 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
600 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
601 SmallVector<SDValue, 8> MemOpChains;
603 // Walk the register/memloc assignments, inserting copies/loads. In the case
604 // of tail call optimization, arguments are handled later.
605 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
608 CCValAssign &VA = ArgLocs[i];
609 SDValue Arg = TheCall->getArg(realArgIdx);
610 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
612 // Promote the value if needed.
613 switch (VA.getLocInfo()) {
614 default: assert(0 && "Unknown loc info!");
615 case CCValAssign::Full: break;
616 case CCValAssign::SExt:
617 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
619 case CCValAssign::ZExt:
620 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
622 case CCValAssign::AExt:
623 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
625 case CCValAssign::BCvt:
626 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
630 // f64 is passed in i32 pairs and must be combined
631 if (VA.needsCustom()) {
632 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
633 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
634 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
635 VA = ArgLocs[++i]; // skip ahead to next loc
637 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1)));
639 assert(VA.isMemLoc());
640 if (StackPtr.getNode() == 0)
641 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
643 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
644 Chain, fmrrd.getValue(1),
647 } else if (VA.isRegLoc()) {
648 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
650 assert(VA.isMemLoc());
651 if (StackPtr.getNode() == 0)
652 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
654 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
659 if (!MemOpChains.empty())
660 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
661 &MemOpChains[0], MemOpChains.size());
663 // Build a sequence of copy-to-reg nodes chained together with token chain
664 // and flag operands which copy the outgoing args into the appropriate regs.
666 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
667 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
668 RegsToPass[i].second, InFlag);
669 InFlag = Chain.getValue(1);
672 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
673 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
674 // node so that legalize doesn't hack it.
675 bool isDirect = false;
676 bool isARMFunc = false;
677 bool isLocalARMFunc = false;
678 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
679 GlobalValue *GV = G->getGlobal();
681 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
682 GV->hasLinkOnceLinkage());
683 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
684 getTargetMachine().getRelocationModel() != Reloc::Static;
685 isARMFunc = !Subtarget->isThumb() || isStub;
686 // ARM call to a local ARM function is predicable.
687 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
688 // tBX takes a register source operand.
689 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
690 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
692 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
693 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
694 Callee = DAG.getLoad(getPointerTy(), dl,
695 DAG.getEntryNode(), CPAddr, NULL, 0);
696 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
697 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
698 getPointerTy(), Callee, PICLabel);
700 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
701 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
703 bool isStub = Subtarget->isTargetDarwin() &&
704 getTargetMachine().getRelocationModel() != Reloc::Static;
705 isARMFunc = !Subtarget->isThumb() || isStub;
706 // tBX takes a register source operand.
707 const char *Sym = S->getSymbol();
708 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
709 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
711 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
712 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
713 Callee = DAG.getLoad(getPointerTy(), dl,
714 DAG.getEntryNode(), CPAddr, NULL, 0);
715 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
716 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
717 getPointerTy(), Callee, PICLabel);
719 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
722 // FIXME: handle tail calls differently.
724 if (Subtarget->isThumb()) {
725 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
726 CallOpc = ARMISD::CALL_NOLINK;
728 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
730 CallOpc = (isDirect || Subtarget->hasV5TOps())
731 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
732 : ARMISD::CALL_NOLINK;
734 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
735 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
736 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
737 InFlag = Chain.getValue(1);
740 std::vector<SDValue> Ops;
741 Ops.push_back(Chain);
742 Ops.push_back(Callee);
744 // Add argument registers to the end of the list so that they are known live
746 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
747 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
748 RegsToPass[i].second.getValueType()));
750 if (InFlag.getNode())
751 Ops.push_back(InFlag);
752 // Returns a chain and a flag for retval copy to use.
753 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
754 &Ops[0], Ops.size());
755 InFlag = Chain.getValue(1);
757 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
758 DAG.getIntPtrConstant(0, true), InFlag);
759 if (RetVT != MVT::Other)
760 InFlag = Chain.getValue(1);
762 // Handle result values, copying them out of physregs into vregs that we
764 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
768 SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
769 // The chain is always operand #0
770 SDValue Chain = Op.getOperand(0);
771 DebugLoc dl = Op.getDebugLoc();
773 // CCValAssign - represent the assignment of the return value to a location.
774 SmallVector<CCValAssign, 16> RVLocs;
775 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
776 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
778 // CCState - Info about the registers and stack slots.
779 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
781 // Analyze return values of ISD::RET.
782 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_ARM);
784 // If this is the first return lowered for this function, add
785 // the regs to the liveout set for the function.
786 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
787 for (unsigned i = 0; i != RVLocs.size(); ++i)
788 if (RVLocs[i].isRegLoc())
789 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
794 // Copy the result values into the output registers.
795 for (unsigned i = 0, realRVLocIdx = 0;
797 ++i, ++realRVLocIdx) {
798 CCValAssign &VA = RVLocs[i];
799 assert(VA.isRegLoc() && "Can only return in registers!");
801 // ISD::RET => ret chain, (regnum1,val1), ...
802 // So i*2+1 index only the regnums
803 SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
805 switch (VA.getLocInfo()) {
806 default: assert(0 && "Unknown loc info!");
807 case CCValAssign::Full: break;
808 case CCValAssign::BCvt:
809 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
813 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
815 if (VA.needsCustom()) {
816 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
817 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
819 Flag = Chain.getValue(1);
820 VA = RVLocs[++i]; // skip ahead to next loc
821 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
824 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
826 // Guarantee that all emitted copies are
827 // stuck together, avoiding something bad.
828 Flag = Chain.getValue(1);
833 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
835 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
840 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
841 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
842 // one of the above mentioned nodes. It has to be wrapped because otherwise
843 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
844 // be used to form addressing mode. These wrapped nodes will be selected
846 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
847 MVT PtrVT = Op.getValueType();
848 // FIXME there is no actual debug info here
849 DebugLoc dl = Op.getDebugLoc();
850 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
852 if (CP->isMachineConstantPoolEntry())
853 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
856 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
858 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
861 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
863 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
865 DebugLoc dl = GA->getDebugLoc();
866 MVT PtrVT = getPointerTy();
867 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
868 ARMConstantPoolValue *CPV =
869 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
870 PCAdj, "tlsgd", true);
871 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
872 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
873 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
874 SDValue Chain = Argument.getValue(1);
876 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
877 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
879 // call __tls_get_addr.
882 Entry.Node = Argument;
883 Entry.Ty = (const Type *) Type::Int32Ty;
884 Args.push_back(Entry);
885 // FIXME: is there useful debug info available here?
886 std::pair<SDValue, SDValue> CallResult =
887 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
888 CallingConv::C, false,
889 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
890 return CallResult.first;
893 // Lower ISD::GlobalTLSAddress using the "initial exec" or
894 // "local exec" model.
896 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
898 GlobalValue *GV = GA->getGlobal();
899 DebugLoc dl = GA->getDebugLoc();
901 SDValue Chain = DAG.getEntryNode();
902 MVT PtrVT = getPointerTy();
903 // Get the Thread Pointer
904 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
906 if (GV->isDeclaration()){
907 // initial exec model
908 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
909 ARMConstantPoolValue *CPV =
910 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
911 PCAdj, "gottpoff", true);
912 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
913 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
914 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
915 Chain = Offset.getValue(1);
917 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
918 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
920 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
923 ARMConstantPoolValue *CPV =
924 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
925 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
926 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
927 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
930 // The address of the thread local variable is the add of the thread
931 // pointer with the offset of the variable.
932 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
936 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
937 // TODO: implement the "local dynamic" model
938 assert(Subtarget->isTargetELF() &&
939 "TLS not implemented for non-ELF targets");
940 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
941 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
942 // otherwise use the "Local Exec" TLS Model
943 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
944 return LowerToTLSGeneralDynamicModel(GA, DAG);
946 return LowerToTLSExecModels(GA, DAG);
949 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
951 MVT PtrVT = getPointerTy();
952 DebugLoc dl = Op.getDebugLoc();
953 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
954 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
955 if (RelocM == Reloc::PIC_) {
956 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
957 ARMConstantPoolValue *CPV =
958 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
959 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
960 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
961 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
963 SDValue Chain = Result.getValue(1);
964 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
965 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
967 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
970 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
971 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
972 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
976 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
977 /// even in non-static mode.
978 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
979 // If symbol visibility is hidden, the extra load is not needed if
980 // the symbol is definitely defined in the current translation unit.
981 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
982 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
984 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
987 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
989 MVT PtrVT = getPointerTy();
990 DebugLoc dl = Op.getDebugLoc();
991 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
992 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
993 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
995 if (RelocM == Reloc::Static)
996 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
998 unsigned PCAdj = (RelocM != Reloc::PIC_)
999 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1000 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1002 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1004 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1006 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1008 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1009 SDValue Chain = Result.getValue(1);
1011 if (RelocM == Reloc::PIC_) {
1012 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1013 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1016 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1021 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1023 assert(Subtarget->isTargetELF() &&
1024 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1025 MVT PtrVT = getPointerTy();
1026 DebugLoc dl = Op.getDebugLoc();
1027 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1028 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1030 ARMCP::CPValue, PCAdj);
1031 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1032 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1033 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1034 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1035 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1039 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1040 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1041 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1042 DebugLoc dl = Op.getDebugLoc();
1044 default: return SDValue(); // Don't custom lower most intrinsics.
1045 case Intrinsic::arm_thread_pointer:
1046 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1047 case Intrinsic::builtinsetjmp:
1048 SDValue Res = DAG.getNode(ARMISD::BUILTIN_SETJMP, dl, MVT::i32,
1054 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1055 unsigned VarArgsFrameIndex) {
1056 // vastart just stores the address of the VarArgsFrameIndex slot into the
1057 // memory location argument.
1058 DebugLoc dl = Op.getDebugLoc();
1059 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1060 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1061 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1062 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1066 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1067 MachineFunction &MF = DAG.getMachineFunction();
1068 MachineFrameInfo *MFI = MF.getFrameInfo();
1070 SDValue Root = Op.getOperand(0);
1071 DebugLoc dl = Op.getDebugLoc();
1072 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1073 unsigned CC = MF.getFunction()->getCallingConv();
1074 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1076 // Assign locations to all of the incoming arguments.
1077 SmallVector<CCValAssign, 16> ArgLocs;
1078 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1079 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_ARM);
1081 SmallVector<SDValue, 16> ArgValues;
1083 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1084 CCValAssign &VA = ArgLocs[i];
1086 // Arguments stored in registers.
1087 if (VA.isRegLoc()) {
1088 MVT RegVT = VA.getLocVT();
1089 TargetRegisterClass *RC;
1090 if (AFI->isThumbFunction())
1091 RC = ARM::tGPRRegisterClass;
1093 RC = ARM::GPRRegisterClass;
1095 if (RegVT == MVT::f64) {
1096 // f64 is passed in pairs of GPRs and must be combined.
1098 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
1099 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1101 // Transform the arguments stored in physical registers into virtual ones.
1102 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1103 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1105 // f64 is passed in i32 pairs and must be combined.
1106 if (VA.needsCustom()) {
1109 VA = ArgLocs[++i]; // skip ahead to next loc
1110 if (VA.isMemLoc()) {
1111 // must be APCS to split like this
1112 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1113 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1115 // Create load node to retrieve arguments from the stack.
1116 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1117 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1119 Reg = MF.addLiveIn(VA.getLocReg(), RC);
1120 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1123 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64,
1124 ArgValue, ArgValue2);
1127 // If this is an 8 or 16-bit value, it is really passed promoted
1128 // to 32 bits. Insert an assert[sz]ext to capture this, then
1129 // truncate to the right size.
1130 switch (VA.getLocInfo()) {
1131 default: assert(0 && "Unknown loc info!");
1132 case CCValAssign::Full: break;
1133 case CCValAssign::BCvt:
1134 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1136 case CCValAssign::SExt:
1137 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1138 DAG.getValueType(VA.getValVT()));
1139 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1141 case CCValAssign::ZExt:
1142 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1143 DAG.getValueType(VA.getValVT()));
1144 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1148 ArgValues.push_back(ArgValue);
1150 } else { // VA.isRegLoc()
1153 assert(VA.isMemLoc());
1154 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1156 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1157 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1159 // Create load nodes to retrieve arguments from the stack.
1160 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1161 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1167 static const unsigned GPRArgRegs[] = {
1168 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1171 unsigned NumGPRs = CCInfo.getFirstUnallocated
1172 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1174 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1175 unsigned VARegSize = (4 - NumGPRs) * 4;
1176 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1177 unsigned ArgOffset = 0;
1178 if (VARegSaveSize) {
1179 // If this function is vararg, store any remaining integer argument regs
1180 // to their spots on the stack so that they may be loaded by deferencing
1181 // the result of va_next.
1182 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1183 ArgOffset = CCInfo.getNextStackOffset();
1184 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1185 VARegSaveSize - VARegSize);
1186 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1188 SmallVector<SDValue, 4> MemOps;
1189 for (; NumGPRs < 4; ++NumGPRs) {
1190 TargetRegisterClass *RC;
1191 if (AFI->isThumbFunction())
1192 RC = ARM::tGPRRegisterClass;
1194 RC = ARM::GPRRegisterClass;
1196 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1197 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1198 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1199 MemOps.push_back(Store);
1200 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1201 DAG.getConstant(4, getPointerTy()));
1203 if (!MemOps.empty())
1204 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1205 &MemOps[0], MemOps.size());
1207 // This will point to the next argument passed via stack.
1208 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1211 ArgValues.push_back(Root);
1213 // Return the new list of results.
1214 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1215 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1218 /// isFloatingPointZero - Return true if this is +0.0.
1219 static bool isFloatingPointZero(SDValue Op) {
1220 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1221 return CFP->getValueAPF().isPosZero();
1222 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1223 // Maybe this has already been legalized into the constant pool?
1224 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1225 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1226 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1227 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1228 return CFP->getValueAPF().isPosZero();
1234 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1235 return ( isThumb && (C & ~255U) == 0) ||
1236 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1239 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1240 /// the given operands.
1241 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1242 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1244 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1245 unsigned C = RHSC->getZExtValue();
1246 if (!isLegalCmpImmediate(C, isThumb)) {
1247 // Constant does not fit, try adjusting it by one?
1252 if (isLegalCmpImmediate(C-1, isThumb)) {
1253 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1254 RHS = DAG.getConstant(C-1, MVT::i32);
1259 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1260 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1261 RHS = DAG.getConstant(C-1, MVT::i32);
1266 if (isLegalCmpImmediate(C+1, isThumb)) {
1267 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1268 RHS = DAG.getConstant(C+1, MVT::i32);
1273 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1274 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1275 RHS = DAG.getConstant(C+1, MVT::i32);
1282 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1283 ARMISD::NodeType CompareType;
1286 CompareType = ARMISD::CMP;
1292 // Uses only N and Z Flags
1293 CompareType = ARMISD::CMPNZ;
1296 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1297 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1300 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1301 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1304 if (!isFloatingPointZero(RHS))
1305 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1307 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1308 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1311 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1312 const ARMSubtarget *ST) {
1313 MVT VT = Op.getValueType();
1314 SDValue LHS = Op.getOperand(0);
1315 SDValue RHS = Op.getOperand(1);
1316 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1317 SDValue TrueVal = Op.getOperand(2);
1318 SDValue FalseVal = Op.getOperand(3);
1319 DebugLoc dl = Op.getDebugLoc();
1321 if (LHS.getValueType() == MVT::i32) {
1323 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1324 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1325 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1328 ARMCC::CondCodes CondCode, CondCode2;
1329 if (FPCCToARMCC(CC, CondCode, CondCode2))
1330 std::swap(TrueVal, FalseVal);
1332 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1333 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1334 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1335 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1337 if (CondCode2 != ARMCC::AL) {
1338 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1339 // FIXME: Needs another CMP because flag can have but one use.
1340 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1341 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1342 Result, TrueVal, ARMCC2, CCR, Cmp2);
1347 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1348 const ARMSubtarget *ST) {
1349 SDValue Chain = Op.getOperand(0);
1350 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1351 SDValue LHS = Op.getOperand(2);
1352 SDValue RHS = Op.getOperand(3);
1353 SDValue Dest = Op.getOperand(4);
1354 DebugLoc dl = Op.getDebugLoc();
1356 if (LHS.getValueType() == MVT::i32) {
1358 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1359 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1360 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1361 Chain, Dest, ARMCC, CCR,Cmp);
1364 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1365 ARMCC::CondCodes CondCode, CondCode2;
1366 if (FPCCToARMCC(CC, CondCode, CondCode2))
1367 // Swap the LHS/RHS of the comparison if needed.
1368 std::swap(LHS, RHS);
1370 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1371 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1372 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1373 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1374 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1375 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1376 if (CondCode2 != ARMCC::AL) {
1377 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1378 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1379 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1384 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1385 SDValue Chain = Op.getOperand(0);
1386 SDValue Table = Op.getOperand(1);
1387 SDValue Index = Op.getOperand(2);
1388 DebugLoc dl = Op.getDebugLoc();
1390 MVT PTy = getPointerTy();
1391 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1392 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1393 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1394 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1395 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1396 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1397 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1398 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1399 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1400 Chain, Addr, NULL, 0);
1401 Chain = Addr.getValue(1);
1403 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1404 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1407 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1408 DebugLoc dl = Op.getDebugLoc();
1410 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1411 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1412 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1415 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1416 MVT VT = Op.getValueType();
1417 DebugLoc dl = Op.getDebugLoc();
1419 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1421 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1422 return DAG.getNode(Opc, dl, VT, Op);
1425 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1426 // Implement fcopysign with a fabs and a conditional fneg.
1427 SDValue Tmp0 = Op.getOperand(0);
1428 SDValue Tmp1 = Op.getOperand(1);
1429 DebugLoc dl = Op.getDebugLoc();
1430 MVT VT = Op.getValueType();
1431 MVT SrcVT = Tmp1.getValueType();
1432 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1433 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1434 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1435 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1436 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1439 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1440 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1441 MFI->setFrameAddressIsTaken(true);
1442 MVT VT = Op.getValueType();
1443 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1444 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1445 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->useThumbBacktraces())
1446 ? ARM::R7 : ARM::R11;
1447 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1449 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1454 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1456 SDValue Dst, SDValue Src,
1457 SDValue Size, unsigned Align,
1459 const Value *DstSV, uint64_t DstSVOff,
1460 const Value *SrcSV, uint64_t SrcSVOff){
1461 // Do repeated 4-byte loads and stores. To be improved.
1462 // This requires 4-byte alignment.
1463 if ((Align & 3) != 0)
1465 // This requires the copy size to be a constant, preferrably
1466 // within a subtarget-specific limit.
1467 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1470 uint64_t SizeVal = ConstantSize->getZExtValue();
1471 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1474 unsigned BytesLeft = SizeVal & 3;
1475 unsigned NumMemOps = SizeVal >> 2;
1476 unsigned EmittedNumMemOps = 0;
1478 unsigned VTSize = 4;
1480 const unsigned MAX_LOADS_IN_LDM = 6;
1481 SDValue TFOps[MAX_LOADS_IN_LDM];
1482 SDValue Loads[MAX_LOADS_IN_LDM];
1483 uint64_t SrcOff = 0, DstOff = 0;
1485 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1486 // same number of stores. The loads and stores will get combined into
1487 // ldm/stm later on.
1488 while (EmittedNumMemOps < NumMemOps) {
1490 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1491 Loads[i] = DAG.getLoad(VT, dl, Chain,
1492 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1493 DAG.getConstant(SrcOff, MVT::i32)),
1494 SrcSV, SrcSVOff + SrcOff);
1495 TFOps[i] = Loads[i].getValue(1);
1498 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1501 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1502 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1503 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1504 DAG.getConstant(DstOff, MVT::i32)),
1505 DstSV, DstSVOff + DstOff);
1508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1510 EmittedNumMemOps += i;
1516 // Issue loads / stores for the trailing (1 - 3) bytes.
1517 unsigned BytesLeftSave = BytesLeft;
1520 if (BytesLeft >= 2) {
1528 Loads[i] = DAG.getLoad(VT, dl, Chain,
1529 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1530 DAG.getConstant(SrcOff, MVT::i32)),
1531 SrcSV, SrcSVOff + SrcOff);
1532 TFOps[i] = Loads[i].getValue(1);
1535 BytesLeft -= VTSize;
1537 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1540 BytesLeft = BytesLeftSave;
1542 if (BytesLeft >= 2) {
1550 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1551 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1552 DAG.getConstant(DstOff, MVT::i32)),
1553 DstSV, DstSVOff + DstOff);
1556 BytesLeft -= VTSize;
1558 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1561 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1562 SDValue Op = N->getOperand(0);
1563 DebugLoc dl = N->getDebugLoc();
1564 if (N->getValueType(0) == MVT::f64) {
1565 // Turn i64->f64 into FMDRR.
1566 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1567 DAG.getConstant(0, MVT::i32));
1568 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1569 DAG.getConstant(1, MVT::i32));
1570 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1573 // Turn f64->i64 into FMRRD.
1574 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1575 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1577 // Merge the pieces into a single i64 value.
1578 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1581 static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1582 assert(N->getValueType(0) == MVT::i64 &&
1583 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1584 "Unknown shift to lower!");
1586 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1587 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1588 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1591 // If we are in thumb mode, we don't have RRX.
1592 if (ST->isThumb()) return SDValue();
1594 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1595 DebugLoc dl = N->getDebugLoc();
1596 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1597 DAG.getConstant(0, MVT::i32));
1598 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1599 DAG.getConstant(1, MVT::i32));
1601 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1602 // captures the result into a carry flag.
1603 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1604 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1606 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1607 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1609 // Merge the pieces into a single i64 value.
1610 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1613 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1614 switch (Op.getOpcode()) {
1615 default: assert(0 && "Don't know how to custom lower this!"); abort();
1616 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1617 case ISD::GlobalAddress:
1618 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1619 LowerGlobalAddressELF(Op, DAG);
1620 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1621 case ISD::CALL: return LowerCALL(Op, DAG);
1622 case ISD::RET: return LowerRET(Op, DAG);
1623 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1624 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1625 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1626 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1627 case ISD::SINT_TO_FP:
1628 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1629 case ISD::FP_TO_SINT:
1630 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1631 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1632 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1633 case ISD::RETURNADDR: break;
1634 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1635 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1636 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1637 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
1639 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget);
1644 /// ReplaceNodeResults - Replace the results of node with an illegal result
1645 /// type with new values built out of custom code.
1646 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
1647 SmallVectorImpl<SDValue>&Results,
1648 SelectionDAG &DAG) {
1649 switch (N->getOpcode()) {
1651 assert(0 && "Don't know how to custom expand this!");
1653 case ISD::BIT_CONVERT:
1654 Results.push_back(ExpandBIT_CONVERT(N, DAG));
1658 SDValue Res = ExpandSRx(N, DAG, Subtarget);
1660 Results.push_back(Res);
1666 //===----------------------------------------------------------------------===//
1667 // ARM Scheduler Hooks
1668 //===----------------------------------------------------------------------===//
1671 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1672 MachineBasicBlock *BB) const {
1673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1674 DebugLoc dl = MI->getDebugLoc();
1675 switch (MI->getOpcode()) {
1676 default: assert(false && "Unexpected instr type to insert");
1677 case ARM::tMOVCCr: {
1678 // To "insert" a SELECT_CC instruction, we actually have to insert the
1679 // diamond control-flow pattern. The incoming instruction knows the
1680 // destination vreg to set, the condition code register to branch on, the
1681 // true/false values to select between, and a branch opcode to use.
1682 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1683 MachineFunction::iterator It = BB;
1689 // cmpTY ccX, r1, r2
1691 // fallthrough --> copy0MBB
1692 MachineBasicBlock *thisMBB = BB;
1693 MachineFunction *F = BB->getParent();
1694 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1695 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1696 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1697 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1698 F->insert(It, copy0MBB);
1699 F->insert(It, sinkMBB);
1700 // Update machine-CFG edges by first adding all successors of the current
1701 // block to the new block which will contain the Phi node for the select.
1702 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1703 e = BB->succ_end(); i != e; ++i)
1704 sinkMBB->addSuccessor(*i);
1705 // Next, remove all successors of the current block, and add the true
1706 // and fallthrough blocks as its successors.
1707 while(!BB->succ_empty())
1708 BB->removeSuccessor(BB->succ_begin());
1709 BB->addSuccessor(copy0MBB);
1710 BB->addSuccessor(sinkMBB);
1713 // %FalseValue = ...
1714 // # fallthrough to sinkMBB
1717 // Update machine-CFG edges
1718 BB->addSuccessor(sinkMBB);
1721 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1724 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1725 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1726 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1728 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1734 //===----------------------------------------------------------------------===//
1735 // ARM Optimization Hooks
1736 //===----------------------------------------------------------------------===//
1739 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1740 TargetLowering::DAGCombinerInfo &DCI) {
1741 SelectionDAG &DAG = DCI.DAG;
1742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1743 MVT VT = N->getValueType(0);
1744 unsigned Opc = N->getOpcode();
1745 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
1746 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
1747 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
1748 ISD::CondCode CC = ISD::SETCC_INVALID;
1751 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
1753 SDValue CCOp = Slct.getOperand(0);
1754 if (CCOp.getOpcode() == ISD::SETCC)
1755 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
1758 bool DoXform = false;
1760 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
1763 if (LHS.getOpcode() == ISD::Constant &&
1764 cast<ConstantSDNode>(LHS)->isNullValue()) {
1766 } else if (CC != ISD::SETCC_INVALID &&
1767 RHS.getOpcode() == ISD::Constant &&
1768 cast<ConstantSDNode>(RHS)->isNullValue()) {
1769 std::swap(LHS, RHS);
1770 SDValue Op0 = Slct.getOperand(0);
1771 MVT OpVT = isSlctCC ? Op0.getValueType() :
1772 Op0.getOperand(0).getValueType();
1773 bool isInt = OpVT.isInteger();
1774 CC = ISD::getSetCCInverse(CC, isInt);
1776 if (!TLI.isCondCodeLegal(CC, OpVT))
1777 return SDValue(); // Inverse operator isn't legal.
1784 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
1786 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
1787 Slct.getOperand(0), Slct.getOperand(1), CC);
1788 SDValue CCOp = Slct.getOperand(0);
1790 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
1791 CCOp.getOperand(0), CCOp.getOperand(1), CC);
1792 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
1793 CCOp, OtherOp, Result);
1798 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
1799 static SDValue PerformADDCombine(SDNode *N,
1800 TargetLowering::DAGCombinerInfo &DCI) {
1801 // added by evan in r37685 with no testcase.
1802 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1804 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1805 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1806 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
1807 if (Result.getNode()) return Result;
1809 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1810 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1811 if (Result.getNode()) return Result;
1817 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1818 static SDValue PerformSUBCombine(SDNode *N,
1819 TargetLowering::DAGCombinerInfo &DCI) {
1820 // added by evan in r37685 with no testcase.
1821 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1823 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1824 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1825 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1826 if (Result.getNode()) return Result;
1833 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1834 static SDValue PerformFMRRDCombine(SDNode *N,
1835 TargetLowering::DAGCombinerInfo &DCI) {
1836 // fmrrd(fmdrr x, y) -> x,y
1837 SDValue InDouble = N->getOperand(0);
1838 if (InDouble.getOpcode() == ARMISD::FMDRR)
1839 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1843 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1844 DAGCombinerInfo &DCI) const {
1845 switch (N->getOpcode()) {
1847 case ISD::ADD: return PerformADDCombine(N, DCI);
1848 case ISD::SUB: return PerformSUBCombine(N, DCI);
1849 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1855 /// isLegalAddressImmediate - Return true if the integer value can be used
1856 /// as the offset of the target addressing mode for load / store of the
1858 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1859 const ARMSubtarget *Subtarget) {
1866 if (Subtarget->isThumb()) {
1871 switch (VT.getSimpleVT()) {
1872 default: return false;
1887 if ((V & (Scale - 1)) != 0)
1890 return V == (V & ((1LL << 5) - 1));
1895 switch (VT.getSimpleVT()) {
1896 default: return false;
1901 return V == (V & ((1LL << 12) - 1));
1904 return V == (V & ((1LL << 8) - 1));
1907 if (!Subtarget->hasVFP2())
1912 return V == (V & ((1LL << 8) - 1));
1916 /// isLegalAddressingMode - Return true if the addressing mode represented
1917 /// by AM is legal for this target, for a load/store of the specified type.
1918 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1919 const Type *Ty) const {
1920 MVT VT = getValueType(Ty, true);
1921 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
1924 // Can never fold addr of global into load/store.
1929 case 0: // no scale reg, must be "r+i" or "r", or "i".
1932 if (Subtarget->isThumb())
1936 // ARM doesn't support any R+R*scale+imm addr modes.
1943 int Scale = AM.Scale;
1944 switch (VT.getSimpleVT()) {
1945 default: return false;
1950 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1951 // ldrd / strd are used, then its address mode is same as i16.
1953 if (Scale < 0) Scale = -Scale;
1957 return isPowerOf2_32(Scale & ~1);
1960 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1965 // Note, we allow "void" uses (basically, uses that aren't loads or
1966 // stores), because arm allows folding a scale into many arithmetic
1967 // operations. This should be made more precise and revisited later.
1969 // Allow r << imm, but the imm has to be a multiple of two.
1970 if (AM.Scale & 1) return false;
1971 return isPowerOf2_32(AM.Scale);
1978 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1979 bool isSEXTLoad, SDValue &Base,
1980 SDValue &Offset, bool &isInc,
1981 SelectionDAG &DAG) {
1982 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1985 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1987 Base = Ptr->getOperand(0);
1988 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1989 int RHSC = (int)RHS->getZExtValue();
1990 if (RHSC < 0 && RHSC > -256) {
1992 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1996 isInc = (Ptr->getOpcode() == ISD::ADD);
1997 Offset = Ptr->getOperand(1);
1999 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
2001 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2002 int RHSC = (int)RHS->getZExtValue();
2003 if (RHSC < 0 && RHSC > -0x1000) {
2005 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
2006 Base = Ptr->getOperand(0);
2011 if (Ptr->getOpcode() == ISD::ADD) {
2013 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
2014 if (ShOpcVal != ARM_AM::no_shift) {
2015 Base = Ptr->getOperand(1);
2016 Offset = Ptr->getOperand(0);
2018 Base = Ptr->getOperand(0);
2019 Offset = Ptr->getOperand(1);
2024 isInc = (Ptr->getOpcode() == ISD::ADD);
2025 Base = Ptr->getOperand(0);
2026 Offset = Ptr->getOperand(1);
2030 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
2034 /// getPreIndexedAddressParts - returns true by value, base pointer and
2035 /// offset pointer and addressing mode by reference if the node's address
2036 /// can be legally represented as pre-indexed load / store address.
2038 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2040 ISD::MemIndexedMode &AM,
2041 SelectionDAG &DAG) const {
2042 if (Subtarget->isThumb())
2047 bool isSEXTLoad = false;
2048 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2049 Ptr = LD->getBasePtr();
2050 VT = LD->getMemoryVT();
2051 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2052 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2053 Ptr = ST->getBasePtr();
2054 VT = ST->getMemoryVT();
2059 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
2062 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
2068 /// getPostIndexedAddressParts - returns true by value, base pointer and
2069 /// offset pointer and addressing mode by reference if this node can be
2070 /// combined with a load / store to form a post-indexed load / store.
2071 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
2074 ISD::MemIndexedMode &AM,
2075 SelectionDAG &DAG) const {
2076 if (Subtarget->isThumb())
2081 bool isSEXTLoad = false;
2082 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2083 VT = LD->getMemoryVT();
2084 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2085 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2086 VT = ST->getMemoryVT();
2091 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
2094 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
2100 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
2104 const SelectionDAG &DAG,
2105 unsigned Depth) const {
2106 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2107 switch (Op.getOpcode()) {
2109 case ARMISD::CMOV: {
2110 // Bits are known zero/one if known on the LHS and RHS.
2111 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2112 if (KnownZero == 0 && KnownOne == 0) return;
2114 APInt KnownZeroRHS, KnownOneRHS;
2115 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
2116 KnownZeroRHS, KnownOneRHS, Depth+1);
2117 KnownZero &= KnownZeroRHS;
2118 KnownOne &= KnownOneRHS;
2124 //===----------------------------------------------------------------------===//
2125 // ARM Inline Assembly Support
2126 //===----------------------------------------------------------------------===//
2128 /// getConstraintType - Given a constraint letter, return the type of
2129 /// constraint it is for this target.
2130 ARMTargetLowering::ConstraintType
2131 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
2132 if (Constraint.size() == 1) {
2133 switch (Constraint[0]) {
2135 case 'l': return C_RegisterClass;
2136 case 'w': return C_RegisterClass;
2139 return TargetLowering::getConstraintType(Constraint);
2142 std::pair<unsigned, const TargetRegisterClass*>
2143 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2145 if (Constraint.size() == 1) {
2146 // GCC RS6000 Constraint Letters
2147 switch (Constraint[0]) {
2149 if (Subtarget->isThumb())
2150 return std::make_pair(0U, ARM::tGPRRegisterClass);
2152 return std::make_pair(0U, ARM::GPRRegisterClass);
2154 return std::make_pair(0U, ARM::GPRRegisterClass);
2157 return std::make_pair(0U, ARM::SPRRegisterClass);
2159 return std::make_pair(0U, ARM::DPRRegisterClass);
2163 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2166 std::vector<unsigned> ARMTargetLowering::
2167 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2169 if (Constraint.size() != 1)
2170 return std::vector<unsigned>();
2172 switch (Constraint[0]) { // GCC ARM Constraint Letters
2175 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2176 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2179 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2180 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2181 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
2182 ARM::R12, ARM::LR, 0);
2185 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
2186 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
2187 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
2188 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
2189 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
2190 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
2191 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
2192 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
2194 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
2195 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
2196 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
2197 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
2201 return std::vector<unsigned>();
2204 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2205 /// vector. If it is invalid, don't add anything to Ops.
2206 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2209 std::vector<SDValue>&Ops,
2210 SelectionDAG &DAG) const {
2211 SDValue Result(0, 0);
2213 switch (Constraint) {
2215 case 'I': case 'J': case 'K': case 'L':
2216 case 'M': case 'N': case 'O':
2217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2221 int64_t CVal64 = C->getSExtValue();
2222 int CVal = (int) CVal64;
2223 // None of these constraints allow values larger than 32 bits. Check
2224 // that the value fits in an int.
2228 switch (Constraint) {
2230 if (Subtarget->isThumb()) {
2231 // This must be a constant between 0 and 255, for ADD immediates.
2232 if (CVal >= 0 && CVal <= 255)
2235 // A constant that can be used as an immediate value in a
2236 // data-processing instruction.
2237 if (ARM_AM::getSOImmVal(CVal) != -1)
2243 if (Subtarget->isThumb()) {
2244 // This must be a constant between -255 and -1, for negated ADD
2245 // immediates. This can be used in GCC with an "n" modifier that
2246 // prints the negated value, for use with SUB instructions. It is
2247 // not useful otherwise but is implemented for compatibility.
2248 if (CVal >= -255 && CVal <= -1)
2251 // This must be a constant between -4095 and 4095. It is not clear
2252 // what this constraint is intended for. Implemented for
2253 // compatibility with GCC.
2254 if (CVal >= -4095 && CVal <= 4095)
2260 if (Subtarget->isThumb()) {
2261 // A 32-bit value where only one byte has a nonzero value. Exclude
2262 // zero to match GCC. This constraint is used by GCC internally for
2263 // constants that can be loaded with a move/shift combination.
2264 // It is not useful otherwise but is implemented for compatibility.
2265 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
2268 // A constant whose bitwise inverse can be used as an immediate
2269 // value in a data-processing instruction. This can be used in GCC
2270 // with a "B" modifier that prints the inverted value, for use with
2271 // BIC and MVN instructions. It is not useful otherwise but is
2272 // implemented for compatibility.
2273 if (ARM_AM::getSOImmVal(~CVal) != -1)
2279 if (Subtarget->isThumb()) {
2280 // This must be a constant between -7 and 7,
2281 // for 3-operand ADD/SUB immediate instructions.
2282 if (CVal >= -7 && CVal < 7)
2285 // A constant whose negation can be used as an immediate value in a
2286 // data-processing instruction. This can be used in GCC with an "n"
2287 // modifier that prints the negated value, for use with SUB
2288 // instructions. It is not useful otherwise but is implemented for
2290 if (ARM_AM::getSOImmVal(-CVal) != -1)
2296 if (Subtarget->isThumb()) {
2297 // This must be a multiple of 4 between 0 and 1020, for
2298 // ADD sp + immediate.
2299 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
2302 // A power of two or a constant between 0 and 32. This is used in
2303 // GCC for the shift amount on shifted register operands, but it is
2304 // useful in general for any shift amounts.
2305 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
2311 if (Subtarget->isThumb()) {
2312 // This must be a constant between 0 and 31, for shift amounts.
2313 if (CVal >= 0 && CVal <= 31)
2319 if (Subtarget->isThumb()) {
2320 // This must be a multiple of 4 between -508 and 508, for
2321 // ADD/SUB sp = sp + immediate.
2322 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
2327 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2331 if (Result.getNode()) {
2332 Ops.push_back(Result);
2335 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,