1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
88 if (ElemTy != MVT::i32) {
89 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
90 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
97 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
98 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
100 if (VT.isInteger()) {
101 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
102 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
104 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
106 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
107 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
108 setTruncStoreAction(VT.getSimpleVT(),
109 (MVT::SimpleValueType)InnerVT, Expand);
111 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
113 // Promote all bit-wise operations.
114 if (VT.isInteger() && VT != PromotedBitwiseVT) {
115 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
126 // Neon does not support vector divide/remainder operations.
127 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
135 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
136 addRegisterClass(VT, ARM::DPRRegisterClass);
137 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
140 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
141 addRegisterClass(VT, ARM::QPRRegisterClass);
142 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
145 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
146 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
147 return new TargetLoweringObjectFileMachO();
149 return new ARMElfTargetObjectFile();
152 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
153 : TargetLowering(TM, createTLOF(TM)) {
154 Subtarget = &TM.getSubtarget<ARMSubtarget>();
155 RegInfo = TM.getRegisterInfo();
156 Itins = TM.getInstrItineraryData();
158 if (Subtarget->isTargetDarwin()) {
159 // Uses VFP for Thumb libfuncs if available.
160 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
161 // Single-precision floating-point arithmetic.
162 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
163 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
164 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
165 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
167 // Double-precision floating-point arithmetic.
168 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
169 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
170 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
171 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
173 // Single-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
175 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
176 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
177 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
178 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
179 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
180 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
181 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
192 // Double-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
194 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
195 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
196 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
197 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
198 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
199 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
200 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
216 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
217 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
219 // Conversions between floating types.
220 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
221 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
229 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
230 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
231 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
235 // These libcalls are not available in 32-bit.
236 setLibcallName(RTLIB::SHL_I128, 0);
237 setLibcallName(RTLIB::SRL_I128, 0);
238 setLibcallName(RTLIB::SRA_I128, 0);
240 if (Subtarget->isAAPCS_ABI()) {
241 // Double-precision floating-point arithmetic helper functions
242 // RTABI chapter 4.1.2, Table 2
243 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
244 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
245 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
246 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
247 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
248 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
252 // Double-precision floating-point comparison helper functions
253 // RTABI chapter 4.1.2, Table 3
254 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
255 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
256 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
257 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
258 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
259 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
260 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
261 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
262 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
263 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
265 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
266 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
267 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
268 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
269 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
270 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
282 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
283 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
284 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
285 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
286 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
293 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
294 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
295 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
296 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
297 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
298 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
299 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
300 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
301 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
303 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
304 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
305 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
306 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
307 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
308 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
317 // Floating-point to integer conversions.
318 // RTABI chapter 4.1.2, Table 6
319 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
320 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
321 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
322 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
323 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
324 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
326 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
327 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
336 // Conversions between floating types.
337 // RTABI chapter 4.1.2, Table 7
338 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
339 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
340 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
343 // Integer to floating-point conversions.
344 // RTABI chapter 4.1.2, Table 8
345 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
346 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
347 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
348 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
349 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
350 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
351 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
352 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
353 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
362 // Long long helper functions
363 // RTABI chapter 4.2, Table 9
364 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
365 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
366 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
367 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
368 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
369 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
370 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
371 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
377 // Integer division functions
378 // RTABI chapter 4.3.1
379 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
380 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
382 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
383 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
385 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
393 if (Subtarget->isThumb1Only())
394 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
396 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
397 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
398 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
399 if (!Subtarget->isFPOnlySP())
400 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
402 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
405 if (Subtarget->hasNEON()) {
406 addDRTypeForNEON(MVT::v2f32);
407 addDRTypeForNEON(MVT::v8i8);
408 addDRTypeForNEON(MVT::v4i16);
409 addDRTypeForNEON(MVT::v2i32);
410 addDRTypeForNEON(MVT::v1i64);
412 addQRTypeForNEON(MVT::v4f32);
413 addQRTypeForNEON(MVT::v2f64);
414 addQRTypeForNEON(MVT::v16i8);
415 addQRTypeForNEON(MVT::v8i16);
416 addQRTypeForNEON(MVT::v4i32);
417 addQRTypeForNEON(MVT::v2i64);
419 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
420 // neither Neon nor VFP support any arithmetic operations on it.
421 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
422 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
423 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
424 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
425 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
427 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
428 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
429 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
432 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
438 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
441 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
443 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
446 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
448 // Neon does not support some operations on v1i64 and v2i64 types.
449 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
450 // Custom handling for some quad-vector types to detect VMULL.
451 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
452 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
453 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
454 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
457 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::SHL);
459 setTargetDAGCombine(ISD::SRL);
460 setTargetDAGCombine(ISD::SRA);
461 setTargetDAGCombine(ISD::SIGN_EXTEND);
462 setTargetDAGCombine(ISD::ZERO_EXTEND);
463 setTargetDAGCombine(ISD::ANY_EXTEND);
464 setTargetDAGCombine(ISD::SELECT_CC);
465 setTargetDAGCombine(ISD::BUILD_VECTOR);
466 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
467 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
468 setTargetDAGCombine(ISD::STORE);
471 computeRegisterProperties();
473 // ARM does not have f32 extending load.
474 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
476 // ARM does not have i1 sign extending load.
477 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
479 // ARM supports all 4 flavors of integer indexed load / store.
480 if (!Subtarget->isThumb1Only()) {
481 for (unsigned im = (unsigned)ISD::PRE_INC;
482 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
483 setIndexedLoadAction(im, MVT::i1, Legal);
484 setIndexedLoadAction(im, MVT::i8, Legal);
485 setIndexedLoadAction(im, MVT::i16, Legal);
486 setIndexedLoadAction(im, MVT::i32, Legal);
487 setIndexedStoreAction(im, MVT::i1, Legal);
488 setIndexedStoreAction(im, MVT::i8, Legal);
489 setIndexedStoreAction(im, MVT::i16, Legal);
490 setIndexedStoreAction(im, MVT::i32, Legal);
494 // i64 operation support.
495 if (Subtarget->isThumb1Only()) {
496 setOperationAction(ISD::MUL, MVT::i64, Expand);
497 setOperationAction(ISD::MULHU, MVT::i32, Expand);
498 setOperationAction(ISD::MULHS, MVT::i32, Expand);
499 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
500 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
502 setOperationAction(ISD::MUL, MVT::i64, Expand);
503 setOperationAction(ISD::MULHU, MVT::i32, Expand);
504 if (!Subtarget->hasV6Ops())
505 setOperationAction(ISD::MULHS, MVT::i32, Expand);
507 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
509 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
510 setOperationAction(ISD::SRL, MVT::i64, Custom);
511 setOperationAction(ISD::SRA, MVT::i64, Custom);
513 // ARM does not have ROTL.
514 setOperationAction(ISD::ROTL, MVT::i32, Expand);
515 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
516 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
517 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
518 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
520 // Only ARMv6 has BSWAP.
521 if (!Subtarget->hasV6Ops())
522 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
524 // These are expanded into libcalls.
525 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
526 // v7M has a hardware divider
527 setOperationAction(ISD::SDIV, MVT::i32, Expand);
528 setOperationAction(ISD::UDIV, MVT::i32, Expand);
530 setOperationAction(ISD::SREM, MVT::i32, Expand);
531 setOperationAction(ISD::UREM, MVT::i32, Expand);
532 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
533 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
535 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
536 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
537 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
538 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
539 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // Use the default implementation.
544 setOperationAction(ISD::VASTART, MVT::Other, Custom);
545 setOperationAction(ISD::VAARG, MVT::Other, Expand);
546 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
547 setOperationAction(ISD::VAEND, MVT::Other, Expand);
548 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
549 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
550 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
551 // FIXME: Shouldn't need this, since no register is used, but the legalizer
552 // doesn't yet know how to not do that for SjLj.
553 setExceptionSelectorRegister(ARM::R0);
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
555 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
556 // the default expansion.
557 if (Subtarget->hasDataBarrier() ||
558 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
559 // membarrier needs custom lowering; the rest are legal and handled
561 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
563 // Set them all for expansion, which will force libcalls.
564 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
566 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
567 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
569 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
570 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
588 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
589 // Since the libcalls include locking, fold in the fences
590 setShouldFoldAtomicFences(true);
592 // 64-bit versions are always libcalls (for now)
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
602 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
604 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
605 if (!Subtarget->hasV6Ops()) {
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
611 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
612 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
613 // iff target supports vfp2.
614 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
615 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
618 // We want to custom lower some of our intrinsics.
619 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
620 if (Subtarget->isTargetDarwin()) {
621 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
622 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
623 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
626 setOperationAction(ISD::SETCC, MVT::i32, Expand);
627 setOperationAction(ISD::SETCC, MVT::f32, Expand);
628 setOperationAction(ISD::SETCC, MVT::f64, Expand);
629 setOperationAction(ISD::SELECT, MVT::i32, Custom);
630 setOperationAction(ISD::SELECT, MVT::f32, Custom);
631 setOperationAction(ISD::SELECT, MVT::f64, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
633 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
634 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
636 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
637 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
638 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
639 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
640 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
642 // We don't support sin/cos/fmod/copysign/pow
643 setOperationAction(ISD::FSIN, MVT::f64, Expand);
644 setOperationAction(ISD::FSIN, MVT::f32, Expand);
645 setOperationAction(ISD::FCOS, MVT::f32, Expand);
646 setOperationAction(ISD::FCOS, MVT::f64, Expand);
647 setOperationAction(ISD::FREM, MVT::f64, Expand);
648 setOperationAction(ISD::FREM, MVT::f32, Expand);
649 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
650 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
651 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
653 setOperationAction(ISD::FPOW, MVT::f64, Expand);
654 setOperationAction(ISD::FPOW, MVT::f32, Expand);
656 // Various VFP goodness
657 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
658 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
659 if (Subtarget->hasVFP2()) {
660 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
661 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
662 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
663 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
665 // Special handling for half-precision FP.
666 if (!Subtarget->hasFP16()) {
667 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
668 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
672 // We have target-specific dag combine patterns for the following nodes:
673 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
674 setTargetDAGCombine(ISD::ADD);
675 setTargetDAGCombine(ISD::SUB);
676 setTargetDAGCombine(ISD::MUL);
678 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
679 setTargetDAGCombine(ISD::OR);
680 if (Subtarget->hasNEON())
681 setTargetDAGCombine(ISD::AND);
683 setStackPointerRegisterToSaveRestore(ARM::SP);
685 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
686 setSchedulingPreference(Sched::RegPressure);
688 setSchedulingPreference(Sched::Hybrid);
690 //// temporary - rewrite interface to use type
691 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
693 // On ARM arguments smaller than 4 bytes are extended, so all arguments
694 // are at least 4 bytes aligned.
695 setMinStackArgumentAlignment(4);
697 benefitFromCodePlacementOpt = true;
700 std::pair<const TargetRegisterClass*, uint8_t>
701 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
702 const TargetRegisterClass *RRC = 0;
704 switch (VT.getSimpleVT().SimpleTy) {
706 return TargetLowering::findRepresentativeClass(VT);
707 // Use DPR as representative register class for all floating point
708 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
709 // the cost is 1 for both f32 and f64.
710 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
711 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
712 RRC = ARM::DPRRegisterClass;
714 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
715 case MVT::v4f32: case MVT::v2f64:
716 RRC = ARM::DPRRegisterClass;
720 RRC = ARM::DPRRegisterClass;
724 RRC = ARM::DPRRegisterClass;
728 return std::make_pair(RRC, Cost);
731 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
734 case ARMISD::Wrapper: return "ARMISD::Wrapper";
735 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
736 case ARMISD::CALL: return "ARMISD::CALL";
737 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
738 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
739 case ARMISD::tCALL: return "ARMISD::tCALL";
740 case ARMISD::BRCOND: return "ARMISD::BRCOND";
741 case ARMISD::BR_JT: return "ARMISD::BR_JT";
742 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
743 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
744 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
745 case ARMISD::CMP: return "ARMISD::CMP";
746 case ARMISD::CMPZ: return "ARMISD::CMPZ";
747 case ARMISD::CMPFP: return "ARMISD::CMPFP";
748 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
749 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
750 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
751 case ARMISD::CMOV: return "ARMISD::CMOV";
752 case ARMISD::CNEG: return "ARMISD::CNEG";
754 case ARMISD::RBIT: return "ARMISD::RBIT";
756 case ARMISD::FTOSI: return "ARMISD::FTOSI";
757 case ARMISD::FTOUI: return "ARMISD::FTOUI";
758 case ARMISD::SITOF: return "ARMISD::SITOF";
759 case ARMISD::UITOF: return "ARMISD::UITOF";
761 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
762 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
763 case ARMISD::RRX: return "ARMISD::RRX";
765 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
766 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
768 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
769 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
770 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
772 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
774 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
776 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
778 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
779 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
781 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
783 case ARMISD::VCEQ: return "ARMISD::VCEQ";
784 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
785 case ARMISD::VCGE: return "ARMISD::VCGE";
786 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
787 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
788 case ARMISD::VCGEU: return "ARMISD::VCGEU";
789 case ARMISD::VCGT: return "ARMISD::VCGT";
790 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
791 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
792 case ARMISD::VCGTU: return "ARMISD::VCGTU";
793 case ARMISD::VTST: return "ARMISD::VTST";
795 case ARMISD::VSHL: return "ARMISD::VSHL";
796 case ARMISD::VSHRs: return "ARMISD::VSHRs";
797 case ARMISD::VSHRu: return "ARMISD::VSHRu";
798 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
799 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
800 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
801 case ARMISD::VSHRN: return "ARMISD::VSHRN";
802 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
803 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
804 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
805 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
806 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
807 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
808 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
809 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
810 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
811 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
812 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
813 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
814 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
815 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
816 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
817 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
818 case ARMISD::VDUP: return "ARMISD::VDUP";
819 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
820 case ARMISD::VEXT: return "ARMISD::VEXT";
821 case ARMISD::VREV64: return "ARMISD::VREV64";
822 case ARMISD::VREV32: return "ARMISD::VREV32";
823 case ARMISD::VREV16: return "ARMISD::VREV16";
824 case ARMISD::VZIP: return "ARMISD::VZIP";
825 case ARMISD::VUZP: return "ARMISD::VUZP";
826 case ARMISD::VTRN: return "ARMISD::VTRN";
827 case ARMISD::VMULLs: return "ARMISD::VMULLs";
828 case ARMISD::VMULLu: return "ARMISD::VMULLu";
829 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
830 case ARMISD::FMAX: return "ARMISD::FMAX";
831 case ARMISD::FMIN: return "ARMISD::FMIN";
832 case ARMISD::BFI: return "ARMISD::BFI";
833 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
834 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
835 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
836 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
837 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
841 /// getRegClassFor - Return the register class that should be used for the
842 /// specified value type.
843 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
844 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
845 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
846 // load / store 4 to 8 consecutive D registers.
847 if (Subtarget->hasNEON()) {
848 if (VT == MVT::v4i64)
849 return ARM::QQPRRegisterClass;
850 else if (VT == MVT::v8i64)
851 return ARM::QQQQPRRegisterClass;
853 return TargetLowering::getRegClassFor(VT);
856 // Create a fast isel object.
858 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
859 return ARM::createFastISel(funcInfo);
862 /// getFunctionAlignment - Return the Log2 alignment of this function.
863 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
864 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
867 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
868 /// be used for loads / stores from the global.
869 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
870 return (Subtarget->isThumb1Only() ? 127 : 4095);
873 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
874 unsigned NumVals = N->getNumValues();
876 return Sched::RegPressure;
878 for (unsigned i = 0; i != NumVals; ++i) {
879 EVT VT = N->getValueType(i);
880 if (VT == MVT::Glue || VT == MVT::Other)
882 if (VT.isFloatingPoint() || VT.isVector())
883 return Sched::Latency;
886 if (!N->isMachineOpcode())
887 return Sched::RegPressure;
889 // Load are scheduled for latency even if there instruction itinerary
891 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
892 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
894 if (TID.getNumDefs() == 0)
895 return Sched::RegPressure;
896 if (!Itins->isEmpty() &&
897 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
898 return Sched::Latency;
900 return Sched::RegPressure;
904 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
905 MachineFunction &MF) const {
906 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
908 switch (RC->getID()) {
911 case ARM::tGPRRegClassID:
912 return TFI->hasFP(MF) ? 4 : 5;
913 case ARM::GPRRegClassID: {
914 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
915 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
917 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
918 case ARM::DPRRegClassID:
923 //===----------------------------------------------------------------------===//
925 //===----------------------------------------------------------------------===//
927 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
928 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
930 default: llvm_unreachable("Unknown condition code!");
931 case ISD::SETNE: return ARMCC::NE;
932 case ISD::SETEQ: return ARMCC::EQ;
933 case ISD::SETGT: return ARMCC::GT;
934 case ISD::SETGE: return ARMCC::GE;
935 case ISD::SETLT: return ARMCC::LT;
936 case ISD::SETLE: return ARMCC::LE;
937 case ISD::SETUGT: return ARMCC::HI;
938 case ISD::SETUGE: return ARMCC::HS;
939 case ISD::SETULT: return ARMCC::LO;
940 case ISD::SETULE: return ARMCC::LS;
944 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
945 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
946 ARMCC::CondCodes &CondCode2) {
947 CondCode2 = ARMCC::AL;
949 default: llvm_unreachable("Unknown FP condition!");
951 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
953 case ISD::SETOGT: CondCode = ARMCC::GT; break;
955 case ISD::SETOGE: CondCode = ARMCC::GE; break;
956 case ISD::SETOLT: CondCode = ARMCC::MI; break;
957 case ISD::SETOLE: CondCode = ARMCC::LS; break;
958 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
959 case ISD::SETO: CondCode = ARMCC::VC; break;
960 case ISD::SETUO: CondCode = ARMCC::VS; break;
961 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
962 case ISD::SETUGT: CondCode = ARMCC::HI; break;
963 case ISD::SETUGE: CondCode = ARMCC::PL; break;
965 case ISD::SETULT: CondCode = ARMCC::LT; break;
967 case ISD::SETULE: CondCode = ARMCC::LE; break;
969 case ISD::SETUNE: CondCode = ARMCC::NE; break;
973 //===----------------------------------------------------------------------===//
974 // Calling Convention Implementation
975 //===----------------------------------------------------------------------===//
977 #include "ARMGenCallingConv.inc"
979 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
980 /// given CallingConvention value.
981 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
983 bool isVarArg) const {
986 llvm_unreachable("Unsupported calling convention");
987 case CallingConv::Fast:
988 if (Subtarget->hasVFP2() && !isVarArg) {
989 if (!Subtarget->isAAPCS_ABI())
990 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
991 // For AAPCS ABI targets, just use VFP variant of the calling convention.
992 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
995 case CallingConv::C: {
996 // Use target triple & subtarget features to do actual dispatch.
997 if (!Subtarget->isAAPCS_ABI())
998 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
999 else if (Subtarget->hasVFP2() &&
1000 FloatABIType == FloatABI::Hard && !isVarArg)
1001 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1002 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1004 case CallingConv::ARM_AAPCS_VFP:
1005 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1006 case CallingConv::ARM_AAPCS:
1007 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1008 case CallingConv::ARM_APCS:
1009 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1013 /// LowerCallResult - Lower the result values of a call into the
1014 /// appropriate copies out of appropriate physical registers.
1016 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1017 CallingConv::ID CallConv, bool isVarArg,
1018 const SmallVectorImpl<ISD::InputArg> &Ins,
1019 DebugLoc dl, SelectionDAG &DAG,
1020 SmallVectorImpl<SDValue> &InVals) const {
1022 // Assign locations to each value returned by this call.
1023 SmallVector<CCValAssign, 16> RVLocs;
1024 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1025 RVLocs, *DAG.getContext());
1026 CCInfo.AnalyzeCallResult(Ins,
1027 CCAssignFnForNode(CallConv, /* Return*/ true,
1030 // Copy all of the result registers out of their specified physreg.
1031 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1032 CCValAssign VA = RVLocs[i];
1035 if (VA.needsCustom()) {
1036 // Handle f64 or half of a v2f64.
1037 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1039 Chain = Lo.getValue(1);
1040 InFlag = Lo.getValue(2);
1041 VA = RVLocs[++i]; // skip ahead to next loc
1042 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1044 Chain = Hi.getValue(1);
1045 InFlag = Hi.getValue(2);
1046 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1048 if (VA.getLocVT() == MVT::v2f64) {
1049 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1050 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1051 DAG.getConstant(0, MVT::i32));
1053 VA = RVLocs[++i]; // skip ahead to next loc
1054 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1055 Chain = Lo.getValue(1);
1056 InFlag = Lo.getValue(2);
1057 VA = RVLocs[++i]; // skip ahead to next loc
1058 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1059 Chain = Hi.getValue(1);
1060 InFlag = Hi.getValue(2);
1061 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1062 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1063 DAG.getConstant(1, MVT::i32));
1066 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1068 Chain = Val.getValue(1);
1069 InFlag = Val.getValue(2);
1072 switch (VA.getLocInfo()) {
1073 default: llvm_unreachable("Unknown loc info!");
1074 case CCValAssign::Full: break;
1075 case CCValAssign::BCvt:
1076 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1080 InVals.push_back(Val);
1086 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1087 /// by "Src" to address "Dst" of size "Size". Alignment information is
1088 /// specified by the specific parameter attribute. The copy will be passed as
1089 /// a byval function parameter.
1090 /// Sometimes what we are copying is the end of a larger object, the part that
1091 /// does not fit in registers.
1093 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1094 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1096 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1097 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1098 /*isVolatile=*/false, /*AlwaysInline=*/false,
1099 MachinePointerInfo(0), MachinePointerInfo(0));
1102 /// LowerMemOpCallTo - Store the argument to the stack.
1104 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1105 SDValue StackPtr, SDValue Arg,
1106 DebugLoc dl, SelectionDAG &DAG,
1107 const CCValAssign &VA,
1108 ISD::ArgFlagsTy Flags) const {
1109 unsigned LocMemOffset = VA.getLocMemOffset();
1110 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1111 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1112 if (Flags.isByVal())
1113 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1115 return DAG.getStore(Chain, dl, Arg, PtrOff,
1116 MachinePointerInfo::getStack(LocMemOffset),
1120 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1121 SDValue Chain, SDValue &Arg,
1122 RegsToPassVector &RegsToPass,
1123 CCValAssign &VA, CCValAssign &NextVA,
1125 SmallVector<SDValue, 8> &MemOpChains,
1126 ISD::ArgFlagsTy Flags) const {
1128 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1129 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1130 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1132 if (NextVA.isRegLoc())
1133 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1135 assert(NextVA.isMemLoc());
1136 if (StackPtr.getNode() == 0)
1137 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1139 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1145 /// LowerCall - Lowering a call into a callseq_start <-
1146 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1149 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1150 CallingConv::ID CallConv, bool isVarArg,
1152 const SmallVectorImpl<ISD::OutputArg> &Outs,
1153 const SmallVectorImpl<SDValue> &OutVals,
1154 const SmallVectorImpl<ISD::InputArg> &Ins,
1155 DebugLoc dl, SelectionDAG &DAG,
1156 SmallVectorImpl<SDValue> &InVals) const {
1157 MachineFunction &MF = DAG.getMachineFunction();
1158 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1159 bool IsSibCall = false;
1160 // Temporarily disable tail calls so things don't break.
1161 if (!EnableARMTailCalls)
1164 // Check if it's really possible to do a tail call.
1165 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1166 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1167 Outs, OutVals, Ins, DAG);
1168 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1169 // detected sibcalls.
1176 // Analyze operands of the call, assigning locations to each operand.
1177 SmallVector<CCValAssign, 16> ArgLocs;
1178 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1180 CCInfo.AnalyzeCallOperands(Outs,
1181 CCAssignFnForNode(CallConv, /* Return*/ false,
1184 // Get a count of how many bytes are to be pushed on the stack.
1185 unsigned NumBytes = CCInfo.getNextStackOffset();
1187 // For tail calls, memory operands are available in our caller's stack.
1191 // Adjust the stack pointer for the new arguments...
1192 // These operations are automatically eliminated by the prolog/epilog pass
1194 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1196 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1198 RegsToPassVector RegsToPass;
1199 SmallVector<SDValue, 8> MemOpChains;
1201 // Walk the register/memloc assignments, inserting copies/loads. In the case
1202 // of tail call optimization, arguments are handled later.
1203 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1205 ++i, ++realArgIdx) {
1206 CCValAssign &VA = ArgLocs[i];
1207 SDValue Arg = OutVals[realArgIdx];
1208 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1210 // Promote the value if needed.
1211 switch (VA.getLocInfo()) {
1212 default: llvm_unreachable("Unknown loc info!");
1213 case CCValAssign::Full: break;
1214 case CCValAssign::SExt:
1215 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1217 case CCValAssign::ZExt:
1218 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1220 case CCValAssign::AExt:
1221 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1223 case CCValAssign::BCvt:
1224 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1228 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1229 if (VA.needsCustom()) {
1230 if (VA.getLocVT() == MVT::v2f64) {
1231 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1232 DAG.getConstant(0, MVT::i32));
1233 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1234 DAG.getConstant(1, MVT::i32));
1236 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1237 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1239 VA = ArgLocs[++i]; // skip ahead to next loc
1240 if (VA.isRegLoc()) {
1241 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1242 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1244 assert(VA.isMemLoc());
1246 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1247 dl, DAG, VA, Flags));
1250 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1251 StackPtr, MemOpChains, Flags);
1253 } else if (VA.isRegLoc()) {
1254 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1255 } else if (!IsSibCall) {
1256 assert(VA.isMemLoc());
1258 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1259 dl, DAG, VA, Flags));
1263 if (!MemOpChains.empty())
1264 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1265 &MemOpChains[0], MemOpChains.size());
1267 // Build a sequence of copy-to-reg nodes chained together with token chain
1268 // and flag operands which copy the outgoing args into the appropriate regs.
1270 // Tail call byval lowering might overwrite argument registers so in case of
1271 // tail call optimization the copies to registers are lowered later.
1273 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1274 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1275 RegsToPass[i].second, InFlag);
1276 InFlag = Chain.getValue(1);
1279 // For tail calls lower the arguments to the 'real' stack slot.
1281 // Force all the incoming stack arguments to be loaded from the stack
1282 // before any new outgoing arguments are stored to the stack, because the
1283 // outgoing stack slots may alias the incoming argument stack slots, and
1284 // the alias isn't otherwise explicit. This is slightly more conservative
1285 // than necessary, because it means that each store effectively depends
1286 // on every argument instead of just those arguments it would clobber.
1288 // Do not flag preceeding copytoreg stuff together with the following stuff.
1290 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1291 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1292 RegsToPass[i].second, InFlag);
1293 InFlag = Chain.getValue(1);
1298 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1299 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1300 // node so that legalize doesn't hack it.
1301 bool isDirect = false;
1302 bool isARMFunc = false;
1303 bool isLocalARMFunc = false;
1304 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1306 if (EnableARMLongCalls) {
1307 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1308 && "long-calls with non-static relocation model!");
1309 // Handle a global address or an external symbol. If it's not one of
1310 // those, the target's already in a register, so we don't need to do
1312 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1313 const GlobalValue *GV = G->getGlobal();
1314 // Create a constant pool entry for the callee address
1315 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1316 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1319 // Get the address of the callee into a register
1320 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1321 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1322 Callee = DAG.getLoad(getPointerTy(), dl,
1323 DAG.getEntryNode(), CPAddr,
1324 MachinePointerInfo::getConstantPool(),
1326 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1327 const char *Sym = S->getSymbol();
1329 // Create a constant pool entry for the callee address
1330 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1331 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1332 Sym, ARMPCLabelIndex, 0);
1333 // Get the address of the callee into a register
1334 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1335 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1336 Callee = DAG.getLoad(getPointerTy(), dl,
1337 DAG.getEntryNode(), CPAddr,
1338 MachinePointerInfo::getConstantPool(),
1341 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1342 const GlobalValue *GV = G->getGlobal();
1344 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1345 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1346 getTargetMachine().getRelocationModel() != Reloc::Static;
1347 isARMFunc = !Subtarget->isThumb() || isStub;
1348 // ARM call to a local ARM function is predicable.
1349 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1350 // tBX takes a register source operand.
1351 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1352 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1353 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1356 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1357 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1358 Callee = DAG.getLoad(getPointerTy(), dl,
1359 DAG.getEntryNode(), CPAddr,
1360 MachinePointerInfo::getConstantPool(),
1362 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1363 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1364 getPointerTy(), Callee, PICLabel);
1366 // On ELF targets for PIC code, direct calls should go through the PLT
1367 unsigned OpFlags = 0;
1368 if (Subtarget->isTargetELF() &&
1369 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1370 OpFlags = ARMII::MO_PLT;
1371 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1373 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1375 bool isStub = Subtarget->isTargetDarwin() &&
1376 getTargetMachine().getRelocationModel() != Reloc::Static;
1377 isARMFunc = !Subtarget->isThumb() || isStub;
1378 // tBX takes a register source operand.
1379 const char *Sym = S->getSymbol();
1380 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1381 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1382 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1383 Sym, ARMPCLabelIndex, 4);
1384 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1385 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1386 Callee = DAG.getLoad(getPointerTy(), dl,
1387 DAG.getEntryNode(), CPAddr,
1388 MachinePointerInfo::getConstantPool(),
1390 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1391 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1392 getPointerTy(), Callee, PICLabel);
1394 unsigned OpFlags = 0;
1395 // On ELF targets for PIC code, direct calls should go through the PLT
1396 if (Subtarget->isTargetELF() &&
1397 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1398 OpFlags = ARMII::MO_PLT;
1399 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1403 // FIXME: handle tail calls differently.
1405 if (Subtarget->isThumb()) {
1406 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1407 CallOpc = ARMISD::CALL_NOLINK;
1409 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1411 CallOpc = (isDirect || Subtarget->hasV5TOps())
1412 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1413 : ARMISD::CALL_NOLINK;
1416 std::vector<SDValue> Ops;
1417 Ops.push_back(Chain);
1418 Ops.push_back(Callee);
1420 // Add argument registers to the end of the list so that they are known live
1422 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1423 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1424 RegsToPass[i].second.getValueType()));
1426 if (InFlag.getNode())
1427 Ops.push_back(InFlag);
1429 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1431 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1433 // Returns a chain and a flag for retval copy to use.
1434 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1435 InFlag = Chain.getValue(1);
1437 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1438 DAG.getIntPtrConstant(0, true), InFlag);
1440 InFlag = Chain.getValue(1);
1442 // Handle result values, copying them out of physregs into vregs that we
1444 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1448 /// MatchingStackOffset - Return true if the given stack call argument is
1449 /// already available in the same position (relatively) of the caller's
1450 /// incoming argument stack.
1452 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1453 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1454 const ARMInstrInfo *TII) {
1455 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1457 if (Arg.getOpcode() == ISD::CopyFromReg) {
1458 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1459 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1461 MachineInstr *Def = MRI->getVRegDef(VR);
1464 if (!Flags.isByVal()) {
1465 if (!TII->isLoadFromStackSlot(Def, FI))
1470 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1471 if (Flags.isByVal())
1472 // ByVal argument is passed in as a pointer but it's now being
1473 // dereferenced. e.g.
1474 // define @foo(%struct.X* %A) {
1475 // tail call @bar(%struct.X* byval %A)
1478 SDValue Ptr = Ld->getBasePtr();
1479 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1482 FI = FINode->getIndex();
1486 assert(FI != INT_MAX);
1487 if (!MFI->isFixedObjectIndex(FI))
1489 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1492 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1493 /// for tail call optimization. Targets which want to do tail call
1494 /// optimization should implement this function.
1496 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1497 CallingConv::ID CalleeCC,
1499 bool isCalleeStructRet,
1500 bool isCallerStructRet,
1501 const SmallVectorImpl<ISD::OutputArg> &Outs,
1502 const SmallVectorImpl<SDValue> &OutVals,
1503 const SmallVectorImpl<ISD::InputArg> &Ins,
1504 SelectionDAG& DAG) const {
1505 const Function *CallerF = DAG.getMachineFunction().getFunction();
1506 CallingConv::ID CallerCC = CallerF->getCallingConv();
1507 bool CCMatch = CallerCC == CalleeCC;
1509 // Look for obvious safe cases to perform tail call optimization that do not
1510 // require ABI changes. This is what gcc calls sibcall.
1512 // Do not sibcall optimize vararg calls unless the call site is not passing
1514 if (isVarArg && !Outs.empty())
1517 // Also avoid sibcall optimization if either caller or callee uses struct
1518 // return semantics.
1519 if (isCalleeStructRet || isCallerStructRet)
1522 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1523 // emitEpilogue is not ready for them.
1524 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1525 // LR. This means if we need to reload LR, it takes an extra instructions,
1526 // which outweighs the value of the tail call; but here we don't know yet
1527 // whether LR is going to be used. Probably the right approach is to
1528 // generate the tail call here and turn it back into CALL/RET in
1529 // emitEpilogue if LR is used.
1531 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1532 // but we need to make sure there are enough registers; the only valid
1533 // registers are the 4 used for parameters. We don't currently do this
1535 if (Subtarget->isThumb1Only())
1538 // If the calling conventions do not match, then we'd better make sure the
1539 // results are returned in the same way as what the caller expects.
1541 SmallVector<CCValAssign, 16> RVLocs1;
1542 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1543 RVLocs1, *DAG.getContext());
1544 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1546 SmallVector<CCValAssign, 16> RVLocs2;
1547 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1548 RVLocs2, *DAG.getContext());
1549 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1551 if (RVLocs1.size() != RVLocs2.size())
1553 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1554 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1556 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1558 if (RVLocs1[i].isRegLoc()) {
1559 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1562 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1568 // If the callee takes no arguments then go on to check the results of the
1570 if (!Outs.empty()) {
1571 // Check if stack adjustment is needed. For now, do not do this if any
1572 // argument is passed on the stack.
1573 SmallVector<CCValAssign, 16> ArgLocs;
1574 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1575 ArgLocs, *DAG.getContext());
1576 CCInfo.AnalyzeCallOperands(Outs,
1577 CCAssignFnForNode(CalleeCC, false, isVarArg));
1578 if (CCInfo.getNextStackOffset()) {
1579 MachineFunction &MF = DAG.getMachineFunction();
1581 // Check if the arguments are already laid out in the right way as
1582 // the caller's fixed stack objects.
1583 MachineFrameInfo *MFI = MF.getFrameInfo();
1584 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1585 const ARMInstrInfo *TII =
1586 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1587 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1589 ++i, ++realArgIdx) {
1590 CCValAssign &VA = ArgLocs[i];
1591 EVT RegVT = VA.getLocVT();
1592 SDValue Arg = OutVals[realArgIdx];
1593 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1594 if (VA.getLocInfo() == CCValAssign::Indirect)
1596 if (VA.needsCustom()) {
1597 // f64 and vector types are split into multiple registers or
1598 // register/stack-slot combinations. The types will not match
1599 // the registers; give up on memory f64 refs until we figure
1600 // out what to do about this.
1603 if (!ArgLocs[++i].isRegLoc())
1605 if (RegVT == MVT::v2f64) {
1606 if (!ArgLocs[++i].isRegLoc())
1608 if (!ArgLocs[++i].isRegLoc())
1611 } else if (!VA.isRegLoc()) {
1612 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1624 ARMTargetLowering::LowerReturn(SDValue Chain,
1625 CallingConv::ID CallConv, bool isVarArg,
1626 const SmallVectorImpl<ISD::OutputArg> &Outs,
1627 const SmallVectorImpl<SDValue> &OutVals,
1628 DebugLoc dl, SelectionDAG &DAG) const {
1630 // CCValAssign - represent the assignment of the return value to a location.
1631 SmallVector<CCValAssign, 16> RVLocs;
1633 // CCState - Info about the registers and stack slots.
1634 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1637 // Analyze outgoing return values.
1638 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1641 // If this is the first return lowered for this function, add
1642 // the regs to the liveout set for the function.
1643 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1644 for (unsigned i = 0; i != RVLocs.size(); ++i)
1645 if (RVLocs[i].isRegLoc())
1646 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1651 // Copy the result values into the output registers.
1652 for (unsigned i = 0, realRVLocIdx = 0;
1654 ++i, ++realRVLocIdx) {
1655 CCValAssign &VA = RVLocs[i];
1656 assert(VA.isRegLoc() && "Can only return in registers!");
1658 SDValue Arg = OutVals[realRVLocIdx];
1660 switch (VA.getLocInfo()) {
1661 default: llvm_unreachable("Unknown loc info!");
1662 case CCValAssign::Full: break;
1663 case CCValAssign::BCvt:
1664 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1668 if (VA.needsCustom()) {
1669 if (VA.getLocVT() == MVT::v2f64) {
1670 // Extract the first half and return it in two registers.
1671 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1672 DAG.getConstant(0, MVT::i32));
1673 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1674 DAG.getVTList(MVT::i32, MVT::i32), Half);
1676 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1677 Flag = Chain.getValue(1);
1678 VA = RVLocs[++i]; // skip ahead to next loc
1679 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1680 HalfGPRs.getValue(1), Flag);
1681 Flag = Chain.getValue(1);
1682 VA = RVLocs[++i]; // skip ahead to next loc
1684 // Extract the 2nd half and fall through to handle it as an f64 value.
1685 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1686 DAG.getConstant(1, MVT::i32));
1688 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1690 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1691 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1692 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1693 Flag = Chain.getValue(1);
1694 VA = RVLocs[++i]; // skip ahead to next loc
1695 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1698 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1700 // Guarantee that all emitted copies are
1701 // stuck together, avoiding something bad.
1702 Flag = Chain.getValue(1);
1707 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1709 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1714 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1715 if (N->getNumValues() != 1)
1717 if (!N->hasNUsesOfValue(1, 0))
1720 unsigned NumCopies = 0;
1722 SDNode *Use = *N->use_begin();
1723 if (Use->getOpcode() == ISD::CopyToReg) {
1724 Copies[NumCopies++] = Use;
1725 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1726 // f64 returned in a pair of GPRs.
1727 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1729 if (UI->getOpcode() != ISD::CopyToReg)
1731 Copies[UI.getUse().getResNo()] = *UI;
1734 } else if (Use->getOpcode() == ISD::BITCAST) {
1735 // f32 returned in a single GPR.
1736 if (!Use->hasNUsesOfValue(1, 0))
1738 Use = *Use->use_begin();
1739 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1741 Copies[NumCopies++] = Use;
1746 if (NumCopies != 1 && NumCopies != 2)
1749 bool HasRet = false;
1750 for (unsigned i = 0; i < NumCopies; ++i) {
1751 SDNode *Copy = Copies[i];
1752 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1754 if (UI->getOpcode() == ISD::CopyToReg) {
1756 if (Use == Copies[0] || Use == Copies[1])
1760 if (UI->getOpcode() != ARMISD::RET_FLAG)
1769 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1770 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1771 // one of the above mentioned nodes. It has to be wrapped because otherwise
1772 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1773 // be used to form addressing mode. These wrapped nodes will be selected
1775 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1776 EVT PtrVT = Op.getValueType();
1777 // FIXME there is no actual debug info here
1778 DebugLoc dl = Op.getDebugLoc();
1779 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1781 if (CP->isMachineConstantPoolEntry())
1782 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1783 CP->getAlignment());
1785 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1786 CP->getAlignment());
1787 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1790 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1791 return MachineJumpTableInfo::EK_Inline;
1794 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1795 SelectionDAG &DAG) const {
1796 MachineFunction &MF = DAG.getMachineFunction();
1797 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1798 unsigned ARMPCLabelIndex = 0;
1799 DebugLoc DL = Op.getDebugLoc();
1800 EVT PtrVT = getPointerTy();
1801 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1802 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1804 if (RelocM == Reloc::Static) {
1805 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1807 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1808 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1809 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1810 ARMCP::CPBlockAddress,
1812 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1814 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1815 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1816 MachinePointerInfo::getConstantPool(),
1818 if (RelocM == Reloc::Static)
1820 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1821 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1824 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1826 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1827 SelectionDAG &DAG) const {
1828 DebugLoc dl = GA->getDebugLoc();
1829 EVT PtrVT = getPointerTy();
1830 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1831 MachineFunction &MF = DAG.getMachineFunction();
1832 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1833 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1834 ARMConstantPoolValue *CPV =
1835 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1836 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1837 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1838 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1839 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1840 MachinePointerInfo::getConstantPool(),
1842 SDValue Chain = Argument.getValue(1);
1844 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1845 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1847 // call __tls_get_addr.
1850 Entry.Node = Argument;
1851 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1852 Args.push_back(Entry);
1853 // FIXME: is there useful debug info available here?
1854 std::pair<SDValue, SDValue> CallResult =
1855 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1856 false, false, false, false,
1857 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1858 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1859 return CallResult.first;
1862 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1863 // "local exec" model.
1865 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1866 SelectionDAG &DAG) const {
1867 const GlobalValue *GV = GA->getGlobal();
1868 DebugLoc dl = GA->getDebugLoc();
1870 SDValue Chain = DAG.getEntryNode();
1871 EVT PtrVT = getPointerTy();
1872 // Get the Thread Pointer
1873 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1875 if (GV->isDeclaration()) {
1876 MachineFunction &MF = DAG.getMachineFunction();
1877 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1878 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1879 // Initial exec model.
1880 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1881 ARMConstantPoolValue *CPV =
1882 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1883 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1884 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1885 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1886 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1887 MachinePointerInfo::getConstantPool(),
1889 Chain = Offset.getValue(1);
1891 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1892 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1894 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1895 MachinePointerInfo::getConstantPool(),
1899 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1900 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1901 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1902 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1903 MachinePointerInfo::getConstantPool(),
1907 // The address of the thread local variable is the add of the thread
1908 // pointer with the offset of the variable.
1909 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1913 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1914 // TODO: implement the "local dynamic" model
1915 assert(Subtarget->isTargetELF() &&
1916 "TLS not implemented for non-ELF targets");
1917 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1918 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1919 // otherwise use the "Local Exec" TLS Model
1920 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1921 return LowerToTLSGeneralDynamicModel(GA, DAG);
1923 return LowerToTLSExecModels(GA, DAG);
1926 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1927 SelectionDAG &DAG) const {
1928 EVT PtrVT = getPointerTy();
1929 DebugLoc dl = Op.getDebugLoc();
1930 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1931 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1932 if (RelocM == Reloc::PIC_) {
1933 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1934 ARMConstantPoolValue *CPV =
1935 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1936 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1937 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1938 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1940 MachinePointerInfo::getConstantPool(),
1942 SDValue Chain = Result.getValue(1);
1943 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1944 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1946 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1947 MachinePointerInfo::getGOT(), false, false, 0);
1950 // If we have T2 ops, we can materialize the address directly via movt/movw
1951 // pair. This is always cheaper.
1952 if (Subtarget->useMovt()) {
1953 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1954 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1956 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1957 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1958 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1959 MachinePointerInfo::getConstantPool(),
1965 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1966 SelectionDAG &DAG) const {
1967 MachineFunction &MF = DAG.getMachineFunction();
1968 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1969 unsigned ARMPCLabelIndex = 0;
1970 EVT PtrVT = getPointerTy();
1971 DebugLoc dl = Op.getDebugLoc();
1972 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1973 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1975 if (RelocM == Reloc::Static)
1976 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1978 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1979 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1980 ARMConstantPoolValue *CPV =
1981 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1982 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1984 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1986 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1987 MachinePointerInfo::getConstantPool(),
1989 SDValue Chain = Result.getValue(1);
1991 if (RelocM == Reloc::PIC_) {
1992 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1993 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1996 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1997 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2003 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2004 SelectionDAG &DAG) const {
2005 assert(Subtarget->isTargetELF() &&
2006 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2007 MachineFunction &MF = DAG.getMachineFunction();
2008 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2009 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2010 EVT PtrVT = getPointerTy();
2011 DebugLoc dl = Op.getDebugLoc();
2012 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2013 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2014 "_GLOBAL_OFFSET_TABLE_",
2015 ARMPCLabelIndex, PCAdj);
2016 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2017 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2018 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2019 MachinePointerInfo::getConstantPool(),
2021 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2022 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2026 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2028 DebugLoc dl = Op.getDebugLoc();
2029 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2030 Op.getOperand(0), Op.getOperand(1));
2034 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2035 DebugLoc dl = Op.getDebugLoc();
2036 SDValue Val = DAG.getConstant(0, MVT::i32);
2037 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2038 Op.getOperand(1), Val);
2042 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2043 DebugLoc dl = Op.getDebugLoc();
2044 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2045 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2049 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2050 const ARMSubtarget *Subtarget) const {
2051 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2052 DebugLoc dl = Op.getDebugLoc();
2054 default: return SDValue(); // Don't custom lower most intrinsics.
2055 case Intrinsic::arm_thread_pointer: {
2056 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2057 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2059 case Intrinsic::eh_sjlj_lsda: {
2060 MachineFunction &MF = DAG.getMachineFunction();
2061 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2062 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2063 EVT PtrVT = getPointerTy();
2064 DebugLoc dl = Op.getDebugLoc();
2065 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2067 unsigned PCAdj = (RelocM != Reloc::PIC_)
2068 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2069 ARMConstantPoolValue *CPV =
2070 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2071 ARMCP::CPLSDA, PCAdj);
2072 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2073 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2075 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2076 MachinePointerInfo::getConstantPool(),
2079 if (RelocM == Reloc::PIC_) {
2080 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2081 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2088 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2089 const ARMSubtarget *Subtarget) {
2090 DebugLoc dl = Op.getDebugLoc();
2091 if (!Subtarget->hasDataBarrier()) {
2092 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2093 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2095 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2096 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2097 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2098 DAG.getConstant(0, MVT::i32));
2101 SDValue Op5 = Op.getOperand(5);
2102 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2103 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2104 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2105 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2107 ARM_MB::MemBOpt DMBOpt;
2108 if (isDeviceBarrier)
2109 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2111 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2112 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2113 DAG.getConstant(DMBOpt, MVT::i32));
2116 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2117 const ARMSubtarget *Subtarget) {
2118 // ARM pre v5TE and Thumb1 does not have preload instructions.
2119 if (!(Subtarget->isThumb2() ||
2120 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2121 // Just preserve the chain.
2122 return Op.getOperand(0);
2124 DebugLoc dl = Op.getDebugLoc();
2125 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2127 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2128 // ARMv7 with MP extension has PLDW.
2129 return Op.getOperand(0);
2131 if (Subtarget->isThumb())
2133 isRead = ~isRead & 1;
2134 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2136 // Currently there is no intrinsic that matches pli.
2137 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2138 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2139 DAG.getConstant(isData, MVT::i32));
2142 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2143 MachineFunction &MF = DAG.getMachineFunction();
2144 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2146 // vastart just stores the address of the VarArgsFrameIndex slot into the
2147 // memory location argument.
2148 DebugLoc dl = Op.getDebugLoc();
2149 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2150 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2151 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2152 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2153 MachinePointerInfo(SV), false, false, 0);
2157 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2158 SDValue &Root, SelectionDAG &DAG,
2159 DebugLoc dl) const {
2160 MachineFunction &MF = DAG.getMachineFunction();
2161 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2163 TargetRegisterClass *RC;
2164 if (AFI->isThumb1OnlyFunction())
2165 RC = ARM::tGPRRegisterClass;
2167 RC = ARM::GPRRegisterClass;
2169 // Transform the arguments stored in physical registers into virtual ones.
2170 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2171 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2174 if (NextVA.isMemLoc()) {
2175 MachineFrameInfo *MFI = MF.getFrameInfo();
2176 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2178 // Create load node to retrieve arguments from the stack.
2179 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2180 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2181 MachinePointerInfo::getFixedStack(FI),
2184 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2185 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2188 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2192 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2193 CallingConv::ID CallConv, bool isVarArg,
2194 const SmallVectorImpl<ISD::InputArg>
2196 DebugLoc dl, SelectionDAG &DAG,
2197 SmallVectorImpl<SDValue> &InVals)
2200 MachineFunction &MF = DAG.getMachineFunction();
2201 MachineFrameInfo *MFI = MF.getFrameInfo();
2203 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2205 // Assign locations to all of the incoming arguments.
2206 SmallVector<CCValAssign, 16> ArgLocs;
2207 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2209 CCInfo.AnalyzeFormalArguments(Ins,
2210 CCAssignFnForNode(CallConv, /* Return*/ false,
2213 SmallVector<SDValue, 16> ArgValues;
2215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2216 CCValAssign &VA = ArgLocs[i];
2218 // Arguments stored in registers.
2219 if (VA.isRegLoc()) {
2220 EVT RegVT = VA.getLocVT();
2223 if (VA.needsCustom()) {
2224 // f64 and vector types are split up into multiple registers or
2225 // combinations of registers and stack slots.
2226 if (VA.getLocVT() == MVT::v2f64) {
2227 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2229 VA = ArgLocs[++i]; // skip ahead to next loc
2231 if (VA.isMemLoc()) {
2232 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2233 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2234 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2235 MachinePointerInfo::getFixedStack(FI),
2238 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2241 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2242 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2243 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2244 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2245 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2247 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2250 TargetRegisterClass *RC;
2252 if (RegVT == MVT::f32)
2253 RC = ARM::SPRRegisterClass;
2254 else if (RegVT == MVT::f64)
2255 RC = ARM::DPRRegisterClass;
2256 else if (RegVT == MVT::v2f64)
2257 RC = ARM::QPRRegisterClass;
2258 else if (RegVT == MVT::i32)
2259 RC = (AFI->isThumb1OnlyFunction() ?
2260 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2262 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2264 // Transform the arguments in physical registers into virtual ones.
2265 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2266 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2269 // If this is an 8 or 16-bit value, it is really passed promoted
2270 // to 32 bits. Insert an assert[sz]ext to capture this, then
2271 // truncate to the right size.
2272 switch (VA.getLocInfo()) {
2273 default: llvm_unreachable("Unknown loc info!");
2274 case CCValAssign::Full: break;
2275 case CCValAssign::BCvt:
2276 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2278 case CCValAssign::SExt:
2279 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2280 DAG.getValueType(VA.getValVT()));
2281 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2283 case CCValAssign::ZExt:
2284 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2285 DAG.getValueType(VA.getValVT()));
2286 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2290 InVals.push_back(ArgValue);
2292 } else { // VA.isRegLoc()
2295 assert(VA.isMemLoc());
2296 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2298 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2299 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2301 // Create load nodes to retrieve arguments from the stack.
2302 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2303 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2304 MachinePointerInfo::getFixedStack(FI),
2311 static const unsigned GPRArgRegs[] = {
2312 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2315 unsigned NumGPRs = CCInfo.getFirstUnallocated
2316 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2318 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2319 unsigned VARegSize = (4 - NumGPRs) * 4;
2320 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2321 unsigned ArgOffset = CCInfo.getNextStackOffset();
2322 if (VARegSaveSize) {
2323 // If this function is vararg, store any remaining integer argument regs
2324 // to their spots on the stack so that they may be loaded by deferencing
2325 // the result of va_next.
2326 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2327 AFI->setVarArgsFrameIndex(
2328 MFI->CreateFixedObject(VARegSaveSize,
2329 ArgOffset + VARegSaveSize - VARegSize,
2331 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2334 SmallVector<SDValue, 4> MemOps;
2335 for (; NumGPRs < 4; ++NumGPRs) {
2336 TargetRegisterClass *RC;
2337 if (AFI->isThumb1OnlyFunction())
2338 RC = ARM::tGPRRegisterClass;
2340 RC = ARM::GPRRegisterClass;
2342 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2343 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2345 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2346 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2348 MemOps.push_back(Store);
2349 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2350 DAG.getConstant(4, getPointerTy()));
2352 if (!MemOps.empty())
2353 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2354 &MemOps[0], MemOps.size());
2356 // This will point to the next argument passed via stack.
2357 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2363 /// isFloatingPointZero - Return true if this is +0.0.
2364 static bool isFloatingPointZero(SDValue Op) {
2365 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2366 return CFP->getValueAPF().isPosZero();
2367 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2368 // Maybe this has already been legalized into the constant pool?
2369 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2370 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2371 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2372 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2373 return CFP->getValueAPF().isPosZero();
2379 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2380 /// the given operands.
2382 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2383 SDValue &ARMcc, SelectionDAG &DAG,
2384 DebugLoc dl) const {
2385 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2386 unsigned C = RHSC->getZExtValue();
2387 if (!isLegalICmpImmediate(C)) {
2388 // Constant does not fit, try adjusting it by one?
2393 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2394 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2395 RHS = DAG.getConstant(C-1, MVT::i32);
2400 if (C != 0 && isLegalICmpImmediate(C-1)) {
2401 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2402 RHS = DAG.getConstant(C-1, MVT::i32);
2407 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2408 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2409 RHS = DAG.getConstant(C+1, MVT::i32);
2414 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2415 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2416 RHS = DAG.getConstant(C+1, MVT::i32);
2423 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2424 ARMISD::NodeType CompareType;
2427 CompareType = ARMISD::CMP;
2432 CompareType = ARMISD::CMPZ;
2435 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2436 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2439 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2441 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2442 DebugLoc dl) const {
2444 if (!isFloatingPointZero(RHS))
2445 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2447 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2448 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2451 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2452 SDValue Cond = Op.getOperand(0);
2453 SDValue SelectTrue = Op.getOperand(1);
2454 SDValue SelectFalse = Op.getOperand(2);
2455 DebugLoc dl = Op.getDebugLoc();
2459 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2460 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2462 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2463 const ConstantSDNode *CMOVTrue =
2464 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2465 const ConstantSDNode *CMOVFalse =
2466 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2468 if (CMOVTrue && CMOVFalse) {
2469 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2470 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2474 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2476 False = SelectFalse;
2477 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2482 if (True.getNode() && False.getNode()) {
2483 EVT VT = Cond.getValueType();
2484 SDValue ARMcc = Cond.getOperand(2);
2485 SDValue CCR = Cond.getOperand(3);
2486 SDValue Cmp = Cond.getOperand(4);
2487 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2492 return DAG.getSelectCC(dl, Cond,
2493 DAG.getConstant(0, Cond.getValueType()),
2494 SelectTrue, SelectFalse, ISD::SETNE);
2497 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2498 EVT VT = Op.getValueType();
2499 SDValue LHS = Op.getOperand(0);
2500 SDValue RHS = Op.getOperand(1);
2501 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2502 SDValue TrueVal = Op.getOperand(2);
2503 SDValue FalseVal = Op.getOperand(3);
2504 DebugLoc dl = Op.getDebugLoc();
2506 if (LHS.getValueType() == MVT::i32) {
2508 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2509 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2510 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2513 ARMCC::CondCodes CondCode, CondCode2;
2514 FPCCToARMCC(CC, CondCode, CondCode2);
2516 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2517 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2519 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2521 if (CondCode2 != ARMCC::AL) {
2522 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2523 // FIXME: Needs another CMP because flag can have but one use.
2524 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2525 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2526 Result, TrueVal, ARMcc2, CCR, Cmp2);
2531 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2532 /// to morph to an integer compare sequence.
2533 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2534 const ARMSubtarget *Subtarget) {
2535 SDNode *N = Op.getNode();
2536 if (!N->hasOneUse())
2537 // Otherwise it requires moving the value from fp to integer registers.
2539 if (!N->getNumValues())
2541 EVT VT = Op.getValueType();
2542 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2543 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2544 // vmrs are very slow, e.g. cortex-a8.
2547 if (isFloatingPointZero(Op)) {
2551 return ISD::isNormalLoad(N);
2554 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2555 if (isFloatingPointZero(Op))
2556 return DAG.getConstant(0, MVT::i32);
2558 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2559 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2560 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2561 Ld->isVolatile(), Ld->isNonTemporal(),
2562 Ld->getAlignment());
2564 llvm_unreachable("Unknown VFP cmp argument!");
2567 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2568 SDValue &RetVal1, SDValue &RetVal2) {
2569 if (isFloatingPointZero(Op)) {
2570 RetVal1 = DAG.getConstant(0, MVT::i32);
2571 RetVal2 = DAG.getConstant(0, MVT::i32);
2575 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2576 SDValue Ptr = Ld->getBasePtr();
2577 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2578 Ld->getChain(), Ptr,
2579 Ld->getPointerInfo(),
2580 Ld->isVolatile(), Ld->isNonTemporal(),
2581 Ld->getAlignment());
2583 EVT PtrType = Ptr.getValueType();
2584 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2585 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2586 PtrType, Ptr, DAG.getConstant(4, PtrType));
2587 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2588 Ld->getChain(), NewPtr,
2589 Ld->getPointerInfo().getWithOffset(4),
2590 Ld->isVolatile(), Ld->isNonTemporal(),
2595 llvm_unreachable("Unknown VFP cmp argument!");
2598 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2599 /// f32 and even f64 comparisons to integer ones.
2601 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2602 SDValue Chain = Op.getOperand(0);
2603 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2604 SDValue LHS = Op.getOperand(2);
2605 SDValue RHS = Op.getOperand(3);
2606 SDValue Dest = Op.getOperand(4);
2607 DebugLoc dl = Op.getDebugLoc();
2609 bool SeenZero = false;
2610 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2611 canChangeToInt(RHS, SeenZero, Subtarget) &&
2612 // If one of the operand is zero, it's safe to ignore the NaN case since
2613 // we only care about equality comparisons.
2614 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2615 // If unsafe fp math optimization is enabled and there are no othter uses of
2616 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2617 // to an integer comparison.
2618 if (CC == ISD::SETOEQ)
2620 else if (CC == ISD::SETUNE)
2624 if (LHS.getValueType() == MVT::f32) {
2625 LHS = bitcastf32Toi32(LHS, DAG);
2626 RHS = bitcastf32Toi32(RHS, DAG);
2627 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2628 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2629 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2630 Chain, Dest, ARMcc, CCR, Cmp);
2635 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2636 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2637 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2638 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2639 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2640 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2641 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2647 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2648 SDValue Chain = Op.getOperand(0);
2649 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2650 SDValue LHS = Op.getOperand(2);
2651 SDValue RHS = Op.getOperand(3);
2652 SDValue Dest = Op.getOperand(4);
2653 DebugLoc dl = Op.getDebugLoc();
2655 if (LHS.getValueType() == MVT::i32) {
2657 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2658 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2659 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2660 Chain, Dest, ARMcc, CCR, Cmp);
2663 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2666 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2667 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2668 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2669 if (Result.getNode())
2673 ARMCC::CondCodes CondCode, CondCode2;
2674 FPCCToARMCC(CC, CondCode, CondCode2);
2676 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2677 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2678 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2679 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2680 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2681 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2682 if (CondCode2 != ARMCC::AL) {
2683 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2684 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2685 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2690 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2691 SDValue Chain = Op.getOperand(0);
2692 SDValue Table = Op.getOperand(1);
2693 SDValue Index = Op.getOperand(2);
2694 DebugLoc dl = Op.getDebugLoc();
2696 EVT PTy = getPointerTy();
2697 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2698 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2699 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2700 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2701 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2702 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2703 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2704 if (Subtarget->isThumb2()) {
2705 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2706 // which does another jump to the destination. This also makes it easier
2707 // to translate it to TBB / TBH later.
2708 // FIXME: This might not work if the function is extremely large.
2709 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2710 Addr, Op.getOperand(2), JTI, UId);
2712 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2713 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2714 MachinePointerInfo::getJumpTable(),
2716 Chain = Addr.getValue(1);
2717 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2718 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2720 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2721 MachinePointerInfo::getJumpTable(), false, false, 0);
2722 Chain = Addr.getValue(1);
2723 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2727 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2728 DebugLoc dl = Op.getDebugLoc();
2731 switch (Op.getOpcode()) {
2733 assert(0 && "Invalid opcode!");
2734 case ISD::FP_TO_SINT:
2735 Opc = ARMISD::FTOSI;
2737 case ISD::FP_TO_UINT:
2738 Opc = ARMISD::FTOUI;
2741 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2742 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2745 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2746 EVT VT = Op.getValueType();
2747 DebugLoc dl = Op.getDebugLoc();
2750 switch (Op.getOpcode()) {
2752 assert(0 && "Invalid opcode!");
2753 case ISD::SINT_TO_FP:
2754 Opc = ARMISD::SITOF;
2756 case ISD::UINT_TO_FP:
2757 Opc = ARMISD::UITOF;
2761 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2762 return DAG.getNode(Opc, dl, VT, Op);
2765 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2766 // Implement fcopysign with a fabs and a conditional fneg.
2767 SDValue Tmp0 = Op.getOperand(0);
2768 SDValue Tmp1 = Op.getOperand(1);
2769 DebugLoc dl = Op.getDebugLoc();
2770 EVT VT = Op.getValueType();
2771 EVT SrcVT = Tmp1.getValueType();
2772 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2773 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2774 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2775 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2776 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2777 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2780 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2781 MachineFunction &MF = DAG.getMachineFunction();
2782 MachineFrameInfo *MFI = MF.getFrameInfo();
2783 MFI->setReturnAddressIsTaken(true);
2785 EVT VT = Op.getValueType();
2786 DebugLoc dl = Op.getDebugLoc();
2787 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2789 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2790 SDValue Offset = DAG.getConstant(4, MVT::i32);
2791 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2792 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2793 MachinePointerInfo(), false, false, 0);
2796 // Return LR, which contains the return address. Mark it an implicit live-in.
2797 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2798 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2801 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2802 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2803 MFI->setFrameAddressIsTaken(true);
2805 EVT VT = Op.getValueType();
2806 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2807 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2808 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2809 ? ARM::R7 : ARM::R11;
2810 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2812 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2813 MachinePointerInfo(),
2818 /// ExpandBITCAST - If the target supports VFP, this function is called to
2819 /// expand a bit convert where either the source or destination type is i64 to
2820 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2821 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2822 /// vectors), since the legalizer won't know what to do with that.
2823 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
2824 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2825 DebugLoc dl = N->getDebugLoc();
2826 SDValue Op = N->getOperand(0);
2828 // This function is only supposed to be called for i64 types, either as the
2829 // source or destination of the bit convert.
2830 EVT SrcVT = Op.getValueType();
2831 EVT DstVT = N->getValueType(0);
2832 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2833 "ExpandBITCAST called for non-i64 type");
2835 // Turn i64->f64 into VMOVDRR.
2836 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2837 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2838 DAG.getConstant(0, MVT::i32));
2839 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2840 DAG.getConstant(1, MVT::i32));
2841 return DAG.getNode(ISD::BITCAST, dl, DstVT,
2842 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2845 // Turn f64->i64 into VMOVRRD.
2846 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2847 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2848 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2849 // Merge the pieces into a single i64 value.
2850 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2856 /// getZeroVector - Returns a vector of specified type with all zero elements.
2857 /// Zero vectors are used to represent vector negation and in those cases
2858 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2859 /// not support i64 elements, so sometimes the zero vectors will need to be
2860 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2862 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2863 assert(VT.isVector() && "Expected a vector type");
2864 // The canonical modified immediate encoding of a zero vector is....0!
2865 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2866 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2867 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2868 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
2871 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2872 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2873 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2874 SelectionDAG &DAG) const {
2875 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2876 EVT VT = Op.getValueType();
2877 unsigned VTBits = VT.getSizeInBits();
2878 DebugLoc dl = Op.getDebugLoc();
2879 SDValue ShOpLo = Op.getOperand(0);
2880 SDValue ShOpHi = Op.getOperand(1);
2881 SDValue ShAmt = Op.getOperand(2);
2883 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2885 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2887 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2888 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2889 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2890 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2891 DAG.getConstant(VTBits, MVT::i32));
2892 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2893 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2894 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2896 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2897 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2899 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2900 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2903 SDValue Ops[2] = { Lo, Hi };
2904 return DAG.getMergeValues(Ops, 2, dl);
2907 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2908 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2909 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2910 SelectionDAG &DAG) const {
2911 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2912 EVT VT = Op.getValueType();
2913 unsigned VTBits = VT.getSizeInBits();
2914 DebugLoc dl = Op.getDebugLoc();
2915 SDValue ShOpLo = Op.getOperand(0);
2916 SDValue ShOpHi = Op.getOperand(1);
2917 SDValue ShAmt = Op.getOperand(2);
2920 assert(Op.getOpcode() == ISD::SHL_PARTS);
2921 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2922 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2923 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2924 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2925 DAG.getConstant(VTBits, MVT::i32));
2926 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2927 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2929 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2930 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2931 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2933 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2934 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2937 SDValue Ops[2] = { Lo, Hi };
2938 return DAG.getMergeValues(Ops, 2, dl);
2941 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2942 SelectionDAG &DAG) const {
2943 // The rounding mode is in bits 23:22 of the FPSCR.
2944 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2945 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2946 // so that the shift + and get folded into a bitfield extract.
2947 DebugLoc dl = Op.getDebugLoc();
2948 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2949 DAG.getConstant(Intrinsic::arm_get_fpscr,
2951 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2952 DAG.getConstant(1U << 22, MVT::i32));
2953 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2954 DAG.getConstant(22, MVT::i32));
2955 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2956 DAG.getConstant(3, MVT::i32));
2959 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2960 const ARMSubtarget *ST) {
2961 EVT VT = N->getValueType(0);
2962 DebugLoc dl = N->getDebugLoc();
2964 if (!ST->hasV6T2Ops())
2967 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2968 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2971 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2972 const ARMSubtarget *ST) {
2973 EVT VT = N->getValueType(0);
2974 DebugLoc dl = N->getDebugLoc();
2979 // Lower vector shifts on NEON to use VSHL.
2980 assert(ST->hasNEON() && "unexpected vector shift");
2982 // Left shifts translate directly to the vshiftu intrinsic.
2983 if (N->getOpcode() == ISD::SHL)
2984 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2985 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2986 N->getOperand(0), N->getOperand(1));
2988 assert((N->getOpcode() == ISD::SRA ||
2989 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2991 // NEON uses the same intrinsics for both left and right shifts. For
2992 // right shifts, the shift amounts are negative, so negate the vector of
2994 EVT ShiftVT = N->getOperand(1).getValueType();
2995 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2996 getZeroVector(ShiftVT, DAG, dl),
2998 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2999 Intrinsic::arm_neon_vshifts :
3000 Intrinsic::arm_neon_vshiftu);
3001 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3002 DAG.getConstant(vshiftInt, MVT::i32),
3003 N->getOperand(0), NegatedCount);
3006 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3007 const ARMSubtarget *ST) {
3008 EVT VT = N->getValueType(0);
3009 DebugLoc dl = N->getDebugLoc();
3011 // We can get here for a node like i32 = ISD::SHL i32, i64
3015 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3016 "Unknown shift to lower!");
3018 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3019 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3020 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3023 // If we are in thumb mode, we don't have RRX.
3024 if (ST->isThumb1Only()) return SDValue();
3026 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3027 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3028 DAG.getConstant(0, MVT::i32));
3029 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3030 DAG.getConstant(1, MVT::i32));
3032 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3033 // captures the result into a carry flag.
3034 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3035 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3037 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3038 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3040 // Merge the pieces into a single i64 value.
3041 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3044 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3045 SDValue TmpOp0, TmpOp1;
3046 bool Invert = false;
3050 SDValue Op0 = Op.getOperand(0);
3051 SDValue Op1 = Op.getOperand(1);
3052 SDValue CC = Op.getOperand(2);
3053 EVT VT = Op.getValueType();
3054 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3055 DebugLoc dl = Op.getDebugLoc();
3057 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3058 switch (SetCCOpcode) {
3059 default: llvm_unreachable("Illegal FP comparison"); break;
3061 case ISD::SETNE: Invert = true; // Fallthrough
3063 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3065 case ISD::SETLT: Swap = true; // Fallthrough
3067 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3069 case ISD::SETLE: Swap = true; // Fallthrough
3071 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3072 case ISD::SETUGE: Swap = true; // Fallthrough
3073 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3074 case ISD::SETUGT: Swap = true; // Fallthrough
3075 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3076 case ISD::SETUEQ: Invert = true; // Fallthrough
3078 // Expand this to (OLT | OGT).
3082 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3083 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3085 case ISD::SETUO: Invert = true; // Fallthrough
3087 // Expand this to (OLT | OGE).
3091 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3092 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3096 // Integer comparisons.
3097 switch (SetCCOpcode) {
3098 default: llvm_unreachable("Illegal integer comparison"); break;
3099 case ISD::SETNE: Invert = true;
3100 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3101 case ISD::SETLT: Swap = true;
3102 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3103 case ISD::SETLE: Swap = true;
3104 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3105 case ISD::SETULT: Swap = true;
3106 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3107 case ISD::SETULE: Swap = true;
3108 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3111 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3112 if (Opc == ARMISD::VCEQ) {
3115 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3117 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3120 // Ignore bitconvert.
3121 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3122 AndOp = AndOp.getOperand(0);
3124 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3126 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3127 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3134 std::swap(Op0, Op1);
3136 // If one of the operands is a constant vector zero, attempt to fold the
3137 // comparison to a specialized compare-against-zero form.
3139 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3141 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3142 if (Opc == ARMISD::VCGE)
3143 Opc = ARMISD::VCLEZ;
3144 else if (Opc == ARMISD::VCGT)
3145 Opc = ARMISD::VCLTZ;
3150 if (SingleOp.getNode()) {
3153 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3155 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3157 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3159 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3161 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3163 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3166 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3170 Result = DAG.getNOT(dl, Result, VT);
3175 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3176 /// valid vector constant for a NEON instruction with a "modified immediate"
3177 /// operand (e.g., VMOV). If so, return the encoded value.
3178 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3179 unsigned SplatBitSize, SelectionDAG &DAG,
3180 EVT &VT, bool is128Bits, NEONModImmType type) {
3181 unsigned OpCmode, Imm;
3183 // SplatBitSize is set to the smallest size that splats the vector, so a
3184 // zero vector will always have SplatBitSize == 8. However, NEON modified
3185 // immediate instructions others than VMOV do not support the 8-bit encoding
3186 // of a zero vector, and the default encoding of zero is supposed to be the
3191 switch (SplatBitSize) {
3193 if (type != VMOVModImm)
3195 // Any 1-byte value is OK. Op=0, Cmode=1110.
3196 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3199 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3203 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3204 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3205 if ((SplatBits & ~0xff) == 0) {
3206 // Value = 0x00nn: Op=x, Cmode=100x.
3211 if ((SplatBits & ~0xff00) == 0) {
3212 // Value = 0xnn00: Op=x, Cmode=101x.
3214 Imm = SplatBits >> 8;
3220 // NEON's 32-bit VMOV supports splat values where:
3221 // * only one byte is nonzero, or
3222 // * the least significant byte is 0xff and the second byte is nonzero, or
3223 // * the least significant 2 bytes are 0xff and the third is nonzero.
3224 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3225 if ((SplatBits & ~0xff) == 0) {
3226 // Value = 0x000000nn: Op=x, Cmode=000x.
3231 if ((SplatBits & ~0xff00) == 0) {
3232 // Value = 0x0000nn00: Op=x, Cmode=001x.
3234 Imm = SplatBits >> 8;
3237 if ((SplatBits & ~0xff0000) == 0) {
3238 // Value = 0x00nn0000: Op=x, Cmode=010x.
3240 Imm = SplatBits >> 16;
3243 if ((SplatBits & ~0xff000000) == 0) {
3244 // Value = 0xnn000000: Op=x, Cmode=011x.
3246 Imm = SplatBits >> 24;
3250 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3251 if (type == OtherModImm) return SDValue();
3253 if ((SplatBits & ~0xffff) == 0 &&
3254 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3255 // Value = 0x0000nnff: Op=x, Cmode=1100.
3257 Imm = SplatBits >> 8;
3262 if ((SplatBits & ~0xffffff) == 0 &&
3263 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3264 // Value = 0x00nnffff: Op=x, Cmode=1101.
3266 Imm = SplatBits >> 16;
3267 SplatBits |= 0xffff;
3271 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3272 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3273 // VMOV.I32. A (very) minor optimization would be to replicate the value
3274 // and fall through here to test for a valid 64-bit splat. But, then the
3275 // caller would also need to check and handle the change in size.
3279 if (type != VMOVModImm)
3281 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3282 uint64_t BitMask = 0xff;
3284 unsigned ImmMask = 1;
3286 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3287 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3290 } else if ((SplatBits & BitMask) != 0) {
3296 // Op=1, Cmode=1110.
3299 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3304 llvm_unreachable("unexpected size for isNEONModifiedImm");
3308 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3309 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3312 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3313 bool &ReverseVEXT, unsigned &Imm) {
3314 unsigned NumElts = VT.getVectorNumElements();
3315 ReverseVEXT = false;
3317 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3323 // If this is a VEXT shuffle, the immediate value is the index of the first
3324 // element. The other shuffle indices must be the successive elements after
3326 unsigned ExpectedElt = Imm;
3327 for (unsigned i = 1; i < NumElts; ++i) {
3328 // Increment the expected index. If it wraps around, it may still be
3329 // a VEXT but the source vectors must be swapped.
3331 if (ExpectedElt == NumElts * 2) {
3336 if (M[i] < 0) continue; // ignore UNDEF indices
3337 if (ExpectedElt != static_cast<unsigned>(M[i]))
3341 // Adjust the index value if the source operands will be swapped.
3348 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3349 /// instruction with the specified blocksize. (The order of the elements
3350 /// within each block of the vector is reversed.)
3351 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3352 unsigned BlockSize) {
3353 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3354 "Only possible block sizes for VREV are: 16, 32, 64");
3356 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3360 unsigned NumElts = VT.getVectorNumElements();
3361 unsigned BlockElts = M[0] + 1;
3362 // If the first shuffle index is UNDEF, be optimistic.
3364 BlockElts = BlockSize / EltSz;
3366 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3369 for (unsigned i = 0; i < NumElts; ++i) {
3370 if (M[i] < 0) continue; // ignore UNDEF indices
3371 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3378 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3379 unsigned &WhichResult) {
3380 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3384 unsigned NumElts = VT.getVectorNumElements();
3385 WhichResult = (M[0] == 0 ? 0 : 1);
3386 for (unsigned i = 0; i < NumElts; i += 2) {
3387 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3388 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3394 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3395 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3396 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3397 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3398 unsigned &WhichResult) {
3399 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3403 unsigned NumElts = VT.getVectorNumElements();
3404 WhichResult = (M[0] == 0 ? 0 : 1);
3405 for (unsigned i = 0; i < NumElts; i += 2) {
3406 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3407 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3413 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3414 unsigned &WhichResult) {
3415 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3419 unsigned NumElts = VT.getVectorNumElements();
3420 WhichResult = (M[0] == 0 ? 0 : 1);
3421 for (unsigned i = 0; i != NumElts; ++i) {
3422 if (M[i] < 0) continue; // ignore UNDEF indices
3423 if ((unsigned) M[i] != 2 * i + WhichResult)
3427 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3428 if (VT.is64BitVector() && EltSz == 32)
3434 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3435 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3436 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3437 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3438 unsigned &WhichResult) {
3439 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3443 unsigned Half = VT.getVectorNumElements() / 2;
3444 WhichResult = (M[0] == 0 ? 0 : 1);
3445 for (unsigned j = 0; j != 2; ++j) {
3446 unsigned Idx = WhichResult;
3447 for (unsigned i = 0; i != Half; ++i) {
3448 int MIdx = M[i + j * Half];
3449 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3455 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3456 if (VT.is64BitVector() && EltSz == 32)
3462 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3463 unsigned &WhichResult) {
3464 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3468 unsigned NumElts = VT.getVectorNumElements();
3469 WhichResult = (M[0] == 0 ? 0 : 1);
3470 unsigned Idx = WhichResult * NumElts / 2;
3471 for (unsigned i = 0; i != NumElts; i += 2) {
3472 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3473 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3478 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3479 if (VT.is64BitVector() && EltSz == 32)
3485 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3486 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3487 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3488 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3489 unsigned &WhichResult) {
3490 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3494 unsigned NumElts = VT.getVectorNumElements();
3495 WhichResult = (M[0] == 0 ? 0 : 1);
3496 unsigned Idx = WhichResult * NumElts / 2;
3497 for (unsigned i = 0; i != NumElts; i += 2) {
3498 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3499 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3504 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3505 if (VT.is64BitVector() && EltSz == 32)
3511 // If N is an integer constant that can be moved into a register in one
3512 // instruction, return an SDValue of such a constant (will become a MOV
3513 // instruction). Otherwise return null.
3514 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3515 const ARMSubtarget *ST, DebugLoc dl) {
3517 if (!isa<ConstantSDNode>(N))
3519 Val = cast<ConstantSDNode>(N)->getZExtValue();
3521 if (ST->isThumb1Only()) {
3522 if (Val <= 255 || ~Val <= 255)
3523 return DAG.getConstant(Val, MVT::i32);
3525 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3526 return DAG.getConstant(Val, MVT::i32);
3531 // If this is a case we can't handle, return null and let the default
3532 // expansion code take care of it.
3533 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3534 const ARMSubtarget *ST) const {
3535 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3536 DebugLoc dl = Op.getDebugLoc();
3537 EVT VT = Op.getValueType();
3539 APInt SplatBits, SplatUndef;
3540 unsigned SplatBitSize;
3542 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3543 if (SplatBitSize <= 64) {
3544 // Check if an immediate VMOV works.
3546 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3547 SplatUndef.getZExtValue(), SplatBitSize,
3548 DAG, VmovVT, VT.is128BitVector(),
3550 if (Val.getNode()) {
3551 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3552 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3555 // Try an immediate VMVN.
3556 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3557 ((1LL << SplatBitSize) - 1));
3558 Val = isNEONModifiedImm(NegatedImm,
3559 SplatUndef.getZExtValue(), SplatBitSize,
3560 DAG, VmovVT, VT.is128BitVector(),
3562 if (Val.getNode()) {
3563 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3564 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3569 // Scan through the operands to see if only one value is used.
3570 unsigned NumElts = VT.getVectorNumElements();
3571 bool isOnlyLowElement = true;
3572 bool usesOnlyOneValue = true;
3573 bool isConstant = true;
3575 for (unsigned i = 0; i < NumElts; ++i) {
3576 SDValue V = Op.getOperand(i);
3577 if (V.getOpcode() == ISD::UNDEF)
3580 isOnlyLowElement = false;
3581 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3584 if (!Value.getNode())
3586 else if (V != Value)
3587 usesOnlyOneValue = false;
3590 if (!Value.getNode())
3591 return DAG.getUNDEF(VT);
3593 if (isOnlyLowElement)
3594 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3596 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3598 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3599 // i32 and try again.
3600 if (usesOnlyOneValue && EltSize <= 32) {
3602 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3603 if (VT.getVectorElementType().isFloatingPoint()) {
3604 SmallVector<SDValue, 8> Ops;
3605 for (unsigned i = 0; i < NumElts; ++i)
3606 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3608 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3609 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3610 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3612 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3614 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3616 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3619 // If all elements are constants and the case above didn't get hit, fall back
3620 // to the default expansion, which will generate a load from the constant
3625 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3627 SDValue shuffle = ReconstructShuffle(Op, DAG);
3628 if (shuffle != SDValue())
3632 // Vectors with 32- or 64-bit elements can be built by directly assigning
3633 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3634 // will be legalized.
3635 if (EltSize >= 32) {
3636 // Do the expansion with floating-point types, since that is what the VFP
3637 // registers are defined to use, and since i64 is not legal.
3638 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3639 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3640 SmallVector<SDValue, 8> Ops;
3641 for (unsigned i = 0; i < NumElts; ++i)
3642 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3643 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3644 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3650 // Gather data to see if the operation can be modelled as a
3651 // shuffle in combination with VEXTs.
3652 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const {
3653 DebugLoc dl = Op.getDebugLoc();
3654 EVT VT = Op.getValueType();
3655 unsigned NumElts = VT.getVectorNumElements();
3657 SmallVector<SDValue, 2> SourceVecs;
3658 SmallVector<unsigned, 2> MinElts;
3659 SmallVector<unsigned, 2> MaxElts;
3661 for (unsigned i = 0; i < NumElts; ++i) {
3662 SDValue V = Op.getOperand(i);
3663 if (V.getOpcode() == ISD::UNDEF)
3665 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3666 // A shuffle can only come from building a vector from various
3667 // elements of other vectors.
3671 // Record this extraction against the appropriate vector if possible...
3672 SDValue SourceVec = V.getOperand(0);
3673 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
3674 bool FoundSource = false;
3675 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
3676 if (SourceVecs[j] == SourceVec) {
3677 if (MinElts[j] > EltNo)
3679 if (MaxElts[j] < EltNo)
3686 // Or record a new source if not...
3688 SourceVecs.push_back(SourceVec);
3689 MinElts.push_back(EltNo);
3690 MaxElts.push_back(EltNo);
3694 // Currently only do something sane when at most two source vectors
3696 if (SourceVecs.size() > 2)
3699 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
3700 int VEXTOffsets[2] = {0, 0};
3702 // This loop extracts the usage patterns of the source vectors
3703 // and prepares appropriate SDValues for a shuffle if possible.
3704 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
3705 if (SourceVecs[i].getValueType() == VT) {
3706 // No VEXT necessary
3707 ShuffleSrcs[i] = SourceVecs[i];
3710 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
3711 // It probably isn't worth padding out a smaller vector just to
3712 // break it down again in a shuffle.
3716 // Since only 64-bit and 128-bit vectors are legal on ARM and
3717 // we've eliminated the other cases...
3718 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts);
3720 if (MaxElts[i] - MinElts[i] >= NumElts) {
3721 // Span too large for a VEXT to cope
3725 if (MinElts[i] >= NumElts) {
3726 // The extraction can just take the second half
3727 VEXTOffsets[i] = NumElts;
3728 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
3729 DAG.getIntPtrConstant(NumElts));
3730 } else if (MaxElts[i] < NumElts) {
3731 // The extraction can just take the first half
3733 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
3734 DAG.getIntPtrConstant(0));
3736 // An actual VEXT is needed
3737 VEXTOffsets[i] = MinElts[i];
3738 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
3739 DAG.getIntPtrConstant(0));
3740 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
3741 DAG.getIntPtrConstant(NumElts));
3742 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
3743 DAG.getConstant(VEXTOffsets[i], MVT::i32));
3747 SmallVector<int, 8> Mask;
3749 for (unsigned i = 0; i < NumElts; ++i) {
3750 SDValue Entry = Op.getOperand(i);
3751 if (Entry.getOpcode() == ISD::UNDEF) {
3756 SDValue ExtractVec = Entry.getOperand(0);
3757 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
3758 if (ExtractVec == SourceVecs[0]) {
3759 Mask.push_back(ExtractElt - VEXTOffsets[0]);
3761 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
3765 // Final check before we try to produce nonsense...
3766 if (isShuffleMaskLegal(Mask, VT))
3767 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], &Mask[0]);
3772 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3773 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3774 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3775 /// are assumed to be legal.
3777 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3779 if (VT.getVectorNumElements() == 4 &&
3780 (VT.is128BitVector() || VT.is64BitVector())) {
3781 unsigned PFIndexes[4];
3782 for (unsigned i = 0; i != 4; ++i) {
3786 PFIndexes[i] = M[i];
3789 // Compute the index in the perfect shuffle table.
3790 unsigned PFTableIndex =
3791 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3792 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3793 unsigned Cost = (PFEntry >> 30);
3800 unsigned Imm, WhichResult;
3802 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3803 return (EltSize >= 32 ||
3804 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3805 isVREVMask(M, VT, 64) ||
3806 isVREVMask(M, VT, 32) ||
3807 isVREVMask(M, VT, 16) ||
3808 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3809 isVTRNMask(M, VT, WhichResult) ||
3810 isVUZPMask(M, VT, WhichResult) ||
3811 isVZIPMask(M, VT, WhichResult) ||
3812 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3813 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3814 isVZIP_v_undef_Mask(M, VT, WhichResult));
3817 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3818 /// the specified operations to build the shuffle.
3819 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3820 SDValue RHS, SelectionDAG &DAG,
3822 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3823 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3824 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3827 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3836 OP_VUZPL, // VUZP, left result
3837 OP_VUZPR, // VUZP, right result
3838 OP_VZIPL, // VZIP, left result
3839 OP_VZIPR, // VZIP, right result
3840 OP_VTRNL, // VTRN, left result
3841 OP_VTRNR // VTRN, right result
3844 if (OpNum == OP_COPY) {
3845 if (LHSID == (1*9+2)*9+3) return LHS;
3846 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3850 SDValue OpLHS, OpRHS;
3851 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3852 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3853 EVT VT = OpLHS.getValueType();
3856 default: llvm_unreachable("Unknown shuffle opcode!");
3858 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3863 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3864 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3868 return DAG.getNode(ARMISD::VEXT, dl, VT,
3870 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3873 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3874 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3877 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3878 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3881 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3882 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3886 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3887 SDValue V1 = Op.getOperand(0);
3888 SDValue V2 = Op.getOperand(1);
3889 DebugLoc dl = Op.getDebugLoc();
3890 EVT VT = Op.getValueType();
3891 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3892 SmallVector<int, 8> ShuffleMask;
3894 // Convert shuffles that are directly supported on NEON to target-specific
3895 // DAG nodes, instead of keeping them as shuffles and matching them again
3896 // during code selection. This is more efficient and avoids the possibility
3897 // of inconsistencies between legalization and selection.
3898 // FIXME: floating-point vectors should be canonicalized to integer vectors
3899 // of the same time so that they get CSEd properly.
3900 SVN->getMask(ShuffleMask);
3902 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3903 if (EltSize <= 32) {
3904 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3905 int Lane = SVN->getSplatIndex();
3906 // If this is undef splat, generate it via "just" vdup, if possible.
3907 if (Lane == -1) Lane = 0;
3909 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3910 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3912 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3913 DAG.getConstant(Lane, MVT::i32));
3918 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3921 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3922 DAG.getConstant(Imm, MVT::i32));
3925 if (isVREVMask(ShuffleMask, VT, 64))
3926 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3927 if (isVREVMask(ShuffleMask, VT, 32))
3928 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3929 if (isVREVMask(ShuffleMask, VT, 16))
3930 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3932 // Check for Neon shuffles that modify both input vectors in place.
3933 // If both results are used, i.e., if there are two shuffles with the same
3934 // source operands and with masks corresponding to both results of one of
3935 // these operations, DAG memoization will ensure that a single node is
3936 // used for both shuffles.
3937 unsigned WhichResult;
3938 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3939 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3940 V1, V2).getValue(WhichResult);
3941 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3942 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3943 V1, V2).getValue(WhichResult);
3944 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3945 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3946 V1, V2).getValue(WhichResult);
3948 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3949 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3950 V1, V1).getValue(WhichResult);
3951 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3952 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3953 V1, V1).getValue(WhichResult);
3954 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3955 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3956 V1, V1).getValue(WhichResult);
3959 // If the shuffle is not directly supported and it has 4 elements, use
3960 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3961 unsigned NumElts = VT.getVectorNumElements();
3963 unsigned PFIndexes[4];
3964 for (unsigned i = 0; i != 4; ++i) {
3965 if (ShuffleMask[i] < 0)
3968 PFIndexes[i] = ShuffleMask[i];
3971 // Compute the index in the perfect shuffle table.
3972 unsigned PFTableIndex =
3973 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3974 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3975 unsigned Cost = (PFEntry >> 30);
3978 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3981 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3982 if (EltSize >= 32) {
3983 // Do the expansion with floating-point types, since that is what the VFP
3984 // registers are defined to use, and since i64 is not legal.
3985 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3986 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3987 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
3988 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
3989 SmallVector<SDValue, 8> Ops;
3990 for (unsigned i = 0; i < NumElts; ++i) {
3991 if (ShuffleMask[i] < 0)
3992 Ops.push_back(DAG.getUNDEF(EltVT));
3994 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3995 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3996 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3999 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4000 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4006 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4007 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4008 SDValue Lane = Op.getOperand(1);
4009 if (!isa<ConstantSDNode>(Lane))
4012 SDValue Vec = Op.getOperand(0);
4013 if (Op.getValueType() == MVT::i32 &&
4014 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4015 DebugLoc dl = Op.getDebugLoc();
4016 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4022 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4023 // The only time a CONCAT_VECTORS operation can have legal types is when
4024 // two 64-bit vectors are concatenated to a 128-bit vector.
4025 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4026 "unexpected CONCAT_VECTORS");
4027 DebugLoc dl = Op.getDebugLoc();
4028 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4029 SDValue Op0 = Op.getOperand(0);
4030 SDValue Op1 = Op.getOperand(1);
4031 if (Op0.getOpcode() != ISD::UNDEF)
4032 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4033 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4034 DAG.getIntPtrConstant(0));
4035 if (Op1.getOpcode() != ISD::UNDEF)
4036 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4037 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4038 DAG.getIntPtrConstant(1));
4039 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4042 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4043 /// element has been zero/sign-extended, depending on the isSigned parameter,
4044 /// from an integer type half its size.
4045 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4047 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4048 EVT VT = N->getValueType(0);
4049 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4050 SDNode *BVN = N->getOperand(0).getNode();
4051 if (BVN->getValueType(0) != MVT::v4i32 ||
4052 BVN->getOpcode() != ISD::BUILD_VECTOR)
4054 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4055 unsigned HiElt = 1 - LoElt;
4056 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4057 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4058 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4059 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4060 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4063 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4064 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4067 if (Hi0->isNullValue() && Hi1->isNullValue())
4073 if (N->getOpcode() != ISD::BUILD_VECTOR)
4076 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4077 SDNode *Elt = N->getOperand(i).getNode();
4078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4079 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4080 unsigned HalfSize = EltSize / 2;
4082 int64_t SExtVal = C->getSExtValue();
4083 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4086 if ((C->getZExtValue() >> HalfSize) != 0)
4097 /// isSignExtended - Check if a node is a vector value that is sign-extended
4098 /// or a constant BUILD_VECTOR with sign-extended elements.
4099 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4100 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4102 if (isExtendedBUILD_VECTOR(N, DAG, true))
4107 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4108 /// or a constant BUILD_VECTOR with zero-extended elements.
4109 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4110 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4112 if (isExtendedBUILD_VECTOR(N, DAG, false))
4117 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4118 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4119 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4120 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4121 return N->getOperand(0);
4122 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4123 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4124 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4125 LD->isNonTemporal(), LD->getAlignment());
4126 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4127 // have been legalized as a BITCAST from v4i32.
4128 if (N->getOpcode() == ISD::BITCAST) {
4129 SDNode *BVN = N->getOperand(0).getNode();
4130 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4131 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4132 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4133 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4134 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4136 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4137 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4138 EVT VT = N->getValueType(0);
4139 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4140 unsigned NumElts = VT.getVectorNumElements();
4141 MVT TruncVT = MVT::getIntegerVT(EltSize);
4142 SmallVector<SDValue, 8> Ops;
4143 for (unsigned i = 0; i != NumElts; ++i) {
4144 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4145 const APInt &CInt = C->getAPIntValue();
4146 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4148 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4149 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4152 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4153 // Multiplications are only custom-lowered for 128-bit vectors so that
4154 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4155 EVT VT = Op.getValueType();
4156 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4157 SDNode *N0 = Op.getOperand(0).getNode();
4158 SDNode *N1 = Op.getOperand(1).getNode();
4159 unsigned NewOpc = 0;
4160 if (isSignExtended(N0, DAG) && isSignExtended(N1, DAG))
4161 NewOpc = ARMISD::VMULLs;
4162 else if (isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG))
4163 NewOpc = ARMISD::VMULLu;
4164 else if (VT == MVT::v2i64)
4165 // Fall through to expand this. It is not legal.
4168 // Other vector multiplications are legal.
4171 // Legalize to a VMULL instruction.
4172 DebugLoc DL = Op.getDebugLoc();
4173 SDValue Op0 = SkipExtension(N0, DAG);
4174 SDValue Op1 = SkipExtension(N1, DAG);
4176 assert(Op0.getValueType().is64BitVector() &&
4177 Op1.getValueType().is64BitVector() &&
4178 "unexpected types for extended operands to VMULL");
4179 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4182 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4183 switch (Op.getOpcode()) {
4184 default: llvm_unreachable("Don't know how to custom lower this!");
4185 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4186 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4187 case ISD::GlobalAddress:
4188 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4189 LowerGlobalAddressELF(Op, DAG);
4190 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4191 case ISD::SELECT: return LowerSELECT(Op, DAG);
4192 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4193 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4194 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4195 case ISD::VASTART: return LowerVASTART(Op, DAG);
4196 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4197 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4198 case ISD::SINT_TO_FP:
4199 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4200 case ISD::FP_TO_SINT:
4201 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4202 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4203 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4204 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4205 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4206 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4207 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4208 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4209 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4211 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4214 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4215 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4216 case ISD::SRL_PARTS:
4217 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4218 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4219 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4220 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4221 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4222 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4223 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4224 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4225 case ISD::MUL: return LowerMUL(Op, DAG);
4230 /// ReplaceNodeResults - Replace the results of node with an illegal result
4231 /// type with new values built out of custom code.
4232 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4233 SmallVectorImpl<SDValue>&Results,
4234 SelectionDAG &DAG) const {
4236 switch (N->getOpcode()) {
4238 llvm_unreachable("Don't know how to custom expand this!");
4241 Res = ExpandBITCAST(N, DAG);
4245 Res = Expand64BitShift(N, DAG, Subtarget);
4249 Results.push_back(Res);
4252 //===----------------------------------------------------------------------===//
4253 // ARM Scheduler Hooks
4254 //===----------------------------------------------------------------------===//
4257 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4258 MachineBasicBlock *BB,
4259 unsigned Size) const {
4260 unsigned dest = MI->getOperand(0).getReg();
4261 unsigned ptr = MI->getOperand(1).getReg();
4262 unsigned oldval = MI->getOperand(2).getReg();
4263 unsigned newval = MI->getOperand(3).getReg();
4264 unsigned scratch = BB->getParent()->getRegInfo()
4265 .createVirtualRegister(ARM::GPRRegisterClass);
4266 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4267 DebugLoc dl = MI->getDebugLoc();
4268 bool isThumb2 = Subtarget->isThumb2();
4270 unsigned ldrOpc, strOpc;
4272 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4274 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4275 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
4278 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4279 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4282 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4283 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4287 MachineFunction *MF = BB->getParent();
4288 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4289 MachineFunction::iterator It = BB;
4290 ++It; // insert the new blocks after the current block
4292 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4293 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4294 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4295 MF->insert(It, loop1MBB);
4296 MF->insert(It, loop2MBB);
4297 MF->insert(It, exitMBB);
4299 // Transfer the remainder of BB and its successor edges to exitMBB.
4300 exitMBB->splice(exitMBB->begin(), BB,
4301 llvm::next(MachineBasicBlock::iterator(MI)),
4303 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4307 // fallthrough --> loop1MBB
4308 BB->addSuccessor(loop1MBB);
4311 // ldrex dest, [ptr]
4315 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4316 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4317 .addReg(dest).addReg(oldval));
4318 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4319 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4320 BB->addSuccessor(loop2MBB);
4321 BB->addSuccessor(exitMBB);
4324 // strex scratch, newval, [ptr]
4328 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4330 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4331 .addReg(scratch).addImm(0));
4332 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4333 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4334 BB->addSuccessor(loop1MBB);
4335 BB->addSuccessor(exitMBB);
4341 MI->eraseFromParent(); // The instruction is gone now.
4347 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4348 unsigned Size, unsigned BinOpcode) const {
4349 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4350 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4352 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4353 MachineFunction *MF = BB->getParent();
4354 MachineFunction::iterator It = BB;
4357 unsigned dest = MI->getOperand(0).getReg();
4358 unsigned ptr = MI->getOperand(1).getReg();
4359 unsigned incr = MI->getOperand(2).getReg();
4360 DebugLoc dl = MI->getDebugLoc();
4362 bool isThumb2 = Subtarget->isThumb2();
4363 unsigned ldrOpc, strOpc;
4365 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4367 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4368 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4371 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4372 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4375 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4376 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4380 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4381 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4382 MF->insert(It, loopMBB);
4383 MF->insert(It, exitMBB);
4385 // Transfer the remainder of BB and its successor edges to exitMBB.
4386 exitMBB->splice(exitMBB->begin(), BB,
4387 llvm::next(MachineBasicBlock::iterator(MI)),
4389 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4391 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4392 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4393 unsigned scratch2 = (!BinOpcode) ? incr :
4394 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4398 // fallthrough --> loopMBB
4399 BB->addSuccessor(loopMBB);
4403 // <binop> scratch2, dest, incr
4404 // strex scratch, scratch2, ptr
4407 // fallthrough --> exitMBB
4409 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4411 // operand order needs to go the other way for NAND
4412 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4413 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4414 addReg(incr).addReg(dest)).addReg(0);
4416 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4417 addReg(dest).addReg(incr)).addReg(0);
4420 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4422 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4423 .addReg(scratch).addImm(0));
4424 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4425 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4427 BB->addSuccessor(loopMBB);
4428 BB->addSuccessor(exitMBB);
4434 MI->eraseFromParent(); // The instruction is gone now.
4440 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4441 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4442 E = MBB->succ_end(); I != E; ++I)
4445 llvm_unreachable("Expecting a BB with two successors!");
4449 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4450 MachineBasicBlock *BB) const {
4451 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4452 DebugLoc dl = MI->getDebugLoc();
4453 bool isThumb2 = Subtarget->isThumb2();
4454 switch (MI->getOpcode()) {
4457 llvm_unreachable("Unexpected instr type to insert");
4459 case ARM::ATOMIC_LOAD_ADD_I8:
4460 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4461 case ARM::ATOMIC_LOAD_ADD_I16:
4462 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4463 case ARM::ATOMIC_LOAD_ADD_I32:
4464 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4466 case ARM::ATOMIC_LOAD_AND_I8:
4467 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4468 case ARM::ATOMIC_LOAD_AND_I16:
4469 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4470 case ARM::ATOMIC_LOAD_AND_I32:
4471 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4473 case ARM::ATOMIC_LOAD_OR_I8:
4474 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4475 case ARM::ATOMIC_LOAD_OR_I16:
4476 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4477 case ARM::ATOMIC_LOAD_OR_I32:
4478 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4480 case ARM::ATOMIC_LOAD_XOR_I8:
4481 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4482 case ARM::ATOMIC_LOAD_XOR_I16:
4483 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4484 case ARM::ATOMIC_LOAD_XOR_I32:
4485 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4487 case ARM::ATOMIC_LOAD_NAND_I8:
4488 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4489 case ARM::ATOMIC_LOAD_NAND_I16:
4490 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4491 case ARM::ATOMIC_LOAD_NAND_I32:
4492 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4494 case ARM::ATOMIC_LOAD_SUB_I8:
4495 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4496 case ARM::ATOMIC_LOAD_SUB_I16:
4497 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4498 case ARM::ATOMIC_LOAD_SUB_I32:
4499 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4501 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4502 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4503 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4505 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4506 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4507 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4509 case ARM::tMOVCCr_pseudo: {
4510 // To "insert" a SELECT_CC instruction, we actually have to insert the
4511 // diamond control-flow pattern. The incoming instruction knows the
4512 // destination vreg to set, the condition code register to branch on, the
4513 // true/false values to select between, and a branch opcode to use.
4514 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4515 MachineFunction::iterator It = BB;
4521 // cmpTY ccX, r1, r2
4523 // fallthrough --> copy0MBB
4524 MachineBasicBlock *thisMBB = BB;
4525 MachineFunction *F = BB->getParent();
4526 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4527 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4528 F->insert(It, copy0MBB);
4529 F->insert(It, sinkMBB);
4531 // Transfer the remainder of BB and its successor edges to sinkMBB.
4532 sinkMBB->splice(sinkMBB->begin(), BB,
4533 llvm::next(MachineBasicBlock::iterator(MI)),
4535 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4537 BB->addSuccessor(copy0MBB);
4538 BB->addSuccessor(sinkMBB);
4540 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4541 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4544 // %FalseValue = ...
4545 // # fallthrough to sinkMBB
4548 // Update machine-CFG edges
4549 BB->addSuccessor(sinkMBB);
4552 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4555 BuildMI(*BB, BB->begin(), dl,
4556 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4557 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4558 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4560 MI->eraseFromParent(); // The pseudo instruction is gone now.
4565 case ARM::BCCZi64: {
4566 // If there is an unconditional branch to the other successor, remove it.
4567 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
4569 // Compare both parts that make up the double comparison separately for
4571 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4573 unsigned LHS1 = MI->getOperand(1).getReg();
4574 unsigned LHS2 = MI->getOperand(2).getReg();
4576 AddDefaultPred(BuildMI(BB, dl,
4577 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4578 .addReg(LHS1).addImm(0));
4579 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4580 .addReg(LHS2).addImm(0)
4581 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4583 unsigned RHS1 = MI->getOperand(3).getReg();
4584 unsigned RHS2 = MI->getOperand(4).getReg();
4585 AddDefaultPred(BuildMI(BB, dl,
4586 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4587 .addReg(LHS1).addReg(RHS1));
4588 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4589 .addReg(LHS2).addReg(RHS2)
4590 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4593 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4594 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4595 if (MI->getOperand(0).getImm() == ARMCC::NE)
4596 std::swap(destMBB, exitMBB);
4598 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4599 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4600 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4603 MI->eraseFromParent(); // The pseudo instruction is gone now.
4609 //===----------------------------------------------------------------------===//
4610 // ARM Optimization Hooks
4611 //===----------------------------------------------------------------------===//
4614 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4615 TargetLowering::DAGCombinerInfo &DCI) {
4616 SelectionDAG &DAG = DCI.DAG;
4617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4618 EVT VT = N->getValueType(0);
4619 unsigned Opc = N->getOpcode();
4620 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4621 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4622 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4623 ISD::CondCode CC = ISD::SETCC_INVALID;
4626 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4628 SDValue CCOp = Slct.getOperand(0);
4629 if (CCOp.getOpcode() == ISD::SETCC)
4630 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4633 bool DoXform = false;
4635 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4638 if (LHS.getOpcode() == ISD::Constant &&
4639 cast<ConstantSDNode>(LHS)->isNullValue()) {
4641 } else if (CC != ISD::SETCC_INVALID &&
4642 RHS.getOpcode() == ISD::Constant &&
4643 cast<ConstantSDNode>(RHS)->isNullValue()) {
4644 std::swap(LHS, RHS);
4645 SDValue Op0 = Slct.getOperand(0);
4646 EVT OpVT = isSlctCC ? Op0.getValueType() :
4647 Op0.getOperand(0).getValueType();
4648 bool isInt = OpVT.isInteger();
4649 CC = ISD::getSetCCInverse(CC, isInt);
4651 if (!TLI.isCondCodeLegal(CC, OpVT))
4652 return SDValue(); // Inverse operator isn't legal.
4659 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4661 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4662 Slct.getOperand(0), Slct.getOperand(1), CC);
4663 SDValue CCOp = Slct.getOperand(0);
4665 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4666 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4667 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4668 CCOp, OtherOp, Result);
4673 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4674 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4675 /// called with the default operands, and if that fails, with commuted
4677 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4678 TargetLowering::DAGCombinerInfo &DCI) {
4679 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4680 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4681 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4682 if (Result.getNode()) return Result;
4687 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4689 static SDValue PerformADDCombine(SDNode *N,
4690 TargetLowering::DAGCombinerInfo &DCI) {
4691 SDValue N0 = N->getOperand(0);
4692 SDValue N1 = N->getOperand(1);
4694 // First try with the default operand order.
4695 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4696 if (Result.getNode())
4699 // If that didn't work, try again with the operands commuted.
4700 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4703 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4705 static SDValue PerformSUBCombine(SDNode *N,
4706 TargetLowering::DAGCombinerInfo &DCI) {
4707 SDValue N0 = N->getOperand(0);
4708 SDValue N1 = N->getOperand(1);
4710 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4711 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4712 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4713 if (Result.getNode()) return Result;
4719 static SDValue PerformMULCombine(SDNode *N,
4720 TargetLowering::DAGCombinerInfo &DCI,
4721 const ARMSubtarget *Subtarget) {
4722 SelectionDAG &DAG = DCI.DAG;
4724 if (Subtarget->isThumb1Only())
4727 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4730 EVT VT = N->getValueType(0);
4734 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4738 uint64_t MulAmt = C->getZExtValue();
4739 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4740 ShiftAmt = ShiftAmt & (32 - 1);
4741 SDValue V = N->getOperand(0);
4742 DebugLoc DL = N->getDebugLoc();
4745 MulAmt >>= ShiftAmt;
4746 if (isPowerOf2_32(MulAmt - 1)) {
4747 // (mul x, 2^N + 1) => (add (shl x, N), x)
4748 Res = DAG.getNode(ISD::ADD, DL, VT,
4749 V, DAG.getNode(ISD::SHL, DL, VT,
4750 V, DAG.getConstant(Log2_32(MulAmt-1),
4752 } else if (isPowerOf2_32(MulAmt + 1)) {
4753 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4754 Res = DAG.getNode(ISD::SUB, DL, VT,
4755 DAG.getNode(ISD::SHL, DL, VT,
4756 V, DAG.getConstant(Log2_32(MulAmt+1),
4763 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4764 DAG.getConstant(ShiftAmt, MVT::i32));
4766 // Do not add new nodes to DAG combiner worklist.
4767 DCI.CombineTo(N, Res, false);
4771 static SDValue PerformANDCombine(SDNode *N,
4772 TargetLowering::DAGCombinerInfo &DCI) {
4773 // Attempt to use immediate-form VBIC
4774 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4775 DebugLoc dl = N->getDebugLoc();
4776 EVT VT = N->getValueType(0);
4777 SelectionDAG &DAG = DCI.DAG;
4779 APInt SplatBits, SplatUndef;
4780 unsigned SplatBitSize;
4783 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4784 if (SplatBitSize <= 64) {
4786 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
4787 SplatUndef.getZExtValue(), SplatBitSize,
4788 DAG, VbicVT, VT.is128BitVector(),
4790 if (Val.getNode()) {
4792 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
4793 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
4794 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
4802 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4803 static SDValue PerformORCombine(SDNode *N,
4804 TargetLowering::DAGCombinerInfo &DCI,
4805 const ARMSubtarget *Subtarget) {
4806 // Attempt to use immediate-form VORR
4807 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4808 DebugLoc dl = N->getDebugLoc();
4809 EVT VT = N->getValueType(0);
4810 SelectionDAG &DAG = DCI.DAG;
4812 APInt SplatBits, SplatUndef;
4813 unsigned SplatBitSize;
4815 if (BVN && Subtarget->hasNEON() &&
4816 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4817 if (SplatBitSize <= 64) {
4819 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4820 SplatUndef.getZExtValue(), SplatBitSize,
4821 DAG, VorrVT, VT.is128BitVector(),
4823 if (Val.getNode()) {
4825 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
4826 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
4827 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
4832 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4835 // BFI is only available on V6T2+
4836 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4839 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4840 DebugLoc DL = N->getDebugLoc();
4841 // 1) or (and A, mask), val => ARMbfi A, val, mask
4842 // iff (val & mask) == val
4844 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4845 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4846 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4847 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4848 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4849 // (i.e., copy a bitfield value into another bitfield of the same width)
4850 if (N0.getOpcode() != ISD::AND)
4856 SDValue N00 = N0.getOperand(0);
4858 // The value and the mask need to be constants so we can verify this is
4859 // actually a bitfield set. If the mask is 0xffff, we can do better
4860 // via a movt instruction, so don't use BFI in that case.
4861 SDValue MaskOp = N0.getOperand(1);
4862 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
4865 unsigned Mask = MaskC->getZExtValue();
4869 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4872 unsigned Val = N1C->getZExtValue();
4873 if ((Val & ~Mask) != Val)
4876 if (ARM::isBitFieldInvertedMask(Mask)) {
4877 Val >>= CountTrailingZeros_32(~Mask);
4879 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
4880 DAG.getConstant(Val, MVT::i32),
4881 DAG.getConstant(Mask, MVT::i32));
4883 // Do not add new nodes to DAG combiner worklist.
4884 DCI.CombineTo(N, Res, false);
4887 } else if (N1.getOpcode() == ISD::AND) {
4888 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4889 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4892 unsigned Mask2 = N11C->getZExtValue();
4894 if (ARM::isBitFieldInvertedMask(Mask) &&
4895 ARM::isBitFieldInvertedMask(~Mask2) &&
4896 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4897 // The pack halfword instruction works better for masks that fit it,
4898 // so use that when it's available.
4899 if (Subtarget->hasT2ExtractPack() &&
4900 (Mask == 0xffff || Mask == 0xffff0000))
4903 unsigned lsb = CountTrailingZeros_32(Mask2);
4904 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4905 DAG.getConstant(lsb, MVT::i32));
4906 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
4907 DAG.getConstant(Mask, MVT::i32));
4908 // Do not add new nodes to DAG combiner worklist.
4909 DCI.CombineTo(N, Res, false);
4911 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4912 ARM::isBitFieldInvertedMask(Mask2) &&
4913 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4914 // The pack halfword instruction works better for masks that fit it,
4915 // so use that when it's available.
4916 if (Subtarget->hasT2ExtractPack() &&
4917 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4920 unsigned lsb = CountTrailingZeros_32(Mask);
4921 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
4922 DAG.getConstant(lsb, MVT::i32));
4923 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4924 DAG.getConstant(Mask2, MVT::i32));
4925 // Do not add new nodes to DAG combiner worklist.
4926 DCI.CombineTo(N, Res, false);
4931 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
4932 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
4933 ARM::isBitFieldInvertedMask(~Mask)) {
4934 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
4935 // where lsb(mask) == #shamt and masked bits of B are known zero.
4936 SDValue ShAmt = N00.getOperand(1);
4937 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4938 unsigned LSB = CountTrailingZeros_32(Mask);
4942 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
4943 DAG.getConstant(~Mask, MVT::i32));
4945 // Do not add new nodes to DAG combiner worklist.
4946 DCI.CombineTo(N, Res, false);
4952 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
4954 static SDValue PerformBFICombine(SDNode *N,
4955 TargetLowering::DAGCombinerInfo &DCI) {
4956 SDValue N1 = N->getOperand(1);
4957 if (N1.getOpcode() == ISD::AND) {
4958 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4961 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
4962 unsigned Mask2 = N11C->getZExtValue();
4963 if ((Mask & Mask2) == Mask2)
4964 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
4965 N->getOperand(0), N1.getOperand(0),
4971 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4972 /// ARMISD::VMOVRRD.
4973 static SDValue PerformVMOVRRDCombine(SDNode *N,
4974 TargetLowering::DAGCombinerInfo &DCI) {
4975 // vmovrrd(vmovdrr x, y) -> x,y
4976 SDValue InDouble = N->getOperand(0);
4977 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4978 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4982 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4983 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4984 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4985 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4986 SDValue Op0 = N->getOperand(0);
4987 SDValue Op1 = N->getOperand(1);
4988 if (Op0.getOpcode() == ISD::BITCAST)
4989 Op0 = Op0.getOperand(0);
4990 if (Op1.getOpcode() == ISD::BITCAST)
4991 Op1 = Op1.getOperand(0);
4992 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4993 Op0.getNode() == Op1.getNode() &&
4994 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4995 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
4996 N->getValueType(0), Op0.getOperand(0));
5000 /// PerformSTORECombine - Target-specific dag combine xforms for
5002 static SDValue PerformSTORECombine(SDNode *N,
5003 TargetLowering::DAGCombinerInfo &DCI) {
5004 // Bitcast an i64 store extracted from a vector to f64.
5005 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5006 StoreSDNode *St = cast<StoreSDNode>(N);
5007 SDValue StVal = St->getValue();
5008 if (!ISD::isNormalStore(St) || St->isVolatile() ||
5009 StVal.getValueType() != MVT::i64 ||
5010 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5013 SelectionDAG &DAG = DCI.DAG;
5014 DebugLoc dl = StVal.getDebugLoc();
5015 SDValue IntVec = StVal.getOperand(0);
5016 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5017 IntVec.getValueType().getVectorNumElements());
5018 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5019 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5020 Vec, StVal.getOperand(1));
5021 dl = N->getDebugLoc();
5022 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5023 // Make the DAGCombiner fold the bitcasts.
5024 DCI.AddToWorklist(Vec.getNode());
5025 DCI.AddToWorklist(ExtElt.getNode());
5026 DCI.AddToWorklist(V.getNode());
5027 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5028 St->getPointerInfo(), St->isVolatile(),
5029 St->isNonTemporal(), St->getAlignment(),
5033 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5034 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5035 /// i64 vector to have f64 elements, since the value can then be loaded
5036 /// directly into a VFP register.
5037 static bool hasNormalLoadOperand(SDNode *N) {
5038 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5039 for (unsigned i = 0; i < NumElts; ++i) {
5040 SDNode *Elt = N->getOperand(i).getNode();
5041 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5047 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5048 /// ISD::BUILD_VECTOR.
5049 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5050 TargetLowering::DAGCombinerInfo &DCI){
5051 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
5052 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
5053 // into a pair of GPRs, which is fine when the value is used as a scalar,
5054 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
5055 SelectionDAG &DAG = DCI.DAG;
5056 if (N->getNumOperands() == 2) {
5057 SDValue RV = PerformVMOVDRRCombine(N, DAG);
5062 // Load i64 elements as f64 values so that type legalization does not split
5063 // them up into i32 values.
5064 EVT VT = N->getValueType(0);
5065 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
5067 DebugLoc dl = N->getDebugLoc();
5068 SmallVector<SDValue, 8> Ops;
5069 unsigned NumElts = VT.getVectorNumElements();
5070 for (unsigned i = 0; i < NumElts; ++i) {
5071 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
5073 // Make the DAGCombiner fold the bitcast.
5074 DCI.AddToWorklist(V.getNode());
5076 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
5077 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
5078 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
5081 /// PerformInsertEltCombine - Target-specific dag combine xforms for
5082 /// ISD::INSERT_VECTOR_ELT.
5083 static SDValue PerformInsertEltCombine(SDNode *N,
5084 TargetLowering::DAGCombinerInfo &DCI) {
5085 // Bitcast an i64 load inserted into a vector to f64.
5086 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5087 EVT VT = N->getValueType(0);
5088 SDNode *Elt = N->getOperand(1).getNode();
5089 if (VT.getVectorElementType() != MVT::i64 ||
5090 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
5093 SelectionDAG &DAG = DCI.DAG;
5094 DebugLoc dl = N->getDebugLoc();
5095 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5096 VT.getVectorNumElements());
5097 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
5098 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
5099 // Make the DAGCombiner fold the bitcasts.
5100 DCI.AddToWorklist(Vec.getNode());
5101 DCI.AddToWorklist(V.getNode());
5102 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
5103 Vec, V, N->getOperand(2));
5104 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
5107 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
5108 /// ISD::VECTOR_SHUFFLE.
5109 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
5110 // The LLVM shufflevector instruction does not require the shuffle mask
5111 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
5112 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
5113 // operands do not match the mask length, they are extended by concatenating
5114 // them with undef vectors. That is probably the right thing for other
5115 // targets, but for NEON it is better to concatenate two double-register
5116 // size vector operands into a single quad-register size vector. Do that
5117 // transformation here:
5118 // shuffle(concat(v1, undef), concat(v2, undef)) ->
5119 // shuffle(concat(v1, v2), undef)
5120 SDValue Op0 = N->getOperand(0);
5121 SDValue Op1 = N->getOperand(1);
5122 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
5123 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
5124 Op0.getNumOperands() != 2 ||
5125 Op1.getNumOperands() != 2)
5127 SDValue Concat0Op1 = Op0.getOperand(1);
5128 SDValue Concat1Op1 = Op1.getOperand(1);
5129 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
5130 Concat1Op1.getOpcode() != ISD::UNDEF)
5132 // Skip the transformation if any of the types are illegal.
5133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5134 EVT VT = N->getValueType(0);
5135 if (!TLI.isTypeLegal(VT) ||
5136 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5137 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5140 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5141 Op0.getOperand(0), Op1.getOperand(0));
5142 // Translate the shuffle mask.
5143 SmallVector<int, 16> NewMask;
5144 unsigned NumElts = VT.getVectorNumElements();
5145 unsigned HalfElts = NumElts/2;
5146 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5147 for (unsigned n = 0; n < NumElts; ++n) {
5148 int MaskElt = SVN->getMaskElt(n);
5150 if (MaskElt < (int)HalfElts)
5152 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5153 NewElt = HalfElts + MaskElt - NumElts;
5154 NewMask.push_back(NewElt);
5156 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5157 DAG.getUNDEF(VT), NewMask.data());
5160 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
5161 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
5162 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
5164 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
5165 SelectionDAG &DAG = DCI.DAG;
5166 EVT VT = N->getValueType(0);
5167 // vldN-dup instructions only support 64-bit vectors for N > 1.
5168 if (!VT.is64BitVector())
5171 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
5172 SDNode *VLD = N->getOperand(0).getNode();
5173 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
5175 unsigned NumVecs = 0;
5176 unsigned NewOpc = 0;
5177 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
5178 if (IntNo == Intrinsic::arm_neon_vld2lane) {
5180 NewOpc = ARMISD::VLD2DUP;
5181 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
5183 NewOpc = ARMISD::VLD3DUP;
5184 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
5186 NewOpc = ARMISD::VLD4DUP;
5191 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
5192 // numbers match the load.
5193 unsigned VLDLaneNo =
5194 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
5195 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5197 // Ignore uses of the chain result.
5198 if (UI.getUse().getResNo() == NumVecs)
5201 if (User->getOpcode() != ARMISD::VDUPLANE ||
5202 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
5206 // Create the vldN-dup node.
5209 for (n = 0; n < NumVecs; ++n)
5211 Tys[n] = MVT::Other;
5212 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
5213 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
5214 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
5215 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
5216 Ops, 2, VLDMemInt->getMemoryVT(),
5217 VLDMemInt->getMemOperand());
5220 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5222 unsigned ResNo = UI.getUse().getResNo();
5223 // Ignore uses of the chain result.
5224 if (ResNo == NumVecs)
5227 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
5230 // Now the vldN-lane intrinsic is dead except for its chain result.
5231 // Update uses of the chain.
5232 std::vector<SDValue> VLDDupResults;
5233 for (unsigned n = 0; n < NumVecs; ++n)
5234 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
5235 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
5236 DCI.CombineTo(VLD, VLDDupResults);
5241 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
5242 /// ARMISD::VDUPLANE.
5243 static SDValue PerformVDUPLANECombine(SDNode *N,
5244 TargetLowering::DAGCombinerInfo &DCI) {
5245 SDValue Op = N->getOperand(0);
5247 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
5248 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
5249 if (CombineVLDDUP(N, DCI))
5250 return SDValue(N, 0);
5252 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
5253 // redundant. Ignore bit_converts for now; element sizes are checked below.
5254 while (Op.getOpcode() == ISD::BITCAST)
5255 Op = Op.getOperand(0);
5256 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
5259 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
5260 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
5261 // The canonical VMOV for a zero vector uses a 32-bit element size.
5262 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5264 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
5266 EVT VT = N->getValueType(0);
5267 if (EltSize > VT.getVectorElementType().getSizeInBits())
5270 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
5273 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5274 /// operand of a vector shift operation, where all the elements of the
5275 /// build_vector must have the same constant integer value.
5276 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5277 // Ignore bit_converts.
5278 while (Op.getOpcode() == ISD::BITCAST)
5279 Op = Op.getOperand(0);
5280 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5281 APInt SplatBits, SplatUndef;
5282 unsigned SplatBitSize;
5284 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5285 HasAnyUndefs, ElementBits) ||
5286 SplatBitSize > ElementBits)
5288 Cnt = SplatBits.getSExtValue();
5292 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5293 /// operand of a vector shift left operation. That value must be in the range:
5294 /// 0 <= Value < ElementBits for a left shift; or
5295 /// 0 <= Value <= ElementBits for a long left shift.
5296 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5297 assert(VT.isVector() && "vector shift count is not a vector type");
5298 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5299 if (! getVShiftImm(Op, ElementBits, Cnt))
5301 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
5304 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5305 /// operand of a vector shift right operation. For a shift opcode, the value
5306 /// is positive, but for an intrinsic the value count must be negative. The
5307 /// absolute value must be in the range:
5308 /// 1 <= |Value| <= ElementBits for a right shift; or
5309 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5310 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5312 assert(VT.isVector() && "vector shift count is not a vector type");
5313 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5314 if (! getVShiftImm(Op, ElementBits, Cnt))
5318 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
5321 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
5322 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
5323 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5326 // Don't do anything for most intrinsics.
5329 // Vector shifts: check for immediate versions and lower them.
5330 // Note: This is done during DAG combining instead of DAG legalizing because
5331 // the build_vectors for 64-bit vector element shift counts are generally
5332 // not legal, and it is hard to see their values after they get legalized to
5333 // loads from a constant pool.
5334 case Intrinsic::arm_neon_vshifts:
5335 case Intrinsic::arm_neon_vshiftu:
5336 case Intrinsic::arm_neon_vshiftls:
5337 case Intrinsic::arm_neon_vshiftlu:
5338 case Intrinsic::arm_neon_vshiftn:
5339 case Intrinsic::arm_neon_vrshifts:
5340 case Intrinsic::arm_neon_vrshiftu:
5341 case Intrinsic::arm_neon_vrshiftn:
5342 case Intrinsic::arm_neon_vqshifts:
5343 case Intrinsic::arm_neon_vqshiftu:
5344 case Intrinsic::arm_neon_vqshiftsu:
5345 case Intrinsic::arm_neon_vqshiftns:
5346 case Intrinsic::arm_neon_vqshiftnu:
5347 case Intrinsic::arm_neon_vqshiftnsu:
5348 case Intrinsic::arm_neon_vqrshiftns:
5349 case Intrinsic::arm_neon_vqrshiftnu:
5350 case Intrinsic::arm_neon_vqrshiftnsu: {
5351 EVT VT = N->getOperand(1).getValueType();
5353 unsigned VShiftOpc = 0;
5356 case Intrinsic::arm_neon_vshifts:
5357 case Intrinsic::arm_neon_vshiftu:
5358 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
5359 VShiftOpc = ARMISD::VSHL;
5362 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
5363 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
5364 ARMISD::VSHRs : ARMISD::VSHRu);
5369 case Intrinsic::arm_neon_vshiftls:
5370 case Intrinsic::arm_neon_vshiftlu:
5371 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
5373 llvm_unreachable("invalid shift count for vshll intrinsic");
5375 case Intrinsic::arm_neon_vrshifts:
5376 case Intrinsic::arm_neon_vrshiftu:
5377 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
5381 case Intrinsic::arm_neon_vqshifts:
5382 case Intrinsic::arm_neon_vqshiftu:
5383 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5387 case Intrinsic::arm_neon_vqshiftsu:
5388 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5390 llvm_unreachable("invalid shift count for vqshlu intrinsic");
5392 case Intrinsic::arm_neon_vshiftn:
5393 case Intrinsic::arm_neon_vrshiftn:
5394 case Intrinsic::arm_neon_vqshiftns:
5395 case Intrinsic::arm_neon_vqshiftnu:
5396 case Intrinsic::arm_neon_vqshiftnsu:
5397 case Intrinsic::arm_neon_vqrshiftns:
5398 case Intrinsic::arm_neon_vqrshiftnu:
5399 case Intrinsic::arm_neon_vqrshiftnsu:
5400 // Narrowing shifts require an immediate right shift.
5401 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
5403 llvm_unreachable("invalid shift count for narrowing vector shift "
5407 llvm_unreachable("unhandled vector shift");
5411 case Intrinsic::arm_neon_vshifts:
5412 case Intrinsic::arm_neon_vshiftu:
5413 // Opcode already set above.
5415 case Intrinsic::arm_neon_vshiftls:
5416 case Intrinsic::arm_neon_vshiftlu:
5417 if (Cnt == VT.getVectorElementType().getSizeInBits())
5418 VShiftOpc = ARMISD::VSHLLi;
5420 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
5421 ARMISD::VSHLLs : ARMISD::VSHLLu);
5423 case Intrinsic::arm_neon_vshiftn:
5424 VShiftOpc = ARMISD::VSHRN; break;
5425 case Intrinsic::arm_neon_vrshifts:
5426 VShiftOpc = ARMISD::VRSHRs; break;
5427 case Intrinsic::arm_neon_vrshiftu:
5428 VShiftOpc = ARMISD::VRSHRu; break;
5429 case Intrinsic::arm_neon_vrshiftn:
5430 VShiftOpc = ARMISD::VRSHRN; break;
5431 case Intrinsic::arm_neon_vqshifts:
5432 VShiftOpc = ARMISD::VQSHLs; break;
5433 case Intrinsic::arm_neon_vqshiftu:
5434 VShiftOpc = ARMISD::VQSHLu; break;
5435 case Intrinsic::arm_neon_vqshiftsu:
5436 VShiftOpc = ARMISD::VQSHLsu; break;
5437 case Intrinsic::arm_neon_vqshiftns:
5438 VShiftOpc = ARMISD::VQSHRNs; break;
5439 case Intrinsic::arm_neon_vqshiftnu:
5440 VShiftOpc = ARMISD::VQSHRNu; break;
5441 case Intrinsic::arm_neon_vqshiftnsu:
5442 VShiftOpc = ARMISD::VQSHRNsu; break;
5443 case Intrinsic::arm_neon_vqrshiftns:
5444 VShiftOpc = ARMISD::VQRSHRNs; break;
5445 case Intrinsic::arm_neon_vqrshiftnu:
5446 VShiftOpc = ARMISD::VQRSHRNu; break;
5447 case Intrinsic::arm_neon_vqrshiftnsu:
5448 VShiftOpc = ARMISD::VQRSHRNsu; break;
5451 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5452 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
5455 case Intrinsic::arm_neon_vshiftins: {
5456 EVT VT = N->getOperand(1).getValueType();
5458 unsigned VShiftOpc = 0;
5460 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
5461 VShiftOpc = ARMISD::VSLI;
5462 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
5463 VShiftOpc = ARMISD::VSRI;
5465 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
5468 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5469 N->getOperand(1), N->getOperand(2),
5470 DAG.getConstant(Cnt, MVT::i32));
5473 case Intrinsic::arm_neon_vqrshifts:
5474 case Intrinsic::arm_neon_vqrshiftu:
5475 // No immediate versions of these to check for.
5482 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
5483 /// lowers them. As with the vector shift intrinsics, this is done during DAG
5484 /// combining instead of DAG legalizing because the build_vectors for 64-bit
5485 /// vector element shift counts are generally not legal, and it is hard to see
5486 /// their values after they get legalized to loads from a constant pool.
5487 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
5488 const ARMSubtarget *ST) {
5489 EVT VT = N->getValueType(0);
5491 // Nothing to be done for scalar shifts.
5492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5493 if (!VT.isVector() || !TLI.isTypeLegal(VT))
5496 assert(ST->hasNEON() && "unexpected vector shift");
5499 switch (N->getOpcode()) {
5500 default: llvm_unreachable("unexpected shift opcode");
5503 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
5504 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
5505 DAG.getConstant(Cnt, MVT::i32));
5510 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
5511 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
5512 ARMISD::VSHRs : ARMISD::VSHRu);
5513 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
5514 DAG.getConstant(Cnt, MVT::i32));
5520 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
5521 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
5522 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
5523 const ARMSubtarget *ST) {
5524 SDValue N0 = N->getOperand(0);
5526 // Check for sign- and zero-extensions of vector extract operations of 8-
5527 // and 16-bit vector elements. NEON supports these directly. They are
5528 // handled during DAG combining because type legalization will promote them
5529 // to 32-bit types and it is messy to recognize the operations after that.
5530 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5531 SDValue Vec = N0.getOperand(0);
5532 SDValue Lane = N0.getOperand(1);
5533 EVT VT = N->getValueType(0);
5534 EVT EltVT = N0.getValueType();
5535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5537 if (VT == MVT::i32 &&
5538 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
5539 TLI.isTypeLegal(Vec.getValueType()) &&
5540 isa<ConstantSDNode>(Lane)) {
5543 switch (N->getOpcode()) {
5544 default: llvm_unreachable("unexpected opcode");
5545 case ISD::SIGN_EXTEND:
5546 Opc = ARMISD::VGETLANEs;
5548 case ISD::ZERO_EXTEND:
5549 case ISD::ANY_EXTEND:
5550 Opc = ARMISD::VGETLANEu;
5553 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
5560 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
5561 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
5562 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
5563 const ARMSubtarget *ST) {
5564 // If the target supports NEON, try to use vmax/vmin instructions for f32
5565 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
5566 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
5567 // a NaN; only do the transformation when it matches that behavior.
5569 // For now only do this when using NEON for FP operations; if using VFP, it
5570 // is not obvious that the benefit outweighs the cost of switching to the
5572 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
5573 N->getValueType(0) != MVT::f32)
5576 SDValue CondLHS = N->getOperand(0);
5577 SDValue CondRHS = N->getOperand(1);
5578 SDValue LHS = N->getOperand(2);
5579 SDValue RHS = N->getOperand(3);
5580 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
5582 unsigned Opcode = 0;
5584 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
5585 IsReversed = false; // x CC y ? x : y
5586 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
5587 IsReversed = true ; // x CC y ? y : x
5601 // If LHS is NaN, an ordered comparison will be false and the result will
5602 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
5603 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5604 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
5605 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5607 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
5608 // will return -0, so vmin can only be used for unsafe math or if one of
5609 // the operands is known to be nonzero.
5610 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
5612 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5614 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5623 // If LHS is NaN, an ordered comparison will be false and the result will
5624 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5625 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5626 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5627 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5629 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5630 // will return +0, so vmax can only be used for unsafe math or if one of
5631 // the operands is known to be nonzero.
5632 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5634 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5636 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5642 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5645 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5646 DAGCombinerInfo &DCI) const {
5647 switch (N->getOpcode()) {
5649 case ISD::ADD: return PerformADDCombine(N, DCI);
5650 case ISD::SUB: return PerformSUBCombine(N, DCI);
5651 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5652 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5653 case ISD::AND: return PerformANDCombine(N, DCI);
5654 case ARMISD::BFI: return PerformBFICombine(N, DCI);
5655 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5656 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5657 case ISD::STORE: return PerformSTORECombine(N, DCI);
5658 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
5659 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
5660 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5661 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
5662 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5665 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5666 case ISD::SIGN_EXTEND:
5667 case ISD::ZERO_EXTEND:
5668 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5669 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5674 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5675 if (!Subtarget->allowsUnalignedMem())
5678 switch (VT.getSimpleVT().SimpleTy) {
5685 // FIXME: VLD1 etc with standard alignment is legal.
5689 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5694 switch (VT.getSimpleVT().SimpleTy) {
5695 default: return false;
5710 if ((V & (Scale - 1)) != 0)
5713 return V == (V & ((1LL << 5) - 1));
5716 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5717 const ARMSubtarget *Subtarget) {
5724 switch (VT.getSimpleVT().SimpleTy) {
5725 default: return false;
5730 // + imm12 or - imm8
5732 return V == (V & ((1LL << 8) - 1));
5733 return V == (V & ((1LL << 12) - 1));
5736 // Same as ARM mode. FIXME: NEON?
5737 if (!Subtarget->hasVFP2())
5742 return V == (V & ((1LL << 8) - 1));
5746 /// isLegalAddressImmediate - Return true if the integer value can be used
5747 /// as the offset of the target addressing mode for load / store of the
5749 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5750 const ARMSubtarget *Subtarget) {
5757 if (Subtarget->isThumb1Only())
5758 return isLegalT1AddressImmediate(V, VT);
5759 else if (Subtarget->isThumb2())
5760 return isLegalT2AddressImmediate(V, VT, Subtarget);
5765 switch (VT.getSimpleVT().SimpleTy) {
5766 default: return false;
5771 return V == (V & ((1LL << 12) - 1));
5774 return V == (V & ((1LL << 8) - 1));
5777 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5782 return V == (V & ((1LL << 8) - 1));
5786 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5788 int Scale = AM.Scale;
5792 switch (VT.getSimpleVT().SimpleTy) {
5793 default: return false;
5802 return Scale == 2 || Scale == 4 || Scale == 8;
5805 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5809 // Note, we allow "void" uses (basically, uses that aren't loads or
5810 // stores), because arm allows folding a scale into many arithmetic
5811 // operations. This should be made more precise and revisited later.
5813 // Allow r << imm, but the imm has to be a multiple of two.
5814 if (Scale & 1) return false;
5815 return isPowerOf2_32(Scale);
5819 /// isLegalAddressingMode - Return true if the addressing mode represented
5820 /// by AM is legal for this target, for a load/store of the specified type.
5821 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5822 const Type *Ty) const {
5823 EVT VT = getValueType(Ty, true);
5824 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5827 // Can never fold addr of global into load/store.
5832 case 0: // no scale reg, must be "r+i" or "r", or "i".
5835 if (Subtarget->isThumb1Only())
5839 // ARM doesn't support any R+R*scale+imm addr modes.
5846 if (Subtarget->isThumb2())
5847 return isLegalT2ScaledAddressingMode(AM, VT);
5849 int Scale = AM.Scale;
5850 switch (VT.getSimpleVT().SimpleTy) {
5851 default: return false;
5855 if (Scale < 0) Scale = -Scale;
5859 return isPowerOf2_32(Scale & ~1);
5863 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5868 // Note, we allow "void" uses (basically, uses that aren't loads or
5869 // stores), because arm allows folding a scale into many arithmetic
5870 // operations. This should be made more precise and revisited later.
5872 // Allow r << imm, but the imm has to be a multiple of two.
5873 if (Scale & 1) return false;
5874 return isPowerOf2_32(Scale);
5881 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5882 /// icmp immediate, that is the target has icmp instructions which can compare
5883 /// a register against the immediate without having to materialize the
5884 /// immediate into a register.
5885 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5886 if (!Subtarget->isThumb())
5887 return ARM_AM::getSOImmVal(Imm) != -1;
5888 if (Subtarget->isThumb2())
5889 return ARM_AM::getT2SOImmVal(Imm) != -1;
5890 return Imm >= 0 && Imm <= 255;
5893 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5894 bool isSEXTLoad, SDValue &Base,
5895 SDValue &Offset, bool &isInc,
5896 SelectionDAG &DAG) {
5897 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5900 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5902 Base = Ptr->getOperand(0);
5903 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5904 int RHSC = (int)RHS->getZExtValue();
5905 if (RHSC < 0 && RHSC > -256) {
5906 assert(Ptr->getOpcode() == ISD::ADD);
5908 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5912 isInc = (Ptr->getOpcode() == ISD::ADD);
5913 Offset = Ptr->getOperand(1);
5915 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5917 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5918 int RHSC = (int)RHS->getZExtValue();
5919 if (RHSC < 0 && RHSC > -0x1000) {
5920 assert(Ptr->getOpcode() == ISD::ADD);
5922 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5923 Base = Ptr->getOperand(0);
5928 if (Ptr->getOpcode() == ISD::ADD) {
5930 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5931 if (ShOpcVal != ARM_AM::no_shift) {
5932 Base = Ptr->getOperand(1);
5933 Offset = Ptr->getOperand(0);
5935 Base = Ptr->getOperand(0);
5936 Offset = Ptr->getOperand(1);
5941 isInc = (Ptr->getOpcode() == ISD::ADD);
5942 Base = Ptr->getOperand(0);
5943 Offset = Ptr->getOperand(1);
5947 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5951 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5952 bool isSEXTLoad, SDValue &Base,
5953 SDValue &Offset, bool &isInc,
5954 SelectionDAG &DAG) {
5955 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5958 Base = Ptr->getOperand(0);
5959 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5960 int RHSC = (int)RHS->getZExtValue();
5961 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5962 assert(Ptr->getOpcode() == ISD::ADD);
5964 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5966 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5967 isInc = Ptr->getOpcode() == ISD::ADD;
5968 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5976 /// getPreIndexedAddressParts - returns true by value, base pointer and
5977 /// offset pointer and addressing mode by reference if the node's address
5978 /// can be legally represented as pre-indexed load / store address.
5980 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5982 ISD::MemIndexedMode &AM,
5983 SelectionDAG &DAG) const {
5984 if (Subtarget->isThumb1Only())
5989 bool isSEXTLoad = false;
5990 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5991 Ptr = LD->getBasePtr();
5992 VT = LD->getMemoryVT();
5993 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5994 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5995 Ptr = ST->getBasePtr();
5996 VT = ST->getMemoryVT();
6001 bool isLegal = false;
6002 if (Subtarget->isThumb2())
6003 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6004 Offset, isInc, DAG);
6006 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6007 Offset, isInc, DAG);
6011 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
6015 /// getPostIndexedAddressParts - returns true by value, base pointer and
6016 /// offset pointer and addressing mode by reference if this node can be
6017 /// combined with a load / store to form a post-indexed load / store.
6018 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
6021 ISD::MemIndexedMode &AM,
6022 SelectionDAG &DAG) const {
6023 if (Subtarget->isThumb1Only())
6028 bool isSEXTLoad = false;
6029 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6030 VT = LD->getMemoryVT();
6031 Ptr = LD->getBasePtr();
6032 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6033 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6034 VT = ST->getMemoryVT();
6035 Ptr = ST->getBasePtr();
6040 bool isLegal = false;
6041 if (Subtarget->isThumb2())
6042 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6045 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6051 // Swap base ptr and offset to catch more post-index load / store when
6052 // it's legal. In Thumb2 mode, offset must be an immediate.
6053 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
6054 !Subtarget->isThumb2())
6055 std::swap(Base, Offset);
6057 // Post-indexed load / store update the base pointer.
6062 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
6066 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6070 const SelectionDAG &DAG,
6071 unsigned Depth) const {
6072 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
6073 switch (Op.getOpcode()) {
6075 case ARMISD::CMOV: {
6076 // Bits are known zero/one if known on the LHS and RHS.
6077 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
6078 if (KnownZero == 0 && KnownOne == 0) return;
6080 APInt KnownZeroRHS, KnownOneRHS;
6081 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
6082 KnownZeroRHS, KnownOneRHS, Depth+1);
6083 KnownZero &= KnownZeroRHS;
6084 KnownOne &= KnownOneRHS;
6090 //===----------------------------------------------------------------------===//
6091 // ARM Inline Assembly Support
6092 //===----------------------------------------------------------------------===//
6094 /// getConstraintType - Given a constraint letter, return the type of
6095 /// constraint it is for this target.
6096 ARMTargetLowering::ConstraintType
6097 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
6098 if (Constraint.size() == 1) {
6099 switch (Constraint[0]) {
6101 case 'l': return C_RegisterClass;
6102 case 'w': return C_RegisterClass;
6105 return TargetLowering::getConstraintType(Constraint);
6108 /// Examine constraint type and operand type and determine a weight value.
6109 /// This object must already have been set up with the operand type
6110 /// and the current alternative constraint selected.
6111 TargetLowering::ConstraintWeight
6112 ARMTargetLowering::getSingleConstraintMatchWeight(
6113 AsmOperandInfo &info, const char *constraint) const {
6114 ConstraintWeight weight = CW_Invalid;
6115 Value *CallOperandVal = info.CallOperandVal;
6116 // If we don't have a value, we can't do a match,
6117 // but allow it at the lowest weight.
6118 if (CallOperandVal == NULL)
6120 const Type *type = CallOperandVal->getType();
6121 // Look at the constraint type.
6122 switch (*constraint) {
6124 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6127 if (type->isIntegerTy()) {
6128 if (Subtarget->isThumb())
6129 weight = CW_SpecificReg;
6131 weight = CW_Register;
6135 if (type->isFloatingPointTy())
6136 weight = CW_Register;
6142 std::pair<unsigned, const TargetRegisterClass*>
6143 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6145 if (Constraint.size() == 1) {
6146 // GCC ARM Constraint Letters
6147 switch (Constraint[0]) {
6149 if (Subtarget->isThumb())
6150 return std::make_pair(0U, ARM::tGPRRegisterClass);
6152 return std::make_pair(0U, ARM::GPRRegisterClass);
6154 return std::make_pair(0U, ARM::GPRRegisterClass);
6157 return std::make_pair(0U, ARM::SPRRegisterClass);
6158 if (VT.getSizeInBits() == 64)
6159 return std::make_pair(0U, ARM::DPRRegisterClass);
6160 if (VT.getSizeInBits() == 128)
6161 return std::make_pair(0U, ARM::QPRRegisterClass);
6165 if (StringRef("{cc}").equals_lower(Constraint))
6166 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
6168 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6171 std::vector<unsigned> ARMTargetLowering::
6172 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6174 if (Constraint.size() != 1)
6175 return std::vector<unsigned>();
6177 switch (Constraint[0]) { // GCC ARM Constraint Letters
6180 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6181 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6184 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6185 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6186 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
6187 ARM::R12, ARM::LR, 0);
6190 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
6191 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
6192 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
6193 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
6194 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
6195 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
6196 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
6197 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
6198 if (VT.getSizeInBits() == 64)
6199 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
6200 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
6201 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
6202 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
6203 if (VT.getSizeInBits() == 128)
6204 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
6205 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
6209 return std::vector<unsigned>();
6212 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6213 /// vector. If it is invalid, don't add anything to Ops.
6214 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6216 std::vector<SDValue>&Ops,
6217 SelectionDAG &DAG) const {
6218 SDValue Result(0, 0);
6220 switch (Constraint) {
6222 case 'I': case 'J': case 'K': case 'L':
6223 case 'M': case 'N': case 'O':
6224 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
6228 int64_t CVal64 = C->getSExtValue();
6229 int CVal = (int) CVal64;
6230 // None of these constraints allow values larger than 32 bits. Check
6231 // that the value fits in an int.
6235 switch (Constraint) {
6237 if (Subtarget->isThumb1Only()) {
6238 // This must be a constant between 0 and 255, for ADD
6240 if (CVal >= 0 && CVal <= 255)
6242 } else if (Subtarget->isThumb2()) {
6243 // A constant that can be used as an immediate value in a
6244 // data-processing instruction.
6245 if (ARM_AM::getT2SOImmVal(CVal) != -1)
6248 // A constant that can be used as an immediate value in a
6249 // data-processing instruction.
6250 if (ARM_AM::getSOImmVal(CVal) != -1)
6256 if (Subtarget->isThumb()) { // FIXME thumb2
6257 // This must be a constant between -255 and -1, for negated ADD
6258 // immediates. This can be used in GCC with an "n" modifier that
6259 // prints the negated value, for use with SUB instructions. It is
6260 // not useful otherwise but is implemented for compatibility.
6261 if (CVal >= -255 && CVal <= -1)
6264 // This must be a constant between -4095 and 4095. It is not clear
6265 // what this constraint is intended for. Implemented for
6266 // compatibility with GCC.
6267 if (CVal >= -4095 && CVal <= 4095)
6273 if (Subtarget->isThumb1Only()) {
6274 // A 32-bit value where only one byte has a nonzero value. Exclude
6275 // zero to match GCC. This constraint is used by GCC internally for
6276 // constants that can be loaded with a move/shift combination.
6277 // It is not useful otherwise but is implemented for compatibility.
6278 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
6280 } else if (Subtarget->isThumb2()) {
6281 // A constant whose bitwise inverse can be used as an immediate
6282 // value in a data-processing instruction. This can be used in GCC
6283 // with a "B" modifier that prints the inverted value, for use with
6284 // BIC and MVN instructions. It is not useful otherwise but is
6285 // implemented for compatibility.
6286 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
6289 // A constant whose bitwise inverse can be used as an immediate
6290 // value in a data-processing instruction. This can be used in GCC
6291 // with a "B" modifier that prints the inverted value, for use with
6292 // BIC and MVN instructions. It is not useful otherwise but is
6293 // implemented for compatibility.
6294 if (ARM_AM::getSOImmVal(~CVal) != -1)
6300 if (Subtarget->isThumb1Only()) {
6301 // This must be a constant between -7 and 7,
6302 // for 3-operand ADD/SUB immediate instructions.
6303 if (CVal >= -7 && CVal < 7)
6305 } else if (Subtarget->isThumb2()) {
6306 // A constant whose negation can be used as an immediate value in a
6307 // data-processing instruction. This can be used in GCC with an "n"
6308 // modifier that prints the negated value, for use with SUB
6309 // instructions. It is not useful otherwise but is implemented for
6311 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
6314 // A constant whose negation can be used as an immediate value in a
6315 // data-processing instruction. This can be used in GCC with an "n"
6316 // modifier that prints the negated value, for use with SUB
6317 // instructions. It is not useful otherwise but is implemented for
6319 if (ARM_AM::getSOImmVal(-CVal) != -1)
6325 if (Subtarget->isThumb()) { // FIXME thumb2
6326 // This must be a multiple of 4 between 0 and 1020, for
6327 // ADD sp + immediate.
6328 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
6331 // A power of two or a constant between 0 and 32. This is used in
6332 // GCC for the shift amount on shifted register operands, but it is
6333 // useful in general for any shift amounts.
6334 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
6340 if (Subtarget->isThumb()) { // FIXME thumb2
6341 // This must be a constant between 0 and 31, for shift amounts.
6342 if (CVal >= 0 && CVal <= 31)
6348 if (Subtarget->isThumb()) { // FIXME thumb2
6349 // This must be a multiple of 4 between -508 and 508, for
6350 // ADD/SUB sp = sp + immediate.
6351 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
6356 Result = DAG.getTargetConstant(CVal, Op.getValueType());
6360 if (Result.getNode()) {
6361 Ops.push_back(Result);
6364 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6368 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6369 // The ARM target isn't yet aware of offsets.
6373 int ARM::getVFPf32Imm(const APFloat &FPImm) {
6374 APInt Imm = FPImm.bitcastToAPInt();
6375 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
6376 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
6377 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
6379 // We can handle 4 bits of mantissa.
6380 // mantissa = (16+UInt(e:f:g:h))/16.
6381 if (Mantissa & 0x7ffff)
6384 if ((Mantissa & 0xf) != Mantissa)
6387 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6388 if (Exp < -3 || Exp > 4)
6390 Exp = ((Exp+3) & 0x7) ^ 4;
6392 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6395 int ARM::getVFPf64Imm(const APFloat &FPImm) {
6396 APInt Imm = FPImm.bitcastToAPInt();
6397 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
6398 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
6399 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
6401 // We can handle 4 bits of mantissa.
6402 // mantissa = (16+UInt(e:f:g:h))/16.
6403 if (Mantissa & 0xffffffffffffLL)
6406 if ((Mantissa & 0xf) != Mantissa)
6409 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6410 if (Exp < -3 || Exp > 4)
6412 Exp = ((Exp+3) & 0x7) ^ 4;
6414 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6417 bool ARM::isBitFieldInvertedMask(unsigned v) {
6418 if (v == 0xffffffff)
6420 // there can be 1's on either or both "outsides", all the "inside"
6422 unsigned int lsb = 0, msb = 31;
6423 while (v & (1 << msb)) --msb;
6424 while (v & (1 << lsb)) ++lsb;
6425 for (unsigned int i = lsb; i <= msb; ++i) {
6432 /// isFPImmLegal - Returns true if the target can instruction select the
6433 /// specified FP immediate natively. If false, the legalizer will
6434 /// materialize the FP immediate as a load from a constant pool.
6435 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
6436 if (!Subtarget->hasVFP3())
6439 return ARM::getVFPf32Imm(Imm) != -1;
6441 return ARM::getVFPf64Imm(Imm) != -1;
6445 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6446 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6447 /// specified in the intrinsic calls.
6448 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6450 unsigned Intrinsic) const {
6451 switch (Intrinsic) {
6452 case Intrinsic::arm_neon_vld1:
6453 case Intrinsic::arm_neon_vld2:
6454 case Intrinsic::arm_neon_vld3:
6455 case Intrinsic::arm_neon_vld4:
6456 case Intrinsic::arm_neon_vld2lane:
6457 case Intrinsic::arm_neon_vld3lane:
6458 case Intrinsic::arm_neon_vld4lane: {
6459 Info.opc = ISD::INTRINSIC_W_CHAIN;
6460 // Conservatively set memVT to the entire set of vectors loaded.
6461 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
6462 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6463 Info.ptrVal = I.getArgOperand(0);
6465 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6466 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6467 Info.vol = false; // volatile loads with NEON intrinsics not supported
6468 Info.readMem = true;
6469 Info.writeMem = false;
6472 case Intrinsic::arm_neon_vst1:
6473 case Intrinsic::arm_neon_vst2:
6474 case Intrinsic::arm_neon_vst3:
6475 case Intrinsic::arm_neon_vst4:
6476 case Intrinsic::arm_neon_vst2lane:
6477 case Intrinsic::arm_neon_vst3lane:
6478 case Intrinsic::arm_neon_vst4lane: {
6479 Info.opc = ISD::INTRINSIC_VOID;
6480 // Conservatively set memVT to the entire set of vectors stored.
6481 unsigned NumElts = 0;
6482 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6483 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
6484 if (!ArgTy->isVectorTy())
6486 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
6488 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6489 Info.ptrVal = I.getArgOperand(0);
6491 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6492 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6493 Info.vol = false; // volatile stores with NEON intrinsics not supported
6494 Info.readMem = false;
6495 Info.writeMem = true;