1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
76 EVT PromotedBitwiseVT) {
77 if (VT != PromotedLdStVT) {
78 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
79 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
80 PromotedLdStVT.getSimpleVT());
82 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
83 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
84 PromotedLdStVT.getSimpleVT());
87 EVT ElemTy = VT.getVectorElementType();
88 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
89 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
91 if (ElemTy != MVT::i32) {
92 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
97 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
98 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
99 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
100 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
101 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
103 if (VT.isInteger()) {
104 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
105 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
107 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
108 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
109 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
110 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
111 setTruncStoreAction(VT.getSimpleVT(),
112 (MVT::SimpleValueType)InnerVT, Expand);
114 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
116 // Promote all bit-wise operations.
117 if (VT.isInteger() && VT != PromotedBitwiseVT) {
118 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
124 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
125 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
126 PromotedBitwiseVT.getSimpleVT());
129 // Neon does not support vector divide/remainder operations.
130 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
134 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
138 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
139 addRegisterClass(VT, ARM::DPRRegisterClass);
140 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
143 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::QPRRegisterClass);
145 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
148 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
149 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
150 return new TargetLoweringObjectFileMachO();
152 return new ARMElfTargetObjectFile();
155 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<ARMSubtarget>();
158 RegInfo = TM.getRegisterInfo();
159 Itins = TM.getInstrItineraryData();
161 if (Subtarget->isTargetDarwin()) {
162 // Uses VFP for Thumb libfuncs if available.
163 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
164 // Single-precision floating-point arithmetic.
165 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
166 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
167 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
168 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
170 // Double-precision floating-point arithmetic.
171 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
172 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
173 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
174 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
176 // Single-precision comparisons.
177 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
178 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
179 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
180 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
181 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
182 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
183 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
184 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
186 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
195 // Double-precision comparisons.
196 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
197 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
198 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
199 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
200 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
201 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
202 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
203 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
205 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
214 // Floating-point to integer conversions.
215 // i64 conversions are done via library routines even when generating VFP
216 // instructions, so use the same ones.
217 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
218 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
219 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
220 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
222 // Conversions between floating types.
223 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
224 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
226 // Integer to floating-point conversions.
227 // i64 conversions are done via library routines even when generating VFP
228 // instructions, so use the same ones.
229 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
230 // e.g., __floatunsidf vs. __floatunssidfvfp.
231 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
232 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
233 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
234 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
238 // These libcalls are not available in 32-bit.
239 setLibcallName(RTLIB::SHL_I128, 0);
240 setLibcallName(RTLIB::SRL_I128, 0);
241 setLibcallName(RTLIB::SRA_I128, 0);
243 if (Subtarget->isAAPCS_ABI()) {
244 // Double-precision floating-point arithmetic helper functions
245 // RTABI chapter 4.1.2, Table 2
246 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
247 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
248 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
249 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
250 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
251 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
252 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
253 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
255 // Double-precision floating-point comparison helper functions
256 // RTABI chapter 4.1.2, Table 3
257 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
258 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
259 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
260 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
261 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
262 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
263 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
264 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
265 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
266 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
267 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
268 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
269 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
270 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
271 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
272 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
273 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
282 // Single-precision floating-point arithmetic helper functions
283 // RTABI chapter 4.1.2, Table 4
284 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
285 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
286 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
287 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
288 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
289 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
293 // Single-precision floating-point comparison helper functions
294 // RTABI chapter 4.1.2, Table 5
295 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
296 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
297 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
298 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
299 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
300 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
301 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
302 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
303 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
304 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
305 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
306 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
307 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
308 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
309 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
310 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
311 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
320 // Floating-point to integer conversions.
321 // RTABI chapter 4.1.2, Table 6
322 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
323 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
324 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
325 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
326 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
327 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
328 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
329 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
330 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
339 // Conversions between floating types.
340 // RTABI chapter 4.1.2, Table 7
341 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
342 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
343 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
344 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
346 // Integer to floating-point conversions.
347 // RTABI chapter 4.1.2, Table 8
348 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
349 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
350 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
351 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
352 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
353 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
354 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
355 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
356 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
365 // Long long helper functions
366 // RTABI chapter 4.2, Table 9
367 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
368 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
369 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
370 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
371 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
372 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
373 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
380 // Integer division functions
381 // RTABI chapter 4.3.1
382 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
383 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
384 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
385 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
386 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
387 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
388 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
396 if (Subtarget->isThumb1Only())
397 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
399 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
400 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
401 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
402 if (!Subtarget->isFPOnlySP())
403 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
405 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
408 if (Subtarget->hasNEON()) {
409 addDRTypeForNEON(MVT::v2f32);
410 addDRTypeForNEON(MVT::v8i8);
411 addDRTypeForNEON(MVT::v4i16);
412 addDRTypeForNEON(MVT::v2i32);
413 addDRTypeForNEON(MVT::v1i64);
415 addQRTypeForNEON(MVT::v4f32);
416 addQRTypeForNEON(MVT::v2f64);
417 addQRTypeForNEON(MVT::v16i8);
418 addQRTypeForNEON(MVT::v8i16);
419 addQRTypeForNEON(MVT::v4i32);
420 addQRTypeForNEON(MVT::v2i64);
422 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
423 // neither Neon nor VFP support any arithmetic operations on it.
424 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
425 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
426 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
427 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
428 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
429 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
430 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
431 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
432 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
434 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
435 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
436 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
437 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
438 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
439 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
441 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
442 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
443 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
444 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
445 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
446 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
447 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
449 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
451 // Neon does not support some operations on v1i64 and v2i64 types.
452 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
453 // Custom handling for some quad-vector types to detect VMULL.
454 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
455 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
456 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
457 // Custom handling for some vector types to avoid expensive expansions
458 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
459 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
460 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
461 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
462 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
463 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
465 setTargetDAGCombine(ISD::INTRINSIC_VOID);
466 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
467 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
468 setTargetDAGCombine(ISD::SHL);
469 setTargetDAGCombine(ISD::SRL);
470 setTargetDAGCombine(ISD::SRA);
471 setTargetDAGCombine(ISD::SIGN_EXTEND);
472 setTargetDAGCombine(ISD::ZERO_EXTEND);
473 setTargetDAGCombine(ISD::ANY_EXTEND);
474 setTargetDAGCombine(ISD::SELECT_CC);
475 setTargetDAGCombine(ISD::BUILD_VECTOR);
476 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
477 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
478 setTargetDAGCombine(ISD::STORE);
481 computeRegisterProperties();
483 // ARM does not have f32 extending load.
484 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
486 // ARM does not have i1 sign extending load.
487 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
489 // ARM supports all 4 flavors of integer indexed load / store.
490 if (!Subtarget->isThumb1Only()) {
491 for (unsigned im = (unsigned)ISD::PRE_INC;
492 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
493 setIndexedLoadAction(im, MVT::i1, Legal);
494 setIndexedLoadAction(im, MVT::i8, Legal);
495 setIndexedLoadAction(im, MVT::i16, Legal);
496 setIndexedLoadAction(im, MVT::i32, Legal);
497 setIndexedStoreAction(im, MVT::i1, Legal);
498 setIndexedStoreAction(im, MVT::i8, Legal);
499 setIndexedStoreAction(im, MVT::i16, Legal);
500 setIndexedStoreAction(im, MVT::i32, Legal);
504 // i64 operation support.
505 if (Subtarget->isThumb1Only()) {
506 setOperationAction(ISD::MUL, MVT::i64, Expand);
507 setOperationAction(ISD::MULHU, MVT::i32, Expand);
508 setOperationAction(ISD::MULHS, MVT::i32, Expand);
509 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
510 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
512 setOperationAction(ISD::MUL, MVT::i64, Expand);
513 setOperationAction(ISD::MULHU, MVT::i32, Expand);
514 if (!Subtarget->hasV6Ops())
515 setOperationAction(ISD::MULHS, MVT::i32, Expand);
517 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
518 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
519 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
520 setOperationAction(ISD::SRL, MVT::i64, Custom);
521 setOperationAction(ISD::SRA, MVT::i64, Custom);
523 // ARM does not have ROTL.
524 setOperationAction(ISD::ROTL, MVT::i32, Expand);
525 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
526 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
527 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
528 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
530 // Only ARMv6 has BSWAP.
531 if (!Subtarget->hasV6Ops())
532 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
534 // These are expanded into libcalls.
535 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
536 // v7M has a hardware divider
537 setOperationAction(ISD::SDIV, MVT::i32, Expand);
538 setOperationAction(ISD::UDIV, MVT::i32, Expand);
540 setOperationAction(ISD::SREM, MVT::i32, Expand);
541 setOperationAction(ISD::UREM, MVT::i32, Expand);
542 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
543 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
545 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
546 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
547 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
548 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
549 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
551 setOperationAction(ISD::TRAP, MVT::Other, Legal);
553 // Use the default implementation.
554 setOperationAction(ISD::VASTART, MVT::Other, Custom);
555 setOperationAction(ISD::VAARG, MVT::Other, Expand);
556 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
557 setOperationAction(ISD::VAEND, MVT::Other, Expand);
558 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
559 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
560 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
561 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
562 setExceptionPointerRegister(ARM::R0);
563 setExceptionSelectorRegister(ARM::R1);
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
566 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
567 // the default expansion.
568 if (Subtarget->hasDataBarrier() ||
569 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
570 // membarrier needs custom lowering; the rest are legal and handled
572 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
574 // Set them all for expansion, which will force libcalls.
575 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
576 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
577 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
578 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
579 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
580 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
581 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
588 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
589 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
590 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
591 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
592 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
600 // Since the libcalls include locking, fold in the fences
601 setShouldFoldAtomicFences(true);
603 // 64-bit versions are always libcalls (for now)
604 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
606 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
608 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
609 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
611 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
613 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
615 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
616 if (!Subtarget->hasV6Ops()) {
617 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
618 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
620 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
622 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
623 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
624 // iff target supports vfp2.
625 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
626 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
629 // We want to custom lower some of our intrinsics.
630 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
631 if (Subtarget->isTargetDarwin()) {
632 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
633 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
634 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
637 setOperationAction(ISD::SETCC, MVT::i32, Expand);
638 setOperationAction(ISD::SETCC, MVT::f32, Expand);
639 setOperationAction(ISD::SETCC, MVT::f64, Expand);
640 setOperationAction(ISD::SELECT, MVT::i32, Custom);
641 setOperationAction(ISD::SELECT, MVT::f32, Custom);
642 setOperationAction(ISD::SELECT, MVT::f64, Custom);
643 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
644 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
645 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
647 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
648 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
649 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
650 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
651 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
653 // We don't support sin/cos/fmod/copysign/pow
654 setOperationAction(ISD::FSIN, MVT::f64, Expand);
655 setOperationAction(ISD::FSIN, MVT::f32, Expand);
656 setOperationAction(ISD::FCOS, MVT::f32, Expand);
657 setOperationAction(ISD::FCOS, MVT::f64, Expand);
658 setOperationAction(ISD::FREM, MVT::f64, Expand);
659 setOperationAction(ISD::FREM, MVT::f32, Expand);
660 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 setOperationAction(ISD::FPOW, MVT::f64, Expand);
665 setOperationAction(ISD::FPOW, MVT::f32, Expand);
667 // Various VFP goodness
668 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
669 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
670 if (Subtarget->hasVFP2()) {
671 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
672 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
673 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
674 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
676 // Special handling for half-precision FP.
677 if (!Subtarget->hasFP16()) {
678 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
679 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
683 // We have target-specific dag combine patterns for the following nodes:
684 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
685 setTargetDAGCombine(ISD::ADD);
686 setTargetDAGCombine(ISD::SUB);
687 setTargetDAGCombine(ISD::MUL);
689 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
690 setTargetDAGCombine(ISD::OR);
691 if (Subtarget->hasNEON())
692 setTargetDAGCombine(ISD::AND);
694 setStackPointerRegisterToSaveRestore(ARM::SP);
696 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
697 setSchedulingPreference(Sched::RegPressure);
699 setSchedulingPreference(Sched::Hybrid);
701 //// temporary - rewrite interface to use type
702 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
704 // On ARM arguments smaller than 4 bytes are extended, so all arguments
705 // are at least 4 bytes aligned.
706 setMinStackArgumentAlignment(4);
708 benefitFromCodePlacementOpt = true;
711 // FIXME: It might make sense to define the representative register class as the
712 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
713 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
714 // SPR's representative would be DPR_VFP2. This should work well if register
715 // pressure tracking were modified such that a register use would increment the
716 // pressure of the register class's representative and all of it's super
717 // classes' representatives transitively. We have not implemented this because
718 // of the difficulty prior to coalescing of modeling operand register classes
719 // due to the common occurence of cross class copies and subregister insertions
721 std::pair<const TargetRegisterClass*, uint8_t>
722 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
723 const TargetRegisterClass *RRC = 0;
725 switch (VT.getSimpleVT().SimpleTy) {
727 return TargetLowering::findRepresentativeClass(VT);
728 // Use DPR as representative register class for all floating point
729 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
730 // the cost is 1 for both f32 and f64.
731 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
732 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
733 RRC = ARM::DPRRegisterClass;
734 // When NEON is used for SP, only half of the register file is available
735 // because operations that define both SP and DP results will be constrained
736 // to the VFP2 class (D0-D15). We currently model this constraint prior to
737 // coalescing by double-counting the SP regs. See the FIXME above.
738 if (Subtarget->useNEONForSinglePrecisionFP())
741 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
742 case MVT::v4f32: case MVT::v2f64:
743 RRC = ARM::DPRRegisterClass;
747 RRC = ARM::DPRRegisterClass;
751 RRC = ARM::DPRRegisterClass;
755 return std::make_pair(RRC, Cost);
758 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
761 case ARMISD::Wrapper: return "ARMISD::Wrapper";
762 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
763 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
764 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
765 case ARMISD::CALL: return "ARMISD::CALL";
766 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
767 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
768 case ARMISD::tCALL: return "ARMISD::tCALL";
769 case ARMISD::BRCOND: return "ARMISD::BRCOND";
770 case ARMISD::BR_JT: return "ARMISD::BR_JT";
771 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
772 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
773 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
774 case ARMISD::CMP: return "ARMISD::CMP";
775 case ARMISD::CMPZ: return "ARMISD::CMPZ";
776 case ARMISD::CMPFP: return "ARMISD::CMPFP";
777 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
778 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
779 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
780 case ARMISD::CMOV: return "ARMISD::CMOV";
781 case ARMISD::CNEG: return "ARMISD::CNEG";
783 case ARMISD::RBIT: return "ARMISD::RBIT";
785 case ARMISD::FTOSI: return "ARMISD::FTOSI";
786 case ARMISD::FTOUI: return "ARMISD::FTOUI";
787 case ARMISD::SITOF: return "ARMISD::SITOF";
788 case ARMISD::UITOF: return "ARMISD::UITOF";
790 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
791 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
792 case ARMISD::RRX: return "ARMISD::RRX";
794 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
795 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
797 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
798 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
799 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
801 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
803 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
805 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
807 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
808 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
810 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
812 case ARMISD::VCEQ: return "ARMISD::VCEQ";
813 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
814 case ARMISD::VCGE: return "ARMISD::VCGE";
815 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
816 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
817 case ARMISD::VCGEU: return "ARMISD::VCGEU";
818 case ARMISD::VCGT: return "ARMISD::VCGT";
819 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
820 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
821 case ARMISD::VCGTU: return "ARMISD::VCGTU";
822 case ARMISD::VTST: return "ARMISD::VTST";
824 case ARMISD::VSHL: return "ARMISD::VSHL";
825 case ARMISD::VSHRs: return "ARMISD::VSHRs";
826 case ARMISD::VSHRu: return "ARMISD::VSHRu";
827 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
828 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
829 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
830 case ARMISD::VSHRN: return "ARMISD::VSHRN";
831 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
832 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
833 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
834 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
835 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
836 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
837 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
838 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
839 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
840 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
841 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
842 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
843 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
844 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
845 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
846 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
847 case ARMISD::VDUP: return "ARMISD::VDUP";
848 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
849 case ARMISD::VEXT: return "ARMISD::VEXT";
850 case ARMISD::VREV64: return "ARMISD::VREV64";
851 case ARMISD::VREV32: return "ARMISD::VREV32";
852 case ARMISD::VREV16: return "ARMISD::VREV16";
853 case ARMISD::VZIP: return "ARMISD::VZIP";
854 case ARMISD::VUZP: return "ARMISD::VUZP";
855 case ARMISD::VTRN: return "ARMISD::VTRN";
856 case ARMISD::VMULLs: return "ARMISD::VMULLs";
857 case ARMISD::VMULLu: return "ARMISD::VMULLu";
858 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
859 case ARMISD::FMAX: return "ARMISD::FMAX";
860 case ARMISD::FMIN: return "ARMISD::FMIN";
861 case ARMISD::BFI: return "ARMISD::BFI";
862 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
863 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
864 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
865 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
866 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
867 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
868 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
869 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
870 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
871 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
872 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
873 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
874 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
875 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
876 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
877 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
878 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
879 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
880 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
881 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
882 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
883 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
887 /// getRegClassFor - Return the register class that should be used for the
888 /// specified value type.
889 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
890 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
891 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
892 // load / store 4 to 8 consecutive D registers.
893 if (Subtarget->hasNEON()) {
894 if (VT == MVT::v4i64)
895 return ARM::QQPRRegisterClass;
896 else if (VT == MVT::v8i64)
897 return ARM::QQQQPRRegisterClass;
899 return TargetLowering::getRegClassFor(VT);
902 // Create a fast isel object.
904 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
905 return ARM::createFastISel(funcInfo);
908 /// getFunctionAlignment - Return the Log2 alignment of this function.
909 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
910 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
913 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
914 /// be used for loads / stores from the global.
915 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
916 return (Subtarget->isThumb1Only() ? 127 : 4095);
919 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
920 unsigned NumVals = N->getNumValues();
922 return Sched::RegPressure;
924 for (unsigned i = 0; i != NumVals; ++i) {
925 EVT VT = N->getValueType(i);
926 if (VT == MVT::Glue || VT == MVT::Other)
928 if (VT.isFloatingPoint() || VT.isVector())
929 return Sched::Latency;
932 if (!N->isMachineOpcode())
933 return Sched::RegPressure;
935 // Load are scheduled for latency even if there instruction itinerary
937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
938 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
940 if (TID.getNumDefs() == 0)
941 return Sched::RegPressure;
942 if (!Itins->isEmpty() &&
943 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
944 return Sched::Latency;
946 return Sched::RegPressure;
949 // FIXME: Move to RegInfo
951 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
952 MachineFunction &MF) const {
953 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
955 switch (RC->getID()) {
958 case ARM::tGPRRegClassID:
959 return TFI->hasFP(MF) ? 4 : 5;
960 case ARM::GPRRegClassID: {
961 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
962 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
964 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
965 case ARM::DPRRegClassID:
970 //===----------------------------------------------------------------------===//
972 //===----------------------------------------------------------------------===//
974 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
975 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
977 default: llvm_unreachable("Unknown condition code!");
978 case ISD::SETNE: return ARMCC::NE;
979 case ISD::SETEQ: return ARMCC::EQ;
980 case ISD::SETGT: return ARMCC::GT;
981 case ISD::SETGE: return ARMCC::GE;
982 case ISD::SETLT: return ARMCC::LT;
983 case ISD::SETLE: return ARMCC::LE;
984 case ISD::SETUGT: return ARMCC::HI;
985 case ISD::SETUGE: return ARMCC::HS;
986 case ISD::SETULT: return ARMCC::LO;
987 case ISD::SETULE: return ARMCC::LS;
991 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
992 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
993 ARMCC::CondCodes &CondCode2) {
994 CondCode2 = ARMCC::AL;
996 default: llvm_unreachable("Unknown FP condition!");
998 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1000 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1002 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1003 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1004 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1005 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1006 case ISD::SETO: CondCode = ARMCC::VC; break;
1007 case ISD::SETUO: CondCode = ARMCC::VS; break;
1008 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1009 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1010 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1012 case ISD::SETULT: CondCode = ARMCC::LT; break;
1014 case ISD::SETULE: CondCode = ARMCC::LE; break;
1016 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1020 //===----------------------------------------------------------------------===//
1021 // Calling Convention Implementation
1022 //===----------------------------------------------------------------------===//
1024 #include "ARMGenCallingConv.inc"
1026 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1027 /// given CallingConvention value.
1028 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1030 bool isVarArg) const {
1033 llvm_unreachable("Unsupported calling convention");
1034 case CallingConv::Fast:
1035 if (Subtarget->hasVFP2() && !isVarArg) {
1036 if (!Subtarget->isAAPCS_ABI())
1037 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1038 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1039 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1042 case CallingConv::C: {
1043 // Use target triple & subtarget features to do actual dispatch.
1044 if (!Subtarget->isAAPCS_ABI())
1045 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1046 else if (Subtarget->hasVFP2() &&
1047 FloatABIType == FloatABI::Hard && !isVarArg)
1048 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1049 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1051 case CallingConv::ARM_AAPCS_VFP:
1052 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1053 case CallingConv::ARM_AAPCS:
1054 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1055 case CallingConv::ARM_APCS:
1056 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1060 /// LowerCallResult - Lower the result values of a call into the
1061 /// appropriate copies out of appropriate physical registers.
1063 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1064 CallingConv::ID CallConv, bool isVarArg,
1065 const SmallVectorImpl<ISD::InputArg> &Ins,
1066 DebugLoc dl, SelectionDAG &DAG,
1067 SmallVectorImpl<SDValue> &InVals) const {
1069 // Assign locations to each value returned by this call.
1070 SmallVector<CCValAssign, 16> RVLocs;
1071 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1072 RVLocs, *DAG.getContext());
1073 CCInfo.AnalyzeCallResult(Ins,
1074 CCAssignFnForNode(CallConv, /* Return*/ true,
1077 // Copy all of the result registers out of their specified physreg.
1078 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1079 CCValAssign VA = RVLocs[i];
1082 if (VA.needsCustom()) {
1083 // Handle f64 or half of a v2f64.
1084 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1086 Chain = Lo.getValue(1);
1087 InFlag = Lo.getValue(2);
1088 VA = RVLocs[++i]; // skip ahead to next loc
1089 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1091 Chain = Hi.getValue(1);
1092 InFlag = Hi.getValue(2);
1093 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1095 if (VA.getLocVT() == MVT::v2f64) {
1096 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1097 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1098 DAG.getConstant(0, MVT::i32));
1100 VA = RVLocs[++i]; // skip ahead to next loc
1101 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1102 Chain = Lo.getValue(1);
1103 InFlag = Lo.getValue(2);
1104 VA = RVLocs[++i]; // skip ahead to next loc
1105 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1106 Chain = Hi.getValue(1);
1107 InFlag = Hi.getValue(2);
1108 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1109 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1110 DAG.getConstant(1, MVT::i32));
1113 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1115 Chain = Val.getValue(1);
1116 InFlag = Val.getValue(2);
1119 switch (VA.getLocInfo()) {
1120 default: llvm_unreachable("Unknown loc info!");
1121 case CCValAssign::Full: break;
1122 case CCValAssign::BCvt:
1123 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1127 InVals.push_back(Val);
1133 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1134 /// by "Src" to address "Dst" of size "Size". Alignment information is
1135 /// specified by the specific parameter attribute. The copy will be passed as
1136 /// a byval function parameter.
1137 /// Sometimes what we are copying is the end of a larger object, the part that
1138 /// does not fit in registers.
1140 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1141 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1143 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1144 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1145 /*isVolatile=*/false, /*AlwaysInline=*/false,
1146 MachinePointerInfo(0), MachinePointerInfo(0));
1149 /// LowerMemOpCallTo - Store the argument to the stack.
1151 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1152 SDValue StackPtr, SDValue Arg,
1153 DebugLoc dl, SelectionDAG &DAG,
1154 const CCValAssign &VA,
1155 ISD::ArgFlagsTy Flags) const {
1156 unsigned LocMemOffset = VA.getLocMemOffset();
1157 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1158 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1159 if (Flags.isByVal())
1160 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1162 return DAG.getStore(Chain, dl, Arg, PtrOff,
1163 MachinePointerInfo::getStack(LocMemOffset),
1167 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1168 SDValue Chain, SDValue &Arg,
1169 RegsToPassVector &RegsToPass,
1170 CCValAssign &VA, CCValAssign &NextVA,
1172 SmallVector<SDValue, 8> &MemOpChains,
1173 ISD::ArgFlagsTy Flags) const {
1175 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1176 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1177 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1179 if (NextVA.isRegLoc())
1180 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1182 assert(NextVA.isMemLoc());
1183 if (StackPtr.getNode() == 0)
1184 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1186 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1192 /// LowerCall - Lowering a call into a callseq_start <-
1193 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1196 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1197 CallingConv::ID CallConv, bool isVarArg,
1199 const SmallVectorImpl<ISD::OutputArg> &Outs,
1200 const SmallVectorImpl<SDValue> &OutVals,
1201 const SmallVectorImpl<ISD::InputArg> &Ins,
1202 DebugLoc dl, SelectionDAG &DAG,
1203 SmallVectorImpl<SDValue> &InVals) const {
1204 MachineFunction &MF = DAG.getMachineFunction();
1205 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1206 bool IsSibCall = false;
1207 // Temporarily disable tail calls so things don't break.
1208 if (!EnableARMTailCalls)
1211 // Check if it's really possible to do a tail call.
1212 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1213 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1214 Outs, OutVals, Ins, DAG);
1215 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1216 // detected sibcalls.
1223 // Analyze operands of the call, assigning locations to each operand.
1224 SmallVector<CCValAssign, 16> ArgLocs;
1225 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1227 CCInfo.AnalyzeCallOperands(Outs,
1228 CCAssignFnForNode(CallConv, /* Return*/ false,
1231 // Get a count of how many bytes are to be pushed on the stack.
1232 unsigned NumBytes = CCInfo.getNextStackOffset();
1234 // For tail calls, memory operands are available in our caller's stack.
1238 // Adjust the stack pointer for the new arguments...
1239 // These operations are automatically eliminated by the prolog/epilog pass
1241 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1243 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1245 RegsToPassVector RegsToPass;
1246 SmallVector<SDValue, 8> MemOpChains;
1248 // Walk the register/memloc assignments, inserting copies/loads. In the case
1249 // of tail call optimization, arguments are handled later.
1250 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1252 ++i, ++realArgIdx) {
1253 CCValAssign &VA = ArgLocs[i];
1254 SDValue Arg = OutVals[realArgIdx];
1255 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1257 // Promote the value if needed.
1258 switch (VA.getLocInfo()) {
1259 default: llvm_unreachable("Unknown loc info!");
1260 case CCValAssign::Full: break;
1261 case CCValAssign::SExt:
1262 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1264 case CCValAssign::ZExt:
1265 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1267 case CCValAssign::AExt:
1268 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1270 case CCValAssign::BCvt:
1271 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1275 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1276 if (VA.needsCustom()) {
1277 if (VA.getLocVT() == MVT::v2f64) {
1278 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1279 DAG.getConstant(0, MVT::i32));
1280 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1281 DAG.getConstant(1, MVT::i32));
1283 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1284 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1286 VA = ArgLocs[++i]; // skip ahead to next loc
1287 if (VA.isRegLoc()) {
1288 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1289 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1291 assert(VA.isMemLoc());
1293 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1294 dl, DAG, VA, Flags));
1297 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1298 StackPtr, MemOpChains, Flags);
1300 } else if (VA.isRegLoc()) {
1301 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1302 } else if (!IsSibCall) {
1303 assert(VA.isMemLoc());
1305 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1306 dl, DAG, VA, Flags));
1310 if (!MemOpChains.empty())
1311 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1312 &MemOpChains[0], MemOpChains.size());
1314 // Build a sequence of copy-to-reg nodes chained together with token chain
1315 // and flag operands which copy the outgoing args into the appropriate regs.
1317 // Tail call byval lowering might overwrite argument registers so in case of
1318 // tail call optimization the copies to registers are lowered later.
1320 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1321 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1322 RegsToPass[i].second, InFlag);
1323 InFlag = Chain.getValue(1);
1326 // For tail calls lower the arguments to the 'real' stack slot.
1328 // Force all the incoming stack arguments to be loaded from the stack
1329 // before any new outgoing arguments are stored to the stack, because the
1330 // outgoing stack slots may alias the incoming argument stack slots, and
1331 // the alias isn't otherwise explicit. This is slightly more conservative
1332 // than necessary, because it means that each store effectively depends
1333 // on every argument instead of just those arguments it would clobber.
1335 // Do not flag preceeding copytoreg stuff together with the following stuff.
1337 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1338 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1339 RegsToPass[i].second, InFlag);
1340 InFlag = Chain.getValue(1);
1345 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1346 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1347 // node so that legalize doesn't hack it.
1348 bool isDirect = false;
1349 bool isARMFunc = false;
1350 bool isLocalARMFunc = false;
1351 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1353 if (EnableARMLongCalls) {
1354 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1355 && "long-calls with non-static relocation model!");
1356 // Handle a global address or an external symbol. If it's not one of
1357 // those, the target's already in a register, so we don't need to do
1359 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1360 const GlobalValue *GV = G->getGlobal();
1361 // Create a constant pool entry for the callee address
1362 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1363 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1366 // Get the address of the callee into a register
1367 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1368 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1369 Callee = DAG.getLoad(getPointerTy(), dl,
1370 DAG.getEntryNode(), CPAddr,
1371 MachinePointerInfo::getConstantPool(),
1373 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1374 const char *Sym = S->getSymbol();
1376 // Create a constant pool entry for the callee address
1377 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1378 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1379 Sym, ARMPCLabelIndex, 0);
1380 // Get the address of the callee into a register
1381 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1382 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1383 Callee = DAG.getLoad(getPointerTy(), dl,
1384 DAG.getEntryNode(), CPAddr,
1385 MachinePointerInfo::getConstantPool(),
1388 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1389 const GlobalValue *GV = G->getGlobal();
1391 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1392 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1393 getTargetMachine().getRelocationModel() != Reloc::Static;
1394 isARMFunc = !Subtarget->isThumb() || isStub;
1395 // ARM call to a local ARM function is predicable.
1396 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1397 // tBX takes a register source operand.
1398 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1399 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1400 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1403 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1404 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1405 Callee = DAG.getLoad(getPointerTy(), dl,
1406 DAG.getEntryNode(), CPAddr,
1407 MachinePointerInfo::getConstantPool(),
1409 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1410 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1411 getPointerTy(), Callee, PICLabel);
1413 // On ELF targets for PIC code, direct calls should go through the PLT
1414 unsigned OpFlags = 0;
1415 if (Subtarget->isTargetELF() &&
1416 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1417 OpFlags = ARMII::MO_PLT;
1418 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1420 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1422 bool isStub = Subtarget->isTargetDarwin() &&
1423 getTargetMachine().getRelocationModel() != Reloc::Static;
1424 isARMFunc = !Subtarget->isThumb() || isStub;
1425 // tBX takes a register source operand.
1426 const char *Sym = S->getSymbol();
1427 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1428 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1429 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1430 Sym, ARMPCLabelIndex, 4);
1431 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1432 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1433 Callee = DAG.getLoad(getPointerTy(), dl,
1434 DAG.getEntryNode(), CPAddr,
1435 MachinePointerInfo::getConstantPool(),
1437 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1438 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1439 getPointerTy(), Callee, PICLabel);
1441 unsigned OpFlags = 0;
1442 // On ELF targets for PIC code, direct calls should go through the PLT
1443 if (Subtarget->isTargetELF() &&
1444 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1445 OpFlags = ARMII::MO_PLT;
1446 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1450 // FIXME: handle tail calls differently.
1452 if (Subtarget->isThumb()) {
1453 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1454 CallOpc = ARMISD::CALL_NOLINK;
1456 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1458 CallOpc = (isDirect || Subtarget->hasV5TOps())
1459 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1460 : ARMISD::CALL_NOLINK;
1463 std::vector<SDValue> Ops;
1464 Ops.push_back(Chain);
1465 Ops.push_back(Callee);
1467 // Add argument registers to the end of the list so that they are known live
1469 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1470 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1471 RegsToPass[i].second.getValueType()));
1473 if (InFlag.getNode())
1474 Ops.push_back(InFlag);
1476 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1478 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1480 // Returns a chain and a flag for retval copy to use.
1481 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1482 InFlag = Chain.getValue(1);
1484 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1485 DAG.getIntPtrConstant(0, true), InFlag);
1487 InFlag = Chain.getValue(1);
1489 // Handle result values, copying them out of physregs into vregs that we
1491 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1495 /// MatchingStackOffset - Return true if the given stack call argument is
1496 /// already available in the same position (relatively) of the caller's
1497 /// incoming argument stack.
1499 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1500 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1501 const ARMInstrInfo *TII) {
1502 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1504 if (Arg.getOpcode() == ISD::CopyFromReg) {
1505 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1506 if (!TargetRegisterInfo::isVirtualRegister(VR))
1508 MachineInstr *Def = MRI->getVRegDef(VR);
1511 if (!Flags.isByVal()) {
1512 if (!TII->isLoadFromStackSlot(Def, FI))
1517 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1518 if (Flags.isByVal())
1519 // ByVal argument is passed in as a pointer but it's now being
1520 // dereferenced. e.g.
1521 // define @foo(%struct.X* %A) {
1522 // tail call @bar(%struct.X* byval %A)
1525 SDValue Ptr = Ld->getBasePtr();
1526 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1529 FI = FINode->getIndex();
1533 assert(FI != INT_MAX);
1534 if (!MFI->isFixedObjectIndex(FI))
1536 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1539 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1540 /// for tail call optimization. Targets which want to do tail call
1541 /// optimization should implement this function.
1543 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1544 CallingConv::ID CalleeCC,
1546 bool isCalleeStructRet,
1547 bool isCallerStructRet,
1548 const SmallVectorImpl<ISD::OutputArg> &Outs,
1549 const SmallVectorImpl<SDValue> &OutVals,
1550 const SmallVectorImpl<ISD::InputArg> &Ins,
1551 SelectionDAG& DAG) const {
1552 const Function *CallerF = DAG.getMachineFunction().getFunction();
1553 CallingConv::ID CallerCC = CallerF->getCallingConv();
1554 bool CCMatch = CallerCC == CalleeCC;
1556 // Look for obvious safe cases to perform tail call optimization that do not
1557 // require ABI changes. This is what gcc calls sibcall.
1559 // Do not sibcall optimize vararg calls unless the call site is not passing
1561 if (isVarArg && !Outs.empty())
1564 // Also avoid sibcall optimization if either caller or callee uses struct
1565 // return semantics.
1566 if (isCalleeStructRet || isCallerStructRet)
1569 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1570 // emitEpilogue is not ready for them.
1571 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1572 // LR. This means if we need to reload LR, it takes an extra instructions,
1573 // which outweighs the value of the tail call; but here we don't know yet
1574 // whether LR is going to be used. Probably the right approach is to
1575 // generate the tail call here and turn it back into CALL/RET in
1576 // emitEpilogue if LR is used.
1578 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1579 // but we need to make sure there are enough registers; the only valid
1580 // registers are the 4 used for parameters. We don't currently do this
1582 if (Subtarget->isThumb1Only())
1585 // If the calling conventions do not match, then we'd better make sure the
1586 // results are returned in the same way as what the caller expects.
1588 SmallVector<CCValAssign, 16> RVLocs1;
1589 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1590 RVLocs1, *DAG.getContext());
1591 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1593 SmallVector<CCValAssign, 16> RVLocs2;
1594 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1595 RVLocs2, *DAG.getContext());
1596 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1598 if (RVLocs1.size() != RVLocs2.size())
1600 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1601 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1603 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1605 if (RVLocs1[i].isRegLoc()) {
1606 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1609 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1615 // If the callee takes no arguments then go on to check the results of the
1617 if (!Outs.empty()) {
1618 // Check if stack adjustment is needed. For now, do not do this if any
1619 // argument is passed on the stack.
1620 SmallVector<CCValAssign, 16> ArgLocs;
1621 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1622 ArgLocs, *DAG.getContext());
1623 CCInfo.AnalyzeCallOperands(Outs,
1624 CCAssignFnForNode(CalleeCC, false, isVarArg));
1625 if (CCInfo.getNextStackOffset()) {
1626 MachineFunction &MF = DAG.getMachineFunction();
1628 // Check if the arguments are already laid out in the right way as
1629 // the caller's fixed stack objects.
1630 MachineFrameInfo *MFI = MF.getFrameInfo();
1631 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1632 const ARMInstrInfo *TII =
1633 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1634 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1636 ++i, ++realArgIdx) {
1637 CCValAssign &VA = ArgLocs[i];
1638 EVT RegVT = VA.getLocVT();
1639 SDValue Arg = OutVals[realArgIdx];
1640 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1641 if (VA.getLocInfo() == CCValAssign::Indirect)
1643 if (VA.needsCustom()) {
1644 // f64 and vector types are split into multiple registers or
1645 // register/stack-slot combinations. The types will not match
1646 // the registers; give up on memory f64 refs until we figure
1647 // out what to do about this.
1650 if (!ArgLocs[++i].isRegLoc())
1652 if (RegVT == MVT::v2f64) {
1653 if (!ArgLocs[++i].isRegLoc())
1655 if (!ArgLocs[++i].isRegLoc())
1658 } else if (!VA.isRegLoc()) {
1659 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1671 ARMTargetLowering::LowerReturn(SDValue Chain,
1672 CallingConv::ID CallConv, bool isVarArg,
1673 const SmallVectorImpl<ISD::OutputArg> &Outs,
1674 const SmallVectorImpl<SDValue> &OutVals,
1675 DebugLoc dl, SelectionDAG &DAG) const {
1677 // CCValAssign - represent the assignment of the return value to a location.
1678 SmallVector<CCValAssign, 16> RVLocs;
1680 // CCState - Info about the registers and stack slots.
1681 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1684 // Analyze outgoing return values.
1685 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1688 // If this is the first return lowered for this function, add
1689 // the regs to the liveout set for the function.
1690 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1691 for (unsigned i = 0; i != RVLocs.size(); ++i)
1692 if (RVLocs[i].isRegLoc())
1693 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1698 // Copy the result values into the output registers.
1699 for (unsigned i = 0, realRVLocIdx = 0;
1701 ++i, ++realRVLocIdx) {
1702 CCValAssign &VA = RVLocs[i];
1703 assert(VA.isRegLoc() && "Can only return in registers!");
1705 SDValue Arg = OutVals[realRVLocIdx];
1707 switch (VA.getLocInfo()) {
1708 default: llvm_unreachable("Unknown loc info!");
1709 case CCValAssign::Full: break;
1710 case CCValAssign::BCvt:
1711 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1715 if (VA.needsCustom()) {
1716 if (VA.getLocVT() == MVT::v2f64) {
1717 // Extract the first half and return it in two registers.
1718 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1719 DAG.getConstant(0, MVT::i32));
1720 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1721 DAG.getVTList(MVT::i32, MVT::i32), Half);
1723 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1724 Flag = Chain.getValue(1);
1725 VA = RVLocs[++i]; // skip ahead to next loc
1726 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1727 HalfGPRs.getValue(1), Flag);
1728 Flag = Chain.getValue(1);
1729 VA = RVLocs[++i]; // skip ahead to next loc
1731 // Extract the 2nd half and fall through to handle it as an f64 value.
1732 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1733 DAG.getConstant(1, MVT::i32));
1735 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1737 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1738 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1739 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1740 Flag = Chain.getValue(1);
1741 VA = RVLocs[++i]; // skip ahead to next loc
1742 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1745 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1747 // Guarantee that all emitted copies are
1748 // stuck together, avoiding something bad.
1749 Flag = Chain.getValue(1);
1754 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1756 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1761 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1762 if (N->getNumValues() != 1)
1764 if (!N->hasNUsesOfValue(1, 0))
1767 unsigned NumCopies = 0;
1769 SDNode *Use = *N->use_begin();
1770 if (Use->getOpcode() == ISD::CopyToReg) {
1771 Copies[NumCopies++] = Use;
1772 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1773 // f64 returned in a pair of GPRs.
1774 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1776 if (UI->getOpcode() != ISD::CopyToReg)
1778 Copies[UI.getUse().getResNo()] = *UI;
1781 } else if (Use->getOpcode() == ISD::BITCAST) {
1782 // f32 returned in a single GPR.
1783 if (!Use->hasNUsesOfValue(1, 0))
1785 Use = *Use->use_begin();
1786 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1788 Copies[NumCopies++] = Use;
1793 if (NumCopies != 1 && NumCopies != 2)
1796 bool HasRet = false;
1797 for (unsigned i = 0; i < NumCopies; ++i) {
1798 SDNode *Copy = Copies[i];
1799 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1801 if (UI->getOpcode() == ISD::CopyToReg) {
1803 if (Use == Copies[0] || Use == Copies[1])
1807 if (UI->getOpcode() != ARMISD::RET_FLAG)
1816 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1817 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1818 // one of the above mentioned nodes. It has to be wrapped because otherwise
1819 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1820 // be used to form addressing mode. These wrapped nodes will be selected
1822 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1823 EVT PtrVT = Op.getValueType();
1824 // FIXME there is no actual debug info here
1825 DebugLoc dl = Op.getDebugLoc();
1826 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1828 if (CP->isMachineConstantPoolEntry())
1829 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1830 CP->getAlignment());
1832 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1833 CP->getAlignment());
1834 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1837 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1838 return MachineJumpTableInfo::EK_Inline;
1841 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1842 SelectionDAG &DAG) const {
1843 MachineFunction &MF = DAG.getMachineFunction();
1844 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1845 unsigned ARMPCLabelIndex = 0;
1846 DebugLoc DL = Op.getDebugLoc();
1847 EVT PtrVT = getPointerTy();
1848 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1849 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1851 if (RelocM == Reloc::Static) {
1852 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1854 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1855 ARMPCLabelIndex = AFI->createPICLabelUId();
1856 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1857 ARMCP::CPBlockAddress,
1859 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1861 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1862 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1863 MachinePointerInfo::getConstantPool(),
1865 if (RelocM == Reloc::Static)
1867 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1868 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1871 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1873 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1874 SelectionDAG &DAG) const {
1875 DebugLoc dl = GA->getDebugLoc();
1876 EVT PtrVT = getPointerTy();
1877 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1878 MachineFunction &MF = DAG.getMachineFunction();
1879 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1880 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1881 ARMConstantPoolValue *CPV =
1882 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1883 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1884 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1885 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1886 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1887 MachinePointerInfo::getConstantPool(),
1889 SDValue Chain = Argument.getValue(1);
1891 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1892 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1894 // call __tls_get_addr.
1897 Entry.Node = Argument;
1898 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1899 Args.push_back(Entry);
1900 // FIXME: is there useful debug info available here?
1901 std::pair<SDValue, SDValue> CallResult =
1902 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1903 false, false, false, false,
1904 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1905 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1906 return CallResult.first;
1909 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1910 // "local exec" model.
1912 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1913 SelectionDAG &DAG) const {
1914 const GlobalValue *GV = GA->getGlobal();
1915 DebugLoc dl = GA->getDebugLoc();
1917 SDValue Chain = DAG.getEntryNode();
1918 EVT PtrVT = getPointerTy();
1919 // Get the Thread Pointer
1920 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1922 if (GV->isDeclaration()) {
1923 MachineFunction &MF = DAG.getMachineFunction();
1924 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1925 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1926 // Initial exec model.
1927 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1928 ARMConstantPoolValue *CPV =
1929 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1930 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1931 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1932 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1933 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1934 MachinePointerInfo::getConstantPool(),
1936 Chain = Offset.getValue(1);
1938 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1939 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1941 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1942 MachinePointerInfo::getConstantPool(),
1946 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1947 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1948 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1949 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1950 MachinePointerInfo::getConstantPool(),
1954 // The address of the thread local variable is the add of the thread
1955 // pointer with the offset of the variable.
1956 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1960 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1961 // TODO: implement the "local dynamic" model
1962 assert(Subtarget->isTargetELF() &&
1963 "TLS not implemented for non-ELF targets");
1964 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1965 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1966 // otherwise use the "Local Exec" TLS Model
1967 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1968 return LowerToTLSGeneralDynamicModel(GA, DAG);
1970 return LowerToTLSExecModels(GA, DAG);
1973 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1974 SelectionDAG &DAG) const {
1975 EVT PtrVT = getPointerTy();
1976 DebugLoc dl = Op.getDebugLoc();
1977 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1978 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1979 if (RelocM == Reloc::PIC_) {
1980 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1981 ARMConstantPoolValue *CPV =
1982 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1983 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1984 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1985 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1987 MachinePointerInfo::getConstantPool(),
1989 SDValue Chain = Result.getValue(1);
1990 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1991 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1993 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1994 MachinePointerInfo::getGOT(), false, false, 0);
1998 // If we have T2 ops, we can materialize the address directly via movt/movw
1999 // pair. This is always cheaper.
2000 if (Subtarget->useMovt()) {
2002 // FIXME: Once remat is capable of dealing with instructions with register
2003 // operands, expand this into two nodes.
2004 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2005 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2007 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2008 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2009 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2010 MachinePointerInfo::getConstantPool(),
2015 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2016 SelectionDAG &DAG) const {
2017 EVT PtrVT = getPointerTy();
2018 DebugLoc dl = Op.getDebugLoc();
2019 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2020 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2021 MachineFunction &MF = DAG.getMachineFunction();
2022 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2024 if (Subtarget->useMovt()) {
2026 // FIXME: Once remat is capable of dealing with instructions with register
2027 // operands, expand this into two nodes.
2028 if (RelocM == Reloc::Static)
2029 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2030 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2032 unsigned Wrapper = (RelocM == Reloc::PIC_)
2033 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2034 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2035 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2036 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2037 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2038 MachinePointerInfo::getGOT(), false, false, 0);
2042 unsigned ARMPCLabelIndex = 0;
2044 if (RelocM == Reloc::Static) {
2045 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2047 ARMPCLabelIndex = AFI->createPICLabelUId();
2048 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2049 ARMConstantPoolValue *CPV =
2050 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2051 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2053 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2055 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2056 MachinePointerInfo::getConstantPool(),
2058 SDValue Chain = Result.getValue(1);
2060 if (RelocM == Reloc::PIC_) {
2061 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2062 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2065 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2066 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2072 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2073 SelectionDAG &DAG) const {
2074 assert(Subtarget->isTargetELF() &&
2075 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2076 MachineFunction &MF = DAG.getMachineFunction();
2077 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2078 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2079 EVT PtrVT = getPointerTy();
2080 DebugLoc dl = Op.getDebugLoc();
2081 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2082 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2083 "_GLOBAL_OFFSET_TABLE_",
2084 ARMPCLabelIndex, PCAdj);
2085 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2086 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2087 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2088 MachinePointerInfo::getConstantPool(),
2090 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2091 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2095 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2097 DebugLoc dl = Op.getDebugLoc();
2098 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2099 Op.getOperand(0), Op.getOperand(1));
2103 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2104 DebugLoc dl = Op.getDebugLoc();
2105 SDValue Val = DAG.getConstant(0, MVT::i32);
2106 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2107 Op.getOperand(1), Val);
2111 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2112 DebugLoc dl = Op.getDebugLoc();
2113 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2114 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2118 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2119 const ARMSubtarget *Subtarget) const {
2120 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2121 DebugLoc dl = Op.getDebugLoc();
2123 default: return SDValue(); // Don't custom lower most intrinsics.
2124 case Intrinsic::arm_thread_pointer: {
2125 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2126 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2128 case Intrinsic::eh_sjlj_lsda: {
2129 MachineFunction &MF = DAG.getMachineFunction();
2130 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2131 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2132 EVT PtrVT = getPointerTy();
2133 DebugLoc dl = Op.getDebugLoc();
2134 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2136 unsigned PCAdj = (RelocM != Reloc::PIC_)
2137 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2138 ARMConstantPoolValue *CPV =
2139 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2140 ARMCP::CPLSDA, PCAdj);
2141 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2142 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2144 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2145 MachinePointerInfo::getConstantPool(),
2148 if (RelocM == Reloc::PIC_) {
2149 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2150 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2157 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2158 const ARMSubtarget *Subtarget) {
2159 DebugLoc dl = Op.getDebugLoc();
2160 if (!Subtarget->hasDataBarrier()) {
2161 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2162 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2164 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2165 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2166 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2167 DAG.getConstant(0, MVT::i32));
2170 SDValue Op5 = Op.getOperand(5);
2171 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2172 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2173 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2174 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2176 ARM_MB::MemBOpt DMBOpt;
2177 if (isDeviceBarrier)
2178 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2180 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2181 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2182 DAG.getConstant(DMBOpt, MVT::i32));
2185 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2186 const ARMSubtarget *Subtarget) {
2187 // ARM pre v5TE and Thumb1 does not have preload instructions.
2188 if (!(Subtarget->isThumb2() ||
2189 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2190 // Just preserve the chain.
2191 return Op.getOperand(0);
2193 DebugLoc dl = Op.getDebugLoc();
2194 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2196 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2197 // ARMv7 with MP extension has PLDW.
2198 return Op.getOperand(0);
2200 if (Subtarget->isThumb())
2202 isRead = ~isRead & 1;
2203 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2205 // Currently there is no intrinsic that matches pli.
2206 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2207 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2208 DAG.getConstant(isData, MVT::i32));
2211 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2212 MachineFunction &MF = DAG.getMachineFunction();
2213 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2215 // vastart just stores the address of the VarArgsFrameIndex slot into the
2216 // memory location argument.
2217 DebugLoc dl = Op.getDebugLoc();
2218 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2219 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2220 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2221 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2222 MachinePointerInfo(SV), false, false, 0);
2226 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2227 SDValue &Root, SelectionDAG &DAG,
2228 DebugLoc dl) const {
2229 MachineFunction &MF = DAG.getMachineFunction();
2230 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2232 TargetRegisterClass *RC;
2233 if (AFI->isThumb1OnlyFunction())
2234 RC = ARM::tGPRRegisterClass;
2236 RC = ARM::GPRRegisterClass;
2238 // Transform the arguments stored in physical registers into virtual ones.
2239 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2240 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2243 if (NextVA.isMemLoc()) {
2244 MachineFrameInfo *MFI = MF.getFrameInfo();
2245 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2247 // Create load node to retrieve arguments from the stack.
2248 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2249 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2250 MachinePointerInfo::getFixedStack(FI),
2253 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2254 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2257 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2261 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2262 CallingConv::ID CallConv, bool isVarArg,
2263 const SmallVectorImpl<ISD::InputArg>
2265 DebugLoc dl, SelectionDAG &DAG,
2266 SmallVectorImpl<SDValue> &InVals)
2269 MachineFunction &MF = DAG.getMachineFunction();
2270 MachineFrameInfo *MFI = MF.getFrameInfo();
2272 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2274 // Assign locations to all of the incoming arguments.
2275 SmallVector<CCValAssign, 16> ArgLocs;
2276 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2278 CCInfo.AnalyzeFormalArguments(Ins,
2279 CCAssignFnForNode(CallConv, /* Return*/ false,
2282 SmallVector<SDValue, 16> ArgValues;
2284 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2285 CCValAssign &VA = ArgLocs[i];
2287 // Arguments stored in registers.
2288 if (VA.isRegLoc()) {
2289 EVT RegVT = VA.getLocVT();
2292 if (VA.needsCustom()) {
2293 // f64 and vector types are split up into multiple registers or
2294 // combinations of registers and stack slots.
2295 if (VA.getLocVT() == MVT::v2f64) {
2296 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2298 VA = ArgLocs[++i]; // skip ahead to next loc
2300 if (VA.isMemLoc()) {
2301 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2302 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2303 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2304 MachinePointerInfo::getFixedStack(FI),
2307 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2310 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2311 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2312 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2313 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2314 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2316 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2319 TargetRegisterClass *RC;
2321 if (RegVT == MVT::f32)
2322 RC = ARM::SPRRegisterClass;
2323 else if (RegVT == MVT::f64)
2324 RC = ARM::DPRRegisterClass;
2325 else if (RegVT == MVT::v2f64)
2326 RC = ARM::QPRRegisterClass;
2327 else if (RegVT == MVT::i32)
2328 RC = (AFI->isThumb1OnlyFunction() ?
2329 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2331 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2333 // Transform the arguments in physical registers into virtual ones.
2334 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2335 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2338 // If this is an 8 or 16-bit value, it is really passed promoted
2339 // to 32 bits. Insert an assert[sz]ext to capture this, then
2340 // truncate to the right size.
2341 switch (VA.getLocInfo()) {
2342 default: llvm_unreachable("Unknown loc info!");
2343 case CCValAssign::Full: break;
2344 case CCValAssign::BCvt:
2345 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2347 case CCValAssign::SExt:
2348 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2349 DAG.getValueType(VA.getValVT()));
2350 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2352 case CCValAssign::ZExt:
2353 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2354 DAG.getValueType(VA.getValVT()));
2355 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2359 InVals.push_back(ArgValue);
2361 } else { // VA.isRegLoc()
2364 assert(VA.isMemLoc());
2365 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2367 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2368 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2370 // Create load nodes to retrieve arguments from the stack.
2371 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2372 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2373 MachinePointerInfo::getFixedStack(FI),
2380 static const unsigned GPRArgRegs[] = {
2381 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2384 unsigned NumGPRs = CCInfo.getFirstUnallocated
2385 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2387 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2388 unsigned VARegSize = (4 - NumGPRs) * 4;
2389 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2390 unsigned ArgOffset = CCInfo.getNextStackOffset();
2391 if (VARegSaveSize) {
2392 // If this function is vararg, store any remaining integer argument regs
2393 // to their spots on the stack so that they may be loaded by deferencing
2394 // the result of va_next.
2395 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2396 AFI->setVarArgsFrameIndex(
2397 MFI->CreateFixedObject(VARegSaveSize,
2398 ArgOffset + VARegSaveSize - VARegSize,
2400 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2403 SmallVector<SDValue, 4> MemOps;
2404 for (; NumGPRs < 4; ++NumGPRs) {
2405 TargetRegisterClass *RC;
2406 if (AFI->isThumb1OnlyFunction())
2407 RC = ARM::tGPRRegisterClass;
2409 RC = ARM::GPRRegisterClass;
2411 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2412 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2414 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2415 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2417 MemOps.push_back(Store);
2418 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2419 DAG.getConstant(4, getPointerTy()));
2421 if (!MemOps.empty())
2422 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2423 &MemOps[0], MemOps.size());
2425 // This will point to the next argument passed via stack.
2426 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2432 /// isFloatingPointZero - Return true if this is +0.0.
2433 static bool isFloatingPointZero(SDValue Op) {
2434 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2435 return CFP->getValueAPF().isPosZero();
2436 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2437 // Maybe this has already been legalized into the constant pool?
2438 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2439 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2440 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2441 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2442 return CFP->getValueAPF().isPosZero();
2448 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2449 /// the given operands.
2451 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2452 SDValue &ARMcc, SelectionDAG &DAG,
2453 DebugLoc dl) const {
2454 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2455 unsigned C = RHSC->getZExtValue();
2456 if (!isLegalICmpImmediate(C)) {
2457 // Constant does not fit, try adjusting it by one?
2462 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2463 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2464 RHS = DAG.getConstant(C-1, MVT::i32);
2469 if (C != 0 && isLegalICmpImmediate(C-1)) {
2470 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2471 RHS = DAG.getConstant(C-1, MVT::i32);
2476 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2477 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2478 RHS = DAG.getConstant(C+1, MVT::i32);
2483 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2484 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2485 RHS = DAG.getConstant(C+1, MVT::i32);
2492 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2493 ARMISD::NodeType CompareType;
2496 CompareType = ARMISD::CMP;
2501 CompareType = ARMISD::CMPZ;
2504 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2505 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2508 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2510 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2511 DebugLoc dl) const {
2513 if (!isFloatingPointZero(RHS))
2514 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2516 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2517 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2520 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2521 SDValue Cond = Op.getOperand(0);
2522 SDValue SelectTrue = Op.getOperand(1);
2523 SDValue SelectFalse = Op.getOperand(2);
2524 DebugLoc dl = Op.getDebugLoc();
2528 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2529 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2531 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2532 const ConstantSDNode *CMOVTrue =
2533 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2534 const ConstantSDNode *CMOVFalse =
2535 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2537 if (CMOVTrue && CMOVFalse) {
2538 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2539 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2543 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2545 False = SelectFalse;
2546 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2551 if (True.getNode() && False.getNode()) {
2552 EVT VT = Cond.getValueType();
2553 SDValue ARMcc = Cond.getOperand(2);
2554 SDValue CCR = Cond.getOperand(3);
2555 SDValue Cmp = Cond.getOperand(4);
2556 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2561 return DAG.getSelectCC(dl, Cond,
2562 DAG.getConstant(0, Cond.getValueType()),
2563 SelectTrue, SelectFalse, ISD::SETNE);
2566 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2567 EVT VT = Op.getValueType();
2568 SDValue LHS = Op.getOperand(0);
2569 SDValue RHS = Op.getOperand(1);
2570 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2571 SDValue TrueVal = Op.getOperand(2);
2572 SDValue FalseVal = Op.getOperand(3);
2573 DebugLoc dl = Op.getDebugLoc();
2575 if (LHS.getValueType() == MVT::i32) {
2577 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2578 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2579 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2582 ARMCC::CondCodes CondCode, CondCode2;
2583 FPCCToARMCC(CC, CondCode, CondCode2);
2585 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2586 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2587 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2588 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2590 if (CondCode2 != ARMCC::AL) {
2591 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2592 // FIXME: Needs another CMP because flag can have but one use.
2593 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2594 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2595 Result, TrueVal, ARMcc2, CCR, Cmp2);
2600 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2601 /// to morph to an integer compare sequence.
2602 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2603 const ARMSubtarget *Subtarget) {
2604 SDNode *N = Op.getNode();
2605 if (!N->hasOneUse())
2606 // Otherwise it requires moving the value from fp to integer registers.
2608 if (!N->getNumValues())
2610 EVT VT = Op.getValueType();
2611 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2612 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2613 // vmrs are very slow, e.g. cortex-a8.
2616 if (isFloatingPointZero(Op)) {
2620 return ISD::isNormalLoad(N);
2623 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2624 if (isFloatingPointZero(Op))
2625 return DAG.getConstant(0, MVT::i32);
2627 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2628 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2629 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2630 Ld->isVolatile(), Ld->isNonTemporal(),
2631 Ld->getAlignment());
2633 llvm_unreachable("Unknown VFP cmp argument!");
2636 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2637 SDValue &RetVal1, SDValue &RetVal2) {
2638 if (isFloatingPointZero(Op)) {
2639 RetVal1 = DAG.getConstant(0, MVT::i32);
2640 RetVal2 = DAG.getConstant(0, MVT::i32);
2644 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2645 SDValue Ptr = Ld->getBasePtr();
2646 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2647 Ld->getChain(), Ptr,
2648 Ld->getPointerInfo(),
2649 Ld->isVolatile(), Ld->isNonTemporal(),
2650 Ld->getAlignment());
2652 EVT PtrType = Ptr.getValueType();
2653 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2654 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2655 PtrType, Ptr, DAG.getConstant(4, PtrType));
2656 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2657 Ld->getChain(), NewPtr,
2658 Ld->getPointerInfo().getWithOffset(4),
2659 Ld->isVolatile(), Ld->isNonTemporal(),
2664 llvm_unreachable("Unknown VFP cmp argument!");
2667 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2668 /// f32 and even f64 comparisons to integer ones.
2670 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2671 SDValue Chain = Op.getOperand(0);
2672 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2673 SDValue LHS = Op.getOperand(2);
2674 SDValue RHS = Op.getOperand(3);
2675 SDValue Dest = Op.getOperand(4);
2676 DebugLoc dl = Op.getDebugLoc();
2678 bool SeenZero = false;
2679 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2680 canChangeToInt(RHS, SeenZero, Subtarget) &&
2681 // If one of the operand is zero, it's safe to ignore the NaN case since
2682 // we only care about equality comparisons.
2683 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2684 // If unsafe fp math optimization is enabled and there are no othter uses of
2685 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2686 // to an integer comparison.
2687 if (CC == ISD::SETOEQ)
2689 else if (CC == ISD::SETUNE)
2693 if (LHS.getValueType() == MVT::f32) {
2694 LHS = bitcastf32Toi32(LHS, DAG);
2695 RHS = bitcastf32Toi32(RHS, DAG);
2696 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2697 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2698 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2699 Chain, Dest, ARMcc, CCR, Cmp);
2704 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2705 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2706 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2707 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2708 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2709 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2710 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2716 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2717 SDValue Chain = Op.getOperand(0);
2718 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2719 SDValue LHS = Op.getOperand(2);
2720 SDValue RHS = Op.getOperand(3);
2721 SDValue Dest = Op.getOperand(4);
2722 DebugLoc dl = Op.getDebugLoc();
2724 if (LHS.getValueType() == MVT::i32) {
2726 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2727 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2728 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2729 Chain, Dest, ARMcc, CCR, Cmp);
2732 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2735 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2736 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2737 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2738 if (Result.getNode())
2742 ARMCC::CondCodes CondCode, CondCode2;
2743 FPCCToARMCC(CC, CondCode, CondCode2);
2745 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2746 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2747 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2748 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2749 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2750 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2751 if (CondCode2 != ARMCC::AL) {
2752 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2753 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2754 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2759 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2760 SDValue Chain = Op.getOperand(0);
2761 SDValue Table = Op.getOperand(1);
2762 SDValue Index = Op.getOperand(2);
2763 DebugLoc dl = Op.getDebugLoc();
2765 EVT PTy = getPointerTy();
2766 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2767 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2768 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2769 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2770 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2771 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2772 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2773 if (Subtarget->isThumb2()) {
2774 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2775 // which does another jump to the destination. This also makes it easier
2776 // to translate it to TBB / TBH later.
2777 // FIXME: This might not work if the function is extremely large.
2778 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2779 Addr, Op.getOperand(2), JTI, UId);
2781 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2782 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2783 MachinePointerInfo::getJumpTable(),
2785 Chain = Addr.getValue(1);
2786 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2787 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2789 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2790 MachinePointerInfo::getJumpTable(), false, false, 0);
2791 Chain = Addr.getValue(1);
2792 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2796 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2797 DebugLoc dl = Op.getDebugLoc();
2800 switch (Op.getOpcode()) {
2802 assert(0 && "Invalid opcode!");
2803 case ISD::FP_TO_SINT:
2804 Opc = ARMISD::FTOSI;
2806 case ISD::FP_TO_UINT:
2807 Opc = ARMISD::FTOUI;
2810 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2811 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2814 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2815 EVT VT = Op.getValueType();
2816 DebugLoc dl = Op.getDebugLoc();
2819 switch (Op.getOpcode()) {
2821 assert(0 && "Invalid opcode!");
2822 case ISD::SINT_TO_FP:
2823 Opc = ARMISD::SITOF;
2825 case ISD::UINT_TO_FP:
2826 Opc = ARMISD::UITOF;
2830 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2831 return DAG.getNode(Opc, dl, VT, Op);
2834 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2835 // Implement fcopysign with a fabs and a conditional fneg.
2836 SDValue Tmp0 = Op.getOperand(0);
2837 SDValue Tmp1 = Op.getOperand(1);
2838 DebugLoc dl = Op.getDebugLoc();
2839 EVT VT = Op.getValueType();
2840 EVT SrcVT = Tmp1.getValueType();
2841 bool F2IisFast = Subtarget->isCortexA9() ||
2842 Tmp0.getOpcode() == ISD::BITCAST || Tmp0.getOpcode() == ARMISD::VMOVDRR;
2844 // Bitcast operand 1 to i32.
2845 if (SrcVT == MVT::f64)
2846 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2847 &Tmp1, 1).getValue(1);
2848 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
2850 // If float to int conversion isn't going to be super expensive, then simply
2851 // or in the signbit.
2853 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
2854 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
2855 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
2856 if (VT == MVT::f32) {
2857 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
2858 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
2859 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
2860 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
2863 // f64: Or the high part with signbit and then combine two parts.
2864 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2866 SDValue Lo = Tmp0.getValue(0);
2867 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
2868 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
2869 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2872 // Remove the signbit of operand 0.
2873 Tmp0 = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2875 // If operand 1 signbit is one, then negate operand 0.
2877 SDValue Cmp = getARMCmp(Tmp1, DAG.getConstant(0, MVT::i32),
2878 ISD::SETLT, ARMcc, DAG, dl);
2879 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2880 return DAG.getNode(ARMISD::CNEG, dl, VT, Tmp0, Tmp0, ARMcc, CCR, Cmp);
2883 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2884 MachineFunction &MF = DAG.getMachineFunction();
2885 MachineFrameInfo *MFI = MF.getFrameInfo();
2886 MFI->setReturnAddressIsTaken(true);
2888 EVT VT = Op.getValueType();
2889 DebugLoc dl = Op.getDebugLoc();
2890 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2892 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2893 SDValue Offset = DAG.getConstant(4, MVT::i32);
2894 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2895 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2896 MachinePointerInfo(), false, false, 0);
2899 // Return LR, which contains the return address. Mark it an implicit live-in.
2900 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2901 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2904 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2905 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2906 MFI->setFrameAddressIsTaken(true);
2908 EVT VT = Op.getValueType();
2909 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2910 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2911 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2912 ? ARM::R7 : ARM::R11;
2913 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2915 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2916 MachinePointerInfo(),
2921 /// ExpandBITCAST - If the target supports VFP, this function is called to
2922 /// expand a bit convert where either the source or destination type is i64 to
2923 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2924 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2925 /// vectors), since the legalizer won't know what to do with that.
2926 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
2927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2928 DebugLoc dl = N->getDebugLoc();
2929 SDValue Op = N->getOperand(0);
2931 // This function is only supposed to be called for i64 types, either as the
2932 // source or destination of the bit convert.
2933 EVT SrcVT = Op.getValueType();
2934 EVT DstVT = N->getValueType(0);
2935 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2936 "ExpandBITCAST called for non-i64 type");
2938 // Turn i64->f64 into VMOVDRR.
2939 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2940 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2941 DAG.getConstant(0, MVT::i32));
2942 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2943 DAG.getConstant(1, MVT::i32));
2944 return DAG.getNode(ISD::BITCAST, dl, DstVT,
2945 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2948 // Turn f64->i64 into VMOVRRD.
2949 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2950 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2951 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2952 // Merge the pieces into a single i64 value.
2953 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2959 /// getZeroVector - Returns a vector of specified type with all zero elements.
2960 /// Zero vectors are used to represent vector negation and in those cases
2961 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2962 /// not support i64 elements, so sometimes the zero vectors will need to be
2963 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2965 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2966 assert(VT.isVector() && "Expected a vector type");
2967 // The canonical modified immediate encoding of a zero vector is....0!
2968 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2969 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2970 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2971 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
2974 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2975 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2976 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2977 SelectionDAG &DAG) const {
2978 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2979 EVT VT = Op.getValueType();
2980 unsigned VTBits = VT.getSizeInBits();
2981 DebugLoc dl = Op.getDebugLoc();
2982 SDValue ShOpLo = Op.getOperand(0);
2983 SDValue ShOpHi = Op.getOperand(1);
2984 SDValue ShAmt = Op.getOperand(2);
2986 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2988 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2990 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2991 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2992 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2993 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2994 DAG.getConstant(VTBits, MVT::i32));
2995 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2996 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2997 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2999 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3000 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3002 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3003 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3006 SDValue Ops[2] = { Lo, Hi };
3007 return DAG.getMergeValues(Ops, 2, dl);
3010 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3011 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3012 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3013 SelectionDAG &DAG) const {
3014 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3015 EVT VT = Op.getValueType();
3016 unsigned VTBits = VT.getSizeInBits();
3017 DebugLoc dl = Op.getDebugLoc();
3018 SDValue ShOpLo = Op.getOperand(0);
3019 SDValue ShOpHi = Op.getOperand(1);
3020 SDValue ShAmt = Op.getOperand(2);
3023 assert(Op.getOpcode() == ISD::SHL_PARTS);
3024 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3025 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3026 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3027 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3028 DAG.getConstant(VTBits, MVT::i32));
3029 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3030 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3032 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3033 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3034 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3036 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3037 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3040 SDValue Ops[2] = { Lo, Hi };
3041 return DAG.getMergeValues(Ops, 2, dl);
3044 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3045 SelectionDAG &DAG) const {
3046 // The rounding mode is in bits 23:22 of the FPSCR.
3047 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3048 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3049 // so that the shift + and get folded into a bitfield extract.
3050 DebugLoc dl = Op.getDebugLoc();
3051 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3052 DAG.getConstant(Intrinsic::arm_get_fpscr,
3054 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3055 DAG.getConstant(1U << 22, MVT::i32));
3056 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3057 DAG.getConstant(22, MVT::i32));
3058 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3059 DAG.getConstant(3, MVT::i32));
3062 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3063 const ARMSubtarget *ST) {
3064 EVT VT = N->getValueType(0);
3065 DebugLoc dl = N->getDebugLoc();
3067 if (!ST->hasV6T2Ops())
3070 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3071 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3074 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3075 const ARMSubtarget *ST) {
3076 EVT VT = N->getValueType(0);
3077 DebugLoc dl = N->getDebugLoc();
3082 // Lower vector shifts on NEON to use VSHL.
3083 assert(ST->hasNEON() && "unexpected vector shift");
3085 // Left shifts translate directly to the vshiftu intrinsic.
3086 if (N->getOpcode() == ISD::SHL)
3087 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3088 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3089 N->getOperand(0), N->getOperand(1));
3091 assert((N->getOpcode() == ISD::SRA ||
3092 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3094 // NEON uses the same intrinsics for both left and right shifts. For
3095 // right shifts, the shift amounts are negative, so negate the vector of
3097 EVT ShiftVT = N->getOperand(1).getValueType();
3098 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3099 getZeroVector(ShiftVT, DAG, dl),
3101 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3102 Intrinsic::arm_neon_vshifts :
3103 Intrinsic::arm_neon_vshiftu);
3104 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3105 DAG.getConstant(vshiftInt, MVT::i32),
3106 N->getOperand(0), NegatedCount);
3109 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3110 const ARMSubtarget *ST) {
3111 EVT VT = N->getValueType(0);
3112 DebugLoc dl = N->getDebugLoc();
3114 // We can get here for a node like i32 = ISD::SHL i32, i64
3118 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3119 "Unknown shift to lower!");
3121 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3122 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3123 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3126 // If we are in thumb mode, we don't have RRX.
3127 if (ST->isThumb1Only()) return SDValue();
3129 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3130 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3131 DAG.getConstant(0, MVT::i32));
3132 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3133 DAG.getConstant(1, MVT::i32));
3135 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3136 // captures the result into a carry flag.
3137 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3138 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3140 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3141 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3143 // Merge the pieces into a single i64 value.
3144 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3147 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3148 SDValue TmpOp0, TmpOp1;
3149 bool Invert = false;
3153 SDValue Op0 = Op.getOperand(0);
3154 SDValue Op1 = Op.getOperand(1);
3155 SDValue CC = Op.getOperand(2);
3156 EVT VT = Op.getValueType();
3157 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3158 DebugLoc dl = Op.getDebugLoc();
3160 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3161 switch (SetCCOpcode) {
3162 default: llvm_unreachable("Illegal FP comparison"); break;
3164 case ISD::SETNE: Invert = true; // Fallthrough
3166 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3168 case ISD::SETLT: Swap = true; // Fallthrough
3170 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3172 case ISD::SETLE: Swap = true; // Fallthrough
3174 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3175 case ISD::SETUGE: Swap = true; // Fallthrough
3176 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3177 case ISD::SETUGT: Swap = true; // Fallthrough
3178 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3179 case ISD::SETUEQ: Invert = true; // Fallthrough
3181 // Expand this to (OLT | OGT).
3185 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3186 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3188 case ISD::SETUO: Invert = true; // Fallthrough
3190 // Expand this to (OLT | OGE).
3194 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3195 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3199 // Integer comparisons.
3200 switch (SetCCOpcode) {
3201 default: llvm_unreachable("Illegal integer comparison"); break;
3202 case ISD::SETNE: Invert = true;
3203 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3204 case ISD::SETLT: Swap = true;
3205 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3206 case ISD::SETLE: Swap = true;
3207 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3208 case ISD::SETULT: Swap = true;
3209 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3210 case ISD::SETULE: Swap = true;
3211 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3214 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3215 if (Opc == ARMISD::VCEQ) {
3218 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3220 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3223 // Ignore bitconvert.
3224 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3225 AndOp = AndOp.getOperand(0);
3227 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3229 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3230 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3237 std::swap(Op0, Op1);
3239 // If one of the operands is a constant vector zero, attempt to fold the
3240 // comparison to a specialized compare-against-zero form.
3242 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3244 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3245 if (Opc == ARMISD::VCGE)
3246 Opc = ARMISD::VCLEZ;
3247 else if (Opc == ARMISD::VCGT)
3248 Opc = ARMISD::VCLTZ;
3253 if (SingleOp.getNode()) {
3256 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3258 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3260 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3262 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3264 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3266 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3269 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3273 Result = DAG.getNOT(dl, Result, VT);
3278 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3279 /// valid vector constant for a NEON instruction with a "modified immediate"
3280 /// operand (e.g., VMOV). If so, return the encoded value.
3281 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3282 unsigned SplatBitSize, SelectionDAG &DAG,
3283 EVT &VT, bool is128Bits, NEONModImmType type) {
3284 unsigned OpCmode, Imm;
3286 // SplatBitSize is set to the smallest size that splats the vector, so a
3287 // zero vector will always have SplatBitSize == 8. However, NEON modified
3288 // immediate instructions others than VMOV do not support the 8-bit encoding
3289 // of a zero vector, and the default encoding of zero is supposed to be the
3294 switch (SplatBitSize) {
3296 if (type != VMOVModImm)
3298 // Any 1-byte value is OK. Op=0, Cmode=1110.
3299 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3302 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3306 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3307 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3308 if ((SplatBits & ~0xff) == 0) {
3309 // Value = 0x00nn: Op=x, Cmode=100x.
3314 if ((SplatBits & ~0xff00) == 0) {
3315 // Value = 0xnn00: Op=x, Cmode=101x.
3317 Imm = SplatBits >> 8;
3323 // NEON's 32-bit VMOV supports splat values where:
3324 // * only one byte is nonzero, or
3325 // * the least significant byte is 0xff and the second byte is nonzero, or
3326 // * the least significant 2 bytes are 0xff and the third is nonzero.
3327 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3328 if ((SplatBits & ~0xff) == 0) {
3329 // Value = 0x000000nn: Op=x, Cmode=000x.
3334 if ((SplatBits & ~0xff00) == 0) {
3335 // Value = 0x0000nn00: Op=x, Cmode=001x.
3337 Imm = SplatBits >> 8;
3340 if ((SplatBits & ~0xff0000) == 0) {
3341 // Value = 0x00nn0000: Op=x, Cmode=010x.
3343 Imm = SplatBits >> 16;
3346 if ((SplatBits & ~0xff000000) == 0) {
3347 // Value = 0xnn000000: Op=x, Cmode=011x.
3349 Imm = SplatBits >> 24;
3353 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3354 if (type == OtherModImm) return SDValue();
3356 if ((SplatBits & ~0xffff) == 0 &&
3357 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3358 // Value = 0x0000nnff: Op=x, Cmode=1100.
3360 Imm = SplatBits >> 8;
3365 if ((SplatBits & ~0xffffff) == 0 &&
3366 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3367 // Value = 0x00nnffff: Op=x, Cmode=1101.
3369 Imm = SplatBits >> 16;
3370 SplatBits |= 0xffff;
3374 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3375 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3376 // VMOV.I32. A (very) minor optimization would be to replicate the value
3377 // and fall through here to test for a valid 64-bit splat. But, then the
3378 // caller would also need to check and handle the change in size.
3382 if (type != VMOVModImm)
3384 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3385 uint64_t BitMask = 0xff;
3387 unsigned ImmMask = 1;
3389 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3390 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3393 } else if ((SplatBits & BitMask) != 0) {
3399 // Op=1, Cmode=1110.
3402 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3407 llvm_unreachable("unexpected size for isNEONModifiedImm");
3411 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3412 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3415 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3416 bool &ReverseVEXT, unsigned &Imm) {
3417 unsigned NumElts = VT.getVectorNumElements();
3418 ReverseVEXT = false;
3420 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3426 // If this is a VEXT shuffle, the immediate value is the index of the first
3427 // element. The other shuffle indices must be the successive elements after
3429 unsigned ExpectedElt = Imm;
3430 for (unsigned i = 1; i < NumElts; ++i) {
3431 // Increment the expected index. If it wraps around, it may still be
3432 // a VEXT but the source vectors must be swapped.
3434 if (ExpectedElt == NumElts * 2) {
3439 if (M[i] < 0) continue; // ignore UNDEF indices
3440 if (ExpectedElt != static_cast<unsigned>(M[i]))
3444 // Adjust the index value if the source operands will be swapped.
3451 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3452 /// instruction with the specified blocksize. (The order of the elements
3453 /// within each block of the vector is reversed.)
3454 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3455 unsigned BlockSize) {
3456 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3457 "Only possible block sizes for VREV are: 16, 32, 64");
3459 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3463 unsigned NumElts = VT.getVectorNumElements();
3464 unsigned BlockElts = M[0] + 1;
3465 // If the first shuffle index is UNDEF, be optimistic.
3467 BlockElts = BlockSize / EltSz;
3469 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3472 for (unsigned i = 0; i < NumElts; ++i) {
3473 if (M[i] < 0) continue; // ignore UNDEF indices
3474 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3481 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3482 unsigned &WhichResult) {
3483 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3487 unsigned NumElts = VT.getVectorNumElements();
3488 WhichResult = (M[0] == 0 ? 0 : 1);
3489 for (unsigned i = 0; i < NumElts; i += 2) {
3490 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3491 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3497 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3498 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3499 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3500 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3501 unsigned &WhichResult) {
3502 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3506 unsigned NumElts = VT.getVectorNumElements();
3507 WhichResult = (M[0] == 0 ? 0 : 1);
3508 for (unsigned i = 0; i < NumElts; i += 2) {
3509 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3510 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3516 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3517 unsigned &WhichResult) {
3518 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3522 unsigned NumElts = VT.getVectorNumElements();
3523 WhichResult = (M[0] == 0 ? 0 : 1);
3524 for (unsigned i = 0; i != NumElts; ++i) {
3525 if (M[i] < 0) continue; // ignore UNDEF indices
3526 if ((unsigned) M[i] != 2 * i + WhichResult)
3530 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3531 if (VT.is64BitVector() && EltSz == 32)
3537 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3538 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3539 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3540 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3541 unsigned &WhichResult) {
3542 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3546 unsigned Half = VT.getVectorNumElements() / 2;
3547 WhichResult = (M[0] == 0 ? 0 : 1);
3548 for (unsigned j = 0; j != 2; ++j) {
3549 unsigned Idx = WhichResult;
3550 for (unsigned i = 0; i != Half; ++i) {
3551 int MIdx = M[i + j * Half];
3552 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3558 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3559 if (VT.is64BitVector() && EltSz == 32)
3565 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3566 unsigned &WhichResult) {
3567 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3571 unsigned NumElts = VT.getVectorNumElements();
3572 WhichResult = (M[0] == 0 ? 0 : 1);
3573 unsigned Idx = WhichResult * NumElts / 2;
3574 for (unsigned i = 0; i != NumElts; i += 2) {
3575 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3576 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3581 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3582 if (VT.is64BitVector() && EltSz == 32)
3588 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3589 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3590 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3591 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3592 unsigned &WhichResult) {
3593 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3597 unsigned NumElts = VT.getVectorNumElements();
3598 WhichResult = (M[0] == 0 ? 0 : 1);
3599 unsigned Idx = WhichResult * NumElts / 2;
3600 for (unsigned i = 0; i != NumElts; i += 2) {
3601 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3602 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3607 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3608 if (VT.is64BitVector() && EltSz == 32)
3614 // If N is an integer constant that can be moved into a register in one
3615 // instruction, return an SDValue of such a constant (will become a MOV
3616 // instruction). Otherwise return null.
3617 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3618 const ARMSubtarget *ST, DebugLoc dl) {
3620 if (!isa<ConstantSDNode>(N))
3622 Val = cast<ConstantSDNode>(N)->getZExtValue();
3624 if (ST->isThumb1Only()) {
3625 if (Val <= 255 || ~Val <= 255)
3626 return DAG.getConstant(Val, MVT::i32);
3628 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3629 return DAG.getConstant(Val, MVT::i32);
3634 // If this is a case we can't handle, return null and let the default
3635 // expansion code take care of it.
3636 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3637 const ARMSubtarget *ST) const {
3638 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3639 DebugLoc dl = Op.getDebugLoc();
3640 EVT VT = Op.getValueType();
3642 APInt SplatBits, SplatUndef;
3643 unsigned SplatBitSize;
3645 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3646 if (SplatBitSize <= 64) {
3647 // Check if an immediate VMOV works.
3649 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3650 SplatUndef.getZExtValue(), SplatBitSize,
3651 DAG, VmovVT, VT.is128BitVector(),
3653 if (Val.getNode()) {
3654 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3655 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3658 // Try an immediate VMVN.
3659 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3660 ((1LL << SplatBitSize) - 1));
3661 Val = isNEONModifiedImm(NegatedImm,
3662 SplatUndef.getZExtValue(), SplatBitSize,
3663 DAG, VmovVT, VT.is128BitVector(),
3665 if (Val.getNode()) {
3666 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3667 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3672 // Scan through the operands to see if only one value is used.
3673 unsigned NumElts = VT.getVectorNumElements();
3674 bool isOnlyLowElement = true;
3675 bool usesOnlyOneValue = true;
3676 bool isConstant = true;
3678 for (unsigned i = 0; i < NumElts; ++i) {
3679 SDValue V = Op.getOperand(i);
3680 if (V.getOpcode() == ISD::UNDEF)
3683 isOnlyLowElement = false;
3684 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3687 if (!Value.getNode())
3689 else if (V != Value)
3690 usesOnlyOneValue = false;
3693 if (!Value.getNode())
3694 return DAG.getUNDEF(VT);
3696 if (isOnlyLowElement)
3697 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3699 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3701 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3702 // i32 and try again.
3703 if (usesOnlyOneValue && EltSize <= 32) {
3705 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3706 if (VT.getVectorElementType().isFloatingPoint()) {
3707 SmallVector<SDValue, 8> Ops;
3708 for (unsigned i = 0; i < NumElts; ++i)
3709 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3711 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3712 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3713 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3715 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3717 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3719 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3722 // If all elements are constants and the case above didn't get hit, fall back
3723 // to the default expansion, which will generate a load from the constant
3728 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3730 SDValue shuffle = ReconstructShuffle(Op, DAG);
3731 if (shuffle != SDValue())
3735 // Vectors with 32- or 64-bit elements can be built by directly assigning
3736 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3737 // will be legalized.
3738 if (EltSize >= 32) {
3739 // Do the expansion with floating-point types, since that is what the VFP
3740 // registers are defined to use, and since i64 is not legal.
3741 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3742 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3743 SmallVector<SDValue, 8> Ops;
3744 for (unsigned i = 0; i < NumElts; ++i)
3745 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3746 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3747 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3753 // Gather data to see if the operation can be modelled as a
3754 // shuffle in combination with VEXTs.
3755 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3756 SelectionDAG &DAG) const {
3757 DebugLoc dl = Op.getDebugLoc();
3758 EVT VT = Op.getValueType();
3759 unsigned NumElts = VT.getVectorNumElements();
3761 SmallVector<SDValue, 2> SourceVecs;
3762 SmallVector<unsigned, 2> MinElts;
3763 SmallVector<unsigned, 2> MaxElts;
3765 for (unsigned i = 0; i < NumElts; ++i) {
3766 SDValue V = Op.getOperand(i);
3767 if (V.getOpcode() == ISD::UNDEF)
3769 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3770 // A shuffle can only come from building a vector from various
3771 // elements of other vectors.
3775 // Record this extraction against the appropriate vector if possible...
3776 SDValue SourceVec = V.getOperand(0);
3777 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
3778 bool FoundSource = false;
3779 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
3780 if (SourceVecs[j] == SourceVec) {
3781 if (MinElts[j] > EltNo)
3783 if (MaxElts[j] < EltNo)
3790 // Or record a new source if not...
3792 SourceVecs.push_back(SourceVec);
3793 MinElts.push_back(EltNo);
3794 MaxElts.push_back(EltNo);
3798 // Currently only do something sane when at most two source vectors
3800 if (SourceVecs.size() > 2)
3803 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
3804 int VEXTOffsets[2] = {0, 0};
3806 // This loop extracts the usage patterns of the source vectors
3807 // and prepares appropriate SDValues for a shuffle if possible.
3808 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
3809 if (SourceVecs[i].getValueType() == VT) {
3810 // No VEXT necessary
3811 ShuffleSrcs[i] = SourceVecs[i];
3814 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
3815 // It probably isn't worth padding out a smaller vector just to
3816 // break it down again in a shuffle.
3820 // Since only 64-bit and 128-bit vectors are legal on ARM and
3821 // we've eliminated the other cases...
3822 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
3823 "unexpected vector sizes in ReconstructShuffle");
3825 if (MaxElts[i] - MinElts[i] >= NumElts) {
3826 // Span too large for a VEXT to cope
3830 if (MinElts[i] >= NumElts) {
3831 // The extraction can just take the second half
3832 VEXTOffsets[i] = NumElts;
3833 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3835 DAG.getIntPtrConstant(NumElts));
3836 } else if (MaxElts[i] < NumElts) {
3837 // The extraction can just take the first half
3839 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3841 DAG.getIntPtrConstant(0));
3843 // An actual VEXT is needed
3844 VEXTOffsets[i] = MinElts[i];
3845 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3847 DAG.getIntPtrConstant(0));
3848 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3850 DAG.getIntPtrConstant(NumElts));
3851 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
3852 DAG.getConstant(VEXTOffsets[i], MVT::i32));
3856 SmallVector<int, 8> Mask;
3858 for (unsigned i = 0; i < NumElts; ++i) {
3859 SDValue Entry = Op.getOperand(i);
3860 if (Entry.getOpcode() == ISD::UNDEF) {
3865 SDValue ExtractVec = Entry.getOperand(0);
3866 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
3867 .getOperand(1))->getSExtValue();
3868 if (ExtractVec == SourceVecs[0]) {
3869 Mask.push_back(ExtractElt - VEXTOffsets[0]);
3871 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
3875 // Final check before we try to produce nonsense...
3876 if (isShuffleMaskLegal(Mask, VT))
3877 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
3883 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3884 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3885 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3886 /// are assumed to be legal.
3888 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3890 if (VT.getVectorNumElements() == 4 &&
3891 (VT.is128BitVector() || VT.is64BitVector())) {
3892 unsigned PFIndexes[4];
3893 for (unsigned i = 0; i != 4; ++i) {
3897 PFIndexes[i] = M[i];
3900 // Compute the index in the perfect shuffle table.
3901 unsigned PFTableIndex =
3902 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3903 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3904 unsigned Cost = (PFEntry >> 30);
3911 unsigned Imm, WhichResult;
3913 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3914 return (EltSize >= 32 ||
3915 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3916 isVREVMask(M, VT, 64) ||
3917 isVREVMask(M, VT, 32) ||
3918 isVREVMask(M, VT, 16) ||
3919 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3920 isVTRNMask(M, VT, WhichResult) ||
3921 isVUZPMask(M, VT, WhichResult) ||
3922 isVZIPMask(M, VT, WhichResult) ||
3923 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3924 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3925 isVZIP_v_undef_Mask(M, VT, WhichResult));
3928 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3929 /// the specified operations to build the shuffle.
3930 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3931 SDValue RHS, SelectionDAG &DAG,
3933 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3934 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3935 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3938 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3947 OP_VUZPL, // VUZP, left result
3948 OP_VUZPR, // VUZP, right result
3949 OP_VZIPL, // VZIP, left result
3950 OP_VZIPR, // VZIP, right result
3951 OP_VTRNL, // VTRN, left result
3952 OP_VTRNR // VTRN, right result
3955 if (OpNum == OP_COPY) {
3956 if (LHSID == (1*9+2)*9+3) return LHS;
3957 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3961 SDValue OpLHS, OpRHS;
3962 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3963 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3964 EVT VT = OpLHS.getValueType();
3967 default: llvm_unreachable("Unknown shuffle opcode!");
3969 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3974 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3975 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3979 return DAG.getNode(ARMISD::VEXT, dl, VT,
3981 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3984 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3985 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3988 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3989 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3992 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3993 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3997 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3998 SDValue V1 = Op.getOperand(0);
3999 SDValue V2 = Op.getOperand(1);
4000 DebugLoc dl = Op.getDebugLoc();
4001 EVT VT = Op.getValueType();
4002 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4003 SmallVector<int, 8> ShuffleMask;
4005 // Convert shuffles that are directly supported on NEON to target-specific
4006 // DAG nodes, instead of keeping them as shuffles and matching them again
4007 // during code selection. This is more efficient and avoids the possibility
4008 // of inconsistencies between legalization and selection.
4009 // FIXME: floating-point vectors should be canonicalized to integer vectors
4010 // of the same time so that they get CSEd properly.
4011 SVN->getMask(ShuffleMask);
4013 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4014 if (EltSize <= 32) {
4015 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4016 int Lane = SVN->getSplatIndex();
4017 // If this is undef splat, generate it via "just" vdup, if possible.
4018 if (Lane == -1) Lane = 0;
4020 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4021 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4023 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4024 DAG.getConstant(Lane, MVT::i32));
4029 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4032 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4033 DAG.getConstant(Imm, MVT::i32));
4036 if (isVREVMask(ShuffleMask, VT, 64))
4037 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4038 if (isVREVMask(ShuffleMask, VT, 32))
4039 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4040 if (isVREVMask(ShuffleMask, VT, 16))
4041 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4043 // Check for Neon shuffles that modify both input vectors in place.
4044 // If both results are used, i.e., if there are two shuffles with the same
4045 // source operands and with masks corresponding to both results of one of
4046 // these operations, DAG memoization will ensure that a single node is
4047 // used for both shuffles.
4048 unsigned WhichResult;
4049 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4050 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4051 V1, V2).getValue(WhichResult);
4052 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4053 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4054 V1, V2).getValue(WhichResult);
4055 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4056 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4057 V1, V2).getValue(WhichResult);
4059 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4060 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4061 V1, V1).getValue(WhichResult);
4062 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4063 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4064 V1, V1).getValue(WhichResult);
4065 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4066 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4067 V1, V1).getValue(WhichResult);
4070 // If the shuffle is not directly supported and it has 4 elements, use
4071 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4072 unsigned NumElts = VT.getVectorNumElements();
4074 unsigned PFIndexes[4];
4075 for (unsigned i = 0; i != 4; ++i) {
4076 if (ShuffleMask[i] < 0)
4079 PFIndexes[i] = ShuffleMask[i];
4082 // Compute the index in the perfect shuffle table.
4083 unsigned PFTableIndex =
4084 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4085 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4086 unsigned Cost = (PFEntry >> 30);
4089 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4092 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4093 if (EltSize >= 32) {
4094 // Do the expansion with floating-point types, since that is what the VFP
4095 // registers are defined to use, and since i64 is not legal.
4096 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4097 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4098 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4099 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4100 SmallVector<SDValue, 8> Ops;
4101 for (unsigned i = 0; i < NumElts; ++i) {
4102 if (ShuffleMask[i] < 0)
4103 Ops.push_back(DAG.getUNDEF(EltVT));
4105 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4106 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4107 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4110 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4111 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4117 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4118 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4119 SDValue Lane = Op.getOperand(1);
4120 if (!isa<ConstantSDNode>(Lane))
4123 SDValue Vec = Op.getOperand(0);
4124 if (Op.getValueType() == MVT::i32 &&
4125 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4126 DebugLoc dl = Op.getDebugLoc();
4127 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4134 // The only time a CONCAT_VECTORS operation can have legal types is when
4135 // two 64-bit vectors are concatenated to a 128-bit vector.
4136 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4137 "unexpected CONCAT_VECTORS");
4138 DebugLoc dl = Op.getDebugLoc();
4139 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4140 SDValue Op0 = Op.getOperand(0);
4141 SDValue Op1 = Op.getOperand(1);
4142 if (Op0.getOpcode() != ISD::UNDEF)
4143 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4144 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4145 DAG.getIntPtrConstant(0));
4146 if (Op1.getOpcode() != ISD::UNDEF)
4147 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4148 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4149 DAG.getIntPtrConstant(1));
4150 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4153 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4154 /// element has been zero/sign-extended, depending on the isSigned parameter,
4155 /// from an integer type half its size.
4156 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4158 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4159 EVT VT = N->getValueType(0);
4160 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4161 SDNode *BVN = N->getOperand(0).getNode();
4162 if (BVN->getValueType(0) != MVT::v4i32 ||
4163 BVN->getOpcode() != ISD::BUILD_VECTOR)
4165 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4166 unsigned HiElt = 1 - LoElt;
4167 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4168 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4169 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4170 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4171 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4174 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4175 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4178 if (Hi0->isNullValue() && Hi1->isNullValue())
4184 if (N->getOpcode() != ISD::BUILD_VECTOR)
4187 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4188 SDNode *Elt = N->getOperand(i).getNode();
4189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4190 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4191 unsigned HalfSize = EltSize / 2;
4193 int64_t SExtVal = C->getSExtValue();
4194 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4197 if ((C->getZExtValue() >> HalfSize) != 0)
4208 /// isSignExtended - Check if a node is a vector value that is sign-extended
4209 /// or a constant BUILD_VECTOR with sign-extended elements.
4210 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4211 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4213 if (isExtendedBUILD_VECTOR(N, DAG, true))
4218 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4219 /// or a constant BUILD_VECTOR with zero-extended elements.
4220 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4221 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4223 if (isExtendedBUILD_VECTOR(N, DAG, false))
4228 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4229 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4230 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4231 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4232 return N->getOperand(0);
4233 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4234 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4235 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4236 LD->isNonTemporal(), LD->getAlignment());
4237 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4238 // have been legalized as a BITCAST from v4i32.
4239 if (N->getOpcode() == ISD::BITCAST) {
4240 SDNode *BVN = N->getOperand(0).getNode();
4241 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4242 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4243 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4244 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4245 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4247 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4248 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4249 EVT VT = N->getValueType(0);
4250 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4251 unsigned NumElts = VT.getVectorNumElements();
4252 MVT TruncVT = MVT::getIntegerVT(EltSize);
4253 SmallVector<SDValue, 8> Ops;
4254 for (unsigned i = 0; i != NumElts; ++i) {
4255 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4256 const APInt &CInt = C->getAPIntValue();
4257 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4259 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4260 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4263 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4264 // Multiplications are only custom-lowered for 128-bit vectors so that
4265 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4266 EVT VT = Op.getValueType();
4267 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4268 SDNode *N0 = Op.getOperand(0).getNode();
4269 SDNode *N1 = Op.getOperand(1).getNode();
4270 unsigned NewOpc = 0;
4271 if (isSignExtended(N0, DAG) && isSignExtended(N1, DAG))
4272 NewOpc = ARMISD::VMULLs;
4273 else if (isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG))
4274 NewOpc = ARMISD::VMULLu;
4275 else if (VT == MVT::v2i64)
4276 // Fall through to expand this. It is not legal.
4279 // Other vector multiplications are legal.
4282 // Legalize to a VMULL instruction.
4283 DebugLoc DL = Op.getDebugLoc();
4284 SDValue Op0 = SkipExtension(N0, DAG);
4285 SDValue Op1 = SkipExtension(N1, DAG);
4287 assert(Op0.getValueType().is64BitVector() &&
4288 Op1.getValueType().is64BitVector() &&
4289 "unexpected types for extended operands to VMULL");
4290 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4294 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4296 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4297 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4298 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4299 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4300 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4301 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4302 // Get reciprocal estimate.
4303 // float4 recip = vrecpeq_f32(yf);
4304 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4305 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4306 // Because char has a smaller range than uchar, we can actually get away
4307 // without any newton steps. This requires that we use a weird bias
4308 // of 0xb000, however (again, this has been exhaustively tested).
4309 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4310 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4311 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4312 Y = DAG.getConstant(0xb000, MVT::i32);
4313 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4314 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4315 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4316 // Convert back to short.
4317 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4318 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4323 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4325 // Convert to float.
4326 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4327 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4328 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4329 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4330 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4331 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4333 // Use reciprocal estimate and one refinement step.
4334 // float4 recip = vrecpeq_f32(yf);
4335 // recip *= vrecpsq_f32(yf, recip);
4336 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4337 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4338 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4339 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4341 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4342 // Because short has a smaller range than ushort, we can actually get away
4343 // with only a single newton step. This requires that we use a weird bias
4344 // of 89, however (again, this has been exhaustively tested).
4345 // float4 result = as_float4(as_int4(xf*recip) + 89);
4346 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4347 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4348 N1 = DAG.getConstant(89, MVT::i32);
4349 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4350 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4351 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4352 // Convert back to integer and return.
4353 // return vmovn_s32(vcvt_s32_f32(result));
4354 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4355 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4359 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4360 EVT VT = Op.getValueType();
4361 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4362 "unexpected type for custom-lowering ISD::SDIV");
4364 DebugLoc dl = Op.getDebugLoc();
4365 SDValue N0 = Op.getOperand(0);
4366 SDValue N1 = Op.getOperand(1);
4369 if (VT == MVT::v8i8) {
4370 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4371 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4373 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4374 DAG.getIntPtrConstant(4));
4375 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4376 DAG.getIntPtrConstant(4));
4377 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4378 DAG.getIntPtrConstant(0));
4379 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4380 DAG.getIntPtrConstant(0));
4382 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4383 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4385 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4386 N0 = LowerCONCAT_VECTORS(N0, DAG);
4388 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4391 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4394 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4395 EVT VT = Op.getValueType();
4396 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4397 "unexpected type for custom-lowering ISD::UDIV");
4399 DebugLoc dl = Op.getDebugLoc();
4400 SDValue N0 = Op.getOperand(0);
4401 SDValue N1 = Op.getOperand(1);
4404 if (VT == MVT::v8i8) {
4405 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4406 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4408 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4409 DAG.getIntPtrConstant(4));
4410 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4411 DAG.getIntPtrConstant(4));
4412 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4413 DAG.getIntPtrConstant(0));
4414 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4415 DAG.getIntPtrConstant(0));
4417 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4418 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4420 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4421 N0 = LowerCONCAT_VECTORS(N0, DAG);
4423 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4424 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4429 // v4i16 sdiv ... Convert to float.
4430 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4431 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4432 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4433 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4434 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4435 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4437 // Use reciprocal estimate and two refinement steps.
4438 // float4 recip = vrecpeq_f32(yf);
4439 // recip *= vrecpsq_f32(yf, recip);
4440 // recip *= vrecpsq_f32(yf, recip);
4441 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4442 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4443 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4444 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4446 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4447 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4448 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4450 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4451 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4452 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4453 // and that it will never cause us to return an answer too large).
4454 // float4 result = as_float4(as_int4(xf*recip) + 89);
4455 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4456 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4457 N1 = DAG.getConstant(2, MVT::i32);
4458 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4459 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4460 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4461 // Convert back to integer and return.
4462 // return vmovn_u32(vcvt_s32_f32(result));
4463 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4464 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4468 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4469 switch (Op.getOpcode()) {
4470 default: llvm_unreachable("Don't know how to custom lower this!");
4471 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4472 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4473 case ISD::GlobalAddress:
4474 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4475 LowerGlobalAddressELF(Op, DAG);
4476 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4477 case ISD::SELECT: return LowerSELECT(Op, DAG);
4478 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4479 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4480 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4481 case ISD::VASTART: return LowerVASTART(Op, DAG);
4482 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4483 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4484 case ISD::SINT_TO_FP:
4485 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4486 case ISD::FP_TO_SINT:
4487 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4488 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4489 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4490 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4491 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4492 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4493 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4494 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4495 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4497 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4500 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4501 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4502 case ISD::SRL_PARTS:
4503 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4504 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4505 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4506 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4507 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4508 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4509 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4510 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4511 case ISD::MUL: return LowerMUL(Op, DAG);
4512 case ISD::SDIV: return LowerSDIV(Op, DAG);
4513 case ISD::UDIV: return LowerUDIV(Op, DAG);
4518 /// ReplaceNodeResults - Replace the results of node with an illegal result
4519 /// type with new values built out of custom code.
4520 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4521 SmallVectorImpl<SDValue>&Results,
4522 SelectionDAG &DAG) const {
4524 switch (N->getOpcode()) {
4526 llvm_unreachable("Don't know how to custom expand this!");
4529 Res = ExpandBITCAST(N, DAG);
4533 Res = Expand64BitShift(N, DAG, Subtarget);
4537 Results.push_back(Res);
4540 //===----------------------------------------------------------------------===//
4541 // ARM Scheduler Hooks
4542 //===----------------------------------------------------------------------===//
4545 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4546 MachineBasicBlock *BB,
4547 unsigned Size) const {
4548 unsigned dest = MI->getOperand(0).getReg();
4549 unsigned ptr = MI->getOperand(1).getReg();
4550 unsigned oldval = MI->getOperand(2).getReg();
4551 unsigned newval = MI->getOperand(3).getReg();
4552 unsigned scratch = BB->getParent()->getRegInfo()
4553 .createVirtualRegister(ARM::GPRRegisterClass);
4554 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4555 DebugLoc dl = MI->getDebugLoc();
4556 bool isThumb2 = Subtarget->isThumb2();
4558 unsigned ldrOpc, strOpc;
4560 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4562 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4563 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4566 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4567 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4570 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4571 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4575 MachineFunction *MF = BB->getParent();
4576 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4577 MachineFunction::iterator It = BB;
4578 ++It; // insert the new blocks after the current block
4580 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4581 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4582 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4583 MF->insert(It, loop1MBB);
4584 MF->insert(It, loop2MBB);
4585 MF->insert(It, exitMBB);
4587 // Transfer the remainder of BB and its successor edges to exitMBB.
4588 exitMBB->splice(exitMBB->begin(), BB,
4589 llvm::next(MachineBasicBlock::iterator(MI)),
4591 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4595 // fallthrough --> loop1MBB
4596 BB->addSuccessor(loop1MBB);
4599 // ldrex dest, [ptr]
4603 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4604 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4605 .addReg(dest).addReg(oldval));
4606 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4607 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4608 BB->addSuccessor(loop2MBB);
4609 BB->addSuccessor(exitMBB);
4612 // strex scratch, newval, [ptr]
4616 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4618 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4619 .addReg(scratch).addImm(0));
4620 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4621 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4622 BB->addSuccessor(loop1MBB);
4623 BB->addSuccessor(exitMBB);
4629 MI->eraseFromParent(); // The instruction is gone now.
4635 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4636 unsigned Size, unsigned BinOpcode) const {
4637 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4638 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4640 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4641 MachineFunction *MF = BB->getParent();
4642 MachineFunction::iterator It = BB;
4645 unsigned dest = MI->getOperand(0).getReg();
4646 unsigned ptr = MI->getOperand(1).getReg();
4647 unsigned incr = MI->getOperand(2).getReg();
4648 DebugLoc dl = MI->getDebugLoc();
4650 bool isThumb2 = Subtarget->isThumb2();
4651 unsigned ldrOpc, strOpc;
4653 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4655 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4656 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4659 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4660 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4663 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4664 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4668 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4669 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4670 MF->insert(It, loopMBB);
4671 MF->insert(It, exitMBB);
4673 // Transfer the remainder of BB and its successor edges to exitMBB.
4674 exitMBB->splice(exitMBB->begin(), BB,
4675 llvm::next(MachineBasicBlock::iterator(MI)),
4677 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4679 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4680 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4681 unsigned scratch2 = (!BinOpcode) ? incr :
4682 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4686 // fallthrough --> loopMBB
4687 BB->addSuccessor(loopMBB);
4691 // <binop> scratch2, dest, incr
4692 // strex scratch, scratch2, ptr
4695 // fallthrough --> exitMBB
4697 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4699 // operand order needs to go the other way for NAND
4700 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4701 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4702 addReg(incr).addReg(dest)).addReg(0);
4704 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4705 addReg(dest).addReg(incr)).addReg(0);
4708 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4710 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4711 .addReg(scratch).addImm(0));
4712 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4713 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4715 BB->addSuccessor(loopMBB);
4716 BB->addSuccessor(exitMBB);
4722 MI->eraseFromParent(); // The instruction is gone now.
4728 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4729 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4730 E = MBB->succ_end(); I != E; ++I)
4733 llvm_unreachable("Expecting a BB with two successors!");
4737 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4738 MachineBasicBlock *BB) const {
4739 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4740 DebugLoc dl = MI->getDebugLoc();
4741 bool isThumb2 = Subtarget->isThumb2();
4742 switch (MI->getOpcode()) {
4745 llvm_unreachable("Unexpected instr type to insert");
4747 case ARM::ATOMIC_LOAD_ADD_I8:
4748 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4749 case ARM::ATOMIC_LOAD_ADD_I16:
4750 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4751 case ARM::ATOMIC_LOAD_ADD_I32:
4752 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4754 case ARM::ATOMIC_LOAD_AND_I8:
4755 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4756 case ARM::ATOMIC_LOAD_AND_I16:
4757 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4758 case ARM::ATOMIC_LOAD_AND_I32:
4759 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4761 case ARM::ATOMIC_LOAD_OR_I8:
4762 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4763 case ARM::ATOMIC_LOAD_OR_I16:
4764 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4765 case ARM::ATOMIC_LOAD_OR_I32:
4766 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4768 case ARM::ATOMIC_LOAD_XOR_I8:
4769 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4770 case ARM::ATOMIC_LOAD_XOR_I16:
4771 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4772 case ARM::ATOMIC_LOAD_XOR_I32:
4773 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4775 case ARM::ATOMIC_LOAD_NAND_I8:
4776 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4777 case ARM::ATOMIC_LOAD_NAND_I16:
4778 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4779 case ARM::ATOMIC_LOAD_NAND_I32:
4780 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4782 case ARM::ATOMIC_LOAD_SUB_I8:
4783 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4784 case ARM::ATOMIC_LOAD_SUB_I16:
4785 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4786 case ARM::ATOMIC_LOAD_SUB_I32:
4787 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4789 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4790 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4791 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4793 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4794 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4795 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4797 case ARM::tMOVCCr_pseudo: {
4798 // To "insert" a SELECT_CC instruction, we actually have to insert the
4799 // diamond control-flow pattern. The incoming instruction knows the
4800 // destination vreg to set, the condition code register to branch on, the
4801 // true/false values to select between, and a branch opcode to use.
4802 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4803 MachineFunction::iterator It = BB;
4809 // cmpTY ccX, r1, r2
4811 // fallthrough --> copy0MBB
4812 MachineBasicBlock *thisMBB = BB;
4813 MachineFunction *F = BB->getParent();
4814 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4815 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4816 F->insert(It, copy0MBB);
4817 F->insert(It, sinkMBB);
4819 // Transfer the remainder of BB and its successor edges to sinkMBB.
4820 sinkMBB->splice(sinkMBB->begin(), BB,
4821 llvm::next(MachineBasicBlock::iterator(MI)),
4823 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4825 BB->addSuccessor(copy0MBB);
4826 BB->addSuccessor(sinkMBB);
4828 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4829 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4832 // %FalseValue = ...
4833 // # fallthrough to sinkMBB
4836 // Update machine-CFG edges
4837 BB->addSuccessor(sinkMBB);
4840 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4843 BuildMI(*BB, BB->begin(), dl,
4844 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4845 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4846 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4848 MI->eraseFromParent(); // The pseudo instruction is gone now.
4853 case ARM::BCCZi64: {
4854 // If there is an unconditional branch to the other successor, remove it.
4855 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
4857 // Compare both parts that make up the double comparison separately for
4859 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4861 unsigned LHS1 = MI->getOperand(1).getReg();
4862 unsigned LHS2 = MI->getOperand(2).getReg();
4864 AddDefaultPred(BuildMI(BB, dl,
4865 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4866 .addReg(LHS1).addImm(0));
4867 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4868 .addReg(LHS2).addImm(0)
4869 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4871 unsigned RHS1 = MI->getOperand(3).getReg();
4872 unsigned RHS2 = MI->getOperand(4).getReg();
4873 AddDefaultPred(BuildMI(BB, dl,
4874 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4875 .addReg(LHS1).addReg(RHS1));
4876 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4877 .addReg(LHS2).addReg(RHS2)
4878 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4881 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4882 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4883 if (MI->getOperand(0).getImm() == ARMCC::NE)
4884 std::swap(destMBB, exitMBB);
4886 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4887 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4888 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4891 MI->eraseFromParent(); // The pseudo instruction is gone now.
4897 //===----------------------------------------------------------------------===//
4898 // ARM Optimization Hooks
4899 //===----------------------------------------------------------------------===//
4902 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4903 TargetLowering::DAGCombinerInfo &DCI) {
4904 SelectionDAG &DAG = DCI.DAG;
4905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4906 EVT VT = N->getValueType(0);
4907 unsigned Opc = N->getOpcode();
4908 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4909 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4910 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4911 ISD::CondCode CC = ISD::SETCC_INVALID;
4914 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4916 SDValue CCOp = Slct.getOperand(0);
4917 if (CCOp.getOpcode() == ISD::SETCC)
4918 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4921 bool DoXform = false;
4923 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4926 if (LHS.getOpcode() == ISD::Constant &&
4927 cast<ConstantSDNode>(LHS)->isNullValue()) {
4929 } else if (CC != ISD::SETCC_INVALID &&
4930 RHS.getOpcode() == ISD::Constant &&
4931 cast<ConstantSDNode>(RHS)->isNullValue()) {
4932 std::swap(LHS, RHS);
4933 SDValue Op0 = Slct.getOperand(0);
4934 EVT OpVT = isSlctCC ? Op0.getValueType() :
4935 Op0.getOperand(0).getValueType();
4936 bool isInt = OpVT.isInteger();
4937 CC = ISD::getSetCCInverse(CC, isInt);
4939 if (!TLI.isCondCodeLegal(CC, OpVT))
4940 return SDValue(); // Inverse operator isn't legal.
4947 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4949 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4950 Slct.getOperand(0), Slct.getOperand(1), CC);
4951 SDValue CCOp = Slct.getOperand(0);
4953 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4954 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4955 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4956 CCOp, OtherOp, Result);
4961 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4962 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4963 /// called with the default operands, and if that fails, with commuted
4965 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4966 TargetLowering::DAGCombinerInfo &DCI) {
4967 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4968 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4969 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4970 if (Result.getNode()) return Result;
4975 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4977 static SDValue PerformADDCombine(SDNode *N,
4978 TargetLowering::DAGCombinerInfo &DCI) {
4979 SDValue N0 = N->getOperand(0);
4980 SDValue N1 = N->getOperand(1);
4982 // First try with the default operand order.
4983 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4984 if (Result.getNode())
4987 // If that didn't work, try again with the operands commuted.
4988 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4991 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4993 static SDValue PerformSUBCombine(SDNode *N,
4994 TargetLowering::DAGCombinerInfo &DCI) {
4995 SDValue N0 = N->getOperand(0);
4996 SDValue N1 = N->getOperand(1);
4998 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4999 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5000 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5001 if (Result.getNode()) return Result;
5007 static SDValue PerformMULCombine(SDNode *N,
5008 TargetLowering::DAGCombinerInfo &DCI,
5009 const ARMSubtarget *Subtarget) {
5010 SelectionDAG &DAG = DCI.DAG;
5012 if (Subtarget->isThumb1Only())
5015 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5018 EVT VT = N->getValueType(0);
5022 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5026 uint64_t MulAmt = C->getZExtValue();
5027 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5028 ShiftAmt = ShiftAmt & (32 - 1);
5029 SDValue V = N->getOperand(0);
5030 DebugLoc DL = N->getDebugLoc();
5033 MulAmt >>= ShiftAmt;
5034 if (isPowerOf2_32(MulAmt - 1)) {
5035 // (mul x, 2^N + 1) => (add (shl x, N), x)
5036 Res = DAG.getNode(ISD::ADD, DL, VT,
5037 V, DAG.getNode(ISD::SHL, DL, VT,
5038 V, DAG.getConstant(Log2_32(MulAmt-1),
5040 } else if (isPowerOf2_32(MulAmt + 1)) {
5041 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5042 Res = DAG.getNode(ISD::SUB, DL, VT,
5043 DAG.getNode(ISD::SHL, DL, VT,
5044 V, DAG.getConstant(Log2_32(MulAmt+1),
5051 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5052 DAG.getConstant(ShiftAmt, MVT::i32));
5054 // Do not add new nodes to DAG combiner worklist.
5055 DCI.CombineTo(N, Res, false);
5059 static SDValue PerformANDCombine(SDNode *N,
5060 TargetLowering::DAGCombinerInfo &DCI) {
5061 // Attempt to use immediate-form VBIC
5062 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5063 DebugLoc dl = N->getDebugLoc();
5064 EVT VT = N->getValueType(0);
5065 SelectionDAG &DAG = DCI.DAG;
5067 APInt SplatBits, SplatUndef;
5068 unsigned SplatBitSize;
5071 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5072 if (SplatBitSize <= 64) {
5074 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5075 SplatUndef.getZExtValue(), SplatBitSize,
5076 DAG, VbicVT, VT.is128BitVector(),
5078 if (Val.getNode()) {
5080 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5081 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5082 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5090 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5091 static SDValue PerformORCombine(SDNode *N,
5092 TargetLowering::DAGCombinerInfo &DCI,
5093 const ARMSubtarget *Subtarget) {
5094 // Attempt to use immediate-form VORR
5095 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5096 DebugLoc dl = N->getDebugLoc();
5097 EVT VT = N->getValueType(0);
5098 SelectionDAG &DAG = DCI.DAG;
5100 APInt SplatBits, SplatUndef;
5101 unsigned SplatBitSize;
5103 if (BVN && Subtarget->hasNEON() &&
5104 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5105 if (SplatBitSize <= 64) {
5107 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5108 SplatUndef.getZExtValue(), SplatBitSize,
5109 DAG, VorrVT, VT.is128BitVector(),
5111 if (Val.getNode()) {
5113 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5114 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5115 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5120 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5123 // BFI is only available on V6T2+
5124 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5127 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
5128 DebugLoc DL = N->getDebugLoc();
5129 // 1) or (and A, mask), val => ARMbfi A, val, mask
5130 // iff (val & mask) == val
5132 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5133 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5134 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
5135 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5136 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
5137 // (i.e., copy a bitfield value into another bitfield of the same width)
5138 if (N0.getOpcode() != ISD::AND)
5144 SDValue N00 = N0.getOperand(0);
5146 // The value and the mask need to be constants so we can verify this is
5147 // actually a bitfield set. If the mask is 0xffff, we can do better
5148 // via a movt instruction, so don't use BFI in that case.
5149 SDValue MaskOp = N0.getOperand(1);
5150 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5153 unsigned Mask = MaskC->getZExtValue();
5157 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5158 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5160 unsigned Val = N1C->getZExtValue();
5161 if ((Val & ~Mask) != Val)
5164 if (ARM::isBitFieldInvertedMask(Mask)) {
5165 Val >>= CountTrailingZeros_32(~Mask);
5167 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5168 DAG.getConstant(Val, MVT::i32),
5169 DAG.getConstant(Mask, MVT::i32));
5171 // Do not add new nodes to DAG combiner worklist.
5172 DCI.CombineTo(N, Res, false);
5175 } else if (N1.getOpcode() == ISD::AND) {
5176 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5177 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5180 unsigned Mask2 = N11C->getZExtValue();
5182 if (ARM::isBitFieldInvertedMask(Mask) &&
5183 ARM::isBitFieldInvertedMask(~Mask2) &&
5184 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
5185 // The pack halfword instruction works better for masks that fit it,
5186 // so use that when it's available.
5187 if (Subtarget->hasT2ExtractPack() &&
5188 (Mask == 0xffff || Mask == 0xffff0000))
5191 unsigned lsb = CountTrailingZeros_32(Mask2);
5192 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5193 DAG.getConstant(lsb, MVT::i32));
5194 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5195 DAG.getConstant(Mask, MVT::i32));
5196 // Do not add new nodes to DAG combiner worklist.
5197 DCI.CombineTo(N, Res, false);
5199 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5200 ARM::isBitFieldInvertedMask(Mask2) &&
5201 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
5202 // The pack halfword instruction works better for masks that fit it,
5203 // so use that when it's available.
5204 if (Subtarget->hasT2ExtractPack() &&
5205 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5208 unsigned lsb = CountTrailingZeros_32(Mask);
5209 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5210 DAG.getConstant(lsb, MVT::i32));
5211 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5212 DAG.getConstant(Mask2, MVT::i32));
5213 // Do not add new nodes to DAG combiner worklist.
5214 DCI.CombineTo(N, Res, false);
5219 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5220 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5221 ARM::isBitFieldInvertedMask(~Mask)) {
5222 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5223 // where lsb(mask) == #shamt and masked bits of B are known zero.
5224 SDValue ShAmt = N00.getOperand(1);
5225 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5226 unsigned LSB = CountTrailingZeros_32(Mask);
5230 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5231 DAG.getConstant(~Mask, MVT::i32));
5233 // Do not add new nodes to DAG combiner worklist.
5234 DCI.CombineTo(N, Res, false);
5240 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5242 static SDValue PerformBFICombine(SDNode *N,
5243 TargetLowering::DAGCombinerInfo &DCI) {
5244 SDValue N1 = N->getOperand(1);
5245 if (N1.getOpcode() == ISD::AND) {
5246 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5249 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5250 unsigned Mask2 = N11C->getZExtValue();
5251 if ((Mask & Mask2) == Mask2)
5252 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5253 N->getOperand(0), N1.getOperand(0),
5259 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5260 /// ARMISD::VMOVRRD.
5261 static SDValue PerformVMOVRRDCombine(SDNode *N,
5262 TargetLowering::DAGCombinerInfo &DCI) {
5263 // vmovrrd(vmovdrr x, y) -> x,y
5264 SDValue InDouble = N->getOperand(0);
5265 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5266 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5270 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5271 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5272 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5273 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5274 SDValue Op0 = N->getOperand(0);
5275 SDValue Op1 = N->getOperand(1);
5276 if (Op0.getOpcode() == ISD::BITCAST)
5277 Op0 = Op0.getOperand(0);
5278 if (Op1.getOpcode() == ISD::BITCAST)
5279 Op1 = Op1.getOperand(0);
5280 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5281 Op0.getNode() == Op1.getNode() &&
5282 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5283 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5284 N->getValueType(0), Op0.getOperand(0));
5288 /// PerformSTORECombine - Target-specific dag combine xforms for
5290 static SDValue PerformSTORECombine(SDNode *N,
5291 TargetLowering::DAGCombinerInfo &DCI) {
5292 // Bitcast an i64 store extracted from a vector to f64.
5293 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5294 StoreSDNode *St = cast<StoreSDNode>(N);
5295 SDValue StVal = St->getValue();
5296 if (!ISD::isNormalStore(St) || St->isVolatile() ||
5297 StVal.getValueType() != MVT::i64 ||
5298 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5301 SelectionDAG &DAG = DCI.DAG;
5302 DebugLoc dl = StVal.getDebugLoc();
5303 SDValue IntVec = StVal.getOperand(0);
5304 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5305 IntVec.getValueType().getVectorNumElements());
5306 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5307 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5308 Vec, StVal.getOperand(1));
5309 dl = N->getDebugLoc();
5310 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5311 // Make the DAGCombiner fold the bitcasts.
5312 DCI.AddToWorklist(Vec.getNode());
5313 DCI.AddToWorklist(ExtElt.getNode());
5314 DCI.AddToWorklist(V.getNode());
5315 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5316 St->getPointerInfo(), St->isVolatile(),
5317 St->isNonTemporal(), St->getAlignment(),
5321 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5322 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5323 /// i64 vector to have f64 elements, since the value can then be loaded
5324 /// directly into a VFP register.
5325 static bool hasNormalLoadOperand(SDNode *N) {
5326 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5327 for (unsigned i = 0; i < NumElts; ++i) {
5328 SDNode *Elt = N->getOperand(i).getNode();
5329 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5335 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5336 /// ISD::BUILD_VECTOR.
5337 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5338 TargetLowering::DAGCombinerInfo &DCI){
5339 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
5340 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
5341 // into a pair of GPRs, which is fine when the value is used as a scalar,
5342 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
5343 SelectionDAG &DAG = DCI.DAG;
5344 if (N->getNumOperands() == 2) {
5345 SDValue RV = PerformVMOVDRRCombine(N, DAG);
5350 // Load i64 elements as f64 values so that type legalization does not split
5351 // them up into i32 values.
5352 EVT VT = N->getValueType(0);
5353 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
5355 DebugLoc dl = N->getDebugLoc();
5356 SmallVector<SDValue, 8> Ops;
5357 unsigned NumElts = VT.getVectorNumElements();
5358 for (unsigned i = 0; i < NumElts; ++i) {
5359 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
5361 // Make the DAGCombiner fold the bitcast.
5362 DCI.AddToWorklist(V.getNode());
5364 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
5365 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
5366 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
5369 /// PerformInsertEltCombine - Target-specific dag combine xforms for
5370 /// ISD::INSERT_VECTOR_ELT.
5371 static SDValue PerformInsertEltCombine(SDNode *N,
5372 TargetLowering::DAGCombinerInfo &DCI) {
5373 // Bitcast an i64 load inserted into a vector to f64.
5374 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5375 EVT VT = N->getValueType(0);
5376 SDNode *Elt = N->getOperand(1).getNode();
5377 if (VT.getVectorElementType() != MVT::i64 ||
5378 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
5381 SelectionDAG &DAG = DCI.DAG;
5382 DebugLoc dl = N->getDebugLoc();
5383 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5384 VT.getVectorNumElements());
5385 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
5386 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
5387 // Make the DAGCombiner fold the bitcasts.
5388 DCI.AddToWorklist(Vec.getNode());
5389 DCI.AddToWorklist(V.getNode());
5390 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
5391 Vec, V, N->getOperand(2));
5392 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
5395 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
5396 /// ISD::VECTOR_SHUFFLE.
5397 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
5398 // The LLVM shufflevector instruction does not require the shuffle mask
5399 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
5400 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
5401 // operands do not match the mask length, they are extended by concatenating
5402 // them with undef vectors. That is probably the right thing for other
5403 // targets, but for NEON it is better to concatenate two double-register
5404 // size vector operands into a single quad-register size vector. Do that
5405 // transformation here:
5406 // shuffle(concat(v1, undef), concat(v2, undef)) ->
5407 // shuffle(concat(v1, v2), undef)
5408 SDValue Op0 = N->getOperand(0);
5409 SDValue Op1 = N->getOperand(1);
5410 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
5411 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
5412 Op0.getNumOperands() != 2 ||
5413 Op1.getNumOperands() != 2)
5415 SDValue Concat0Op1 = Op0.getOperand(1);
5416 SDValue Concat1Op1 = Op1.getOperand(1);
5417 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
5418 Concat1Op1.getOpcode() != ISD::UNDEF)
5420 // Skip the transformation if any of the types are illegal.
5421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5422 EVT VT = N->getValueType(0);
5423 if (!TLI.isTypeLegal(VT) ||
5424 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5425 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5428 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5429 Op0.getOperand(0), Op1.getOperand(0));
5430 // Translate the shuffle mask.
5431 SmallVector<int, 16> NewMask;
5432 unsigned NumElts = VT.getVectorNumElements();
5433 unsigned HalfElts = NumElts/2;
5434 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5435 for (unsigned n = 0; n < NumElts; ++n) {
5436 int MaskElt = SVN->getMaskElt(n);
5438 if (MaskElt < (int)HalfElts)
5440 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5441 NewElt = HalfElts + MaskElt - NumElts;
5442 NewMask.push_back(NewElt);
5444 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5445 DAG.getUNDEF(VT), NewMask.data());
5448 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
5449 /// NEON load/store intrinsics to merge base address updates.
5450 static SDValue CombineBaseUpdate(SDNode *N,
5451 TargetLowering::DAGCombinerInfo &DCI) {
5452 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5455 SelectionDAG &DAG = DCI.DAG;
5456 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
5457 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
5458 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
5459 SDValue Addr = N->getOperand(AddrOpIdx);
5461 // Search for a use of the address operand that is an increment.
5462 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
5463 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
5465 if (User->getOpcode() != ISD::ADD ||
5466 UI.getUse().getResNo() != Addr.getResNo())
5469 // Check that the add is independent of the load/store. Otherwise, folding
5470 // it would create a cycle.
5471 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
5474 // Find the new opcode for the updating load/store.
5476 bool isLaneOp = false;
5477 unsigned NewOpc = 0;
5478 unsigned NumVecs = 0;
5480 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
5482 default: assert(0 && "unexpected intrinsic for Neon base update");
5483 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
5485 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
5487 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
5489 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
5491 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
5492 NumVecs = 2; isLaneOp = true; break;
5493 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
5494 NumVecs = 3; isLaneOp = true; break;
5495 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
5496 NumVecs = 4; isLaneOp = true; break;
5497 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
5498 NumVecs = 1; isLoad = false; break;
5499 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
5500 NumVecs = 2; isLoad = false; break;
5501 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
5502 NumVecs = 3; isLoad = false; break;
5503 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
5504 NumVecs = 4; isLoad = false; break;
5505 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
5506 NumVecs = 2; isLoad = false; isLaneOp = true; break;
5507 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
5508 NumVecs = 3; isLoad = false; isLaneOp = true; break;
5509 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
5510 NumVecs = 4; isLoad = false; isLaneOp = true; break;
5514 switch (N->getOpcode()) {
5515 default: assert(0 && "unexpected opcode for Neon base update");
5516 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
5517 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
5518 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
5522 // Find the size of memory referenced by the load/store.
5525 VecTy = N->getValueType(0);
5527 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
5528 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
5530 NumBytes /= VecTy.getVectorNumElements();
5532 // If the increment is a constant, it must match the memory ref size.
5533 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
5534 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
5535 uint64_t IncVal = CInc->getZExtValue();
5536 if (IncVal != NumBytes)
5538 } else if (NumBytes >= 3 * 16) {
5539 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
5540 // separate instructions that make it harder to use a non-constant update.
5544 // Create the new updating load/store node.
5546 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
5548 for (n = 0; n < NumResultVecs; ++n)
5550 Tys[n++] = MVT::i32;
5551 Tys[n] = MVT::Other;
5552 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
5553 SmallVector<SDValue, 8> Ops;
5554 Ops.push_back(N->getOperand(0)); // incoming chain
5555 Ops.push_back(N->getOperand(AddrOpIdx));
5557 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
5558 Ops.push_back(N->getOperand(i));
5560 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
5561 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
5562 Ops.data(), Ops.size(),
5563 MemInt->getMemoryVT(),
5564 MemInt->getMemOperand());
5567 std::vector<SDValue> NewResults;
5568 for (unsigned i = 0; i < NumResultVecs; ++i) {
5569 NewResults.push_back(SDValue(UpdN.getNode(), i));
5571 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
5572 DCI.CombineTo(N, NewResults);
5573 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
5580 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
5581 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
5582 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
5584 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
5585 SelectionDAG &DAG = DCI.DAG;
5586 EVT VT = N->getValueType(0);
5587 // vldN-dup instructions only support 64-bit vectors for N > 1.
5588 if (!VT.is64BitVector())
5591 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
5592 SDNode *VLD = N->getOperand(0).getNode();
5593 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
5595 unsigned NumVecs = 0;
5596 unsigned NewOpc = 0;
5597 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
5598 if (IntNo == Intrinsic::arm_neon_vld2lane) {
5600 NewOpc = ARMISD::VLD2DUP;
5601 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
5603 NewOpc = ARMISD::VLD3DUP;
5604 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
5606 NewOpc = ARMISD::VLD4DUP;
5611 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
5612 // numbers match the load.
5613 unsigned VLDLaneNo =
5614 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
5615 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5617 // Ignore uses of the chain result.
5618 if (UI.getUse().getResNo() == NumVecs)
5621 if (User->getOpcode() != ARMISD::VDUPLANE ||
5622 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
5626 // Create the vldN-dup node.
5629 for (n = 0; n < NumVecs; ++n)
5631 Tys[n] = MVT::Other;
5632 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
5633 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
5634 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
5635 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
5636 Ops, 2, VLDMemInt->getMemoryVT(),
5637 VLDMemInt->getMemOperand());
5640 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5642 unsigned ResNo = UI.getUse().getResNo();
5643 // Ignore uses of the chain result.
5644 if (ResNo == NumVecs)
5647 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
5650 // Now the vldN-lane intrinsic is dead except for its chain result.
5651 // Update uses of the chain.
5652 std::vector<SDValue> VLDDupResults;
5653 for (unsigned n = 0; n < NumVecs; ++n)
5654 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
5655 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
5656 DCI.CombineTo(VLD, VLDDupResults);
5661 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
5662 /// ARMISD::VDUPLANE.
5663 static SDValue PerformVDUPLANECombine(SDNode *N,
5664 TargetLowering::DAGCombinerInfo &DCI) {
5665 SDValue Op = N->getOperand(0);
5667 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
5668 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
5669 if (CombineVLDDUP(N, DCI))
5670 return SDValue(N, 0);
5672 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
5673 // redundant. Ignore bit_converts for now; element sizes are checked below.
5674 while (Op.getOpcode() == ISD::BITCAST)
5675 Op = Op.getOperand(0);
5676 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
5679 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
5680 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
5681 // The canonical VMOV for a zero vector uses a 32-bit element size.
5682 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5684 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
5686 EVT VT = N->getValueType(0);
5687 if (EltSize > VT.getVectorElementType().getSizeInBits())
5690 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
5693 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5694 /// operand of a vector shift operation, where all the elements of the
5695 /// build_vector must have the same constant integer value.
5696 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5697 // Ignore bit_converts.
5698 while (Op.getOpcode() == ISD::BITCAST)
5699 Op = Op.getOperand(0);
5700 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5701 APInt SplatBits, SplatUndef;
5702 unsigned SplatBitSize;
5704 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5705 HasAnyUndefs, ElementBits) ||
5706 SplatBitSize > ElementBits)
5708 Cnt = SplatBits.getSExtValue();
5712 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5713 /// operand of a vector shift left operation. That value must be in the range:
5714 /// 0 <= Value < ElementBits for a left shift; or
5715 /// 0 <= Value <= ElementBits for a long left shift.
5716 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5717 assert(VT.isVector() && "vector shift count is not a vector type");
5718 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5719 if (! getVShiftImm(Op, ElementBits, Cnt))
5721 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
5724 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5725 /// operand of a vector shift right operation. For a shift opcode, the value
5726 /// is positive, but for an intrinsic the value count must be negative. The
5727 /// absolute value must be in the range:
5728 /// 1 <= |Value| <= ElementBits for a right shift; or
5729 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5730 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5732 assert(VT.isVector() && "vector shift count is not a vector type");
5733 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5734 if (! getVShiftImm(Op, ElementBits, Cnt))
5738 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
5741 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
5742 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
5743 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5746 // Don't do anything for most intrinsics.
5749 // Vector shifts: check for immediate versions and lower them.
5750 // Note: This is done during DAG combining instead of DAG legalizing because
5751 // the build_vectors for 64-bit vector element shift counts are generally
5752 // not legal, and it is hard to see their values after they get legalized to
5753 // loads from a constant pool.
5754 case Intrinsic::arm_neon_vshifts:
5755 case Intrinsic::arm_neon_vshiftu:
5756 case Intrinsic::arm_neon_vshiftls:
5757 case Intrinsic::arm_neon_vshiftlu:
5758 case Intrinsic::arm_neon_vshiftn:
5759 case Intrinsic::arm_neon_vrshifts:
5760 case Intrinsic::arm_neon_vrshiftu:
5761 case Intrinsic::arm_neon_vrshiftn:
5762 case Intrinsic::arm_neon_vqshifts:
5763 case Intrinsic::arm_neon_vqshiftu:
5764 case Intrinsic::arm_neon_vqshiftsu:
5765 case Intrinsic::arm_neon_vqshiftns:
5766 case Intrinsic::arm_neon_vqshiftnu:
5767 case Intrinsic::arm_neon_vqshiftnsu:
5768 case Intrinsic::arm_neon_vqrshiftns:
5769 case Intrinsic::arm_neon_vqrshiftnu:
5770 case Intrinsic::arm_neon_vqrshiftnsu: {
5771 EVT VT = N->getOperand(1).getValueType();
5773 unsigned VShiftOpc = 0;
5776 case Intrinsic::arm_neon_vshifts:
5777 case Intrinsic::arm_neon_vshiftu:
5778 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
5779 VShiftOpc = ARMISD::VSHL;
5782 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
5783 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
5784 ARMISD::VSHRs : ARMISD::VSHRu);
5789 case Intrinsic::arm_neon_vshiftls:
5790 case Intrinsic::arm_neon_vshiftlu:
5791 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
5793 llvm_unreachable("invalid shift count for vshll intrinsic");
5795 case Intrinsic::arm_neon_vrshifts:
5796 case Intrinsic::arm_neon_vrshiftu:
5797 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
5801 case Intrinsic::arm_neon_vqshifts:
5802 case Intrinsic::arm_neon_vqshiftu:
5803 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5807 case Intrinsic::arm_neon_vqshiftsu:
5808 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5810 llvm_unreachable("invalid shift count for vqshlu intrinsic");
5812 case Intrinsic::arm_neon_vshiftn:
5813 case Intrinsic::arm_neon_vrshiftn:
5814 case Intrinsic::arm_neon_vqshiftns:
5815 case Intrinsic::arm_neon_vqshiftnu:
5816 case Intrinsic::arm_neon_vqshiftnsu:
5817 case Intrinsic::arm_neon_vqrshiftns:
5818 case Intrinsic::arm_neon_vqrshiftnu:
5819 case Intrinsic::arm_neon_vqrshiftnsu:
5820 // Narrowing shifts require an immediate right shift.
5821 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
5823 llvm_unreachable("invalid shift count for narrowing vector shift "
5827 llvm_unreachable("unhandled vector shift");
5831 case Intrinsic::arm_neon_vshifts:
5832 case Intrinsic::arm_neon_vshiftu:
5833 // Opcode already set above.
5835 case Intrinsic::arm_neon_vshiftls:
5836 case Intrinsic::arm_neon_vshiftlu:
5837 if (Cnt == VT.getVectorElementType().getSizeInBits())
5838 VShiftOpc = ARMISD::VSHLLi;
5840 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
5841 ARMISD::VSHLLs : ARMISD::VSHLLu);
5843 case Intrinsic::arm_neon_vshiftn:
5844 VShiftOpc = ARMISD::VSHRN; break;
5845 case Intrinsic::arm_neon_vrshifts:
5846 VShiftOpc = ARMISD::VRSHRs; break;
5847 case Intrinsic::arm_neon_vrshiftu:
5848 VShiftOpc = ARMISD::VRSHRu; break;
5849 case Intrinsic::arm_neon_vrshiftn:
5850 VShiftOpc = ARMISD::VRSHRN; break;
5851 case Intrinsic::arm_neon_vqshifts:
5852 VShiftOpc = ARMISD::VQSHLs; break;
5853 case Intrinsic::arm_neon_vqshiftu:
5854 VShiftOpc = ARMISD::VQSHLu; break;
5855 case Intrinsic::arm_neon_vqshiftsu:
5856 VShiftOpc = ARMISD::VQSHLsu; break;
5857 case Intrinsic::arm_neon_vqshiftns:
5858 VShiftOpc = ARMISD::VQSHRNs; break;
5859 case Intrinsic::arm_neon_vqshiftnu:
5860 VShiftOpc = ARMISD::VQSHRNu; break;
5861 case Intrinsic::arm_neon_vqshiftnsu:
5862 VShiftOpc = ARMISD::VQSHRNsu; break;
5863 case Intrinsic::arm_neon_vqrshiftns:
5864 VShiftOpc = ARMISD::VQRSHRNs; break;
5865 case Intrinsic::arm_neon_vqrshiftnu:
5866 VShiftOpc = ARMISD::VQRSHRNu; break;
5867 case Intrinsic::arm_neon_vqrshiftnsu:
5868 VShiftOpc = ARMISD::VQRSHRNsu; break;
5871 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5872 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
5875 case Intrinsic::arm_neon_vshiftins: {
5876 EVT VT = N->getOperand(1).getValueType();
5878 unsigned VShiftOpc = 0;
5880 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
5881 VShiftOpc = ARMISD::VSLI;
5882 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
5883 VShiftOpc = ARMISD::VSRI;
5885 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
5888 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5889 N->getOperand(1), N->getOperand(2),
5890 DAG.getConstant(Cnt, MVT::i32));
5893 case Intrinsic::arm_neon_vqrshifts:
5894 case Intrinsic::arm_neon_vqrshiftu:
5895 // No immediate versions of these to check for.
5902 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
5903 /// lowers them. As with the vector shift intrinsics, this is done during DAG
5904 /// combining instead of DAG legalizing because the build_vectors for 64-bit
5905 /// vector element shift counts are generally not legal, and it is hard to see
5906 /// their values after they get legalized to loads from a constant pool.
5907 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
5908 const ARMSubtarget *ST) {
5909 EVT VT = N->getValueType(0);
5911 // Nothing to be done for scalar shifts.
5912 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5913 if (!VT.isVector() || !TLI.isTypeLegal(VT))
5916 assert(ST->hasNEON() && "unexpected vector shift");
5919 switch (N->getOpcode()) {
5920 default: llvm_unreachable("unexpected shift opcode");
5923 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
5924 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
5925 DAG.getConstant(Cnt, MVT::i32));
5930 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
5931 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
5932 ARMISD::VSHRs : ARMISD::VSHRu);
5933 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
5934 DAG.getConstant(Cnt, MVT::i32));
5940 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
5941 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
5942 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
5943 const ARMSubtarget *ST) {
5944 SDValue N0 = N->getOperand(0);
5946 // Check for sign- and zero-extensions of vector extract operations of 8-
5947 // and 16-bit vector elements. NEON supports these directly. They are
5948 // handled during DAG combining because type legalization will promote them
5949 // to 32-bit types and it is messy to recognize the operations after that.
5950 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5951 SDValue Vec = N0.getOperand(0);
5952 SDValue Lane = N0.getOperand(1);
5953 EVT VT = N->getValueType(0);
5954 EVT EltVT = N0.getValueType();
5955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5957 if (VT == MVT::i32 &&
5958 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
5959 TLI.isTypeLegal(Vec.getValueType()) &&
5960 isa<ConstantSDNode>(Lane)) {
5963 switch (N->getOpcode()) {
5964 default: llvm_unreachable("unexpected opcode");
5965 case ISD::SIGN_EXTEND:
5966 Opc = ARMISD::VGETLANEs;
5968 case ISD::ZERO_EXTEND:
5969 case ISD::ANY_EXTEND:
5970 Opc = ARMISD::VGETLANEu;
5973 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
5980 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
5981 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
5982 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
5983 const ARMSubtarget *ST) {
5984 // If the target supports NEON, try to use vmax/vmin instructions for f32
5985 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
5986 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
5987 // a NaN; only do the transformation when it matches that behavior.
5989 // For now only do this when using NEON for FP operations; if using VFP, it
5990 // is not obvious that the benefit outweighs the cost of switching to the
5992 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
5993 N->getValueType(0) != MVT::f32)
5996 SDValue CondLHS = N->getOperand(0);
5997 SDValue CondRHS = N->getOperand(1);
5998 SDValue LHS = N->getOperand(2);
5999 SDValue RHS = N->getOperand(3);
6000 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6002 unsigned Opcode = 0;
6004 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6005 IsReversed = false; // x CC y ? x : y
6006 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6007 IsReversed = true ; // x CC y ? y : x
6021 // If LHS is NaN, an ordered comparison will be false and the result will
6022 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6023 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6024 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6025 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6027 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6028 // will return -0, so vmin can only be used for unsafe math or if one of
6029 // the operands is known to be nonzero.
6030 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6032 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6034 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6043 // If LHS is NaN, an ordered comparison will be false and the result will
6044 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6045 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6046 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6047 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6049 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6050 // will return +0, so vmax can only be used for unsafe math or if one of
6051 // the operands is known to be nonzero.
6052 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6054 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6056 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6062 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6065 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6066 DAGCombinerInfo &DCI) const {
6067 switch (N->getOpcode()) {
6069 case ISD::ADD: return PerformADDCombine(N, DCI);
6070 case ISD::SUB: return PerformSUBCombine(N, DCI);
6071 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6072 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6073 case ISD::AND: return PerformANDCombine(N, DCI);
6074 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6075 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6076 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6077 case ISD::STORE: return PerformSTORECombine(N, DCI);
6078 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6079 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6080 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6081 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6082 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6085 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6086 case ISD::SIGN_EXTEND:
6087 case ISD::ZERO_EXTEND:
6088 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6089 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6090 case ARMISD::VLD2DUP:
6091 case ARMISD::VLD3DUP:
6092 case ARMISD::VLD4DUP:
6093 return CombineBaseUpdate(N, DCI);
6094 case ISD::INTRINSIC_VOID:
6095 case ISD::INTRINSIC_W_CHAIN:
6096 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6097 case Intrinsic::arm_neon_vld1:
6098 case Intrinsic::arm_neon_vld2:
6099 case Intrinsic::arm_neon_vld3:
6100 case Intrinsic::arm_neon_vld4:
6101 case Intrinsic::arm_neon_vld2lane:
6102 case Intrinsic::arm_neon_vld3lane:
6103 case Intrinsic::arm_neon_vld4lane:
6104 case Intrinsic::arm_neon_vst1:
6105 case Intrinsic::arm_neon_vst2:
6106 case Intrinsic::arm_neon_vst3:
6107 case Intrinsic::arm_neon_vst4:
6108 case Intrinsic::arm_neon_vst2lane:
6109 case Intrinsic::arm_neon_vst3lane:
6110 case Intrinsic::arm_neon_vst4lane:
6111 return CombineBaseUpdate(N, DCI);
6119 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6121 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6124 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6125 if (!Subtarget->allowsUnalignedMem())
6128 switch (VT.getSimpleVT().SimpleTy) {
6135 // FIXME: VLD1 etc with standard alignment is legal.
6139 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6144 switch (VT.getSimpleVT().SimpleTy) {
6145 default: return false;
6160 if ((V & (Scale - 1)) != 0)
6163 return V == (V & ((1LL << 5) - 1));
6166 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6167 const ARMSubtarget *Subtarget) {
6174 switch (VT.getSimpleVT().SimpleTy) {
6175 default: return false;
6180 // + imm12 or - imm8
6182 return V == (V & ((1LL << 8) - 1));
6183 return V == (V & ((1LL << 12) - 1));
6186 // Same as ARM mode. FIXME: NEON?
6187 if (!Subtarget->hasVFP2())
6192 return V == (V & ((1LL << 8) - 1));
6196 /// isLegalAddressImmediate - Return true if the integer value can be used
6197 /// as the offset of the target addressing mode for load / store of the
6199 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6200 const ARMSubtarget *Subtarget) {
6207 if (Subtarget->isThumb1Only())
6208 return isLegalT1AddressImmediate(V, VT);
6209 else if (Subtarget->isThumb2())
6210 return isLegalT2AddressImmediate(V, VT, Subtarget);
6215 switch (VT.getSimpleVT().SimpleTy) {
6216 default: return false;
6221 return V == (V & ((1LL << 12) - 1));
6224 return V == (V & ((1LL << 8) - 1));
6227 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6232 return V == (V & ((1LL << 8) - 1));
6236 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6238 int Scale = AM.Scale;
6242 switch (VT.getSimpleVT().SimpleTy) {
6243 default: return false;
6252 return Scale == 2 || Scale == 4 || Scale == 8;
6255 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6259 // Note, we allow "void" uses (basically, uses that aren't loads or
6260 // stores), because arm allows folding a scale into many arithmetic
6261 // operations. This should be made more precise and revisited later.
6263 // Allow r << imm, but the imm has to be a multiple of two.
6264 if (Scale & 1) return false;
6265 return isPowerOf2_32(Scale);
6269 /// isLegalAddressingMode - Return true if the addressing mode represented
6270 /// by AM is legal for this target, for a load/store of the specified type.
6271 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6272 const Type *Ty) const {
6273 EVT VT = getValueType(Ty, true);
6274 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6277 // Can never fold addr of global into load/store.
6282 case 0: // no scale reg, must be "r+i" or "r", or "i".
6285 if (Subtarget->isThumb1Only())
6289 // ARM doesn't support any R+R*scale+imm addr modes.
6296 if (Subtarget->isThumb2())
6297 return isLegalT2ScaledAddressingMode(AM, VT);
6299 int Scale = AM.Scale;
6300 switch (VT.getSimpleVT().SimpleTy) {
6301 default: return false;
6305 if (Scale < 0) Scale = -Scale;
6309 return isPowerOf2_32(Scale & ~1);
6313 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6318 // Note, we allow "void" uses (basically, uses that aren't loads or
6319 // stores), because arm allows folding a scale into many arithmetic
6320 // operations. This should be made more precise and revisited later.
6322 // Allow r << imm, but the imm has to be a multiple of two.
6323 if (Scale & 1) return false;
6324 return isPowerOf2_32(Scale);
6331 /// isLegalICmpImmediate - Return true if the specified immediate is legal
6332 /// icmp immediate, that is the target has icmp instructions which can compare
6333 /// a register against the immediate without having to materialize the
6334 /// immediate into a register.
6335 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
6336 if (!Subtarget->isThumb())
6337 return ARM_AM::getSOImmVal(Imm) != -1;
6338 if (Subtarget->isThumb2())
6339 return ARM_AM::getT2SOImmVal(Imm) != -1;
6340 return Imm >= 0 && Imm <= 255;
6343 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
6344 bool isSEXTLoad, SDValue &Base,
6345 SDValue &Offset, bool &isInc,
6346 SelectionDAG &DAG) {
6347 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6350 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
6352 Base = Ptr->getOperand(0);
6353 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6354 int RHSC = (int)RHS->getZExtValue();
6355 if (RHSC < 0 && RHSC > -256) {
6356 assert(Ptr->getOpcode() == ISD::ADD);
6358 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6362 isInc = (Ptr->getOpcode() == ISD::ADD);
6363 Offset = Ptr->getOperand(1);
6365 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
6367 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6368 int RHSC = (int)RHS->getZExtValue();
6369 if (RHSC < 0 && RHSC > -0x1000) {
6370 assert(Ptr->getOpcode() == ISD::ADD);
6372 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6373 Base = Ptr->getOperand(0);
6378 if (Ptr->getOpcode() == ISD::ADD) {
6380 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
6381 if (ShOpcVal != ARM_AM::no_shift) {
6382 Base = Ptr->getOperand(1);
6383 Offset = Ptr->getOperand(0);
6385 Base = Ptr->getOperand(0);
6386 Offset = Ptr->getOperand(1);
6391 isInc = (Ptr->getOpcode() == ISD::ADD);
6392 Base = Ptr->getOperand(0);
6393 Offset = Ptr->getOperand(1);
6397 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
6401 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
6402 bool isSEXTLoad, SDValue &Base,
6403 SDValue &Offset, bool &isInc,
6404 SelectionDAG &DAG) {
6405 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6408 Base = Ptr->getOperand(0);
6409 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6410 int RHSC = (int)RHS->getZExtValue();
6411 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
6412 assert(Ptr->getOpcode() == ISD::ADD);
6414 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6416 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
6417 isInc = Ptr->getOpcode() == ISD::ADD;
6418 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
6426 /// getPreIndexedAddressParts - returns true by value, base pointer and
6427 /// offset pointer and addressing mode by reference if the node's address
6428 /// can be legally represented as pre-indexed load / store address.
6430 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
6432 ISD::MemIndexedMode &AM,
6433 SelectionDAG &DAG) const {
6434 if (Subtarget->isThumb1Only())
6439 bool isSEXTLoad = false;
6440 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6441 Ptr = LD->getBasePtr();
6442 VT = LD->getMemoryVT();
6443 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6444 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6445 Ptr = ST->getBasePtr();
6446 VT = ST->getMemoryVT();
6451 bool isLegal = false;
6452 if (Subtarget->isThumb2())
6453 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6454 Offset, isInc, DAG);
6456 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6457 Offset, isInc, DAG);
6461 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
6465 /// getPostIndexedAddressParts - returns true by value, base pointer and
6466 /// offset pointer and addressing mode by reference if this node can be
6467 /// combined with a load / store to form a post-indexed load / store.
6468 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
6471 ISD::MemIndexedMode &AM,
6472 SelectionDAG &DAG) const {
6473 if (Subtarget->isThumb1Only())
6478 bool isSEXTLoad = false;
6479 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6480 VT = LD->getMemoryVT();
6481 Ptr = LD->getBasePtr();
6482 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6483 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6484 VT = ST->getMemoryVT();
6485 Ptr = ST->getBasePtr();
6490 bool isLegal = false;
6491 if (Subtarget->isThumb2())
6492 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6495 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6501 // Swap base ptr and offset to catch more post-index load / store when
6502 // it's legal. In Thumb2 mode, offset must be an immediate.
6503 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
6504 !Subtarget->isThumb2())
6505 std::swap(Base, Offset);
6507 // Post-indexed load / store update the base pointer.
6512 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
6516 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6520 const SelectionDAG &DAG,
6521 unsigned Depth) const {
6522 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
6523 switch (Op.getOpcode()) {
6525 case ARMISD::CMOV: {
6526 // Bits are known zero/one if known on the LHS and RHS.
6527 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
6528 if (KnownZero == 0 && KnownOne == 0) return;
6530 APInt KnownZeroRHS, KnownOneRHS;
6531 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
6532 KnownZeroRHS, KnownOneRHS, Depth+1);
6533 KnownZero &= KnownZeroRHS;
6534 KnownOne &= KnownOneRHS;
6540 //===----------------------------------------------------------------------===//
6541 // ARM Inline Assembly Support
6542 //===----------------------------------------------------------------------===//
6544 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
6545 // Looking for "rev" which is V6+.
6546 if (!Subtarget->hasV6Ops())
6549 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
6550 std::string AsmStr = IA->getAsmString();
6551 SmallVector<StringRef, 4> AsmPieces;
6552 SplitString(AsmStr, AsmPieces, ";\n");
6554 switch (AsmPieces.size()) {
6555 default: return false;
6557 AsmStr = AsmPieces[0];
6559 SplitString(AsmStr, AsmPieces, " \t,");
6562 if (AsmPieces.size() == 3 &&
6563 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
6564 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
6565 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
6566 if (Ty && Ty->getBitWidth() == 32)
6567 return IntrinsicLowering::LowerToByteSwap(CI);
6575 /// getConstraintType - Given a constraint letter, return the type of
6576 /// constraint it is for this target.
6577 ARMTargetLowering::ConstraintType
6578 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
6579 if (Constraint.size() == 1) {
6580 switch (Constraint[0]) {
6582 case 'l': return C_RegisterClass;
6583 case 'w': return C_RegisterClass;
6586 return TargetLowering::getConstraintType(Constraint);
6589 /// Examine constraint type and operand type and determine a weight value.
6590 /// This object must already have been set up with the operand type
6591 /// and the current alternative constraint selected.
6592 TargetLowering::ConstraintWeight
6593 ARMTargetLowering::getSingleConstraintMatchWeight(
6594 AsmOperandInfo &info, const char *constraint) const {
6595 ConstraintWeight weight = CW_Invalid;
6596 Value *CallOperandVal = info.CallOperandVal;
6597 // If we don't have a value, we can't do a match,
6598 // but allow it at the lowest weight.
6599 if (CallOperandVal == NULL)
6601 const Type *type = CallOperandVal->getType();
6602 // Look at the constraint type.
6603 switch (*constraint) {
6605 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6608 if (type->isIntegerTy()) {
6609 if (Subtarget->isThumb())
6610 weight = CW_SpecificReg;
6612 weight = CW_Register;
6616 if (type->isFloatingPointTy())
6617 weight = CW_Register;
6623 std::pair<unsigned, const TargetRegisterClass*>
6624 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6626 if (Constraint.size() == 1) {
6627 // GCC ARM Constraint Letters
6628 switch (Constraint[0]) {
6630 if (Subtarget->isThumb())
6631 return std::make_pair(0U, ARM::tGPRRegisterClass);
6633 return std::make_pair(0U, ARM::GPRRegisterClass);
6635 return std::make_pair(0U, ARM::GPRRegisterClass);
6638 return std::make_pair(0U, ARM::SPRRegisterClass);
6639 if (VT.getSizeInBits() == 64)
6640 return std::make_pair(0U, ARM::DPRRegisterClass);
6641 if (VT.getSizeInBits() == 128)
6642 return std::make_pair(0U, ARM::QPRRegisterClass);
6646 if (StringRef("{cc}").equals_lower(Constraint))
6647 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
6649 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6652 std::vector<unsigned> ARMTargetLowering::
6653 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6655 if (Constraint.size() != 1)
6656 return std::vector<unsigned>();
6658 switch (Constraint[0]) { // GCC ARM Constraint Letters
6661 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6662 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6665 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6666 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6667 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
6668 ARM::R12, ARM::LR, 0);
6671 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
6672 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
6673 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
6674 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
6675 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
6676 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
6677 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
6678 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
6679 if (VT.getSizeInBits() == 64)
6680 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
6681 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
6682 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
6683 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
6684 if (VT.getSizeInBits() == 128)
6685 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
6686 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
6690 return std::vector<unsigned>();
6693 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6694 /// vector. If it is invalid, don't add anything to Ops.
6695 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6697 std::vector<SDValue>&Ops,
6698 SelectionDAG &DAG) const {
6699 SDValue Result(0, 0);
6701 switch (Constraint) {
6703 case 'I': case 'J': case 'K': case 'L':
6704 case 'M': case 'N': case 'O':
6705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
6709 int64_t CVal64 = C->getSExtValue();
6710 int CVal = (int) CVal64;
6711 // None of these constraints allow values larger than 32 bits. Check
6712 // that the value fits in an int.
6716 switch (Constraint) {
6718 if (Subtarget->isThumb1Only()) {
6719 // This must be a constant between 0 and 255, for ADD
6721 if (CVal >= 0 && CVal <= 255)
6723 } else if (Subtarget->isThumb2()) {
6724 // A constant that can be used as an immediate value in a
6725 // data-processing instruction.
6726 if (ARM_AM::getT2SOImmVal(CVal) != -1)
6729 // A constant that can be used as an immediate value in a
6730 // data-processing instruction.
6731 if (ARM_AM::getSOImmVal(CVal) != -1)
6737 if (Subtarget->isThumb()) { // FIXME thumb2
6738 // This must be a constant between -255 and -1, for negated ADD
6739 // immediates. This can be used in GCC with an "n" modifier that
6740 // prints the negated value, for use with SUB instructions. It is
6741 // not useful otherwise but is implemented for compatibility.
6742 if (CVal >= -255 && CVal <= -1)
6745 // This must be a constant between -4095 and 4095. It is not clear
6746 // what this constraint is intended for. Implemented for
6747 // compatibility with GCC.
6748 if (CVal >= -4095 && CVal <= 4095)
6754 if (Subtarget->isThumb1Only()) {
6755 // A 32-bit value where only one byte has a nonzero value. Exclude
6756 // zero to match GCC. This constraint is used by GCC internally for
6757 // constants that can be loaded with a move/shift combination.
6758 // It is not useful otherwise but is implemented for compatibility.
6759 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
6761 } else if (Subtarget->isThumb2()) {
6762 // A constant whose bitwise inverse can be used as an immediate
6763 // value in a data-processing instruction. This can be used in GCC
6764 // with a "B" modifier that prints the inverted value, for use with
6765 // BIC and MVN instructions. It is not useful otherwise but is
6766 // implemented for compatibility.
6767 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
6770 // A constant whose bitwise inverse can be used as an immediate
6771 // value in a data-processing instruction. This can be used in GCC
6772 // with a "B" modifier that prints the inverted value, for use with
6773 // BIC and MVN instructions. It is not useful otherwise but is
6774 // implemented for compatibility.
6775 if (ARM_AM::getSOImmVal(~CVal) != -1)
6781 if (Subtarget->isThumb1Only()) {
6782 // This must be a constant between -7 and 7,
6783 // for 3-operand ADD/SUB immediate instructions.
6784 if (CVal >= -7 && CVal < 7)
6786 } else if (Subtarget->isThumb2()) {
6787 // A constant whose negation can be used as an immediate value in a
6788 // data-processing instruction. This can be used in GCC with an "n"
6789 // modifier that prints the negated value, for use with SUB
6790 // instructions. It is not useful otherwise but is implemented for
6792 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
6795 // A constant whose negation can be used as an immediate value in a
6796 // data-processing instruction. This can be used in GCC with an "n"
6797 // modifier that prints the negated value, for use with SUB
6798 // instructions. It is not useful otherwise but is implemented for
6800 if (ARM_AM::getSOImmVal(-CVal) != -1)
6806 if (Subtarget->isThumb()) { // FIXME thumb2
6807 // This must be a multiple of 4 between 0 and 1020, for
6808 // ADD sp + immediate.
6809 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
6812 // A power of two or a constant between 0 and 32. This is used in
6813 // GCC for the shift amount on shifted register operands, but it is
6814 // useful in general for any shift amounts.
6815 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
6821 if (Subtarget->isThumb()) { // FIXME thumb2
6822 // This must be a constant between 0 and 31, for shift amounts.
6823 if (CVal >= 0 && CVal <= 31)
6829 if (Subtarget->isThumb()) { // FIXME thumb2
6830 // This must be a multiple of 4 between -508 and 508, for
6831 // ADD/SUB sp = sp + immediate.
6832 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
6837 Result = DAG.getTargetConstant(CVal, Op.getValueType());
6841 if (Result.getNode()) {
6842 Ops.push_back(Result);
6845 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6849 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6850 // The ARM target isn't yet aware of offsets.
6854 int ARM::getVFPf32Imm(const APFloat &FPImm) {
6855 APInt Imm = FPImm.bitcastToAPInt();
6856 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
6857 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
6858 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
6860 // We can handle 4 bits of mantissa.
6861 // mantissa = (16+UInt(e:f:g:h))/16.
6862 if (Mantissa & 0x7ffff)
6865 if ((Mantissa & 0xf) != Mantissa)
6868 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6869 if (Exp < -3 || Exp > 4)
6871 Exp = ((Exp+3) & 0x7) ^ 4;
6873 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6876 int ARM::getVFPf64Imm(const APFloat &FPImm) {
6877 APInt Imm = FPImm.bitcastToAPInt();
6878 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
6879 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
6880 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
6882 // We can handle 4 bits of mantissa.
6883 // mantissa = (16+UInt(e:f:g:h))/16.
6884 if (Mantissa & 0xffffffffffffLL)
6887 if ((Mantissa & 0xf) != Mantissa)
6890 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6891 if (Exp < -3 || Exp > 4)
6893 Exp = ((Exp+3) & 0x7) ^ 4;
6895 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6898 bool ARM::isBitFieldInvertedMask(unsigned v) {
6899 if (v == 0xffffffff)
6901 // there can be 1's on either or both "outsides", all the "inside"
6903 unsigned int lsb = 0, msb = 31;
6904 while (v & (1 << msb)) --msb;
6905 while (v & (1 << lsb)) ++lsb;
6906 for (unsigned int i = lsb; i <= msb; ++i) {
6913 /// isFPImmLegal - Returns true if the target can instruction select the
6914 /// specified FP immediate natively. If false, the legalizer will
6915 /// materialize the FP immediate as a load from a constant pool.
6916 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
6917 if (!Subtarget->hasVFP3())
6920 return ARM::getVFPf32Imm(Imm) != -1;
6922 return ARM::getVFPf64Imm(Imm) != -1;
6926 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6927 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6928 /// specified in the intrinsic calls.
6929 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6931 unsigned Intrinsic) const {
6932 switch (Intrinsic) {
6933 case Intrinsic::arm_neon_vld1:
6934 case Intrinsic::arm_neon_vld2:
6935 case Intrinsic::arm_neon_vld3:
6936 case Intrinsic::arm_neon_vld4:
6937 case Intrinsic::arm_neon_vld2lane:
6938 case Intrinsic::arm_neon_vld3lane:
6939 case Intrinsic::arm_neon_vld4lane: {
6940 Info.opc = ISD::INTRINSIC_W_CHAIN;
6941 // Conservatively set memVT to the entire set of vectors loaded.
6942 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
6943 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6944 Info.ptrVal = I.getArgOperand(0);
6946 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6947 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6948 Info.vol = false; // volatile loads with NEON intrinsics not supported
6949 Info.readMem = true;
6950 Info.writeMem = false;
6953 case Intrinsic::arm_neon_vst1:
6954 case Intrinsic::arm_neon_vst2:
6955 case Intrinsic::arm_neon_vst3:
6956 case Intrinsic::arm_neon_vst4:
6957 case Intrinsic::arm_neon_vst2lane:
6958 case Intrinsic::arm_neon_vst3lane:
6959 case Intrinsic::arm_neon_vst4lane: {
6960 Info.opc = ISD::INTRINSIC_VOID;
6961 // Conservatively set memVT to the entire set of vectors stored.
6962 unsigned NumElts = 0;
6963 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6964 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
6965 if (!ArgTy->isVectorTy())
6967 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
6969 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6970 Info.ptrVal = I.getArgOperand(0);
6972 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6973 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6974 Info.vol = false; // volatile stores with NEON intrinsics not supported
6975 Info.readMem = false;
6976 Info.writeMem = true;