1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
76 EVT PromotedBitwiseVT) {
77 if (VT != PromotedLdStVT) {
78 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
79 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
80 PromotedLdStVT.getSimpleVT());
82 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
83 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
84 PromotedLdStVT.getSimpleVT());
87 EVT ElemTy = VT.getVectorElementType();
88 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
89 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
91 if (ElemTy != MVT::i32) {
92 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
97 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
98 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
99 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
100 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
101 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
103 if (VT.isInteger()) {
104 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
105 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
106 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
107 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
108 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
109 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
110 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
111 setTruncStoreAction(VT.getSimpleVT(),
112 (MVT::SimpleValueType)InnerVT, Expand);
114 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
116 // Promote all bit-wise operations.
117 if (VT.isInteger() && VT != PromotedBitwiseVT) {
118 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
124 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
125 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
126 PromotedBitwiseVT.getSimpleVT());
129 // Neon does not support vector divide/remainder operations.
130 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
134 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
138 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
139 addRegisterClass(VT, ARM::DPRRegisterClass);
140 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
143 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::QPRRegisterClass);
145 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
148 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
149 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
150 return new TargetLoweringObjectFileMachO();
152 return new ARMElfTargetObjectFile();
155 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<ARMSubtarget>();
158 RegInfo = TM.getRegisterInfo();
159 Itins = TM.getInstrItineraryData();
161 if (Subtarget->isTargetDarwin()) {
162 // Uses VFP for Thumb libfuncs if available.
163 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
164 // Single-precision floating-point arithmetic.
165 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
166 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
167 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
168 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
170 // Double-precision floating-point arithmetic.
171 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
172 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
173 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
174 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
176 // Single-precision comparisons.
177 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
178 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
179 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
180 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
181 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
182 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
183 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
184 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
186 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
195 // Double-precision comparisons.
196 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
197 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
198 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
199 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
200 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
201 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
202 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
203 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
205 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
214 // Floating-point to integer conversions.
215 // i64 conversions are done via library routines even when generating VFP
216 // instructions, so use the same ones.
217 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
218 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
219 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
220 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
222 // Conversions between floating types.
223 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
224 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
226 // Integer to floating-point conversions.
227 // i64 conversions are done via library routines even when generating VFP
228 // instructions, so use the same ones.
229 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
230 // e.g., __floatunsidf vs. __floatunssidfvfp.
231 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
232 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
233 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
234 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
238 // These libcalls are not available in 32-bit.
239 setLibcallName(RTLIB::SHL_I128, 0);
240 setLibcallName(RTLIB::SRL_I128, 0);
241 setLibcallName(RTLIB::SRA_I128, 0);
243 if (Subtarget->isAAPCS_ABI()) {
244 // Double-precision floating-point arithmetic helper functions
245 // RTABI chapter 4.1.2, Table 2
246 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
247 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
248 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
249 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
250 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
251 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
252 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
253 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
255 // Double-precision floating-point comparison helper functions
256 // RTABI chapter 4.1.2, Table 3
257 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
258 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
259 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
260 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
261 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
262 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
263 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
264 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
265 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
266 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
267 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
268 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
269 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
270 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
271 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
272 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
273 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
282 // Single-precision floating-point arithmetic helper functions
283 // RTABI chapter 4.1.2, Table 4
284 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
285 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
286 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
287 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
288 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
289 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
293 // Single-precision floating-point comparison helper functions
294 // RTABI chapter 4.1.2, Table 5
295 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
296 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
297 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
298 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
299 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
300 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
301 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
302 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
303 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
304 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
305 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
306 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
307 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
308 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
309 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
310 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
311 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
320 // Floating-point to integer conversions.
321 // RTABI chapter 4.1.2, Table 6
322 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
323 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
324 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
325 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
326 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
327 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
328 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
329 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
330 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
339 // Conversions between floating types.
340 // RTABI chapter 4.1.2, Table 7
341 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
342 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
343 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
344 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
346 // Integer to floating-point conversions.
347 // RTABI chapter 4.1.2, Table 8
348 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
349 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
350 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
351 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
352 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
353 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
354 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
355 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
356 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
365 // Long long helper functions
366 // RTABI chapter 4.2, Table 9
367 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
368 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
369 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
370 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
371 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
372 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
373 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
380 // Integer division functions
381 // RTABI chapter 4.3.1
382 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
383 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
384 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
385 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
386 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
387 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
388 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
396 if (HasDivModLibcall) {
397 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
398 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
401 if (Subtarget->isThumb1Only())
402 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
404 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
405 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
406 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
407 if (!Subtarget->isFPOnlySP())
408 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
410 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
413 if (Subtarget->hasNEON()) {
414 addDRTypeForNEON(MVT::v2f32);
415 addDRTypeForNEON(MVT::v8i8);
416 addDRTypeForNEON(MVT::v4i16);
417 addDRTypeForNEON(MVT::v2i32);
418 addDRTypeForNEON(MVT::v1i64);
420 addQRTypeForNEON(MVT::v4f32);
421 addQRTypeForNEON(MVT::v2f64);
422 addQRTypeForNEON(MVT::v16i8);
423 addQRTypeForNEON(MVT::v8i16);
424 addQRTypeForNEON(MVT::v4i32);
425 addQRTypeForNEON(MVT::v2i64);
427 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
428 // neither Neon nor VFP support any arithmetic operations on it.
429 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
431 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
432 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
433 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
434 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
435 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
436 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
437 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
438 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
439 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
441 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
442 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
443 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
444 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
445 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
446 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
447 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
448 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
449 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
450 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
451 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
452 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
454 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
456 // Neon does not support some operations on v1i64 and v2i64 types.
457 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
458 // Custom handling for some quad-vector types to detect VMULL.
459 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
460 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
461 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
462 // Custom handling for some vector types to avoid expensive expansions
463 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
464 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
465 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
466 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
467 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
468 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
469 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
470 // a destination type that is wider than the source.
471 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
472 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
474 setTargetDAGCombine(ISD::INTRINSIC_VOID);
475 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
476 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
477 setTargetDAGCombine(ISD::SHL);
478 setTargetDAGCombine(ISD::SRL);
479 setTargetDAGCombine(ISD::SRA);
480 setTargetDAGCombine(ISD::SIGN_EXTEND);
481 setTargetDAGCombine(ISD::ZERO_EXTEND);
482 setTargetDAGCombine(ISD::ANY_EXTEND);
483 setTargetDAGCombine(ISD::SELECT_CC);
484 setTargetDAGCombine(ISD::BUILD_VECTOR);
485 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
486 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
487 setTargetDAGCombine(ISD::STORE);
490 computeRegisterProperties();
492 // ARM does not have f32 extending load.
493 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
495 // ARM does not have i1 sign extending load.
496 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
498 // ARM supports all 4 flavors of integer indexed load / store.
499 if (!Subtarget->isThumb1Only()) {
500 for (unsigned im = (unsigned)ISD::PRE_INC;
501 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
502 setIndexedLoadAction(im, MVT::i1, Legal);
503 setIndexedLoadAction(im, MVT::i8, Legal);
504 setIndexedLoadAction(im, MVT::i16, Legal);
505 setIndexedLoadAction(im, MVT::i32, Legal);
506 setIndexedStoreAction(im, MVT::i1, Legal);
507 setIndexedStoreAction(im, MVT::i8, Legal);
508 setIndexedStoreAction(im, MVT::i16, Legal);
509 setIndexedStoreAction(im, MVT::i32, Legal);
513 // i64 operation support.
514 if (Subtarget->isThumb1Only()) {
515 setOperationAction(ISD::MUL, MVT::i64, Expand);
516 setOperationAction(ISD::MULHU, MVT::i32, Expand);
517 setOperationAction(ISD::MULHS, MVT::i32, Expand);
518 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
519 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
521 setOperationAction(ISD::MUL, MVT::i64, Expand);
522 setOperationAction(ISD::MULHU, MVT::i32, Expand);
523 if (!Subtarget->hasV6Ops())
524 setOperationAction(ISD::MULHS, MVT::i32, Expand);
526 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
527 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
528 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
529 setOperationAction(ISD::SRL, MVT::i64, Custom);
530 setOperationAction(ISD::SRA, MVT::i64, Custom);
532 // ARM does not have ROTL.
533 setOperationAction(ISD::ROTL, MVT::i32, Expand);
534 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
535 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
536 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
537 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
539 // Only ARMv6 has BSWAP.
540 if (!Subtarget->hasV6Ops())
541 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
543 // These are expanded into libcalls.
544 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
545 // v7M has a hardware divider
546 setOperationAction(ISD::SDIV, MVT::i32, Expand);
547 setOperationAction(ISD::UDIV, MVT::i32, Expand);
549 setOperationAction(ISD::SREM, MVT::i32, Expand);
550 setOperationAction(ISD::UREM, MVT::i32, Expand);
551 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
552 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
554 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
555 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
556 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
557 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
558 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
560 setOperationAction(ISD::TRAP, MVT::Other, Legal);
562 // Use the default implementation.
563 setOperationAction(ISD::VASTART, MVT::Other, Custom);
564 setOperationAction(ISD::VAARG, MVT::Other, Expand);
565 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
566 setOperationAction(ISD::VAEND, MVT::Other, Expand);
567 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
568 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
569 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
570 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
571 setExceptionPointerRegister(ARM::R0);
572 setExceptionSelectorRegister(ARM::R1);
574 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
575 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
576 // the default expansion.
577 if (Subtarget->hasDataBarrier() ||
578 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
579 // membarrier needs custom lowering; the rest are legal and handled
581 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
583 // Set them all for expansion, which will force libcalls.
584 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
585 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
586 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
587 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
588 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
589 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
590 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
591 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
592 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
601 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
602 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
603 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
604 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
605 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
606 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
607 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
608 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
609 // Since the libcalls include locking, fold in the fences
610 setShouldFoldAtomicFences(true);
612 // 64-bit versions are always libcalls (for now)
613 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
614 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
622 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
624 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
625 if (!Subtarget->hasV6Ops()) {
626 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
627 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
629 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
631 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
632 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
633 // iff target supports vfp2.
634 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
635 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
638 // We want to custom lower some of our intrinsics.
639 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
640 if (Subtarget->isTargetDarwin()) {
641 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
642 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
643 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
646 setOperationAction(ISD::SETCC, MVT::i32, Expand);
647 setOperationAction(ISD::SETCC, MVT::f32, Expand);
648 setOperationAction(ISD::SETCC, MVT::f64, Expand);
649 setOperationAction(ISD::SELECT, MVT::i32, Custom);
650 setOperationAction(ISD::SELECT, MVT::f32, Custom);
651 setOperationAction(ISD::SELECT, MVT::f64, Custom);
652 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
653 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
654 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
656 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
657 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
658 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
659 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
660 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
662 // We don't support sin/cos/fmod/copysign/pow
663 setOperationAction(ISD::FSIN, MVT::f64, Expand);
664 setOperationAction(ISD::FSIN, MVT::f32, Expand);
665 setOperationAction(ISD::FCOS, MVT::f32, Expand);
666 setOperationAction(ISD::FCOS, MVT::f64, Expand);
667 setOperationAction(ISD::FREM, MVT::f64, Expand);
668 setOperationAction(ISD::FREM, MVT::f32, Expand);
669 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 setOperationAction(ISD::FPOW, MVT::f64, Expand);
674 setOperationAction(ISD::FPOW, MVT::f32, Expand);
676 // Various VFP goodness
677 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
678 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
679 if (Subtarget->hasVFP2()) {
680 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
681 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
682 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
683 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
685 // Special handling for half-precision FP.
686 if (!Subtarget->hasFP16()) {
687 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
688 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
692 // We have target-specific dag combine patterns for the following nodes:
693 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
694 setTargetDAGCombine(ISD::ADD);
695 setTargetDAGCombine(ISD::SUB);
696 setTargetDAGCombine(ISD::MUL);
698 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
699 setTargetDAGCombine(ISD::OR);
700 if (Subtarget->hasNEON())
701 setTargetDAGCombine(ISD::AND);
703 setStackPointerRegisterToSaveRestore(ARM::SP);
705 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
706 setSchedulingPreference(Sched::RegPressure);
708 setSchedulingPreference(Sched::Hybrid);
710 //// temporary - rewrite interface to use type
711 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
713 // On ARM arguments smaller than 4 bytes are extended, so all arguments
714 // are at least 4 bytes aligned.
715 setMinStackArgumentAlignment(4);
717 benefitFromCodePlacementOpt = true;
720 // FIXME: It might make sense to define the representative register class as the
721 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
722 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
723 // SPR's representative would be DPR_VFP2. This should work well if register
724 // pressure tracking were modified such that a register use would increment the
725 // pressure of the register class's representative and all of it's super
726 // classes' representatives transitively. We have not implemented this because
727 // of the difficulty prior to coalescing of modeling operand register classes
728 // due to the common occurence of cross class copies and subregister insertions
730 std::pair<const TargetRegisterClass*, uint8_t>
731 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
732 const TargetRegisterClass *RRC = 0;
734 switch (VT.getSimpleVT().SimpleTy) {
736 return TargetLowering::findRepresentativeClass(VT);
737 // Use DPR as representative register class for all floating point
738 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
739 // the cost is 1 for both f32 and f64.
740 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
741 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
742 RRC = ARM::DPRRegisterClass;
743 // When NEON is used for SP, only half of the register file is available
744 // because operations that define both SP and DP results will be constrained
745 // to the VFP2 class (D0-D15). We currently model this constraint prior to
746 // coalescing by double-counting the SP regs. See the FIXME above.
747 if (Subtarget->useNEONForSinglePrecisionFP())
750 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
751 case MVT::v4f32: case MVT::v2f64:
752 RRC = ARM::DPRRegisterClass;
756 RRC = ARM::DPRRegisterClass;
760 RRC = ARM::DPRRegisterClass;
764 return std::make_pair(RRC, Cost);
767 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
770 case ARMISD::Wrapper: return "ARMISD::Wrapper";
771 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
772 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
773 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
774 case ARMISD::CALL: return "ARMISD::CALL";
775 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
776 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
777 case ARMISD::tCALL: return "ARMISD::tCALL";
778 case ARMISD::BRCOND: return "ARMISD::BRCOND";
779 case ARMISD::BR_JT: return "ARMISD::BR_JT";
780 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
781 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
782 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
783 case ARMISD::CMP: return "ARMISD::CMP";
784 case ARMISD::CMPZ: return "ARMISD::CMPZ";
785 case ARMISD::CMPFP: return "ARMISD::CMPFP";
786 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
787 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
788 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
789 case ARMISD::CMOV: return "ARMISD::CMOV";
791 case ARMISD::RBIT: return "ARMISD::RBIT";
793 case ARMISD::FTOSI: return "ARMISD::FTOSI";
794 case ARMISD::FTOUI: return "ARMISD::FTOUI";
795 case ARMISD::SITOF: return "ARMISD::SITOF";
796 case ARMISD::UITOF: return "ARMISD::UITOF";
798 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
799 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
800 case ARMISD::RRX: return "ARMISD::RRX";
802 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
803 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
805 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
806 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
807 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
809 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
811 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
813 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
815 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
816 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
818 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
820 case ARMISD::VCEQ: return "ARMISD::VCEQ";
821 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
822 case ARMISD::VCGE: return "ARMISD::VCGE";
823 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
824 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
825 case ARMISD::VCGEU: return "ARMISD::VCGEU";
826 case ARMISD::VCGT: return "ARMISD::VCGT";
827 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
828 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
829 case ARMISD::VCGTU: return "ARMISD::VCGTU";
830 case ARMISD::VTST: return "ARMISD::VTST";
832 case ARMISD::VSHL: return "ARMISD::VSHL";
833 case ARMISD::VSHRs: return "ARMISD::VSHRs";
834 case ARMISD::VSHRu: return "ARMISD::VSHRu";
835 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
836 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
837 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
838 case ARMISD::VSHRN: return "ARMISD::VSHRN";
839 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
840 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
841 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
842 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
843 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
844 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
845 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
846 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
847 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
848 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
849 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
850 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
851 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
852 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
853 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
854 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
855 case ARMISD::VDUP: return "ARMISD::VDUP";
856 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
857 case ARMISD::VEXT: return "ARMISD::VEXT";
858 case ARMISD::VREV64: return "ARMISD::VREV64";
859 case ARMISD::VREV32: return "ARMISD::VREV32";
860 case ARMISD::VREV16: return "ARMISD::VREV16";
861 case ARMISD::VZIP: return "ARMISD::VZIP";
862 case ARMISD::VUZP: return "ARMISD::VUZP";
863 case ARMISD::VTRN: return "ARMISD::VTRN";
864 case ARMISD::VTBL1: return "ARMISD::VTBL1";
865 case ARMISD::VTBL2: return "ARMISD::VTBL2";
866 case ARMISD::VMULLs: return "ARMISD::VMULLs";
867 case ARMISD::VMULLu: return "ARMISD::VMULLu";
868 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
869 case ARMISD::FMAX: return "ARMISD::FMAX";
870 case ARMISD::FMIN: return "ARMISD::FMIN";
871 case ARMISD::BFI: return "ARMISD::BFI";
872 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
873 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
874 case ARMISD::VBSL: return "ARMISD::VBSL";
875 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
876 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
877 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
878 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
879 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
880 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
881 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
882 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
883 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
884 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
885 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
886 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
887 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
888 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
889 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
890 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
891 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
892 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
893 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
894 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
898 /// getRegClassFor - Return the register class that should be used for the
899 /// specified value type.
900 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
901 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
902 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
903 // load / store 4 to 8 consecutive D registers.
904 if (Subtarget->hasNEON()) {
905 if (VT == MVT::v4i64)
906 return ARM::QQPRRegisterClass;
907 else if (VT == MVT::v8i64)
908 return ARM::QQQQPRRegisterClass;
910 return TargetLowering::getRegClassFor(VT);
913 // Create a fast isel object.
915 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
916 return ARM::createFastISel(funcInfo);
919 /// getFunctionAlignment - Return the Log2 alignment of this function.
920 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
921 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
924 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
925 /// be used for loads / stores from the global.
926 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
927 return (Subtarget->isThumb1Only() ? 127 : 4095);
930 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
931 unsigned NumVals = N->getNumValues();
933 return Sched::RegPressure;
935 for (unsigned i = 0; i != NumVals; ++i) {
936 EVT VT = N->getValueType(i);
937 if (VT == MVT::Glue || VT == MVT::Other)
939 if (VT.isFloatingPoint() || VT.isVector())
940 return Sched::Latency;
943 if (!N->isMachineOpcode())
944 return Sched::RegPressure;
946 // Load are scheduled for latency even if there instruction itinerary
948 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
949 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
951 if (TID.getNumDefs() == 0)
952 return Sched::RegPressure;
953 if (!Itins->isEmpty() &&
954 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
955 return Sched::Latency;
957 return Sched::RegPressure;
960 //===----------------------------------------------------------------------===//
962 //===----------------------------------------------------------------------===//
964 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
965 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
967 default: llvm_unreachable("Unknown condition code!");
968 case ISD::SETNE: return ARMCC::NE;
969 case ISD::SETEQ: return ARMCC::EQ;
970 case ISD::SETGT: return ARMCC::GT;
971 case ISD::SETGE: return ARMCC::GE;
972 case ISD::SETLT: return ARMCC::LT;
973 case ISD::SETLE: return ARMCC::LE;
974 case ISD::SETUGT: return ARMCC::HI;
975 case ISD::SETUGE: return ARMCC::HS;
976 case ISD::SETULT: return ARMCC::LO;
977 case ISD::SETULE: return ARMCC::LS;
981 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
982 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
983 ARMCC::CondCodes &CondCode2) {
984 CondCode2 = ARMCC::AL;
986 default: llvm_unreachable("Unknown FP condition!");
988 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
990 case ISD::SETOGT: CondCode = ARMCC::GT; break;
992 case ISD::SETOGE: CondCode = ARMCC::GE; break;
993 case ISD::SETOLT: CondCode = ARMCC::MI; break;
994 case ISD::SETOLE: CondCode = ARMCC::LS; break;
995 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
996 case ISD::SETO: CondCode = ARMCC::VC; break;
997 case ISD::SETUO: CondCode = ARMCC::VS; break;
998 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
999 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1000 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1002 case ISD::SETULT: CondCode = ARMCC::LT; break;
1004 case ISD::SETULE: CondCode = ARMCC::LE; break;
1006 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1010 //===----------------------------------------------------------------------===//
1011 // Calling Convention Implementation
1012 //===----------------------------------------------------------------------===//
1014 #include "ARMGenCallingConv.inc"
1016 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1017 /// given CallingConvention value.
1018 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1020 bool isVarArg) const {
1023 llvm_unreachable("Unsupported calling convention");
1024 case CallingConv::Fast:
1025 if (Subtarget->hasVFP2() && !isVarArg) {
1026 if (!Subtarget->isAAPCS_ABI())
1027 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1028 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1029 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1032 case CallingConv::C: {
1033 // Use target triple & subtarget features to do actual dispatch.
1034 if (!Subtarget->isAAPCS_ABI())
1035 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1036 else if (Subtarget->hasVFP2() &&
1037 FloatABIType == FloatABI::Hard && !isVarArg)
1038 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1039 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1041 case CallingConv::ARM_AAPCS_VFP:
1042 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1043 case CallingConv::ARM_AAPCS:
1044 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1045 case CallingConv::ARM_APCS:
1046 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1050 /// LowerCallResult - Lower the result values of a call into the
1051 /// appropriate copies out of appropriate physical registers.
1053 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1054 CallingConv::ID CallConv, bool isVarArg,
1055 const SmallVectorImpl<ISD::InputArg> &Ins,
1056 DebugLoc dl, SelectionDAG &DAG,
1057 SmallVectorImpl<SDValue> &InVals) const {
1059 // Assign locations to each value returned by this call.
1060 SmallVector<CCValAssign, 16> RVLocs;
1061 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1062 RVLocs, *DAG.getContext());
1063 CCInfo.AnalyzeCallResult(Ins,
1064 CCAssignFnForNode(CallConv, /* Return*/ true,
1067 // Copy all of the result registers out of their specified physreg.
1068 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1069 CCValAssign VA = RVLocs[i];
1072 if (VA.needsCustom()) {
1073 // Handle f64 or half of a v2f64.
1074 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1076 Chain = Lo.getValue(1);
1077 InFlag = Lo.getValue(2);
1078 VA = RVLocs[++i]; // skip ahead to next loc
1079 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1081 Chain = Hi.getValue(1);
1082 InFlag = Hi.getValue(2);
1083 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1085 if (VA.getLocVT() == MVT::v2f64) {
1086 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1087 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1088 DAG.getConstant(0, MVT::i32));
1090 VA = RVLocs[++i]; // skip ahead to next loc
1091 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1092 Chain = Lo.getValue(1);
1093 InFlag = Lo.getValue(2);
1094 VA = RVLocs[++i]; // skip ahead to next loc
1095 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1096 Chain = Hi.getValue(1);
1097 InFlag = Hi.getValue(2);
1098 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1099 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1100 DAG.getConstant(1, MVT::i32));
1103 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1105 Chain = Val.getValue(1);
1106 InFlag = Val.getValue(2);
1109 switch (VA.getLocInfo()) {
1110 default: llvm_unreachable("Unknown loc info!");
1111 case CCValAssign::Full: break;
1112 case CCValAssign::BCvt:
1113 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1117 InVals.push_back(Val);
1123 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1124 /// by "Src" to address "Dst" of size "Size". Alignment information is
1125 /// specified by the specific parameter attribute. The copy will be passed as
1126 /// a byval function parameter.
1127 /// Sometimes what we are copying is the end of a larger object, the part that
1128 /// does not fit in registers.
1130 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1131 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1133 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1134 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1135 /*isVolatile=*/false, /*AlwaysInline=*/false,
1136 MachinePointerInfo(0), MachinePointerInfo(0));
1139 /// LowerMemOpCallTo - Store the argument to the stack.
1141 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1142 SDValue StackPtr, SDValue Arg,
1143 DebugLoc dl, SelectionDAG &DAG,
1144 const CCValAssign &VA,
1145 ISD::ArgFlagsTy Flags) const {
1146 unsigned LocMemOffset = VA.getLocMemOffset();
1147 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1148 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1149 if (Flags.isByVal())
1150 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1152 return DAG.getStore(Chain, dl, Arg, PtrOff,
1153 MachinePointerInfo::getStack(LocMemOffset),
1157 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1158 SDValue Chain, SDValue &Arg,
1159 RegsToPassVector &RegsToPass,
1160 CCValAssign &VA, CCValAssign &NextVA,
1162 SmallVector<SDValue, 8> &MemOpChains,
1163 ISD::ArgFlagsTy Flags) const {
1165 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1166 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1167 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1169 if (NextVA.isRegLoc())
1170 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1172 assert(NextVA.isMemLoc());
1173 if (StackPtr.getNode() == 0)
1174 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1176 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1182 /// LowerCall - Lowering a call into a callseq_start <-
1183 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1186 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1187 CallingConv::ID CallConv, bool isVarArg,
1189 const SmallVectorImpl<ISD::OutputArg> &Outs,
1190 const SmallVectorImpl<SDValue> &OutVals,
1191 const SmallVectorImpl<ISD::InputArg> &Ins,
1192 DebugLoc dl, SelectionDAG &DAG,
1193 SmallVectorImpl<SDValue> &InVals) const {
1194 MachineFunction &MF = DAG.getMachineFunction();
1195 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1196 bool IsSibCall = false;
1197 // Temporarily disable tail calls so things don't break.
1198 if (!EnableARMTailCalls)
1201 // Check if it's really possible to do a tail call.
1202 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1203 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1204 Outs, OutVals, Ins, DAG);
1205 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1206 // detected sibcalls.
1213 // Analyze operands of the call, assigning locations to each operand.
1214 SmallVector<CCValAssign, 16> ArgLocs;
1215 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1217 CCInfo.AnalyzeCallOperands(Outs,
1218 CCAssignFnForNode(CallConv, /* Return*/ false,
1221 // Get a count of how many bytes are to be pushed on the stack.
1222 unsigned NumBytes = CCInfo.getNextStackOffset();
1224 // For tail calls, memory operands are available in our caller's stack.
1228 // Adjust the stack pointer for the new arguments...
1229 // These operations are automatically eliminated by the prolog/epilog pass
1231 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1233 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1235 RegsToPassVector RegsToPass;
1236 SmallVector<SDValue, 8> MemOpChains;
1238 // Walk the register/memloc assignments, inserting copies/loads. In the case
1239 // of tail call optimization, arguments are handled later.
1240 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1242 ++i, ++realArgIdx) {
1243 CCValAssign &VA = ArgLocs[i];
1244 SDValue Arg = OutVals[realArgIdx];
1245 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1246 bool isByVal = Flags.isByVal();
1248 // Promote the value if needed.
1249 switch (VA.getLocInfo()) {
1250 default: llvm_unreachable("Unknown loc info!");
1251 case CCValAssign::Full: break;
1252 case CCValAssign::SExt:
1253 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1255 case CCValAssign::ZExt:
1256 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1258 case CCValAssign::AExt:
1259 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1261 case CCValAssign::BCvt:
1262 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1266 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1267 if (VA.needsCustom()) {
1268 if (VA.getLocVT() == MVT::v2f64) {
1269 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1270 DAG.getConstant(0, MVT::i32));
1271 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1272 DAG.getConstant(1, MVT::i32));
1274 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1275 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1277 VA = ArgLocs[++i]; // skip ahead to next loc
1278 if (VA.isRegLoc()) {
1279 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1280 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1282 assert(VA.isMemLoc());
1284 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1285 dl, DAG, VA, Flags));
1288 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1289 StackPtr, MemOpChains, Flags);
1291 } else if (VA.isRegLoc()) {
1292 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1293 } else if (!IsSibCall || isByVal) {
1294 assert(VA.isMemLoc());
1296 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1297 dl, DAG, VA, Flags));
1301 if (!MemOpChains.empty())
1302 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1303 &MemOpChains[0], MemOpChains.size());
1305 // Build a sequence of copy-to-reg nodes chained together with token chain
1306 // and flag operands which copy the outgoing args into the appropriate regs.
1308 // Tail call byval lowering might overwrite argument registers so in case of
1309 // tail call optimization the copies to registers are lowered later.
1311 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1312 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1313 RegsToPass[i].second, InFlag);
1314 InFlag = Chain.getValue(1);
1317 // For tail calls lower the arguments to the 'real' stack slot.
1319 // Force all the incoming stack arguments to be loaded from the stack
1320 // before any new outgoing arguments are stored to the stack, because the
1321 // outgoing stack slots may alias the incoming argument stack slots, and
1322 // the alias isn't otherwise explicit. This is slightly more conservative
1323 // than necessary, because it means that each store effectively depends
1324 // on every argument instead of just those arguments it would clobber.
1326 // Do not flag preceeding copytoreg stuff together with the following stuff.
1328 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1329 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1330 RegsToPass[i].second, InFlag);
1331 InFlag = Chain.getValue(1);
1336 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1337 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1338 // node so that legalize doesn't hack it.
1339 bool isDirect = false;
1340 bool isARMFunc = false;
1341 bool isLocalARMFunc = false;
1342 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1344 if (EnableARMLongCalls) {
1345 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1346 && "long-calls with non-static relocation model!");
1347 // Handle a global address or an external symbol. If it's not one of
1348 // those, the target's already in a register, so we don't need to do
1350 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1351 const GlobalValue *GV = G->getGlobal();
1352 // Create a constant pool entry for the callee address
1353 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1354 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1357 // Get the address of the callee into a register
1358 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1359 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1360 Callee = DAG.getLoad(getPointerTy(), dl,
1361 DAG.getEntryNode(), CPAddr,
1362 MachinePointerInfo::getConstantPool(),
1364 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1365 const char *Sym = S->getSymbol();
1367 // Create a constant pool entry for the callee address
1368 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1369 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1370 Sym, ARMPCLabelIndex, 0);
1371 // Get the address of the callee into a register
1372 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1373 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1374 Callee = DAG.getLoad(getPointerTy(), dl,
1375 DAG.getEntryNode(), CPAddr,
1376 MachinePointerInfo::getConstantPool(),
1379 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1380 const GlobalValue *GV = G->getGlobal();
1382 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1383 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1384 getTargetMachine().getRelocationModel() != Reloc::Static;
1385 isARMFunc = !Subtarget->isThumb() || isStub;
1386 // ARM call to a local ARM function is predicable.
1387 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1388 // tBX takes a register source operand.
1389 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1390 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1391 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1394 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1395 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1396 Callee = DAG.getLoad(getPointerTy(), dl,
1397 DAG.getEntryNode(), CPAddr,
1398 MachinePointerInfo::getConstantPool(),
1400 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1401 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1402 getPointerTy(), Callee, PICLabel);
1404 // On ELF targets for PIC code, direct calls should go through the PLT
1405 unsigned OpFlags = 0;
1406 if (Subtarget->isTargetELF() &&
1407 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1408 OpFlags = ARMII::MO_PLT;
1409 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1411 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1413 bool isStub = Subtarget->isTargetDarwin() &&
1414 getTargetMachine().getRelocationModel() != Reloc::Static;
1415 isARMFunc = !Subtarget->isThumb() || isStub;
1416 // tBX takes a register source operand.
1417 const char *Sym = S->getSymbol();
1418 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1419 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1420 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1421 Sym, ARMPCLabelIndex, 4);
1422 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1423 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1424 Callee = DAG.getLoad(getPointerTy(), dl,
1425 DAG.getEntryNode(), CPAddr,
1426 MachinePointerInfo::getConstantPool(),
1428 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1429 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1430 getPointerTy(), Callee, PICLabel);
1432 unsigned OpFlags = 0;
1433 // On ELF targets for PIC code, direct calls should go through the PLT
1434 if (Subtarget->isTargetELF() &&
1435 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1436 OpFlags = ARMII::MO_PLT;
1437 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1441 // FIXME: handle tail calls differently.
1443 if (Subtarget->isThumb()) {
1444 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1445 CallOpc = ARMISD::CALL_NOLINK;
1447 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1449 CallOpc = (isDirect || Subtarget->hasV5TOps())
1450 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1451 : ARMISD::CALL_NOLINK;
1454 std::vector<SDValue> Ops;
1455 Ops.push_back(Chain);
1456 Ops.push_back(Callee);
1458 // Add argument registers to the end of the list so that they are known live
1460 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1461 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1462 RegsToPass[i].second.getValueType()));
1464 if (InFlag.getNode())
1465 Ops.push_back(InFlag);
1467 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1469 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1471 // Returns a chain and a flag for retval copy to use.
1472 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1473 InFlag = Chain.getValue(1);
1475 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1476 DAG.getIntPtrConstant(0, true), InFlag);
1478 InFlag = Chain.getValue(1);
1480 // Handle result values, copying them out of physregs into vregs that we
1482 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1486 /// HandleByVal - Every parameter *after* a byval parameter is passed
1487 /// on the stack. Confiscate all the parameter registers to insure
1490 llvm::ARMTargetLowering::HandleByVal(CCState *State) const {
1491 static const unsigned RegList1[] = {
1492 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1494 do {} while (State->AllocateReg(RegList1, 4));
1497 /// MatchingStackOffset - Return true if the given stack call argument is
1498 /// already available in the same position (relatively) of the caller's
1499 /// incoming argument stack.
1501 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1502 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1503 const ARMInstrInfo *TII) {
1504 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1506 if (Arg.getOpcode() == ISD::CopyFromReg) {
1507 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1508 if (!TargetRegisterInfo::isVirtualRegister(VR))
1510 MachineInstr *Def = MRI->getVRegDef(VR);
1513 if (!Flags.isByVal()) {
1514 if (!TII->isLoadFromStackSlot(Def, FI))
1519 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1520 if (Flags.isByVal())
1521 // ByVal argument is passed in as a pointer but it's now being
1522 // dereferenced. e.g.
1523 // define @foo(%struct.X* %A) {
1524 // tail call @bar(%struct.X* byval %A)
1527 SDValue Ptr = Ld->getBasePtr();
1528 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1531 FI = FINode->getIndex();
1535 assert(FI != INT_MAX);
1536 if (!MFI->isFixedObjectIndex(FI))
1538 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1541 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1542 /// for tail call optimization. Targets which want to do tail call
1543 /// optimization should implement this function.
1545 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1546 CallingConv::ID CalleeCC,
1548 bool isCalleeStructRet,
1549 bool isCallerStructRet,
1550 const SmallVectorImpl<ISD::OutputArg> &Outs,
1551 const SmallVectorImpl<SDValue> &OutVals,
1552 const SmallVectorImpl<ISD::InputArg> &Ins,
1553 SelectionDAG& DAG) const {
1554 const Function *CallerF = DAG.getMachineFunction().getFunction();
1555 CallingConv::ID CallerCC = CallerF->getCallingConv();
1556 bool CCMatch = CallerCC == CalleeCC;
1558 // Look for obvious safe cases to perform tail call optimization that do not
1559 // require ABI changes. This is what gcc calls sibcall.
1561 // Do not sibcall optimize vararg calls unless the call site is not passing
1563 if (isVarArg && !Outs.empty())
1566 // Also avoid sibcall optimization if either caller or callee uses struct
1567 // return semantics.
1568 if (isCalleeStructRet || isCallerStructRet)
1571 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1572 // emitEpilogue is not ready for them.
1573 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1574 // LR. This means if we need to reload LR, it takes an extra instructions,
1575 // which outweighs the value of the tail call; but here we don't know yet
1576 // whether LR is going to be used. Probably the right approach is to
1577 // generate the tail call here and turn it back into CALL/RET in
1578 // emitEpilogue if LR is used.
1580 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1581 // but we need to make sure there are enough registers; the only valid
1582 // registers are the 4 used for parameters. We don't currently do this
1584 if (Subtarget->isThumb1Only())
1587 // If the calling conventions do not match, then we'd better make sure the
1588 // results are returned in the same way as what the caller expects.
1590 SmallVector<CCValAssign, 16> RVLocs1;
1591 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1592 RVLocs1, *DAG.getContext());
1593 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1595 SmallVector<CCValAssign, 16> RVLocs2;
1596 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1597 RVLocs2, *DAG.getContext());
1598 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1600 if (RVLocs1.size() != RVLocs2.size())
1602 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1603 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1605 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1607 if (RVLocs1[i].isRegLoc()) {
1608 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1611 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1617 // If the callee takes no arguments then go on to check the results of the
1619 if (!Outs.empty()) {
1620 // Check if stack adjustment is needed. For now, do not do this if any
1621 // argument is passed on the stack.
1622 SmallVector<CCValAssign, 16> ArgLocs;
1623 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1624 ArgLocs, *DAG.getContext());
1625 CCInfo.AnalyzeCallOperands(Outs,
1626 CCAssignFnForNode(CalleeCC, false, isVarArg));
1627 if (CCInfo.getNextStackOffset()) {
1628 MachineFunction &MF = DAG.getMachineFunction();
1630 // Check if the arguments are already laid out in the right way as
1631 // the caller's fixed stack objects.
1632 MachineFrameInfo *MFI = MF.getFrameInfo();
1633 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1634 const ARMInstrInfo *TII =
1635 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1636 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1638 ++i, ++realArgIdx) {
1639 CCValAssign &VA = ArgLocs[i];
1640 EVT RegVT = VA.getLocVT();
1641 SDValue Arg = OutVals[realArgIdx];
1642 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1643 if (VA.getLocInfo() == CCValAssign::Indirect)
1645 if (VA.needsCustom()) {
1646 // f64 and vector types are split into multiple registers or
1647 // register/stack-slot combinations. The types will not match
1648 // the registers; give up on memory f64 refs until we figure
1649 // out what to do about this.
1652 if (!ArgLocs[++i].isRegLoc())
1654 if (RegVT == MVT::v2f64) {
1655 if (!ArgLocs[++i].isRegLoc())
1657 if (!ArgLocs[++i].isRegLoc())
1660 } else if (!VA.isRegLoc()) {
1661 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1673 ARMTargetLowering::LowerReturn(SDValue Chain,
1674 CallingConv::ID CallConv, bool isVarArg,
1675 const SmallVectorImpl<ISD::OutputArg> &Outs,
1676 const SmallVectorImpl<SDValue> &OutVals,
1677 DebugLoc dl, SelectionDAG &DAG) const {
1679 // CCValAssign - represent the assignment of the return value to a location.
1680 SmallVector<CCValAssign, 16> RVLocs;
1682 // CCState - Info about the registers and stack slots.
1683 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1686 // Analyze outgoing return values.
1687 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1690 // If this is the first return lowered for this function, add
1691 // the regs to the liveout set for the function.
1692 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1693 for (unsigned i = 0; i != RVLocs.size(); ++i)
1694 if (RVLocs[i].isRegLoc())
1695 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1700 // Copy the result values into the output registers.
1701 for (unsigned i = 0, realRVLocIdx = 0;
1703 ++i, ++realRVLocIdx) {
1704 CCValAssign &VA = RVLocs[i];
1705 assert(VA.isRegLoc() && "Can only return in registers!");
1707 SDValue Arg = OutVals[realRVLocIdx];
1709 switch (VA.getLocInfo()) {
1710 default: llvm_unreachable("Unknown loc info!");
1711 case CCValAssign::Full: break;
1712 case CCValAssign::BCvt:
1713 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1717 if (VA.needsCustom()) {
1718 if (VA.getLocVT() == MVT::v2f64) {
1719 // Extract the first half and return it in two registers.
1720 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1721 DAG.getConstant(0, MVT::i32));
1722 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1723 DAG.getVTList(MVT::i32, MVT::i32), Half);
1725 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1726 Flag = Chain.getValue(1);
1727 VA = RVLocs[++i]; // skip ahead to next loc
1728 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1729 HalfGPRs.getValue(1), Flag);
1730 Flag = Chain.getValue(1);
1731 VA = RVLocs[++i]; // skip ahead to next loc
1733 // Extract the 2nd half and fall through to handle it as an f64 value.
1734 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1735 DAG.getConstant(1, MVT::i32));
1737 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1739 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1740 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1741 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1742 Flag = Chain.getValue(1);
1743 VA = RVLocs[++i]; // skip ahead to next loc
1744 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1747 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1749 // Guarantee that all emitted copies are
1750 // stuck together, avoiding something bad.
1751 Flag = Chain.getValue(1);
1756 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1758 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1763 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1764 if (N->getNumValues() != 1)
1766 if (!N->hasNUsesOfValue(1, 0))
1769 unsigned NumCopies = 0;
1771 SDNode *Use = *N->use_begin();
1772 if (Use->getOpcode() == ISD::CopyToReg) {
1773 Copies[NumCopies++] = Use;
1774 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1775 // f64 returned in a pair of GPRs.
1776 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1778 if (UI->getOpcode() != ISD::CopyToReg)
1780 Copies[UI.getUse().getResNo()] = *UI;
1783 } else if (Use->getOpcode() == ISD::BITCAST) {
1784 // f32 returned in a single GPR.
1785 if (!Use->hasNUsesOfValue(1, 0))
1787 Use = *Use->use_begin();
1788 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1790 Copies[NumCopies++] = Use;
1795 if (NumCopies != 1 && NumCopies != 2)
1798 bool HasRet = false;
1799 for (unsigned i = 0; i < NumCopies; ++i) {
1800 SDNode *Copy = Copies[i];
1801 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1803 if (UI->getOpcode() == ISD::CopyToReg) {
1805 if (Use == Copies[0] || Use == Copies[1])
1809 if (UI->getOpcode() != ARMISD::RET_FLAG)
1818 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1819 if (!EnableARMTailCalls)
1822 if (!CI->isTailCall())
1825 return !Subtarget->isThumb1Only();
1828 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1829 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1830 // one of the above mentioned nodes. It has to be wrapped because otherwise
1831 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1832 // be used to form addressing mode. These wrapped nodes will be selected
1834 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1835 EVT PtrVT = Op.getValueType();
1836 // FIXME there is no actual debug info here
1837 DebugLoc dl = Op.getDebugLoc();
1838 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1840 if (CP->isMachineConstantPoolEntry())
1841 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1842 CP->getAlignment());
1844 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1845 CP->getAlignment());
1846 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1849 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1850 return MachineJumpTableInfo::EK_Inline;
1853 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1854 SelectionDAG &DAG) const {
1855 MachineFunction &MF = DAG.getMachineFunction();
1856 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1857 unsigned ARMPCLabelIndex = 0;
1858 DebugLoc DL = Op.getDebugLoc();
1859 EVT PtrVT = getPointerTy();
1860 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1861 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1863 if (RelocM == Reloc::Static) {
1864 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1866 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1867 ARMPCLabelIndex = AFI->createPICLabelUId();
1868 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1869 ARMCP::CPBlockAddress,
1871 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1873 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1874 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1875 MachinePointerInfo::getConstantPool(),
1877 if (RelocM == Reloc::Static)
1879 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1880 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1883 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1885 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1886 SelectionDAG &DAG) const {
1887 DebugLoc dl = GA->getDebugLoc();
1888 EVT PtrVT = getPointerTy();
1889 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1892 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1893 ARMConstantPoolValue *CPV =
1894 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1895 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1896 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1897 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1898 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1899 MachinePointerInfo::getConstantPool(),
1901 SDValue Chain = Argument.getValue(1);
1903 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1904 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1906 // call __tls_get_addr.
1909 Entry.Node = Argument;
1910 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1911 Args.push_back(Entry);
1912 // FIXME: is there useful debug info available here?
1913 std::pair<SDValue, SDValue> CallResult =
1914 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1915 false, false, false, false,
1916 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1917 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1918 return CallResult.first;
1921 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1922 // "local exec" model.
1924 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1925 SelectionDAG &DAG) const {
1926 const GlobalValue *GV = GA->getGlobal();
1927 DebugLoc dl = GA->getDebugLoc();
1929 SDValue Chain = DAG.getEntryNode();
1930 EVT PtrVT = getPointerTy();
1931 // Get the Thread Pointer
1932 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1934 if (GV->isDeclaration()) {
1935 MachineFunction &MF = DAG.getMachineFunction();
1936 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1937 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1938 // Initial exec model.
1939 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1940 ARMConstantPoolValue *CPV =
1941 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1942 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1943 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1944 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1945 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1946 MachinePointerInfo::getConstantPool(),
1948 Chain = Offset.getValue(1);
1950 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1951 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1953 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1954 MachinePointerInfo::getConstantPool(),
1958 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1959 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1960 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1961 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1962 MachinePointerInfo::getConstantPool(),
1966 // The address of the thread local variable is the add of the thread
1967 // pointer with the offset of the variable.
1968 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1972 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1973 // TODO: implement the "local dynamic" model
1974 assert(Subtarget->isTargetELF() &&
1975 "TLS not implemented for non-ELF targets");
1976 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1977 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1978 // otherwise use the "Local Exec" TLS Model
1979 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1980 return LowerToTLSGeneralDynamicModel(GA, DAG);
1982 return LowerToTLSExecModels(GA, DAG);
1985 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1986 SelectionDAG &DAG) const {
1987 EVT PtrVT = getPointerTy();
1988 DebugLoc dl = Op.getDebugLoc();
1989 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1990 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1991 if (RelocM == Reloc::PIC_) {
1992 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1993 ARMConstantPoolValue *CPV =
1994 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1995 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1996 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1997 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1999 MachinePointerInfo::getConstantPool(),
2001 SDValue Chain = Result.getValue(1);
2002 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2003 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2005 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2006 MachinePointerInfo::getGOT(), false, false, 0);
2010 // If we have T2 ops, we can materialize the address directly via movt/movw
2011 // pair. This is always cheaper.
2012 if (Subtarget->useMovt()) {
2014 // FIXME: Once remat is capable of dealing with instructions with register
2015 // operands, expand this into two nodes.
2016 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2017 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2019 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2020 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2021 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2022 MachinePointerInfo::getConstantPool(),
2027 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2028 SelectionDAG &DAG) const {
2029 EVT PtrVT = getPointerTy();
2030 DebugLoc dl = Op.getDebugLoc();
2031 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2032 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2033 MachineFunction &MF = DAG.getMachineFunction();
2034 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2036 if (Subtarget->useMovt()) {
2038 // FIXME: Once remat is capable of dealing with instructions with register
2039 // operands, expand this into two nodes.
2040 if (RelocM == Reloc::Static)
2041 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2042 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2044 unsigned Wrapper = (RelocM == Reloc::PIC_)
2045 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2046 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2047 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2048 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2049 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2050 MachinePointerInfo::getGOT(), false, false, 0);
2054 unsigned ARMPCLabelIndex = 0;
2056 if (RelocM == Reloc::Static) {
2057 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2059 ARMPCLabelIndex = AFI->createPICLabelUId();
2060 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2061 ARMConstantPoolValue *CPV =
2062 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2063 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2065 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2067 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2068 MachinePointerInfo::getConstantPool(),
2070 SDValue Chain = Result.getValue(1);
2072 if (RelocM == Reloc::PIC_) {
2073 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2074 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2077 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2078 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2084 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2085 SelectionDAG &DAG) const {
2086 assert(Subtarget->isTargetELF() &&
2087 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2088 MachineFunction &MF = DAG.getMachineFunction();
2089 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2090 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2091 EVT PtrVT = getPointerTy();
2092 DebugLoc dl = Op.getDebugLoc();
2093 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2094 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2095 "_GLOBAL_OFFSET_TABLE_",
2096 ARMPCLabelIndex, PCAdj);
2097 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2098 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2099 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2100 MachinePointerInfo::getConstantPool(),
2102 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2103 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2107 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2109 DebugLoc dl = Op.getDebugLoc();
2110 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2115 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2116 DebugLoc dl = Op.getDebugLoc();
2117 SDValue Val = DAG.getConstant(0, MVT::i32);
2118 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2119 Op.getOperand(1), Val);
2123 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2124 DebugLoc dl = Op.getDebugLoc();
2125 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2126 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2130 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2131 const ARMSubtarget *Subtarget) const {
2132 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2133 DebugLoc dl = Op.getDebugLoc();
2135 default: return SDValue(); // Don't custom lower most intrinsics.
2136 case Intrinsic::arm_thread_pointer: {
2137 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2138 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2140 case Intrinsic::eh_sjlj_lsda: {
2141 MachineFunction &MF = DAG.getMachineFunction();
2142 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2143 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2144 EVT PtrVT = getPointerTy();
2145 DebugLoc dl = Op.getDebugLoc();
2146 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2148 unsigned PCAdj = (RelocM != Reloc::PIC_)
2149 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2150 ARMConstantPoolValue *CPV =
2151 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2152 ARMCP::CPLSDA, PCAdj);
2153 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2154 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2156 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2157 MachinePointerInfo::getConstantPool(),
2160 if (RelocM == Reloc::PIC_) {
2161 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2162 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2166 case Intrinsic::arm_neon_vmulls:
2167 case Intrinsic::arm_neon_vmullu: {
2168 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2169 ? ARMISD::VMULLs : ARMISD::VMULLu;
2170 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2171 Op.getOperand(1), Op.getOperand(2));
2176 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2177 const ARMSubtarget *Subtarget) {
2178 DebugLoc dl = Op.getDebugLoc();
2179 if (!Subtarget->hasDataBarrier()) {
2180 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2181 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2183 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2184 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2185 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2186 DAG.getConstant(0, MVT::i32));
2189 SDValue Op5 = Op.getOperand(5);
2190 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2191 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2192 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2193 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2195 ARM_MB::MemBOpt DMBOpt;
2196 if (isDeviceBarrier)
2197 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2199 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2200 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2201 DAG.getConstant(DMBOpt, MVT::i32));
2204 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2205 const ARMSubtarget *Subtarget) {
2206 // ARM pre v5TE and Thumb1 does not have preload instructions.
2207 if (!(Subtarget->isThumb2() ||
2208 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2209 // Just preserve the chain.
2210 return Op.getOperand(0);
2212 DebugLoc dl = Op.getDebugLoc();
2213 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2215 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2216 // ARMv7 with MP extension has PLDW.
2217 return Op.getOperand(0);
2219 if (Subtarget->isThumb())
2221 isRead = ~isRead & 1;
2222 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2224 // Currently there is no intrinsic that matches pli.
2225 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2226 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2227 DAG.getConstant(isData, MVT::i32));
2230 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2231 MachineFunction &MF = DAG.getMachineFunction();
2232 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2234 // vastart just stores the address of the VarArgsFrameIndex slot into the
2235 // memory location argument.
2236 DebugLoc dl = Op.getDebugLoc();
2237 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2238 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2239 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2240 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2241 MachinePointerInfo(SV), false, false, 0);
2245 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2246 SDValue &Root, SelectionDAG &DAG,
2247 DebugLoc dl) const {
2248 MachineFunction &MF = DAG.getMachineFunction();
2249 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2251 TargetRegisterClass *RC;
2252 if (AFI->isThumb1OnlyFunction())
2253 RC = ARM::tGPRRegisterClass;
2255 RC = ARM::GPRRegisterClass;
2257 // Transform the arguments stored in physical registers into virtual ones.
2258 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2259 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2262 if (NextVA.isMemLoc()) {
2263 MachineFrameInfo *MFI = MF.getFrameInfo();
2264 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2266 // Create load node to retrieve arguments from the stack.
2267 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2268 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2269 MachinePointerInfo::getFixedStack(FI),
2272 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2273 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2276 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2280 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2281 CallingConv::ID CallConv, bool isVarArg,
2282 const SmallVectorImpl<ISD::InputArg>
2284 DebugLoc dl, SelectionDAG &DAG,
2285 SmallVectorImpl<SDValue> &InVals)
2288 MachineFunction &MF = DAG.getMachineFunction();
2289 MachineFrameInfo *MFI = MF.getFrameInfo();
2291 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2293 // Assign locations to all of the incoming arguments.
2294 SmallVector<CCValAssign, 16> ArgLocs;
2295 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2297 CCInfo.AnalyzeFormalArguments(Ins,
2298 CCAssignFnForNode(CallConv, /* Return*/ false,
2301 SmallVector<SDValue, 16> ArgValues;
2302 int lastInsIndex = -1;
2305 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2306 CCValAssign &VA = ArgLocs[i];
2308 // Arguments stored in registers.
2309 if (VA.isRegLoc()) {
2310 EVT RegVT = VA.getLocVT();
2312 if (VA.needsCustom()) {
2313 // f64 and vector types are split up into multiple registers or
2314 // combinations of registers and stack slots.
2315 if (VA.getLocVT() == MVT::v2f64) {
2316 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2318 VA = ArgLocs[++i]; // skip ahead to next loc
2320 if (VA.isMemLoc()) {
2321 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2322 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2323 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2324 MachinePointerInfo::getFixedStack(FI),
2327 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2330 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2331 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2332 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2333 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2334 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2336 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2339 TargetRegisterClass *RC;
2341 if (RegVT == MVT::f32)
2342 RC = ARM::SPRRegisterClass;
2343 else if (RegVT == MVT::f64)
2344 RC = ARM::DPRRegisterClass;
2345 else if (RegVT == MVT::v2f64)
2346 RC = ARM::QPRRegisterClass;
2347 else if (RegVT == MVT::i32)
2348 RC = (AFI->isThumb1OnlyFunction() ?
2349 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2351 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2353 // Transform the arguments in physical registers into virtual ones.
2354 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2355 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2358 // If this is an 8 or 16-bit value, it is really passed promoted
2359 // to 32 bits. Insert an assert[sz]ext to capture this, then
2360 // truncate to the right size.
2361 switch (VA.getLocInfo()) {
2362 default: llvm_unreachable("Unknown loc info!");
2363 case CCValAssign::Full: break;
2364 case CCValAssign::BCvt:
2365 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2367 case CCValAssign::SExt:
2368 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2369 DAG.getValueType(VA.getValVT()));
2370 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2372 case CCValAssign::ZExt:
2373 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2374 DAG.getValueType(VA.getValVT()));
2375 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2379 InVals.push_back(ArgValue);
2381 } else { // VA.isRegLoc()
2384 assert(VA.isMemLoc());
2385 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2387 int index = ArgLocs[i].getValNo();
2389 // Some Ins[] entries become multiple ArgLoc[] entries.
2390 // Process them only once.
2391 if (index != lastInsIndex)
2393 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2394 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2395 // changed with more analysis.
2396 // In case of tail call optimization mark all arguments mutable. Since they
2397 // could be overwritten by lowering of arguments in case of a tail call.
2398 if (Flags.isByVal()) {
2399 unsigned Bytes = Flags.getByValSize();
2400 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2401 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), false);
2402 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2404 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2405 VA.getLocMemOffset(), true);
2407 // Create load nodes to retrieve arguments from the stack.
2408 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2409 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2410 MachinePointerInfo::getFixedStack(FI),
2413 lastInsIndex = index;
2420 static const unsigned GPRArgRegs[] = {
2421 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2424 unsigned NumGPRs = CCInfo.getFirstUnallocated
2425 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2427 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2428 unsigned VARegSize = (4 - NumGPRs) * 4;
2429 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2430 unsigned ArgOffset = CCInfo.getNextStackOffset();
2431 if (VARegSaveSize) {
2432 // If this function is vararg, store any remaining integer argument regs
2433 // to their spots on the stack so that they may be loaded by deferencing
2434 // the result of va_next.
2435 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2436 AFI->setVarArgsFrameIndex(
2437 MFI->CreateFixedObject(VARegSaveSize,
2438 ArgOffset + VARegSaveSize - VARegSize,
2440 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2443 SmallVector<SDValue, 4> MemOps;
2444 for (; NumGPRs < 4; ++NumGPRs) {
2445 TargetRegisterClass *RC;
2446 if (AFI->isThumb1OnlyFunction())
2447 RC = ARM::tGPRRegisterClass;
2449 RC = ARM::GPRRegisterClass;
2451 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2452 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2454 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2455 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2457 MemOps.push_back(Store);
2458 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2459 DAG.getConstant(4, getPointerTy()));
2461 if (!MemOps.empty())
2462 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2463 &MemOps[0], MemOps.size());
2465 // This will point to the next argument passed via stack.
2466 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2472 /// isFloatingPointZero - Return true if this is +0.0.
2473 static bool isFloatingPointZero(SDValue Op) {
2474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2475 return CFP->getValueAPF().isPosZero();
2476 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2477 // Maybe this has already been legalized into the constant pool?
2478 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2479 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2480 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2481 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2482 return CFP->getValueAPF().isPosZero();
2488 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2489 /// the given operands.
2491 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2492 SDValue &ARMcc, SelectionDAG &DAG,
2493 DebugLoc dl) const {
2494 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2495 unsigned C = RHSC->getZExtValue();
2496 if (!isLegalICmpImmediate(C)) {
2497 // Constant does not fit, try adjusting it by one?
2502 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2503 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2504 RHS = DAG.getConstant(C-1, MVT::i32);
2509 if (C != 0 && isLegalICmpImmediate(C-1)) {
2510 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2511 RHS = DAG.getConstant(C-1, MVT::i32);
2516 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2517 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2518 RHS = DAG.getConstant(C+1, MVT::i32);
2523 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2524 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2525 RHS = DAG.getConstant(C+1, MVT::i32);
2532 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2533 ARMISD::NodeType CompareType;
2536 CompareType = ARMISD::CMP;
2541 CompareType = ARMISD::CMPZ;
2544 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2545 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2548 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2550 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2551 DebugLoc dl) const {
2553 if (!isFloatingPointZero(RHS))
2554 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2556 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2557 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2560 /// duplicateCmp - Glue values can have only one use, so this function
2561 /// duplicates a comparison node.
2563 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2564 unsigned Opc = Cmp.getOpcode();
2565 DebugLoc DL = Cmp.getDebugLoc();
2566 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2567 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2569 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2570 Cmp = Cmp.getOperand(0);
2571 Opc = Cmp.getOpcode();
2572 if (Opc == ARMISD::CMPFP)
2573 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2575 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2576 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2578 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2581 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2582 SDValue Cond = Op.getOperand(0);
2583 SDValue SelectTrue = Op.getOperand(1);
2584 SDValue SelectFalse = Op.getOperand(2);
2585 DebugLoc dl = Op.getDebugLoc();
2589 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2590 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2592 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2593 const ConstantSDNode *CMOVTrue =
2594 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2595 const ConstantSDNode *CMOVFalse =
2596 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2598 if (CMOVTrue && CMOVFalse) {
2599 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2600 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2604 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2606 False = SelectFalse;
2607 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2612 if (True.getNode() && False.getNode()) {
2613 EVT VT = Cond.getValueType();
2614 SDValue ARMcc = Cond.getOperand(2);
2615 SDValue CCR = Cond.getOperand(3);
2616 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2617 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2622 return DAG.getSelectCC(dl, Cond,
2623 DAG.getConstant(0, Cond.getValueType()),
2624 SelectTrue, SelectFalse, ISD::SETNE);
2627 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2628 EVT VT = Op.getValueType();
2629 SDValue LHS = Op.getOperand(0);
2630 SDValue RHS = Op.getOperand(1);
2631 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2632 SDValue TrueVal = Op.getOperand(2);
2633 SDValue FalseVal = Op.getOperand(3);
2634 DebugLoc dl = Op.getDebugLoc();
2636 if (LHS.getValueType() == MVT::i32) {
2638 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2639 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2640 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2643 ARMCC::CondCodes CondCode, CondCode2;
2644 FPCCToARMCC(CC, CondCode, CondCode2);
2646 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2647 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2648 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2649 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2651 if (CondCode2 != ARMCC::AL) {
2652 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2653 // FIXME: Needs another CMP because flag can have but one use.
2654 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2655 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2656 Result, TrueVal, ARMcc2, CCR, Cmp2);
2661 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2662 /// to morph to an integer compare sequence.
2663 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2664 const ARMSubtarget *Subtarget) {
2665 SDNode *N = Op.getNode();
2666 if (!N->hasOneUse())
2667 // Otherwise it requires moving the value from fp to integer registers.
2669 if (!N->getNumValues())
2671 EVT VT = Op.getValueType();
2672 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2673 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2674 // vmrs are very slow, e.g. cortex-a8.
2677 if (isFloatingPointZero(Op)) {
2681 return ISD::isNormalLoad(N);
2684 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2685 if (isFloatingPointZero(Op))
2686 return DAG.getConstant(0, MVT::i32);
2688 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2689 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2690 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2691 Ld->isVolatile(), Ld->isNonTemporal(),
2692 Ld->getAlignment());
2694 llvm_unreachable("Unknown VFP cmp argument!");
2697 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2698 SDValue &RetVal1, SDValue &RetVal2) {
2699 if (isFloatingPointZero(Op)) {
2700 RetVal1 = DAG.getConstant(0, MVT::i32);
2701 RetVal2 = DAG.getConstant(0, MVT::i32);
2705 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2706 SDValue Ptr = Ld->getBasePtr();
2707 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2708 Ld->getChain(), Ptr,
2709 Ld->getPointerInfo(),
2710 Ld->isVolatile(), Ld->isNonTemporal(),
2711 Ld->getAlignment());
2713 EVT PtrType = Ptr.getValueType();
2714 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2715 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2716 PtrType, Ptr, DAG.getConstant(4, PtrType));
2717 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2718 Ld->getChain(), NewPtr,
2719 Ld->getPointerInfo().getWithOffset(4),
2720 Ld->isVolatile(), Ld->isNonTemporal(),
2725 llvm_unreachable("Unknown VFP cmp argument!");
2728 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2729 /// f32 and even f64 comparisons to integer ones.
2731 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2732 SDValue Chain = Op.getOperand(0);
2733 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2734 SDValue LHS = Op.getOperand(2);
2735 SDValue RHS = Op.getOperand(3);
2736 SDValue Dest = Op.getOperand(4);
2737 DebugLoc dl = Op.getDebugLoc();
2739 bool SeenZero = false;
2740 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2741 canChangeToInt(RHS, SeenZero, Subtarget) &&
2742 // If one of the operand is zero, it's safe to ignore the NaN case since
2743 // we only care about equality comparisons.
2744 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2745 // If unsafe fp math optimization is enabled and there are no other uses of
2746 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2747 // to an integer comparison.
2748 if (CC == ISD::SETOEQ)
2750 else if (CC == ISD::SETUNE)
2754 if (LHS.getValueType() == MVT::f32) {
2755 LHS = bitcastf32Toi32(LHS, DAG);
2756 RHS = bitcastf32Toi32(RHS, DAG);
2757 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2758 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2759 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2760 Chain, Dest, ARMcc, CCR, Cmp);
2765 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2766 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2767 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2768 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2769 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2770 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2771 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2777 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2778 SDValue Chain = Op.getOperand(0);
2779 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2780 SDValue LHS = Op.getOperand(2);
2781 SDValue RHS = Op.getOperand(3);
2782 SDValue Dest = Op.getOperand(4);
2783 DebugLoc dl = Op.getDebugLoc();
2785 if (LHS.getValueType() == MVT::i32) {
2787 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2788 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2789 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2790 Chain, Dest, ARMcc, CCR, Cmp);
2793 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2796 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2797 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2798 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2799 if (Result.getNode())
2803 ARMCC::CondCodes CondCode, CondCode2;
2804 FPCCToARMCC(CC, CondCode, CondCode2);
2806 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2807 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2808 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2809 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2810 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2811 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2812 if (CondCode2 != ARMCC::AL) {
2813 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2814 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2815 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2820 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2821 SDValue Chain = Op.getOperand(0);
2822 SDValue Table = Op.getOperand(1);
2823 SDValue Index = Op.getOperand(2);
2824 DebugLoc dl = Op.getDebugLoc();
2826 EVT PTy = getPointerTy();
2827 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2828 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2829 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2830 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2831 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2832 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2833 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2834 if (Subtarget->isThumb2()) {
2835 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2836 // which does another jump to the destination. This also makes it easier
2837 // to translate it to TBB / TBH later.
2838 // FIXME: This might not work if the function is extremely large.
2839 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2840 Addr, Op.getOperand(2), JTI, UId);
2842 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2843 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2844 MachinePointerInfo::getJumpTable(),
2846 Chain = Addr.getValue(1);
2847 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2848 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2850 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2851 MachinePointerInfo::getJumpTable(), false, false, 0);
2852 Chain = Addr.getValue(1);
2853 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2857 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2858 DebugLoc dl = Op.getDebugLoc();
2861 switch (Op.getOpcode()) {
2863 assert(0 && "Invalid opcode!");
2864 case ISD::FP_TO_SINT:
2865 Opc = ARMISD::FTOSI;
2867 case ISD::FP_TO_UINT:
2868 Opc = ARMISD::FTOUI;
2871 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2872 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2875 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2876 EVT VT = Op.getValueType();
2877 DebugLoc dl = Op.getDebugLoc();
2879 EVT OperandVT = Op.getOperand(0).getValueType();
2880 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2881 if (VT != MVT::v4f32)
2882 return DAG.UnrollVectorOp(Op.getNode());
2886 switch (Op.getOpcode()) {
2888 assert(0 && "Invalid opcode!");
2889 case ISD::SINT_TO_FP:
2890 CastOpc = ISD::SIGN_EXTEND;
2891 Opc = ISD::SINT_TO_FP;
2893 case ISD::UINT_TO_FP:
2894 CastOpc = ISD::ZERO_EXTEND;
2895 Opc = ISD::UINT_TO_FP;
2899 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
2900 return DAG.getNode(Opc, dl, VT, Op);
2903 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2904 EVT VT = Op.getValueType();
2906 return LowerVectorINT_TO_FP(Op, DAG);
2908 DebugLoc dl = Op.getDebugLoc();
2911 switch (Op.getOpcode()) {
2913 assert(0 && "Invalid opcode!");
2914 case ISD::SINT_TO_FP:
2915 Opc = ARMISD::SITOF;
2917 case ISD::UINT_TO_FP:
2918 Opc = ARMISD::UITOF;
2922 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2923 return DAG.getNode(Opc, dl, VT, Op);
2926 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2927 // Implement fcopysign with a fabs and a conditional fneg.
2928 SDValue Tmp0 = Op.getOperand(0);
2929 SDValue Tmp1 = Op.getOperand(1);
2930 DebugLoc dl = Op.getDebugLoc();
2931 EVT VT = Op.getValueType();
2932 EVT SrcVT = Tmp1.getValueType();
2933 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
2934 Tmp0.getOpcode() == ARMISD::VMOVDRR;
2935 bool UseNEON = !InGPR && Subtarget->hasNEON();
2938 // Use VBSL to copy the sign bit.
2939 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
2940 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
2941 DAG.getTargetConstant(EncodedVal, MVT::i32));
2942 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
2944 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
2945 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
2946 DAG.getConstant(32, MVT::i32));
2947 else /*if (VT == MVT::f32)*/
2948 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
2949 if (SrcVT == MVT::f32) {
2950 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
2952 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
2953 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
2954 DAG.getConstant(32, MVT::i32));
2956 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
2957 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
2959 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
2961 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
2962 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
2963 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
2965 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
2966 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
2967 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
2968 if (VT == MVT::f32) {
2969 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
2970 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
2971 DAG.getConstant(0, MVT::i32));
2973 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
2979 // Bitcast operand 1 to i32.
2980 if (SrcVT == MVT::f64)
2981 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2982 &Tmp1, 1).getValue(1);
2983 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
2985 // Or in the signbit with integer operations.
2986 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
2987 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
2988 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
2989 if (VT == MVT::f32) {
2990 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
2991 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
2992 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
2993 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
2996 // f64: Or the high part with signbit and then combine two parts.
2997 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
2999 SDValue Lo = Tmp0.getValue(0);
3000 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3001 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3002 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3005 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3006 MachineFunction &MF = DAG.getMachineFunction();
3007 MachineFrameInfo *MFI = MF.getFrameInfo();
3008 MFI->setReturnAddressIsTaken(true);
3010 EVT VT = Op.getValueType();
3011 DebugLoc dl = Op.getDebugLoc();
3012 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3014 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3015 SDValue Offset = DAG.getConstant(4, MVT::i32);
3016 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3017 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3018 MachinePointerInfo(), false, false, 0);
3021 // Return LR, which contains the return address. Mark it an implicit live-in.
3022 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3023 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3026 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3027 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3028 MFI->setFrameAddressIsTaken(true);
3030 EVT VT = Op.getValueType();
3031 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3032 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3033 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3034 ? ARM::R7 : ARM::R11;
3035 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3037 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3038 MachinePointerInfo(),
3043 /// ExpandBITCAST - If the target supports VFP, this function is called to
3044 /// expand a bit convert where either the source or destination type is i64 to
3045 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3046 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3047 /// vectors), since the legalizer won't know what to do with that.
3048 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3050 DebugLoc dl = N->getDebugLoc();
3051 SDValue Op = N->getOperand(0);
3053 // This function is only supposed to be called for i64 types, either as the
3054 // source or destination of the bit convert.
3055 EVT SrcVT = Op.getValueType();
3056 EVT DstVT = N->getValueType(0);
3057 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3058 "ExpandBITCAST called for non-i64 type");
3060 // Turn i64->f64 into VMOVDRR.
3061 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3062 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3063 DAG.getConstant(0, MVT::i32));
3064 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3065 DAG.getConstant(1, MVT::i32));
3066 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3067 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3070 // Turn f64->i64 into VMOVRRD.
3071 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3072 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3073 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3074 // Merge the pieces into a single i64 value.
3075 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3081 /// getZeroVector - Returns a vector of specified type with all zero elements.
3082 /// Zero vectors are used to represent vector negation and in those cases
3083 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3084 /// not support i64 elements, so sometimes the zero vectors will need to be
3085 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3087 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3088 assert(VT.isVector() && "Expected a vector type");
3089 // The canonical modified immediate encoding of a zero vector is....0!
3090 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3091 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3092 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3093 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3096 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3097 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3098 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3099 SelectionDAG &DAG) const {
3100 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3101 EVT VT = Op.getValueType();
3102 unsigned VTBits = VT.getSizeInBits();
3103 DebugLoc dl = Op.getDebugLoc();
3104 SDValue ShOpLo = Op.getOperand(0);
3105 SDValue ShOpHi = Op.getOperand(1);
3106 SDValue ShAmt = Op.getOperand(2);
3108 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3110 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3112 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3113 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3114 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3115 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3116 DAG.getConstant(VTBits, MVT::i32));
3117 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3118 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3119 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3121 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3122 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3124 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3125 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3128 SDValue Ops[2] = { Lo, Hi };
3129 return DAG.getMergeValues(Ops, 2, dl);
3132 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3133 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3134 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3135 SelectionDAG &DAG) const {
3136 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3137 EVT VT = Op.getValueType();
3138 unsigned VTBits = VT.getSizeInBits();
3139 DebugLoc dl = Op.getDebugLoc();
3140 SDValue ShOpLo = Op.getOperand(0);
3141 SDValue ShOpHi = Op.getOperand(1);
3142 SDValue ShAmt = Op.getOperand(2);
3145 assert(Op.getOpcode() == ISD::SHL_PARTS);
3146 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3147 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3148 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3149 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3150 DAG.getConstant(VTBits, MVT::i32));
3151 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3152 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3154 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3155 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3156 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3158 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3159 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3162 SDValue Ops[2] = { Lo, Hi };
3163 return DAG.getMergeValues(Ops, 2, dl);
3166 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3167 SelectionDAG &DAG) const {
3168 // The rounding mode is in bits 23:22 of the FPSCR.
3169 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3170 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3171 // so that the shift + and get folded into a bitfield extract.
3172 DebugLoc dl = Op.getDebugLoc();
3173 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3174 DAG.getConstant(Intrinsic::arm_get_fpscr,
3176 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3177 DAG.getConstant(1U << 22, MVT::i32));
3178 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3179 DAG.getConstant(22, MVT::i32));
3180 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3181 DAG.getConstant(3, MVT::i32));
3184 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3185 const ARMSubtarget *ST) {
3186 EVT VT = N->getValueType(0);
3187 DebugLoc dl = N->getDebugLoc();
3189 if (!ST->hasV6T2Ops())
3192 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3193 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3196 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3197 const ARMSubtarget *ST) {
3198 EVT VT = N->getValueType(0);
3199 DebugLoc dl = N->getDebugLoc();
3204 // Lower vector shifts on NEON to use VSHL.
3205 assert(ST->hasNEON() && "unexpected vector shift");
3207 // Left shifts translate directly to the vshiftu intrinsic.
3208 if (N->getOpcode() == ISD::SHL)
3209 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3210 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3211 N->getOperand(0), N->getOperand(1));
3213 assert((N->getOpcode() == ISD::SRA ||
3214 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3216 // NEON uses the same intrinsics for both left and right shifts. For
3217 // right shifts, the shift amounts are negative, so negate the vector of
3219 EVT ShiftVT = N->getOperand(1).getValueType();
3220 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3221 getZeroVector(ShiftVT, DAG, dl),
3223 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3224 Intrinsic::arm_neon_vshifts :
3225 Intrinsic::arm_neon_vshiftu);
3226 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3227 DAG.getConstant(vshiftInt, MVT::i32),
3228 N->getOperand(0), NegatedCount);
3231 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3232 const ARMSubtarget *ST) {
3233 EVT VT = N->getValueType(0);
3234 DebugLoc dl = N->getDebugLoc();
3236 // We can get here for a node like i32 = ISD::SHL i32, i64
3240 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3241 "Unknown shift to lower!");
3243 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3244 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3245 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3248 // If we are in thumb mode, we don't have RRX.
3249 if (ST->isThumb1Only()) return SDValue();
3251 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3252 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3253 DAG.getConstant(0, MVT::i32));
3254 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3255 DAG.getConstant(1, MVT::i32));
3257 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3258 // captures the result into a carry flag.
3259 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3260 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3262 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3263 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3265 // Merge the pieces into a single i64 value.
3266 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3269 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3270 SDValue TmpOp0, TmpOp1;
3271 bool Invert = false;
3275 SDValue Op0 = Op.getOperand(0);
3276 SDValue Op1 = Op.getOperand(1);
3277 SDValue CC = Op.getOperand(2);
3278 EVT VT = Op.getValueType();
3279 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3280 DebugLoc dl = Op.getDebugLoc();
3282 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3283 switch (SetCCOpcode) {
3284 default: llvm_unreachable("Illegal FP comparison"); break;
3286 case ISD::SETNE: Invert = true; // Fallthrough
3288 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3290 case ISD::SETLT: Swap = true; // Fallthrough
3292 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3294 case ISD::SETLE: Swap = true; // Fallthrough
3296 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3297 case ISD::SETUGE: Swap = true; // Fallthrough
3298 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3299 case ISD::SETUGT: Swap = true; // Fallthrough
3300 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3301 case ISD::SETUEQ: Invert = true; // Fallthrough
3303 // Expand this to (OLT | OGT).
3307 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3308 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3310 case ISD::SETUO: Invert = true; // Fallthrough
3312 // Expand this to (OLT | OGE).
3316 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3317 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3321 // Integer comparisons.
3322 switch (SetCCOpcode) {
3323 default: llvm_unreachable("Illegal integer comparison"); break;
3324 case ISD::SETNE: Invert = true;
3325 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3326 case ISD::SETLT: Swap = true;
3327 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3328 case ISD::SETLE: Swap = true;
3329 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3330 case ISD::SETULT: Swap = true;
3331 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3332 case ISD::SETULE: Swap = true;
3333 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3336 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3337 if (Opc == ARMISD::VCEQ) {
3340 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3342 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3345 // Ignore bitconvert.
3346 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3347 AndOp = AndOp.getOperand(0);
3349 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3351 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3352 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3359 std::swap(Op0, Op1);
3361 // If one of the operands is a constant vector zero, attempt to fold the
3362 // comparison to a specialized compare-against-zero form.
3364 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3366 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3367 if (Opc == ARMISD::VCGE)
3368 Opc = ARMISD::VCLEZ;
3369 else if (Opc == ARMISD::VCGT)
3370 Opc = ARMISD::VCLTZ;
3375 if (SingleOp.getNode()) {
3378 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3380 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3382 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3384 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3386 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3388 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3391 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3395 Result = DAG.getNOT(dl, Result, VT);
3400 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3401 /// valid vector constant for a NEON instruction with a "modified immediate"
3402 /// operand (e.g., VMOV). If so, return the encoded value.
3403 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3404 unsigned SplatBitSize, SelectionDAG &DAG,
3405 EVT &VT, bool is128Bits, NEONModImmType type) {
3406 unsigned OpCmode, Imm;
3408 // SplatBitSize is set to the smallest size that splats the vector, so a
3409 // zero vector will always have SplatBitSize == 8. However, NEON modified
3410 // immediate instructions others than VMOV do not support the 8-bit encoding
3411 // of a zero vector, and the default encoding of zero is supposed to be the
3416 switch (SplatBitSize) {
3418 if (type != VMOVModImm)
3420 // Any 1-byte value is OK. Op=0, Cmode=1110.
3421 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3424 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3428 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3429 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3430 if ((SplatBits & ~0xff) == 0) {
3431 // Value = 0x00nn: Op=x, Cmode=100x.
3436 if ((SplatBits & ~0xff00) == 0) {
3437 // Value = 0xnn00: Op=x, Cmode=101x.
3439 Imm = SplatBits >> 8;
3445 // NEON's 32-bit VMOV supports splat values where:
3446 // * only one byte is nonzero, or
3447 // * the least significant byte is 0xff and the second byte is nonzero, or
3448 // * the least significant 2 bytes are 0xff and the third is nonzero.
3449 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3450 if ((SplatBits & ~0xff) == 0) {
3451 // Value = 0x000000nn: Op=x, Cmode=000x.
3456 if ((SplatBits & ~0xff00) == 0) {
3457 // Value = 0x0000nn00: Op=x, Cmode=001x.
3459 Imm = SplatBits >> 8;
3462 if ((SplatBits & ~0xff0000) == 0) {
3463 // Value = 0x00nn0000: Op=x, Cmode=010x.
3465 Imm = SplatBits >> 16;
3468 if ((SplatBits & ~0xff000000) == 0) {
3469 // Value = 0xnn000000: Op=x, Cmode=011x.
3471 Imm = SplatBits >> 24;
3475 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3476 if (type == OtherModImm) return SDValue();
3478 if ((SplatBits & ~0xffff) == 0 &&
3479 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3480 // Value = 0x0000nnff: Op=x, Cmode=1100.
3482 Imm = SplatBits >> 8;
3487 if ((SplatBits & ~0xffffff) == 0 &&
3488 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3489 // Value = 0x00nnffff: Op=x, Cmode=1101.
3491 Imm = SplatBits >> 16;
3492 SplatBits |= 0xffff;
3496 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3497 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3498 // VMOV.I32. A (very) minor optimization would be to replicate the value
3499 // and fall through here to test for a valid 64-bit splat. But, then the
3500 // caller would also need to check and handle the change in size.
3504 if (type != VMOVModImm)
3506 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3507 uint64_t BitMask = 0xff;
3509 unsigned ImmMask = 1;
3511 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3512 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3515 } else if ((SplatBits & BitMask) != 0) {
3521 // Op=1, Cmode=1110.
3524 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3529 llvm_unreachable("unexpected size for isNEONModifiedImm");
3533 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3534 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3537 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3538 bool &ReverseVEXT, unsigned &Imm) {
3539 unsigned NumElts = VT.getVectorNumElements();
3540 ReverseVEXT = false;
3542 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3548 // If this is a VEXT shuffle, the immediate value is the index of the first
3549 // element. The other shuffle indices must be the successive elements after
3551 unsigned ExpectedElt = Imm;
3552 for (unsigned i = 1; i < NumElts; ++i) {
3553 // Increment the expected index. If it wraps around, it may still be
3554 // a VEXT but the source vectors must be swapped.
3556 if (ExpectedElt == NumElts * 2) {
3561 if (M[i] < 0) continue; // ignore UNDEF indices
3562 if (ExpectedElt != static_cast<unsigned>(M[i]))
3566 // Adjust the index value if the source operands will be swapped.
3573 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3574 /// instruction with the specified blocksize. (The order of the elements
3575 /// within each block of the vector is reversed.)
3576 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3577 unsigned BlockSize) {
3578 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3579 "Only possible block sizes for VREV are: 16, 32, 64");
3581 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3585 unsigned NumElts = VT.getVectorNumElements();
3586 unsigned BlockElts = M[0] + 1;
3587 // If the first shuffle index is UNDEF, be optimistic.
3589 BlockElts = BlockSize / EltSz;
3591 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3594 for (unsigned i = 0; i < NumElts; ++i) {
3595 if (M[i] < 0) continue; // ignore UNDEF indices
3596 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3603 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3604 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3605 // range, then 0 is placed into the resulting vector. So pretty much any mask
3606 // of 8 elements can work here.
3607 return VT == MVT::v8i8 && M.size() == 8;
3610 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3611 unsigned &WhichResult) {
3612 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3616 unsigned NumElts = VT.getVectorNumElements();
3617 WhichResult = (M[0] == 0 ? 0 : 1);
3618 for (unsigned i = 0; i < NumElts; i += 2) {
3619 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3620 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3626 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3627 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3628 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3629 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3630 unsigned &WhichResult) {
3631 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3635 unsigned NumElts = VT.getVectorNumElements();
3636 WhichResult = (M[0] == 0 ? 0 : 1);
3637 for (unsigned i = 0; i < NumElts; i += 2) {
3638 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3639 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3645 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3646 unsigned &WhichResult) {
3647 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3651 unsigned NumElts = VT.getVectorNumElements();
3652 WhichResult = (M[0] == 0 ? 0 : 1);
3653 for (unsigned i = 0; i != NumElts; ++i) {
3654 if (M[i] < 0) continue; // ignore UNDEF indices
3655 if ((unsigned) M[i] != 2 * i + WhichResult)
3659 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3660 if (VT.is64BitVector() && EltSz == 32)
3666 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3667 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3668 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3669 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3670 unsigned &WhichResult) {
3671 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3675 unsigned Half = VT.getVectorNumElements() / 2;
3676 WhichResult = (M[0] == 0 ? 0 : 1);
3677 for (unsigned j = 0; j != 2; ++j) {
3678 unsigned Idx = WhichResult;
3679 for (unsigned i = 0; i != Half; ++i) {
3680 int MIdx = M[i + j * Half];
3681 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3687 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3688 if (VT.is64BitVector() && EltSz == 32)
3694 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3695 unsigned &WhichResult) {
3696 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3700 unsigned NumElts = VT.getVectorNumElements();
3701 WhichResult = (M[0] == 0 ? 0 : 1);
3702 unsigned Idx = WhichResult * NumElts / 2;
3703 for (unsigned i = 0; i != NumElts; i += 2) {
3704 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3705 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3710 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3711 if (VT.is64BitVector() && EltSz == 32)
3717 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3718 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3719 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3720 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3721 unsigned &WhichResult) {
3722 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3726 unsigned NumElts = VT.getVectorNumElements();
3727 WhichResult = (M[0] == 0 ? 0 : 1);
3728 unsigned Idx = WhichResult * NumElts / 2;
3729 for (unsigned i = 0; i != NumElts; i += 2) {
3730 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3731 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3736 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3737 if (VT.is64BitVector() && EltSz == 32)
3743 // If N is an integer constant that can be moved into a register in one
3744 // instruction, return an SDValue of such a constant (will become a MOV
3745 // instruction). Otherwise return null.
3746 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3747 const ARMSubtarget *ST, DebugLoc dl) {
3749 if (!isa<ConstantSDNode>(N))
3751 Val = cast<ConstantSDNode>(N)->getZExtValue();
3753 if (ST->isThumb1Only()) {
3754 if (Val <= 255 || ~Val <= 255)
3755 return DAG.getConstant(Val, MVT::i32);
3757 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3758 return DAG.getConstant(Val, MVT::i32);
3763 // If this is a case we can't handle, return null and let the default
3764 // expansion code take care of it.
3765 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3766 const ARMSubtarget *ST) const {
3767 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3768 DebugLoc dl = Op.getDebugLoc();
3769 EVT VT = Op.getValueType();
3771 APInt SplatBits, SplatUndef;
3772 unsigned SplatBitSize;
3774 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3775 if (SplatBitSize <= 64) {
3776 // Check if an immediate VMOV works.
3778 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3779 SplatUndef.getZExtValue(), SplatBitSize,
3780 DAG, VmovVT, VT.is128BitVector(),
3782 if (Val.getNode()) {
3783 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3784 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3787 // Try an immediate VMVN.
3788 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3789 ((1LL << SplatBitSize) - 1));
3790 Val = isNEONModifiedImm(NegatedImm,
3791 SplatUndef.getZExtValue(), SplatBitSize,
3792 DAG, VmovVT, VT.is128BitVector(),
3794 if (Val.getNode()) {
3795 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3796 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3801 // Scan through the operands to see if only one value is used.
3802 unsigned NumElts = VT.getVectorNumElements();
3803 bool isOnlyLowElement = true;
3804 bool usesOnlyOneValue = true;
3805 bool isConstant = true;
3807 for (unsigned i = 0; i < NumElts; ++i) {
3808 SDValue V = Op.getOperand(i);
3809 if (V.getOpcode() == ISD::UNDEF)
3812 isOnlyLowElement = false;
3813 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3816 if (!Value.getNode())
3818 else if (V != Value)
3819 usesOnlyOneValue = false;
3822 if (!Value.getNode())
3823 return DAG.getUNDEF(VT);
3825 if (isOnlyLowElement)
3826 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3828 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3830 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3831 // i32 and try again.
3832 if (usesOnlyOneValue && EltSize <= 32) {
3834 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3835 if (VT.getVectorElementType().isFloatingPoint()) {
3836 SmallVector<SDValue, 8> Ops;
3837 for (unsigned i = 0; i < NumElts; ++i)
3838 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3840 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3841 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3842 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3844 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3846 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3848 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3851 // If all elements are constants and the case above didn't get hit, fall back
3852 // to the default expansion, which will generate a load from the constant
3857 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3859 SDValue shuffle = ReconstructShuffle(Op, DAG);
3860 if (shuffle != SDValue())
3864 // Vectors with 32- or 64-bit elements can be built by directly assigning
3865 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3866 // will be legalized.
3867 if (EltSize >= 32) {
3868 // Do the expansion with floating-point types, since that is what the VFP
3869 // registers are defined to use, and since i64 is not legal.
3870 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3871 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3872 SmallVector<SDValue, 8> Ops;
3873 for (unsigned i = 0; i < NumElts; ++i)
3874 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3875 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3876 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3882 // Gather data to see if the operation can be modelled as a
3883 // shuffle in combination with VEXTs.
3884 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3885 SelectionDAG &DAG) const {
3886 DebugLoc dl = Op.getDebugLoc();
3887 EVT VT = Op.getValueType();
3888 unsigned NumElts = VT.getVectorNumElements();
3890 SmallVector<SDValue, 2> SourceVecs;
3891 SmallVector<unsigned, 2> MinElts;
3892 SmallVector<unsigned, 2> MaxElts;
3894 for (unsigned i = 0; i < NumElts; ++i) {
3895 SDValue V = Op.getOperand(i);
3896 if (V.getOpcode() == ISD::UNDEF)
3898 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3899 // A shuffle can only come from building a vector from various
3900 // elements of other vectors.
3904 // Record this extraction against the appropriate vector if possible...
3905 SDValue SourceVec = V.getOperand(0);
3906 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
3907 bool FoundSource = false;
3908 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
3909 if (SourceVecs[j] == SourceVec) {
3910 if (MinElts[j] > EltNo)
3912 if (MaxElts[j] < EltNo)
3919 // Or record a new source if not...
3921 SourceVecs.push_back(SourceVec);
3922 MinElts.push_back(EltNo);
3923 MaxElts.push_back(EltNo);
3927 // Currently only do something sane when at most two source vectors
3929 if (SourceVecs.size() > 2)
3932 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
3933 int VEXTOffsets[2] = {0, 0};
3935 // This loop extracts the usage patterns of the source vectors
3936 // and prepares appropriate SDValues for a shuffle if possible.
3937 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
3938 if (SourceVecs[i].getValueType() == VT) {
3939 // No VEXT necessary
3940 ShuffleSrcs[i] = SourceVecs[i];
3943 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
3944 // It probably isn't worth padding out a smaller vector just to
3945 // break it down again in a shuffle.
3949 // Since only 64-bit and 128-bit vectors are legal on ARM and
3950 // we've eliminated the other cases...
3951 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
3952 "unexpected vector sizes in ReconstructShuffle");
3954 if (MaxElts[i] - MinElts[i] >= NumElts) {
3955 // Span too large for a VEXT to cope
3959 if (MinElts[i] >= NumElts) {
3960 // The extraction can just take the second half
3961 VEXTOffsets[i] = NumElts;
3962 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3964 DAG.getIntPtrConstant(NumElts));
3965 } else if (MaxElts[i] < NumElts) {
3966 // The extraction can just take the first half
3968 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3970 DAG.getIntPtrConstant(0));
3972 // An actual VEXT is needed
3973 VEXTOffsets[i] = MinElts[i];
3974 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3976 DAG.getIntPtrConstant(0));
3977 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
3979 DAG.getIntPtrConstant(NumElts));
3980 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
3981 DAG.getConstant(VEXTOffsets[i], MVT::i32));
3985 SmallVector<int, 8> Mask;
3987 for (unsigned i = 0; i < NumElts; ++i) {
3988 SDValue Entry = Op.getOperand(i);
3989 if (Entry.getOpcode() == ISD::UNDEF) {
3994 SDValue ExtractVec = Entry.getOperand(0);
3995 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
3996 .getOperand(1))->getSExtValue();
3997 if (ExtractVec == SourceVecs[0]) {
3998 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4000 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4004 // Final check before we try to produce nonsense...
4005 if (isShuffleMaskLegal(Mask, VT))
4006 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4012 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4013 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4014 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4015 /// are assumed to be legal.
4017 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4019 if (VT.getVectorNumElements() == 4 &&
4020 (VT.is128BitVector() || VT.is64BitVector())) {
4021 unsigned PFIndexes[4];
4022 for (unsigned i = 0; i != 4; ++i) {
4026 PFIndexes[i] = M[i];
4029 // Compute the index in the perfect shuffle table.
4030 unsigned PFTableIndex =
4031 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4032 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4033 unsigned Cost = (PFEntry >> 30);
4040 unsigned Imm, WhichResult;
4042 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4043 return (EltSize >= 32 ||
4044 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4045 isVREVMask(M, VT, 64) ||
4046 isVREVMask(M, VT, 32) ||
4047 isVREVMask(M, VT, 16) ||
4048 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4049 isVTBLMask(M, VT) ||
4050 isVTRNMask(M, VT, WhichResult) ||
4051 isVUZPMask(M, VT, WhichResult) ||
4052 isVZIPMask(M, VT, WhichResult) ||
4053 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4054 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4055 isVZIP_v_undef_Mask(M, VT, WhichResult));
4058 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4059 /// the specified operations to build the shuffle.
4060 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4061 SDValue RHS, SelectionDAG &DAG,
4063 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4064 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4065 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4068 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4077 OP_VUZPL, // VUZP, left result
4078 OP_VUZPR, // VUZP, right result
4079 OP_VZIPL, // VZIP, left result
4080 OP_VZIPR, // VZIP, right result
4081 OP_VTRNL, // VTRN, left result
4082 OP_VTRNR // VTRN, right result
4085 if (OpNum == OP_COPY) {
4086 if (LHSID == (1*9+2)*9+3) return LHS;
4087 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4091 SDValue OpLHS, OpRHS;
4092 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4093 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4094 EVT VT = OpLHS.getValueType();
4097 default: llvm_unreachable("Unknown shuffle opcode!");
4099 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4104 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4105 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4109 return DAG.getNode(ARMISD::VEXT, dl, VT,
4111 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4114 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4115 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4118 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4119 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4122 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4123 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4127 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4128 SmallVectorImpl<int> &ShuffleMask,
4129 SelectionDAG &DAG) {
4130 // Check to see if we can use the VTBL instruction.
4131 SDValue V1 = Op.getOperand(0);
4132 SDValue V2 = Op.getOperand(1);
4133 DebugLoc DL = Op.getDebugLoc();
4135 SmallVector<SDValue, 8> VTBLMask;
4136 for (SmallVectorImpl<int>::iterator
4137 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4138 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4140 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4141 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4142 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4145 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4146 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4150 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4151 SDValue V1 = Op.getOperand(0);
4152 SDValue V2 = Op.getOperand(1);
4153 DebugLoc dl = Op.getDebugLoc();
4154 EVT VT = Op.getValueType();
4155 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4156 SmallVector<int, 8> ShuffleMask;
4158 // Convert shuffles that are directly supported on NEON to target-specific
4159 // DAG nodes, instead of keeping them as shuffles and matching them again
4160 // during code selection. This is more efficient and avoids the possibility
4161 // of inconsistencies between legalization and selection.
4162 // FIXME: floating-point vectors should be canonicalized to integer vectors
4163 // of the same time so that they get CSEd properly.
4164 SVN->getMask(ShuffleMask);
4166 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4167 if (EltSize <= 32) {
4168 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4169 int Lane = SVN->getSplatIndex();
4170 // If this is undef splat, generate it via "just" vdup, if possible.
4171 if (Lane == -1) Lane = 0;
4173 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4174 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4176 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4177 DAG.getConstant(Lane, MVT::i32));
4182 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4185 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4186 DAG.getConstant(Imm, MVT::i32));
4189 if (isVREVMask(ShuffleMask, VT, 64))
4190 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4191 if (isVREVMask(ShuffleMask, VT, 32))
4192 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4193 if (isVREVMask(ShuffleMask, VT, 16))
4194 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4196 // Check for Neon shuffles that modify both input vectors in place.
4197 // If both results are used, i.e., if there are two shuffles with the same
4198 // source operands and with masks corresponding to both results of one of
4199 // these operations, DAG memoization will ensure that a single node is
4200 // used for both shuffles.
4201 unsigned WhichResult;
4202 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4203 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4204 V1, V2).getValue(WhichResult);
4205 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4206 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4207 V1, V2).getValue(WhichResult);
4208 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4209 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4210 V1, V2).getValue(WhichResult);
4212 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4213 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4214 V1, V1).getValue(WhichResult);
4215 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4216 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4217 V1, V1).getValue(WhichResult);
4218 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4219 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4220 V1, V1).getValue(WhichResult);
4223 // If the shuffle is not directly supported and it has 4 elements, use
4224 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4225 unsigned NumElts = VT.getVectorNumElements();
4227 unsigned PFIndexes[4];
4228 for (unsigned i = 0; i != 4; ++i) {
4229 if (ShuffleMask[i] < 0)
4232 PFIndexes[i] = ShuffleMask[i];
4235 // Compute the index in the perfect shuffle table.
4236 unsigned PFTableIndex =
4237 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4238 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4239 unsigned Cost = (PFEntry >> 30);
4242 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4245 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4246 if (EltSize >= 32) {
4247 // Do the expansion with floating-point types, since that is what the VFP
4248 // registers are defined to use, and since i64 is not legal.
4249 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4250 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4251 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4252 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4253 SmallVector<SDValue, 8> Ops;
4254 for (unsigned i = 0; i < NumElts; ++i) {
4255 if (ShuffleMask[i] < 0)
4256 Ops.push_back(DAG.getUNDEF(EltVT));
4258 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4259 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4260 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4263 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4264 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4267 if (VT == MVT::v8i8) {
4268 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4269 if (NewOp.getNode())
4276 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4277 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4278 SDValue Lane = Op.getOperand(1);
4279 if (!isa<ConstantSDNode>(Lane))
4282 SDValue Vec = Op.getOperand(0);
4283 if (Op.getValueType() == MVT::i32 &&
4284 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4285 DebugLoc dl = Op.getDebugLoc();
4286 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4292 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4293 // The only time a CONCAT_VECTORS operation can have legal types is when
4294 // two 64-bit vectors are concatenated to a 128-bit vector.
4295 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4296 "unexpected CONCAT_VECTORS");
4297 DebugLoc dl = Op.getDebugLoc();
4298 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4299 SDValue Op0 = Op.getOperand(0);
4300 SDValue Op1 = Op.getOperand(1);
4301 if (Op0.getOpcode() != ISD::UNDEF)
4302 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4303 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4304 DAG.getIntPtrConstant(0));
4305 if (Op1.getOpcode() != ISD::UNDEF)
4306 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4307 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4308 DAG.getIntPtrConstant(1));
4309 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4312 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4313 /// element has been zero/sign-extended, depending on the isSigned parameter,
4314 /// from an integer type half its size.
4315 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4317 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4318 EVT VT = N->getValueType(0);
4319 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4320 SDNode *BVN = N->getOperand(0).getNode();
4321 if (BVN->getValueType(0) != MVT::v4i32 ||
4322 BVN->getOpcode() != ISD::BUILD_VECTOR)
4324 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4325 unsigned HiElt = 1 - LoElt;
4326 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4327 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4328 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4329 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4330 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4333 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4334 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4337 if (Hi0->isNullValue() && Hi1->isNullValue())
4343 if (N->getOpcode() != ISD::BUILD_VECTOR)
4346 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4347 SDNode *Elt = N->getOperand(i).getNode();
4348 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4349 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4350 unsigned HalfSize = EltSize / 2;
4352 int64_t SExtVal = C->getSExtValue();
4353 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4356 if ((C->getZExtValue() >> HalfSize) != 0)
4367 /// isSignExtended - Check if a node is a vector value that is sign-extended
4368 /// or a constant BUILD_VECTOR with sign-extended elements.
4369 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4370 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4372 if (isExtendedBUILD_VECTOR(N, DAG, true))
4377 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4378 /// or a constant BUILD_VECTOR with zero-extended elements.
4379 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4380 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4382 if (isExtendedBUILD_VECTOR(N, DAG, false))
4387 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4388 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4389 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4390 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4391 return N->getOperand(0);
4392 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4393 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4394 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4395 LD->isNonTemporal(), LD->getAlignment());
4396 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4397 // have been legalized as a BITCAST from v4i32.
4398 if (N->getOpcode() == ISD::BITCAST) {
4399 SDNode *BVN = N->getOperand(0).getNode();
4400 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4401 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4402 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4403 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4404 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4406 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4407 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4408 EVT VT = N->getValueType(0);
4409 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4410 unsigned NumElts = VT.getVectorNumElements();
4411 MVT TruncVT = MVT::getIntegerVT(EltSize);
4412 SmallVector<SDValue, 8> Ops;
4413 for (unsigned i = 0; i != NumElts; ++i) {
4414 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4415 const APInt &CInt = C->getAPIntValue();
4416 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4418 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4419 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4422 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4423 unsigned Opcode = N->getOpcode();
4424 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4425 SDNode *N0 = N->getOperand(0).getNode();
4426 SDNode *N1 = N->getOperand(1).getNode();
4427 return N0->hasOneUse() && N1->hasOneUse() &&
4428 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4433 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4434 unsigned Opcode = N->getOpcode();
4435 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4436 SDNode *N0 = N->getOperand(0).getNode();
4437 SDNode *N1 = N->getOperand(1).getNode();
4438 return N0->hasOneUse() && N1->hasOneUse() &&
4439 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4444 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4445 // Multiplications are only custom-lowered for 128-bit vectors so that
4446 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4447 EVT VT = Op.getValueType();
4448 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4449 SDNode *N0 = Op.getOperand(0).getNode();
4450 SDNode *N1 = Op.getOperand(1).getNode();
4451 unsigned NewOpc = 0;
4453 bool isN0SExt = isSignExtended(N0, DAG);
4454 bool isN1SExt = isSignExtended(N1, DAG);
4455 if (isN0SExt && isN1SExt)
4456 NewOpc = ARMISD::VMULLs;
4458 bool isN0ZExt = isZeroExtended(N0, DAG);
4459 bool isN1ZExt = isZeroExtended(N1, DAG);
4460 if (isN0ZExt && isN1ZExt)
4461 NewOpc = ARMISD::VMULLu;
4462 else if (isN1SExt || isN1ZExt) {
4463 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4464 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4465 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4466 NewOpc = ARMISD::VMULLs;
4468 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4469 NewOpc = ARMISD::VMULLu;
4471 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4473 NewOpc = ARMISD::VMULLu;
4479 if (VT == MVT::v2i64)
4480 // Fall through to expand this. It is not legal.
4483 // Other vector multiplications are legal.
4488 // Legalize to a VMULL instruction.
4489 DebugLoc DL = Op.getDebugLoc();
4491 SDValue Op1 = SkipExtension(N1, DAG);
4493 Op0 = SkipExtension(N0, DAG);
4494 assert(Op0.getValueType().is64BitVector() &&
4495 Op1.getValueType().is64BitVector() &&
4496 "unexpected types for extended operands to VMULL");
4497 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4500 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4501 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4508 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4509 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4510 EVT Op1VT = Op1.getValueType();
4511 return DAG.getNode(N0->getOpcode(), DL, VT,
4512 DAG.getNode(NewOpc, DL, VT,
4513 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4514 DAG.getNode(NewOpc, DL, VT,
4515 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4519 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4521 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4522 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4523 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4524 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4525 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4526 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4527 // Get reciprocal estimate.
4528 // float4 recip = vrecpeq_f32(yf);
4529 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4530 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4531 // Because char has a smaller range than uchar, we can actually get away
4532 // without any newton steps. This requires that we use a weird bias
4533 // of 0xb000, however (again, this has been exhaustively tested).
4534 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4535 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4536 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4537 Y = DAG.getConstant(0xb000, MVT::i32);
4538 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4539 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4540 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4541 // Convert back to short.
4542 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4543 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4548 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4550 // Convert to float.
4551 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4552 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4553 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4554 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4555 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4556 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4558 // Use reciprocal estimate and one refinement step.
4559 // float4 recip = vrecpeq_f32(yf);
4560 // recip *= vrecpsq_f32(yf, recip);
4561 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4562 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4563 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4564 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4566 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4567 // Because short has a smaller range than ushort, we can actually get away
4568 // with only a single newton step. This requires that we use a weird bias
4569 // of 89, however (again, this has been exhaustively tested).
4570 // float4 result = as_float4(as_int4(xf*recip) + 89);
4571 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4572 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4573 N1 = DAG.getConstant(89, MVT::i32);
4574 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4575 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4576 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4577 // Convert back to integer and return.
4578 // return vmovn_s32(vcvt_s32_f32(result));
4579 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4580 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4584 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4585 EVT VT = Op.getValueType();
4586 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4587 "unexpected type for custom-lowering ISD::SDIV");
4589 DebugLoc dl = Op.getDebugLoc();
4590 SDValue N0 = Op.getOperand(0);
4591 SDValue N1 = Op.getOperand(1);
4594 if (VT == MVT::v8i8) {
4595 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4596 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4598 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4599 DAG.getIntPtrConstant(4));
4600 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4601 DAG.getIntPtrConstant(4));
4602 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4603 DAG.getIntPtrConstant(0));
4604 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4605 DAG.getIntPtrConstant(0));
4607 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4608 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4610 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4611 N0 = LowerCONCAT_VECTORS(N0, DAG);
4613 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4616 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4619 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4620 EVT VT = Op.getValueType();
4621 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4622 "unexpected type for custom-lowering ISD::UDIV");
4624 DebugLoc dl = Op.getDebugLoc();
4625 SDValue N0 = Op.getOperand(0);
4626 SDValue N1 = Op.getOperand(1);
4629 if (VT == MVT::v8i8) {
4630 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4631 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4633 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4634 DAG.getIntPtrConstant(4));
4635 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4636 DAG.getIntPtrConstant(4));
4637 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4638 DAG.getIntPtrConstant(0));
4639 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4640 DAG.getIntPtrConstant(0));
4642 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4643 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4645 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4646 N0 = LowerCONCAT_VECTORS(N0, DAG);
4648 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4649 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4654 // v4i16 sdiv ... Convert to float.
4655 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4656 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4657 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4658 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4659 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4660 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4662 // Use reciprocal estimate and two refinement steps.
4663 // float4 recip = vrecpeq_f32(yf);
4664 // recip *= vrecpsq_f32(yf, recip);
4665 // recip *= vrecpsq_f32(yf, recip);
4666 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4667 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4668 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4669 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4671 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4672 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4673 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4675 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4676 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4677 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4678 // and that it will never cause us to return an answer too large).
4679 // float4 result = as_float4(as_int4(xf*recip) + 89);
4680 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4681 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4682 N1 = DAG.getConstant(2, MVT::i32);
4683 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4684 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4685 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4686 // Convert back to integer and return.
4687 // return vmovn_u32(vcvt_s32_f32(result));
4688 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4689 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4693 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4694 switch (Op.getOpcode()) {
4695 default: llvm_unreachable("Don't know how to custom lower this!");
4696 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4697 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4698 case ISD::GlobalAddress:
4699 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4700 LowerGlobalAddressELF(Op, DAG);
4701 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4702 case ISD::SELECT: return LowerSELECT(Op, DAG);
4703 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4704 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4705 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4706 case ISD::VASTART: return LowerVASTART(Op, DAG);
4707 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4708 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4709 case ISD::SINT_TO_FP:
4710 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4711 case ISD::FP_TO_SINT:
4712 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4713 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4714 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4715 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4716 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4717 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4718 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4719 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4720 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4722 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4725 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4726 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4727 case ISD::SRL_PARTS:
4728 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4729 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4730 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4731 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4732 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4733 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4734 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4735 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4736 case ISD::MUL: return LowerMUL(Op, DAG);
4737 case ISD::SDIV: return LowerSDIV(Op, DAG);
4738 case ISD::UDIV: return LowerUDIV(Op, DAG);
4743 /// ReplaceNodeResults - Replace the results of node with an illegal result
4744 /// type with new values built out of custom code.
4745 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4746 SmallVectorImpl<SDValue>&Results,
4747 SelectionDAG &DAG) const {
4749 switch (N->getOpcode()) {
4751 llvm_unreachable("Don't know how to custom expand this!");
4754 Res = ExpandBITCAST(N, DAG);
4758 Res = Expand64BitShift(N, DAG, Subtarget);
4762 Results.push_back(Res);
4765 //===----------------------------------------------------------------------===//
4766 // ARM Scheduler Hooks
4767 //===----------------------------------------------------------------------===//
4770 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4771 MachineBasicBlock *BB,
4772 unsigned Size) const {
4773 unsigned dest = MI->getOperand(0).getReg();
4774 unsigned ptr = MI->getOperand(1).getReg();
4775 unsigned oldval = MI->getOperand(2).getReg();
4776 unsigned newval = MI->getOperand(3).getReg();
4777 unsigned scratch = BB->getParent()->getRegInfo()
4778 .createVirtualRegister(ARM::GPRRegisterClass);
4779 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4780 DebugLoc dl = MI->getDebugLoc();
4781 bool isThumb2 = Subtarget->isThumb2();
4783 unsigned ldrOpc, strOpc;
4785 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4787 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4788 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4791 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4792 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4795 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4796 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4800 MachineFunction *MF = BB->getParent();
4801 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4802 MachineFunction::iterator It = BB;
4803 ++It; // insert the new blocks after the current block
4805 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4806 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4807 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4808 MF->insert(It, loop1MBB);
4809 MF->insert(It, loop2MBB);
4810 MF->insert(It, exitMBB);
4812 // Transfer the remainder of BB and its successor edges to exitMBB.
4813 exitMBB->splice(exitMBB->begin(), BB,
4814 llvm::next(MachineBasicBlock::iterator(MI)),
4816 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4820 // fallthrough --> loop1MBB
4821 BB->addSuccessor(loop1MBB);
4824 // ldrex dest, [ptr]
4828 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4829 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4830 .addReg(dest).addReg(oldval));
4831 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4832 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4833 BB->addSuccessor(loop2MBB);
4834 BB->addSuccessor(exitMBB);
4837 // strex scratch, newval, [ptr]
4841 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4843 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4844 .addReg(scratch).addImm(0));
4845 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4846 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4847 BB->addSuccessor(loop1MBB);
4848 BB->addSuccessor(exitMBB);
4854 MI->eraseFromParent(); // The instruction is gone now.
4860 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4861 unsigned Size, unsigned BinOpcode) const {
4862 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4865 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4866 MachineFunction *MF = BB->getParent();
4867 MachineFunction::iterator It = BB;
4870 unsigned dest = MI->getOperand(0).getReg();
4871 unsigned ptr = MI->getOperand(1).getReg();
4872 unsigned incr = MI->getOperand(2).getReg();
4873 DebugLoc dl = MI->getDebugLoc();
4875 bool isThumb2 = Subtarget->isThumb2();
4876 unsigned ldrOpc, strOpc;
4878 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4880 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4881 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4884 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4885 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4888 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4889 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4893 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4894 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4895 MF->insert(It, loopMBB);
4896 MF->insert(It, exitMBB);
4898 // Transfer the remainder of BB and its successor edges to exitMBB.
4899 exitMBB->splice(exitMBB->begin(), BB,
4900 llvm::next(MachineBasicBlock::iterator(MI)),
4902 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4904 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4905 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4906 unsigned scratch2 = (!BinOpcode) ? incr :
4907 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4911 // fallthrough --> loopMBB
4912 BB->addSuccessor(loopMBB);
4916 // <binop> scratch2, dest, incr
4917 // strex scratch, scratch2, ptr
4920 // fallthrough --> exitMBB
4922 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4924 // operand order needs to go the other way for NAND
4925 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4926 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4927 addReg(incr).addReg(dest)).addReg(0);
4929 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4930 addReg(dest).addReg(incr)).addReg(0);
4933 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4935 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4936 .addReg(scratch).addImm(0));
4937 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4938 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4940 BB->addSuccessor(loopMBB);
4941 BB->addSuccessor(exitMBB);
4947 MI->eraseFromParent(); // The instruction is gone now.
4953 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4954 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4955 E = MBB->succ_end(); I != E; ++I)
4958 llvm_unreachable("Expecting a BB with two successors!");
4962 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4963 MachineBasicBlock *BB) const {
4964 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4965 DebugLoc dl = MI->getDebugLoc();
4966 bool isThumb2 = Subtarget->isThumb2();
4967 switch (MI->getOpcode()) {
4970 llvm_unreachable("Unexpected instr type to insert");
4972 case ARM::ATOMIC_LOAD_ADD_I8:
4973 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4974 case ARM::ATOMIC_LOAD_ADD_I16:
4975 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4976 case ARM::ATOMIC_LOAD_ADD_I32:
4977 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4979 case ARM::ATOMIC_LOAD_AND_I8:
4980 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4981 case ARM::ATOMIC_LOAD_AND_I16:
4982 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4983 case ARM::ATOMIC_LOAD_AND_I32:
4984 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4986 case ARM::ATOMIC_LOAD_OR_I8:
4987 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4988 case ARM::ATOMIC_LOAD_OR_I16:
4989 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4990 case ARM::ATOMIC_LOAD_OR_I32:
4991 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4993 case ARM::ATOMIC_LOAD_XOR_I8:
4994 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4995 case ARM::ATOMIC_LOAD_XOR_I16:
4996 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4997 case ARM::ATOMIC_LOAD_XOR_I32:
4998 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5000 case ARM::ATOMIC_LOAD_NAND_I8:
5001 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5002 case ARM::ATOMIC_LOAD_NAND_I16:
5003 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5004 case ARM::ATOMIC_LOAD_NAND_I32:
5005 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5007 case ARM::ATOMIC_LOAD_SUB_I8:
5008 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5009 case ARM::ATOMIC_LOAD_SUB_I16:
5010 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5011 case ARM::ATOMIC_LOAD_SUB_I32:
5012 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5014 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5015 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5016 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5018 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5019 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5020 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5033 unsigned OldOpc = MI->getOpcode();
5070 llvm_unreachable("Unknown opcode?");
5073 MachineInstrBuilder MIB =
5074 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(Opc));
5075 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5076 MIB.addOperand(MI->getOperand(i));
5077 AddDefaultPred(MIB);
5078 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5079 MI->eraseFromParent();
5084 case ARM::tMOVCCr_pseudo: {
5085 // To "insert" a SELECT_CC instruction, we actually have to insert the
5086 // diamond control-flow pattern. The incoming instruction knows the
5087 // destination vreg to set, the condition code register to branch on, the
5088 // true/false values to select between, and a branch opcode to use.
5089 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5090 MachineFunction::iterator It = BB;
5096 // cmpTY ccX, r1, r2
5098 // fallthrough --> copy0MBB
5099 MachineBasicBlock *thisMBB = BB;
5100 MachineFunction *F = BB->getParent();
5101 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5102 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5103 F->insert(It, copy0MBB);
5104 F->insert(It, sinkMBB);
5106 // Transfer the remainder of BB and its successor edges to sinkMBB.
5107 sinkMBB->splice(sinkMBB->begin(), BB,
5108 llvm::next(MachineBasicBlock::iterator(MI)),
5110 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5112 BB->addSuccessor(copy0MBB);
5113 BB->addSuccessor(sinkMBB);
5115 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5116 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5119 // %FalseValue = ...
5120 // # fallthrough to sinkMBB
5123 // Update machine-CFG edges
5124 BB->addSuccessor(sinkMBB);
5127 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5130 BuildMI(*BB, BB->begin(), dl,
5131 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5132 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5133 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5135 MI->eraseFromParent(); // The pseudo instruction is gone now.
5140 case ARM::BCCZi64: {
5141 // If there is an unconditional branch to the other successor, remove it.
5142 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5144 // Compare both parts that make up the double comparison separately for
5146 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5148 unsigned LHS1 = MI->getOperand(1).getReg();
5149 unsigned LHS2 = MI->getOperand(2).getReg();
5151 AddDefaultPred(BuildMI(BB, dl,
5152 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5153 .addReg(LHS1).addImm(0));
5154 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5155 .addReg(LHS2).addImm(0)
5156 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5158 unsigned RHS1 = MI->getOperand(3).getReg();
5159 unsigned RHS2 = MI->getOperand(4).getReg();
5160 AddDefaultPred(BuildMI(BB, dl,
5161 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5162 .addReg(LHS1).addReg(RHS1));
5163 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5164 .addReg(LHS2).addReg(RHS2)
5165 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5168 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5169 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5170 if (MI->getOperand(0).getImm() == ARMCC::NE)
5171 std::swap(destMBB, exitMBB);
5173 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5174 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5175 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5178 MI->eraseFromParent(); // The pseudo instruction is gone now.
5184 //===----------------------------------------------------------------------===//
5185 // ARM Optimization Hooks
5186 //===----------------------------------------------------------------------===//
5189 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5190 TargetLowering::DAGCombinerInfo &DCI) {
5191 SelectionDAG &DAG = DCI.DAG;
5192 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5193 EVT VT = N->getValueType(0);
5194 unsigned Opc = N->getOpcode();
5195 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5196 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5197 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5198 ISD::CondCode CC = ISD::SETCC_INVALID;
5201 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5203 SDValue CCOp = Slct.getOperand(0);
5204 if (CCOp.getOpcode() == ISD::SETCC)
5205 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5208 bool DoXform = false;
5210 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5213 if (LHS.getOpcode() == ISD::Constant &&
5214 cast<ConstantSDNode>(LHS)->isNullValue()) {
5216 } else if (CC != ISD::SETCC_INVALID &&
5217 RHS.getOpcode() == ISD::Constant &&
5218 cast<ConstantSDNode>(RHS)->isNullValue()) {
5219 std::swap(LHS, RHS);
5220 SDValue Op0 = Slct.getOperand(0);
5221 EVT OpVT = isSlctCC ? Op0.getValueType() :
5222 Op0.getOperand(0).getValueType();
5223 bool isInt = OpVT.isInteger();
5224 CC = ISD::getSetCCInverse(CC, isInt);
5226 if (!TLI.isCondCodeLegal(CC, OpVT))
5227 return SDValue(); // Inverse operator isn't legal.
5234 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5236 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5237 Slct.getOperand(0), Slct.getOperand(1), CC);
5238 SDValue CCOp = Slct.getOperand(0);
5240 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5241 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5242 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5243 CCOp, OtherOp, Result);
5248 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5249 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5250 /// called with the default operands, and if that fails, with commuted
5252 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5253 TargetLowering::DAGCombinerInfo &DCI) {
5254 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5255 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5256 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5257 if (Result.getNode()) return Result;
5262 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5264 static SDValue PerformADDCombine(SDNode *N,
5265 TargetLowering::DAGCombinerInfo &DCI) {
5266 SDValue N0 = N->getOperand(0);
5267 SDValue N1 = N->getOperand(1);
5269 // First try with the default operand order.
5270 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
5271 if (Result.getNode())
5274 // If that didn't work, try again with the operands commuted.
5275 return PerformADDCombineWithOperands(N, N1, N0, DCI);
5278 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5280 static SDValue PerformSUBCombine(SDNode *N,
5281 TargetLowering::DAGCombinerInfo &DCI) {
5282 SDValue N0 = N->getOperand(0);
5283 SDValue N1 = N->getOperand(1);
5285 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5286 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5287 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5288 if (Result.getNode()) return Result;
5294 /// PerformVMULCombine
5295 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5296 /// special multiplier accumulator forwarding.
5302 static SDValue PerformVMULCombine(SDNode *N,
5303 TargetLowering::DAGCombinerInfo &DCI,
5304 const ARMSubtarget *Subtarget) {
5305 if (!Subtarget->hasVMLxForwarding())
5308 SelectionDAG &DAG = DCI.DAG;
5309 SDValue N0 = N->getOperand(0);
5310 SDValue N1 = N->getOperand(1);
5311 unsigned Opcode = N0.getOpcode();
5312 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5313 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5314 Opcode = N0.getOpcode();
5315 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5316 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5321 EVT VT = N->getValueType(0);
5322 DebugLoc DL = N->getDebugLoc();
5323 SDValue N00 = N0->getOperand(0);
5324 SDValue N01 = N0->getOperand(1);
5325 return DAG.getNode(Opcode, DL, VT,
5326 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5327 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5330 static SDValue PerformMULCombine(SDNode *N,
5331 TargetLowering::DAGCombinerInfo &DCI,
5332 const ARMSubtarget *Subtarget) {
5333 SelectionDAG &DAG = DCI.DAG;
5335 if (Subtarget->isThumb1Only())
5338 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5341 EVT VT = N->getValueType(0);
5342 if (VT.is64BitVector() || VT.is128BitVector())
5343 return PerformVMULCombine(N, DCI, Subtarget);
5347 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5351 uint64_t MulAmt = C->getZExtValue();
5352 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5353 ShiftAmt = ShiftAmt & (32 - 1);
5354 SDValue V = N->getOperand(0);
5355 DebugLoc DL = N->getDebugLoc();
5358 MulAmt >>= ShiftAmt;
5359 if (isPowerOf2_32(MulAmt - 1)) {
5360 // (mul x, 2^N + 1) => (add (shl x, N), x)
5361 Res = DAG.getNode(ISD::ADD, DL, VT,
5362 V, DAG.getNode(ISD::SHL, DL, VT,
5363 V, DAG.getConstant(Log2_32(MulAmt-1),
5365 } else if (isPowerOf2_32(MulAmt + 1)) {
5366 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5367 Res = DAG.getNode(ISD::SUB, DL, VT,
5368 DAG.getNode(ISD::SHL, DL, VT,
5369 V, DAG.getConstant(Log2_32(MulAmt+1),
5376 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5377 DAG.getConstant(ShiftAmt, MVT::i32));
5379 // Do not add new nodes to DAG combiner worklist.
5380 DCI.CombineTo(N, Res, false);
5384 static SDValue PerformANDCombine(SDNode *N,
5385 TargetLowering::DAGCombinerInfo &DCI) {
5387 // Attempt to use immediate-form VBIC
5388 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5389 DebugLoc dl = N->getDebugLoc();
5390 EVT VT = N->getValueType(0);
5391 SelectionDAG &DAG = DCI.DAG;
5393 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5396 APInt SplatBits, SplatUndef;
5397 unsigned SplatBitSize;
5400 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5401 if (SplatBitSize <= 64) {
5403 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5404 SplatUndef.getZExtValue(), SplatBitSize,
5405 DAG, VbicVT, VT.is128BitVector(),
5407 if (Val.getNode()) {
5409 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5410 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5411 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5419 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5420 static SDValue PerformORCombine(SDNode *N,
5421 TargetLowering::DAGCombinerInfo &DCI,
5422 const ARMSubtarget *Subtarget) {
5423 // Attempt to use immediate-form VORR
5424 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5425 DebugLoc dl = N->getDebugLoc();
5426 EVT VT = N->getValueType(0);
5427 SelectionDAG &DAG = DCI.DAG;
5429 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5432 APInt SplatBits, SplatUndef;
5433 unsigned SplatBitSize;
5435 if (BVN && Subtarget->hasNEON() &&
5436 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5437 if (SplatBitSize <= 64) {
5439 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5440 SplatUndef.getZExtValue(), SplatBitSize,
5441 DAG, VorrVT, VT.is128BitVector(),
5443 if (Val.getNode()) {
5445 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5446 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5447 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5452 SDValue N0 = N->getOperand(0);
5453 if (N0.getOpcode() != ISD::AND)
5455 SDValue N1 = N->getOperand(1);
5457 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5458 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5459 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5461 unsigned SplatBitSize;
5464 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5466 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5467 HasAnyUndefs) && !HasAnyUndefs) {
5468 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5470 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5471 HasAnyUndefs) && !HasAnyUndefs &&
5472 SplatBits0 == ~SplatBits1) {
5473 // Canonicalize the vector type to make instruction selection simpler.
5474 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5475 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5476 N0->getOperand(1), N0->getOperand(0),
5478 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5483 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5486 // BFI is only available on V6T2+
5487 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5490 DebugLoc DL = N->getDebugLoc();
5491 // 1) or (and A, mask), val => ARMbfi A, val, mask
5492 // iff (val & mask) == val
5494 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5495 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5496 // && mask == ~mask2
5497 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5498 // && ~mask == mask2
5499 // (i.e., copy a bitfield value into another bitfield of the same width)
5504 SDValue N00 = N0.getOperand(0);
5506 // The value and the mask need to be constants so we can verify this is
5507 // actually a bitfield set. If the mask is 0xffff, we can do better
5508 // via a movt instruction, so don't use BFI in that case.
5509 SDValue MaskOp = N0.getOperand(1);
5510 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5513 unsigned Mask = MaskC->getZExtValue();
5517 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5518 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5520 unsigned Val = N1C->getZExtValue();
5521 if ((Val & ~Mask) != Val)
5524 if (ARM::isBitFieldInvertedMask(Mask)) {
5525 Val >>= CountTrailingZeros_32(~Mask);
5527 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5528 DAG.getConstant(Val, MVT::i32),
5529 DAG.getConstant(Mask, MVT::i32));
5531 // Do not add new nodes to DAG combiner worklist.
5532 DCI.CombineTo(N, Res, false);
5535 } else if (N1.getOpcode() == ISD::AND) {
5536 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5537 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5540 unsigned Mask2 = N11C->getZExtValue();
5542 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5544 if (ARM::isBitFieldInvertedMask(Mask) &&
5546 // The pack halfword instruction works better for masks that fit it,
5547 // so use that when it's available.
5548 if (Subtarget->hasT2ExtractPack() &&
5549 (Mask == 0xffff || Mask == 0xffff0000))
5552 unsigned amt = CountTrailingZeros_32(Mask2);
5553 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5554 DAG.getConstant(amt, MVT::i32));
5555 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5556 DAG.getConstant(Mask, MVT::i32));
5557 // Do not add new nodes to DAG combiner worklist.
5558 DCI.CombineTo(N, Res, false);
5560 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5562 // The pack halfword instruction works better for masks that fit it,
5563 // so use that when it's available.
5564 if (Subtarget->hasT2ExtractPack() &&
5565 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5568 unsigned lsb = CountTrailingZeros_32(Mask);
5569 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5570 DAG.getConstant(lsb, MVT::i32));
5571 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5572 DAG.getConstant(Mask2, MVT::i32));
5573 // Do not add new nodes to DAG combiner worklist.
5574 DCI.CombineTo(N, Res, false);
5579 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5580 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5581 ARM::isBitFieldInvertedMask(~Mask)) {
5582 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5583 // where lsb(mask) == #shamt and masked bits of B are known zero.
5584 SDValue ShAmt = N00.getOperand(1);
5585 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5586 unsigned LSB = CountTrailingZeros_32(Mask);
5590 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5591 DAG.getConstant(~Mask, MVT::i32));
5593 // Do not add new nodes to DAG combiner worklist.
5594 DCI.CombineTo(N, Res, false);
5600 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5602 static SDValue PerformBFICombine(SDNode *N,
5603 TargetLowering::DAGCombinerInfo &DCI) {
5604 SDValue N1 = N->getOperand(1);
5605 if (N1.getOpcode() == ISD::AND) {
5606 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5609 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5610 unsigned Mask2 = N11C->getZExtValue();
5611 if ((Mask & Mask2) == Mask2)
5612 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5613 N->getOperand(0), N1.getOperand(0),
5619 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5620 /// ARMISD::VMOVRRD.
5621 static SDValue PerformVMOVRRDCombine(SDNode *N,
5622 TargetLowering::DAGCombinerInfo &DCI) {
5623 // vmovrrd(vmovdrr x, y) -> x,y
5624 SDValue InDouble = N->getOperand(0);
5625 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5626 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5628 // vmovrrd(load f64) -> (load i32), (load i32)
5629 SDNode *InNode = InDouble.getNode();
5630 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
5631 InNode->getValueType(0) == MVT::f64 &&
5632 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
5633 !cast<LoadSDNode>(InNode)->isVolatile()) {
5634 // TODO: Should this be done for non-FrameIndex operands?
5635 LoadSDNode *LD = cast<LoadSDNode>(InNode);
5637 SelectionDAG &DAG = DCI.DAG;
5638 DebugLoc DL = LD->getDebugLoc();
5639 SDValue BasePtr = LD->getBasePtr();
5640 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
5641 LD->getPointerInfo(), LD->isVolatile(),
5642 LD->isNonTemporal(), LD->getAlignment());
5644 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5645 DAG.getConstant(4, MVT::i32));
5646 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
5647 LD->getPointerInfo(), LD->isVolatile(),
5648 LD->isNonTemporal(),
5649 std::min(4U, LD->getAlignment() / 2));
5651 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
5652 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
5653 DCI.RemoveFromWorklist(LD);
5661 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5662 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5663 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5664 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5665 SDValue Op0 = N->getOperand(0);
5666 SDValue Op1 = N->getOperand(1);
5667 if (Op0.getOpcode() == ISD::BITCAST)
5668 Op0 = Op0.getOperand(0);
5669 if (Op1.getOpcode() == ISD::BITCAST)
5670 Op1 = Op1.getOperand(0);
5671 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5672 Op0.getNode() == Op1.getNode() &&
5673 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5674 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5675 N->getValueType(0), Op0.getOperand(0));
5679 /// PerformSTORECombine - Target-specific dag combine xforms for
5681 static SDValue PerformSTORECombine(SDNode *N,
5682 TargetLowering::DAGCombinerInfo &DCI) {
5683 // Bitcast an i64 store extracted from a vector to f64.
5684 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5685 StoreSDNode *St = cast<StoreSDNode>(N);
5686 SDValue StVal = St->getValue();
5687 if (!ISD::isNormalStore(St) || St->isVolatile() ||
5688 StVal.getValueType() != MVT::i64 ||
5689 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5692 SelectionDAG &DAG = DCI.DAG;
5693 DebugLoc dl = StVal.getDebugLoc();
5694 SDValue IntVec = StVal.getOperand(0);
5695 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5696 IntVec.getValueType().getVectorNumElements());
5697 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5698 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5699 Vec, StVal.getOperand(1));
5700 dl = N->getDebugLoc();
5701 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5702 // Make the DAGCombiner fold the bitcasts.
5703 DCI.AddToWorklist(Vec.getNode());
5704 DCI.AddToWorklist(ExtElt.getNode());
5705 DCI.AddToWorklist(V.getNode());
5706 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5707 St->getPointerInfo(), St->isVolatile(),
5708 St->isNonTemporal(), St->getAlignment(),
5712 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5713 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5714 /// i64 vector to have f64 elements, since the value can then be loaded
5715 /// directly into a VFP register.
5716 static bool hasNormalLoadOperand(SDNode *N) {
5717 unsigned NumElts = N->getValueType(0).getVectorNumElements();
5718 for (unsigned i = 0; i < NumElts; ++i) {
5719 SDNode *Elt = N->getOperand(i).getNode();
5720 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
5726 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
5727 /// ISD::BUILD_VECTOR.
5728 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
5729 TargetLowering::DAGCombinerInfo &DCI){
5730 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
5731 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
5732 // into a pair of GPRs, which is fine when the value is used as a scalar,
5733 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
5734 SelectionDAG &DAG = DCI.DAG;
5735 if (N->getNumOperands() == 2) {
5736 SDValue RV = PerformVMOVDRRCombine(N, DAG);
5741 // Load i64 elements as f64 values so that type legalization does not split
5742 // them up into i32 values.
5743 EVT VT = N->getValueType(0);
5744 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
5746 DebugLoc dl = N->getDebugLoc();
5747 SmallVector<SDValue, 8> Ops;
5748 unsigned NumElts = VT.getVectorNumElements();
5749 for (unsigned i = 0; i < NumElts; ++i) {
5750 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
5752 // Make the DAGCombiner fold the bitcast.
5753 DCI.AddToWorklist(V.getNode());
5755 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
5756 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
5757 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
5760 /// PerformInsertEltCombine - Target-specific dag combine xforms for
5761 /// ISD::INSERT_VECTOR_ELT.
5762 static SDValue PerformInsertEltCombine(SDNode *N,
5763 TargetLowering::DAGCombinerInfo &DCI) {
5764 // Bitcast an i64 load inserted into a vector to f64.
5765 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5766 EVT VT = N->getValueType(0);
5767 SDNode *Elt = N->getOperand(1).getNode();
5768 if (VT.getVectorElementType() != MVT::i64 ||
5769 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
5772 SelectionDAG &DAG = DCI.DAG;
5773 DebugLoc dl = N->getDebugLoc();
5774 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5775 VT.getVectorNumElements());
5776 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
5777 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
5778 // Make the DAGCombiner fold the bitcasts.
5779 DCI.AddToWorklist(Vec.getNode());
5780 DCI.AddToWorklist(V.getNode());
5781 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
5782 Vec, V, N->getOperand(2));
5783 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
5786 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
5787 /// ISD::VECTOR_SHUFFLE.
5788 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
5789 // The LLVM shufflevector instruction does not require the shuffle mask
5790 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
5791 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
5792 // operands do not match the mask length, they are extended by concatenating
5793 // them with undef vectors. That is probably the right thing for other
5794 // targets, but for NEON it is better to concatenate two double-register
5795 // size vector operands into a single quad-register size vector. Do that
5796 // transformation here:
5797 // shuffle(concat(v1, undef), concat(v2, undef)) ->
5798 // shuffle(concat(v1, v2), undef)
5799 SDValue Op0 = N->getOperand(0);
5800 SDValue Op1 = N->getOperand(1);
5801 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
5802 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
5803 Op0.getNumOperands() != 2 ||
5804 Op1.getNumOperands() != 2)
5806 SDValue Concat0Op1 = Op0.getOperand(1);
5807 SDValue Concat1Op1 = Op1.getOperand(1);
5808 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
5809 Concat1Op1.getOpcode() != ISD::UNDEF)
5811 // Skip the transformation if any of the types are illegal.
5812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5813 EVT VT = N->getValueType(0);
5814 if (!TLI.isTypeLegal(VT) ||
5815 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5816 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5819 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5820 Op0.getOperand(0), Op1.getOperand(0));
5821 // Translate the shuffle mask.
5822 SmallVector<int, 16> NewMask;
5823 unsigned NumElts = VT.getVectorNumElements();
5824 unsigned HalfElts = NumElts/2;
5825 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5826 for (unsigned n = 0; n < NumElts; ++n) {
5827 int MaskElt = SVN->getMaskElt(n);
5829 if (MaskElt < (int)HalfElts)
5831 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5832 NewElt = HalfElts + MaskElt - NumElts;
5833 NewMask.push_back(NewElt);
5835 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5836 DAG.getUNDEF(VT), NewMask.data());
5839 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
5840 /// NEON load/store intrinsics to merge base address updates.
5841 static SDValue CombineBaseUpdate(SDNode *N,
5842 TargetLowering::DAGCombinerInfo &DCI) {
5843 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5846 SelectionDAG &DAG = DCI.DAG;
5847 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
5848 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
5849 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
5850 SDValue Addr = N->getOperand(AddrOpIdx);
5852 // Search for a use of the address operand that is an increment.
5853 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
5854 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
5856 if (User->getOpcode() != ISD::ADD ||
5857 UI.getUse().getResNo() != Addr.getResNo())
5860 // Check that the add is independent of the load/store. Otherwise, folding
5861 // it would create a cycle.
5862 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
5865 // Find the new opcode for the updating load/store.
5867 bool isLaneOp = false;
5868 unsigned NewOpc = 0;
5869 unsigned NumVecs = 0;
5871 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
5873 default: assert(0 && "unexpected intrinsic for Neon base update");
5874 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
5876 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
5878 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
5880 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
5882 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
5883 NumVecs = 2; isLaneOp = true; break;
5884 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
5885 NumVecs = 3; isLaneOp = true; break;
5886 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
5887 NumVecs = 4; isLaneOp = true; break;
5888 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
5889 NumVecs = 1; isLoad = false; break;
5890 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
5891 NumVecs = 2; isLoad = false; break;
5892 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
5893 NumVecs = 3; isLoad = false; break;
5894 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
5895 NumVecs = 4; isLoad = false; break;
5896 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
5897 NumVecs = 2; isLoad = false; isLaneOp = true; break;
5898 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
5899 NumVecs = 3; isLoad = false; isLaneOp = true; break;
5900 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
5901 NumVecs = 4; isLoad = false; isLaneOp = true; break;
5905 switch (N->getOpcode()) {
5906 default: assert(0 && "unexpected opcode for Neon base update");
5907 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
5908 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
5909 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
5913 // Find the size of memory referenced by the load/store.
5916 VecTy = N->getValueType(0);
5918 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
5919 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
5921 NumBytes /= VecTy.getVectorNumElements();
5923 // If the increment is a constant, it must match the memory ref size.
5924 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
5925 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
5926 uint64_t IncVal = CInc->getZExtValue();
5927 if (IncVal != NumBytes)
5929 } else if (NumBytes >= 3 * 16) {
5930 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
5931 // separate instructions that make it harder to use a non-constant update.
5935 // Create the new updating load/store node.
5937 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
5939 for (n = 0; n < NumResultVecs; ++n)
5941 Tys[n++] = MVT::i32;
5942 Tys[n] = MVT::Other;
5943 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
5944 SmallVector<SDValue, 8> Ops;
5945 Ops.push_back(N->getOperand(0)); // incoming chain
5946 Ops.push_back(N->getOperand(AddrOpIdx));
5948 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
5949 Ops.push_back(N->getOperand(i));
5951 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
5952 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
5953 Ops.data(), Ops.size(),
5954 MemInt->getMemoryVT(),
5955 MemInt->getMemOperand());
5958 std::vector<SDValue> NewResults;
5959 for (unsigned i = 0; i < NumResultVecs; ++i) {
5960 NewResults.push_back(SDValue(UpdN.getNode(), i));
5962 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
5963 DCI.CombineTo(N, NewResults);
5964 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
5971 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
5972 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
5973 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
5975 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
5976 SelectionDAG &DAG = DCI.DAG;
5977 EVT VT = N->getValueType(0);
5978 // vldN-dup instructions only support 64-bit vectors for N > 1.
5979 if (!VT.is64BitVector())
5982 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
5983 SDNode *VLD = N->getOperand(0).getNode();
5984 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
5986 unsigned NumVecs = 0;
5987 unsigned NewOpc = 0;
5988 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
5989 if (IntNo == Intrinsic::arm_neon_vld2lane) {
5991 NewOpc = ARMISD::VLD2DUP;
5992 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
5994 NewOpc = ARMISD::VLD3DUP;
5995 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
5997 NewOpc = ARMISD::VLD4DUP;
6002 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6003 // numbers match the load.
6004 unsigned VLDLaneNo =
6005 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6006 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6008 // Ignore uses of the chain result.
6009 if (UI.getUse().getResNo() == NumVecs)
6012 if (User->getOpcode() != ARMISD::VDUPLANE ||
6013 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6017 // Create the vldN-dup node.
6020 for (n = 0; n < NumVecs; ++n)
6022 Tys[n] = MVT::Other;
6023 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6024 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6025 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6026 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6027 Ops, 2, VLDMemInt->getMemoryVT(),
6028 VLDMemInt->getMemOperand());
6031 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6033 unsigned ResNo = UI.getUse().getResNo();
6034 // Ignore uses of the chain result.
6035 if (ResNo == NumVecs)
6038 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6041 // Now the vldN-lane intrinsic is dead except for its chain result.
6042 // Update uses of the chain.
6043 std::vector<SDValue> VLDDupResults;
6044 for (unsigned n = 0; n < NumVecs; ++n)
6045 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6046 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6047 DCI.CombineTo(VLD, VLDDupResults);
6052 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6053 /// ARMISD::VDUPLANE.
6054 static SDValue PerformVDUPLANECombine(SDNode *N,
6055 TargetLowering::DAGCombinerInfo &DCI) {
6056 SDValue Op = N->getOperand(0);
6058 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6059 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6060 if (CombineVLDDUP(N, DCI))
6061 return SDValue(N, 0);
6063 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6064 // redundant. Ignore bit_converts for now; element sizes are checked below.
6065 while (Op.getOpcode() == ISD::BITCAST)
6066 Op = Op.getOperand(0);
6067 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6070 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6071 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6072 // The canonical VMOV for a zero vector uses a 32-bit element size.
6073 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6075 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6077 EVT VT = N->getValueType(0);
6078 if (EltSize > VT.getVectorElementType().getSizeInBits())
6081 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6084 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6085 /// operand of a vector shift operation, where all the elements of the
6086 /// build_vector must have the same constant integer value.
6087 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6088 // Ignore bit_converts.
6089 while (Op.getOpcode() == ISD::BITCAST)
6090 Op = Op.getOperand(0);
6091 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6092 APInt SplatBits, SplatUndef;
6093 unsigned SplatBitSize;
6095 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6096 HasAnyUndefs, ElementBits) ||
6097 SplatBitSize > ElementBits)
6099 Cnt = SplatBits.getSExtValue();
6103 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6104 /// operand of a vector shift left operation. That value must be in the range:
6105 /// 0 <= Value < ElementBits for a left shift; or
6106 /// 0 <= Value <= ElementBits for a long left shift.
6107 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6108 assert(VT.isVector() && "vector shift count is not a vector type");
6109 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6110 if (! getVShiftImm(Op, ElementBits, Cnt))
6112 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6115 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6116 /// operand of a vector shift right operation. For a shift opcode, the value
6117 /// is positive, but for an intrinsic the value count must be negative. The
6118 /// absolute value must be in the range:
6119 /// 1 <= |Value| <= ElementBits for a right shift; or
6120 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6121 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6123 assert(VT.isVector() && "vector shift count is not a vector type");
6124 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6125 if (! getVShiftImm(Op, ElementBits, Cnt))
6129 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6132 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6133 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6134 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6137 // Don't do anything for most intrinsics.
6140 // Vector shifts: check for immediate versions and lower them.
6141 // Note: This is done during DAG combining instead of DAG legalizing because
6142 // the build_vectors for 64-bit vector element shift counts are generally
6143 // not legal, and it is hard to see their values after they get legalized to
6144 // loads from a constant pool.
6145 case Intrinsic::arm_neon_vshifts:
6146 case Intrinsic::arm_neon_vshiftu:
6147 case Intrinsic::arm_neon_vshiftls:
6148 case Intrinsic::arm_neon_vshiftlu:
6149 case Intrinsic::arm_neon_vshiftn:
6150 case Intrinsic::arm_neon_vrshifts:
6151 case Intrinsic::arm_neon_vrshiftu:
6152 case Intrinsic::arm_neon_vrshiftn:
6153 case Intrinsic::arm_neon_vqshifts:
6154 case Intrinsic::arm_neon_vqshiftu:
6155 case Intrinsic::arm_neon_vqshiftsu:
6156 case Intrinsic::arm_neon_vqshiftns:
6157 case Intrinsic::arm_neon_vqshiftnu:
6158 case Intrinsic::arm_neon_vqshiftnsu:
6159 case Intrinsic::arm_neon_vqrshiftns:
6160 case Intrinsic::arm_neon_vqrshiftnu:
6161 case Intrinsic::arm_neon_vqrshiftnsu: {
6162 EVT VT = N->getOperand(1).getValueType();
6164 unsigned VShiftOpc = 0;
6167 case Intrinsic::arm_neon_vshifts:
6168 case Intrinsic::arm_neon_vshiftu:
6169 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6170 VShiftOpc = ARMISD::VSHL;
6173 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6174 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6175 ARMISD::VSHRs : ARMISD::VSHRu);
6180 case Intrinsic::arm_neon_vshiftls:
6181 case Intrinsic::arm_neon_vshiftlu:
6182 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6184 llvm_unreachable("invalid shift count for vshll intrinsic");
6186 case Intrinsic::arm_neon_vrshifts:
6187 case Intrinsic::arm_neon_vrshiftu:
6188 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6192 case Intrinsic::arm_neon_vqshifts:
6193 case Intrinsic::arm_neon_vqshiftu:
6194 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6198 case Intrinsic::arm_neon_vqshiftsu:
6199 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6201 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6203 case Intrinsic::arm_neon_vshiftn:
6204 case Intrinsic::arm_neon_vrshiftn:
6205 case Intrinsic::arm_neon_vqshiftns:
6206 case Intrinsic::arm_neon_vqshiftnu:
6207 case Intrinsic::arm_neon_vqshiftnsu:
6208 case Intrinsic::arm_neon_vqrshiftns:
6209 case Intrinsic::arm_neon_vqrshiftnu:
6210 case Intrinsic::arm_neon_vqrshiftnsu:
6211 // Narrowing shifts require an immediate right shift.
6212 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6214 llvm_unreachable("invalid shift count for narrowing vector shift "
6218 llvm_unreachable("unhandled vector shift");
6222 case Intrinsic::arm_neon_vshifts:
6223 case Intrinsic::arm_neon_vshiftu:
6224 // Opcode already set above.
6226 case Intrinsic::arm_neon_vshiftls:
6227 case Intrinsic::arm_neon_vshiftlu:
6228 if (Cnt == VT.getVectorElementType().getSizeInBits())
6229 VShiftOpc = ARMISD::VSHLLi;
6231 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6232 ARMISD::VSHLLs : ARMISD::VSHLLu);
6234 case Intrinsic::arm_neon_vshiftn:
6235 VShiftOpc = ARMISD::VSHRN; break;
6236 case Intrinsic::arm_neon_vrshifts:
6237 VShiftOpc = ARMISD::VRSHRs; break;
6238 case Intrinsic::arm_neon_vrshiftu:
6239 VShiftOpc = ARMISD::VRSHRu; break;
6240 case Intrinsic::arm_neon_vrshiftn:
6241 VShiftOpc = ARMISD::VRSHRN; break;
6242 case Intrinsic::arm_neon_vqshifts:
6243 VShiftOpc = ARMISD::VQSHLs; break;
6244 case Intrinsic::arm_neon_vqshiftu:
6245 VShiftOpc = ARMISD::VQSHLu; break;
6246 case Intrinsic::arm_neon_vqshiftsu:
6247 VShiftOpc = ARMISD::VQSHLsu; break;
6248 case Intrinsic::arm_neon_vqshiftns:
6249 VShiftOpc = ARMISD::VQSHRNs; break;
6250 case Intrinsic::arm_neon_vqshiftnu:
6251 VShiftOpc = ARMISD::VQSHRNu; break;
6252 case Intrinsic::arm_neon_vqshiftnsu:
6253 VShiftOpc = ARMISD::VQSHRNsu; break;
6254 case Intrinsic::arm_neon_vqrshiftns:
6255 VShiftOpc = ARMISD::VQRSHRNs; break;
6256 case Intrinsic::arm_neon_vqrshiftnu:
6257 VShiftOpc = ARMISD::VQRSHRNu; break;
6258 case Intrinsic::arm_neon_vqrshiftnsu:
6259 VShiftOpc = ARMISD::VQRSHRNsu; break;
6262 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6263 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6266 case Intrinsic::arm_neon_vshiftins: {
6267 EVT VT = N->getOperand(1).getValueType();
6269 unsigned VShiftOpc = 0;
6271 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6272 VShiftOpc = ARMISD::VSLI;
6273 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6274 VShiftOpc = ARMISD::VSRI;
6276 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6279 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6280 N->getOperand(1), N->getOperand(2),
6281 DAG.getConstant(Cnt, MVT::i32));
6284 case Intrinsic::arm_neon_vqrshifts:
6285 case Intrinsic::arm_neon_vqrshiftu:
6286 // No immediate versions of these to check for.
6293 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6294 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6295 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6296 /// vector element shift counts are generally not legal, and it is hard to see
6297 /// their values after they get legalized to loads from a constant pool.
6298 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6299 const ARMSubtarget *ST) {
6300 EVT VT = N->getValueType(0);
6302 // Nothing to be done for scalar shifts.
6303 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6304 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6307 assert(ST->hasNEON() && "unexpected vector shift");
6310 switch (N->getOpcode()) {
6311 default: llvm_unreachable("unexpected shift opcode");
6314 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6315 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6316 DAG.getConstant(Cnt, MVT::i32));
6321 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6322 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6323 ARMISD::VSHRs : ARMISD::VSHRu);
6324 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6325 DAG.getConstant(Cnt, MVT::i32));
6331 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6332 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6333 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6334 const ARMSubtarget *ST) {
6335 SDValue N0 = N->getOperand(0);
6337 // Check for sign- and zero-extensions of vector extract operations of 8-
6338 // and 16-bit vector elements. NEON supports these directly. They are
6339 // handled during DAG combining because type legalization will promote them
6340 // to 32-bit types and it is messy to recognize the operations after that.
6341 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6342 SDValue Vec = N0.getOperand(0);
6343 SDValue Lane = N0.getOperand(1);
6344 EVT VT = N->getValueType(0);
6345 EVT EltVT = N0.getValueType();
6346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6348 if (VT == MVT::i32 &&
6349 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6350 TLI.isTypeLegal(Vec.getValueType()) &&
6351 isa<ConstantSDNode>(Lane)) {
6354 switch (N->getOpcode()) {
6355 default: llvm_unreachable("unexpected opcode");
6356 case ISD::SIGN_EXTEND:
6357 Opc = ARMISD::VGETLANEs;
6359 case ISD::ZERO_EXTEND:
6360 case ISD::ANY_EXTEND:
6361 Opc = ARMISD::VGETLANEu;
6364 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6371 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6372 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6373 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6374 const ARMSubtarget *ST) {
6375 // If the target supports NEON, try to use vmax/vmin instructions for f32
6376 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6377 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6378 // a NaN; only do the transformation when it matches that behavior.
6380 // For now only do this when using NEON for FP operations; if using VFP, it
6381 // is not obvious that the benefit outweighs the cost of switching to the
6383 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6384 N->getValueType(0) != MVT::f32)
6387 SDValue CondLHS = N->getOperand(0);
6388 SDValue CondRHS = N->getOperand(1);
6389 SDValue LHS = N->getOperand(2);
6390 SDValue RHS = N->getOperand(3);
6391 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6393 unsigned Opcode = 0;
6395 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6396 IsReversed = false; // x CC y ? x : y
6397 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6398 IsReversed = true ; // x CC y ? y : x
6412 // If LHS is NaN, an ordered comparison will be false and the result will
6413 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6414 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6415 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6416 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6418 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6419 // will return -0, so vmin can only be used for unsafe math or if one of
6420 // the operands is known to be nonzero.
6421 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6423 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6425 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6434 // If LHS is NaN, an ordered comparison will be false and the result will
6435 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6436 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6437 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6438 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6440 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6441 // will return +0, so vmax can only be used for unsafe math or if one of
6442 // the operands is known to be nonzero.
6443 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6445 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6447 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6453 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6456 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6457 DAGCombinerInfo &DCI) const {
6458 switch (N->getOpcode()) {
6460 case ISD::ADD: return PerformADDCombine(N, DCI);
6461 case ISD::SUB: return PerformSUBCombine(N, DCI);
6462 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6463 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6464 case ISD::AND: return PerformANDCombine(N, DCI);
6465 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6466 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6467 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6468 case ISD::STORE: return PerformSTORECombine(N, DCI);
6469 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6470 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6471 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6472 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6473 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6476 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6477 case ISD::SIGN_EXTEND:
6478 case ISD::ZERO_EXTEND:
6479 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6480 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6481 case ARMISD::VLD2DUP:
6482 case ARMISD::VLD3DUP:
6483 case ARMISD::VLD4DUP:
6484 return CombineBaseUpdate(N, DCI);
6485 case ISD::INTRINSIC_VOID:
6486 case ISD::INTRINSIC_W_CHAIN:
6487 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6488 case Intrinsic::arm_neon_vld1:
6489 case Intrinsic::arm_neon_vld2:
6490 case Intrinsic::arm_neon_vld3:
6491 case Intrinsic::arm_neon_vld4:
6492 case Intrinsic::arm_neon_vld2lane:
6493 case Intrinsic::arm_neon_vld3lane:
6494 case Intrinsic::arm_neon_vld4lane:
6495 case Intrinsic::arm_neon_vst1:
6496 case Intrinsic::arm_neon_vst2:
6497 case Intrinsic::arm_neon_vst3:
6498 case Intrinsic::arm_neon_vst4:
6499 case Intrinsic::arm_neon_vst2lane:
6500 case Intrinsic::arm_neon_vst3lane:
6501 case Intrinsic::arm_neon_vst4lane:
6502 return CombineBaseUpdate(N, DCI);
6510 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6512 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6515 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6516 if (!Subtarget->allowsUnalignedMem())
6519 switch (VT.getSimpleVT().SimpleTy) {
6526 // FIXME: VLD1 etc with standard alignment is legal.
6530 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6535 switch (VT.getSimpleVT().SimpleTy) {
6536 default: return false;
6551 if ((V & (Scale - 1)) != 0)
6554 return V == (V & ((1LL << 5) - 1));
6557 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6558 const ARMSubtarget *Subtarget) {
6565 switch (VT.getSimpleVT().SimpleTy) {
6566 default: return false;
6571 // + imm12 or - imm8
6573 return V == (V & ((1LL << 8) - 1));
6574 return V == (V & ((1LL << 12) - 1));
6577 // Same as ARM mode. FIXME: NEON?
6578 if (!Subtarget->hasVFP2())
6583 return V == (V & ((1LL << 8) - 1));
6587 /// isLegalAddressImmediate - Return true if the integer value can be used
6588 /// as the offset of the target addressing mode for load / store of the
6590 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6591 const ARMSubtarget *Subtarget) {
6598 if (Subtarget->isThumb1Only())
6599 return isLegalT1AddressImmediate(V, VT);
6600 else if (Subtarget->isThumb2())
6601 return isLegalT2AddressImmediate(V, VT, Subtarget);
6606 switch (VT.getSimpleVT().SimpleTy) {
6607 default: return false;
6612 return V == (V & ((1LL << 12) - 1));
6615 return V == (V & ((1LL << 8) - 1));
6618 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6623 return V == (V & ((1LL << 8) - 1));
6627 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6629 int Scale = AM.Scale;
6633 switch (VT.getSimpleVT().SimpleTy) {
6634 default: return false;
6643 return Scale == 2 || Scale == 4 || Scale == 8;
6646 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6650 // Note, we allow "void" uses (basically, uses that aren't loads or
6651 // stores), because arm allows folding a scale into many arithmetic
6652 // operations. This should be made more precise and revisited later.
6654 // Allow r << imm, but the imm has to be a multiple of two.
6655 if (Scale & 1) return false;
6656 return isPowerOf2_32(Scale);
6660 /// isLegalAddressingMode - Return true if the addressing mode represented
6661 /// by AM is legal for this target, for a load/store of the specified type.
6662 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6663 const Type *Ty) const {
6664 EVT VT = getValueType(Ty, true);
6665 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6668 // Can never fold addr of global into load/store.
6673 case 0: // no scale reg, must be "r+i" or "r", or "i".
6676 if (Subtarget->isThumb1Only())
6680 // ARM doesn't support any R+R*scale+imm addr modes.
6687 if (Subtarget->isThumb2())
6688 return isLegalT2ScaledAddressingMode(AM, VT);
6690 int Scale = AM.Scale;
6691 switch (VT.getSimpleVT().SimpleTy) {
6692 default: return false;
6696 if (Scale < 0) Scale = -Scale;
6700 return isPowerOf2_32(Scale & ~1);
6704 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6709 // Note, we allow "void" uses (basically, uses that aren't loads or
6710 // stores), because arm allows folding a scale into many arithmetic
6711 // operations. This should be made more precise and revisited later.
6713 // Allow r << imm, but the imm has to be a multiple of two.
6714 if (Scale & 1) return false;
6715 return isPowerOf2_32(Scale);
6722 /// isLegalICmpImmediate - Return true if the specified immediate is legal
6723 /// icmp immediate, that is the target has icmp instructions which can compare
6724 /// a register against the immediate without having to materialize the
6725 /// immediate into a register.
6726 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
6727 if (!Subtarget->isThumb())
6728 return ARM_AM::getSOImmVal(Imm) != -1;
6729 if (Subtarget->isThumb2())
6730 return ARM_AM::getT2SOImmVal(Imm) != -1;
6731 return Imm >= 0 && Imm <= 255;
6734 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
6735 bool isSEXTLoad, SDValue &Base,
6736 SDValue &Offset, bool &isInc,
6737 SelectionDAG &DAG) {
6738 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6741 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
6743 Base = Ptr->getOperand(0);
6744 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6745 int RHSC = (int)RHS->getZExtValue();
6746 if (RHSC < 0 && RHSC > -256) {
6747 assert(Ptr->getOpcode() == ISD::ADD);
6749 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6753 isInc = (Ptr->getOpcode() == ISD::ADD);
6754 Offset = Ptr->getOperand(1);
6756 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
6758 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6759 int RHSC = (int)RHS->getZExtValue();
6760 if (RHSC < 0 && RHSC > -0x1000) {
6761 assert(Ptr->getOpcode() == ISD::ADD);
6763 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6764 Base = Ptr->getOperand(0);
6769 if (Ptr->getOpcode() == ISD::ADD) {
6771 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
6772 if (ShOpcVal != ARM_AM::no_shift) {
6773 Base = Ptr->getOperand(1);
6774 Offset = Ptr->getOperand(0);
6776 Base = Ptr->getOperand(0);
6777 Offset = Ptr->getOperand(1);
6782 isInc = (Ptr->getOpcode() == ISD::ADD);
6783 Base = Ptr->getOperand(0);
6784 Offset = Ptr->getOperand(1);
6788 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
6792 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
6793 bool isSEXTLoad, SDValue &Base,
6794 SDValue &Offset, bool &isInc,
6795 SelectionDAG &DAG) {
6796 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
6799 Base = Ptr->getOperand(0);
6800 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
6801 int RHSC = (int)RHS->getZExtValue();
6802 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
6803 assert(Ptr->getOpcode() == ISD::ADD);
6805 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
6807 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
6808 isInc = Ptr->getOpcode() == ISD::ADD;
6809 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
6817 /// getPreIndexedAddressParts - returns true by value, base pointer and
6818 /// offset pointer and addressing mode by reference if the node's address
6819 /// can be legally represented as pre-indexed load / store address.
6821 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
6823 ISD::MemIndexedMode &AM,
6824 SelectionDAG &DAG) const {
6825 if (Subtarget->isThumb1Only())
6830 bool isSEXTLoad = false;
6831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6832 Ptr = LD->getBasePtr();
6833 VT = LD->getMemoryVT();
6834 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6835 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6836 Ptr = ST->getBasePtr();
6837 VT = ST->getMemoryVT();
6842 bool isLegal = false;
6843 if (Subtarget->isThumb2())
6844 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6845 Offset, isInc, DAG);
6847 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
6848 Offset, isInc, DAG);
6852 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
6856 /// getPostIndexedAddressParts - returns true by value, base pointer and
6857 /// offset pointer and addressing mode by reference if this node can be
6858 /// combined with a load / store to form a post-indexed load / store.
6859 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
6862 ISD::MemIndexedMode &AM,
6863 SelectionDAG &DAG) const {
6864 if (Subtarget->isThumb1Only())
6869 bool isSEXTLoad = false;
6870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6871 VT = LD->getMemoryVT();
6872 Ptr = LD->getBasePtr();
6873 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
6874 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6875 VT = ST->getMemoryVT();
6876 Ptr = ST->getBasePtr();
6881 bool isLegal = false;
6882 if (Subtarget->isThumb2())
6883 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6886 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
6892 // Swap base ptr and offset to catch more post-index load / store when
6893 // it's legal. In Thumb2 mode, offset must be an immediate.
6894 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
6895 !Subtarget->isThumb2())
6896 std::swap(Base, Offset);
6898 // Post-indexed load / store update the base pointer.
6903 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
6907 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6911 const SelectionDAG &DAG,
6912 unsigned Depth) const {
6913 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
6914 switch (Op.getOpcode()) {
6916 case ARMISD::CMOV: {
6917 // Bits are known zero/one if known on the LHS and RHS.
6918 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
6919 if (KnownZero == 0 && KnownOne == 0) return;
6921 APInt KnownZeroRHS, KnownOneRHS;
6922 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
6923 KnownZeroRHS, KnownOneRHS, Depth+1);
6924 KnownZero &= KnownZeroRHS;
6925 KnownOne &= KnownOneRHS;
6931 //===----------------------------------------------------------------------===//
6932 // ARM Inline Assembly Support
6933 //===----------------------------------------------------------------------===//
6935 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
6936 // Looking for "rev" which is V6+.
6937 if (!Subtarget->hasV6Ops())
6940 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
6941 std::string AsmStr = IA->getAsmString();
6942 SmallVector<StringRef, 4> AsmPieces;
6943 SplitString(AsmStr, AsmPieces, ";\n");
6945 switch (AsmPieces.size()) {
6946 default: return false;
6948 AsmStr = AsmPieces[0];
6950 SplitString(AsmStr, AsmPieces, " \t,");
6953 if (AsmPieces.size() == 3 &&
6954 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
6955 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
6956 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
6957 if (Ty && Ty->getBitWidth() == 32)
6958 return IntrinsicLowering::LowerToByteSwap(CI);
6966 /// getConstraintType - Given a constraint letter, return the type of
6967 /// constraint it is for this target.
6968 ARMTargetLowering::ConstraintType
6969 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
6970 if (Constraint.size() == 1) {
6971 switch (Constraint[0]) {
6973 case 'l': return C_RegisterClass;
6974 case 'w': return C_RegisterClass;
6977 return TargetLowering::getConstraintType(Constraint);
6980 /// Examine constraint type and operand type and determine a weight value.
6981 /// This object must already have been set up with the operand type
6982 /// and the current alternative constraint selected.
6983 TargetLowering::ConstraintWeight
6984 ARMTargetLowering::getSingleConstraintMatchWeight(
6985 AsmOperandInfo &info, const char *constraint) const {
6986 ConstraintWeight weight = CW_Invalid;
6987 Value *CallOperandVal = info.CallOperandVal;
6988 // If we don't have a value, we can't do a match,
6989 // but allow it at the lowest weight.
6990 if (CallOperandVal == NULL)
6992 const Type *type = CallOperandVal->getType();
6993 // Look at the constraint type.
6994 switch (*constraint) {
6996 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6999 if (type->isIntegerTy()) {
7000 if (Subtarget->isThumb())
7001 weight = CW_SpecificReg;
7003 weight = CW_Register;
7007 if (type->isFloatingPointTy())
7008 weight = CW_Register;
7014 std::pair<unsigned, const TargetRegisterClass*>
7015 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7017 if (Constraint.size() == 1) {
7018 // GCC ARM Constraint Letters
7019 switch (Constraint[0]) {
7021 if (Subtarget->isThumb())
7022 return std::make_pair(0U, ARM::tGPRRegisterClass);
7024 return std::make_pair(0U, ARM::GPRRegisterClass);
7026 return std::make_pair(0U, ARM::GPRRegisterClass);
7029 return std::make_pair(0U, ARM::SPRRegisterClass);
7030 if (VT.getSizeInBits() == 64)
7031 return std::make_pair(0U, ARM::DPRRegisterClass);
7032 if (VT.getSizeInBits() == 128)
7033 return std::make_pair(0U, ARM::QPRRegisterClass);
7037 if (StringRef("{cc}").equals_lower(Constraint))
7038 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7040 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7043 std::vector<unsigned> ARMTargetLowering::
7044 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7046 if (Constraint.size() != 1)
7047 return std::vector<unsigned>();
7049 switch (Constraint[0]) { // GCC ARM Constraint Letters
7052 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7053 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7056 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7057 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7058 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
7059 ARM::R12, ARM::LR, 0);
7062 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
7063 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
7064 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
7065 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
7066 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
7067 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
7068 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
7069 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
7070 if (VT.getSizeInBits() == 64)
7071 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
7072 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
7073 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
7074 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
7075 if (VT.getSizeInBits() == 128)
7076 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
7077 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
7081 return std::vector<unsigned>();
7084 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7085 /// vector. If it is invalid, don't add anything to Ops.
7086 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7088 std::vector<SDValue>&Ops,
7089 SelectionDAG &DAG) const {
7090 SDValue Result(0, 0);
7092 switch (Constraint) {
7094 case 'I': case 'J': case 'K': case 'L':
7095 case 'M': case 'N': case 'O':
7096 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7100 int64_t CVal64 = C->getSExtValue();
7101 int CVal = (int) CVal64;
7102 // None of these constraints allow values larger than 32 bits. Check
7103 // that the value fits in an int.
7107 switch (Constraint) {
7109 if (Subtarget->isThumb1Only()) {
7110 // This must be a constant between 0 and 255, for ADD
7112 if (CVal >= 0 && CVal <= 255)
7114 } else if (Subtarget->isThumb2()) {
7115 // A constant that can be used as an immediate value in a
7116 // data-processing instruction.
7117 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7120 // A constant that can be used as an immediate value in a
7121 // data-processing instruction.
7122 if (ARM_AM::getSOImmVal(CVal) != -1)
7128 if (Subtarget->isThumb()) { // FIXME thumb2
7129 // This must be a constant between -255 and -1, for negated ADD
7130 // immediates. This can be used in GCC with an "n" modifier that
7131 // prints the negated value, for use with SUB instructions. It is
7132 // not useful otherwise but is implemented for compatibility.
7133 if (CVal >= -255 && CVal <= -1)
7136 // This must be a constant between -4095 and 4095. It is not clear
7137 // what this constraint is intended for. Implemented for
7138 // compatibility with GCC.
7139 if (CVal >= -4095 && CVal <= 4095)
7145 if (Subtarget->isThumb1Only()) {
7146 // A 32-bit value where only one byte has a nonzero value. Exclude
7147 // zero to match GCC. This constraint is used by GCC internally for
7148 // constants that can be loaded with a move/shift combination.
7149 // It is not useful otherwise but is implemented for compatibility.
7150 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7152 } else if (Subtarget->isThumb2()) {
7153 // A constant whose bitwise inverse can be used as an immediate
7154 // value in a data-processing instruction. This can be used in GCC
7155 // with a "B" modifier that prints the inverted value, for use with
7156 // BIC and MVN instructions. It is not useful otherwise but is
7157 // implemented for compatibility.
7158 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7161 // A constant whose bitwise inverse can be used as an immediate
7162 // value in a data-processing instruction. This can be used in GCC
7163 // with a "B" modifier that prints the inverted value, for use with
7164 // BIC and MVN instructions. It is not useful otherwise but is
7165 // implemented for compatibility.
7166 if (ARM_AM::getSOImmVal(~CVal) != -1)
7172 if (Subtarget->isThumb1Only()) {
7173 // This must be a constant between -7 and 7,
7174 // for 3-operand ADD/SUB immediate instructions.
7175 if (CVal >= -7 && CVal < 7)
7177 } else if (Subtarget->isThumb2()) {
7178 // A constant whose negation can be used as an immediate value in a
7179 // data-processing instruction. This can be used in GCC with an "n"
7180 // modifier that prints the negated value, for use with SUB
7181 // instructions. It is not useful otherwise but is implemented for
7183 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7186 // A constant whose negation can be used as an immediate value in a
7187 // data-processing instruction. This can be used in GCC with an "n"
7188 // modifier that prints the negated value, for use with SUB
7189 // instructions. It is not useful otherwise but is implemented for
7191 if (ARM_AM::getSOImmVal(-CVal) != -1)
7197 if (Subtarget->isThumb()) { // FIXME thumb2
7198 // This must be a multiple of 4 between 0 and 1020, for
7199 // ADD sp + immediate.
7200 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7203 // A power of two or a constant between 0 and 32. This is used in
7204 // GCC for the shift amount on shifted register operands, but it is
7205 // useful in general for any shift amounts.
7206 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7212 if (Subtarget->isThumb()) { // FIXME thumb2
7213 // This must be a constant between 0 and 31, for shift amounts.
7214 if (CVal >= 0 && CVal <= 31)
7220 if (Subtarget->isThumb()) { // FIXME thumb2
7221 // This must be a multiple of 4 between -508 and 508, for
7222 // ADD/SUB sp = sp + immediate.
7223 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7228 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7232 if (Result.getNode()) {
7233 Ops.push_back(Result);
7236 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7240 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7241 // The ARM target isn't yet aware of offsets.
7245 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7246 APInt Imm = FPImm.bitcastToAPInt();
7247 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7248 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7249 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7251 // We can handle 4 bits of mantissa.
7252 // mantissa = (16+UInt(e:f:g:h))/16.
7253 if (Mantissa & 0x7ffff)
7256 if ((Mantissa & 0xf) != Mantissa)
7259 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7260 if (Exp < -3 || Exp > 4)
7262 Exp = ((Exp+3) & 0x7) ^ 4;
7264 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7267 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7268 APInt Imm = FPImm.bitcastToAPInt();
7269 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7270 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7271 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7273 // We can handle 4 bits of mantissa.
7274 // mantissa = (16+UInt(e:f:g:h))/16.
7275 if (Mantissa & 0xffffffffffffLL)
7278 if ((Mantissa & 0xf) != Mantissa)
7281 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7282 if (Exp < -3 || Exp > 4)
7284 Exp = ((Exp+3) & 0x7) ^ 4;
7286 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7289 bool ARM::isBitFieldInvertedMask(unsigned v) {
7290 if (v == 0xffffffff)
7292 // there can be 1's on either or both "outsides", all the "inside"
7294 unsigned int lsb = 0, msb = 31;
7295 while (v & (1 << msb)) --msb;
7296 while (v & (1 << lsb)) ++lsb;
7297 for (unsigned int i = lsb; i <= msb; ++i) {
7304 /// isFPImmLegal - Returns true if the target can instruction select the
7305 /// specified FP immediate natively. If false, the legalizer will
7306 /// materialize the FP immediate as a load from a constant pool.
7307 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7308 if (!Subtarget->hasVFP3())
7311 return ARM::getVFPf32Imm(Imm) != -1;
7313 return ARM::getVFPf64Imm(Imm) != -1;
7317 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7318 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7319 /// specified in the intrinsic calls.
7320 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7322 unsigned Intrinsic) const {
7323 switch (Intrinsic) {
7324 case Intrinsic::arm_neon_vld1:
7325 case Intrinsic::arm_neon_vld2:
7326 case Intrinsic::arm_neon_vld3:
7327 case Intrinsic::arm_neon_vld4:
7328 case Intrinsic::arm_neon_vld2lane:
7329 case Intrinsic::arm_neon_vld3lane:
7330 case Intrinsic::arm_neon_vld4lane: {
7331 Info.opc = ISD::INTRINSIC_W_CHAIN;
7332 // Conservatively set memVT to the entire set of vectors loaded.
7333 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7334 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7335 Info.ptrVal = I.getArgOperand(0);
7337 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7338 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7339 Info.vol = false; // volatile loads with NEON intrinsics not supported
7340 Info.readMem = true;
7341 Info.writeMem = false;
7344 case Intrinsic::arm_neon_vst1:
7345 case Intrinsic::arm_neon_vst2:
7346 case Intrinsic::arm_neon_vst3:
7347 case Intrinsic::arm_neon_vst4:
7348 case Intrinsic::arm_neon_vst2lane:
7349 case Intrinsic::arm_neon_vst3lane:
7350 case Intrinsic::arm_neon_vst4lane: {
7351 Info.opc = ISD::INTRINSIC_VOID;
7352 // Conservatively set memVT to the entire set of vectors stored.
7353 unsigned NumElts = 0;
7354 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7355 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7356 if (!ArgTy->isVectorTy())
7358 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7360 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7361 Info.ptrVal = I.getArgOperand(0);
7363 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7364 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7365 Info.vol = false; // volatile stores with NEON intrinsics not supported
7366 Info.readMem = false;
7367 Info.writeMem = true;