1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/VectorExtras.h"
36 #include "llvm/Support/MathExtras.h"
39 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM), ARMPCLabelIndex(0) {
41 Subtarget = &TM.getSubtarget<ARMSubtarget>();
43 if (Subtarget->isTargetDarwin()) {
44 // Uses VFP for Thumb libfuncs if available.
45 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
46 // Single-precision floating-point arithmetic.
47 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
48 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
49 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
50 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
52 // Double-precision floating-point arithmetic.
53 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
54 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
55 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
56 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
58 // Single-precision comparisons.
59 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
60 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
61 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
62 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
63 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
64 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
65 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
66 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
68 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
69 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
70 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
71 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
72 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
77 // Double-precision comparisons.
78 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
79 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
80 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
81 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
82 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
83 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
84 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
85 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
87 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
88 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
89 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
96 // Floating-point to integer conversions.
97 // i64 conversions are done via library routines even when generating VFP
98 // instructions, so use the same ones.
99 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
100 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
101 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
102 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
104 // Conversions between floating types.
105 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
106 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
108 // Integer to floating-point conversions.
109 // i64 conversions are done via library routines even when generating VFP
110 // instructions, so use the same ones.
111 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
112 // __floatunsidf vs. __floatunssidfvfp.
113 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
114 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
115 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
116 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
120 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
121 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
122 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
123 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
125 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
127 computeRegisterProperties();
129 // ARM does not have f32 extending load.
130 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
132 // ARM does not have i1 sign extending load.
133 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
135 // ARM supports all 4 flavors of integer indexed load / store.
136 for (unsigned im = (unsigned)ISD::PRE_INC;
137 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
138 setIndexedLoadAction(im, MVT::i1, Legal);
139 setIndexedLoadAction(im, MVT::i8, Legal);
140 setIndexedLoadAction(im, MVT::i16, Legal);
141 setIndexedLoadAction(im, MVT::i32, Legal);
142 setIndexedStoreAction(im, MVT::i1, Legal);
143 setIndexedStoreAction(im, MVT::i8, Legal);
144 setIndexedStoreAction(im, MVT::i16, Legal);
145 setIndexedStoreAction(im, MVT::i32, Legal);
148 // i64 operation support.
149 if (Subtarget->isThumb()) {
150 setOperationAction(ISD::MUL, MVT::i64, Expand);
151 setOperationAction(ISD::MULHU, MVT::i32, Expand);
152 setOperationAction(ISD::MULHS, MVT::i32, Expand);
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
156 setOperationAction(ISD::MUL, MVT::i64, Expand);
157 setOperationAction(ISD::MULHU, MVT::i32, Expand);
158 if (!Subtarget->hasV6Ops())
159 setOperationAction(ISD::MULHS, MVT::i32, Expand);
161 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
162 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
163 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
164 setOperationAction(ISD::SRL, MVT::i64, Custom);
165 setOperationAction(ISD::SRA, MVT::i64, Custom);
167 // ARM does not have ROTL.
168 setOperationAction(ISD::ROTL, MVT::i32, Expand);
169 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
170 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
171 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
172 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
174 // Only ARMv6 has BSWAP.
175 if (!Subtarget->hasV6Ops())
176 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
178 // These are expanded into libcalls.
179 setOperationAction(ISD::SDIV, MVT::i32, Expand);
180 setOperationAction(ISD::UDIV, MVT::i32, Expand);
181 setOperationAction(ISD::SREM, MVT::i32, Expand);
182 setOperationAction(ISD::UREM, MVT::i32, Expand);
183 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
184 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
186 // Support label based line numbers.
187 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
188 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
190 setOperationAction(ISD::RET, MVT::Other, Custom);
191 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
192 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
193 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
196 // Use the default implementation.
197 setOperationAction(ISD::VASTART , MVT::Other, Custom);
198 setOperationAction(ISD::VAARG , MVT::Other, Expand);
199 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
200 setOperationAction(ISD::VAEND , MVT::Other, Expand);
201 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
202 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
203 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
204 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
206 if (!Subtarget->hasV6Ops()) {
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
210 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
212 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
213 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
214 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
216 // We want to custom lower some of our intrinsics.
217 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
219 setOperationAction(ISD::SETCC , MVT::i32, Expand);
220 setOperationAction(ISD::SETCC , MVT::f32, Expand);
221 setOperationAction(ISD::SETCC , MVT::f64, Expand);
222 setOperationAction(ISD::SELECT , MVT::i32, Expand);
223 setOperationAction(ISD::SELECT , MVT::f32, Expand);
224 setOperationAction(ISD::SELECT , MVT::f64, Expand);
225 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
226 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
227 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
229 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
230 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
231 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
232 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
233 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
235 // We don't support sin/cos/fmod/copysign/pow
236 setOperationAction(ISD::FSIN , MVT::f64, Expand);
237 setOperationAction(ISD::FSIN , MVT::f32, Expand);
238 setOperationAction(ISD::FCOS , MVT::f32, Expand);
239 setOperationAction(ISD::FCOS , MVT::f64, Expand);
240 setOperationAction(ISD::FREM , MVT::f64, Expand);
241 setOperationAction(ISD::FREM , MVT::f32, Expand);
242 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
243 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
246 setOperationAction(ISD::FPOW , MVT::f64, Expand);
247 setOperationAction(ISD::FPOW , MVT::f32, Expand);
249 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
250 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
251 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
252 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
257 // We have target-specific dag combine patterns for the following nodes:
258 // ARMISD::FMRRD - No need to call setTargetDAGCombine
260 setStackPointerRegisterToSaveRestore(ARM::SP);
261 setSchedulingPreference(SchedulingForRegPressure);
262 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
263 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
265 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
269 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
272 case ARMISD::Wrapper: return "ARMISD::Wrapper";
273 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
274 case ARMISD::CALL: return "ARMISD::CALL";
275 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
276 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
277 case ARMISD::tCALL: return "ARMISD::tCALL";
278 case ARMISD::BRCOND: return "ARMISD::BRCOND";
279 case ARMISD::BR_JT: return "ARMISD::BR_JT";
280 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
281 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
282 case ARMISD::CMP: return "ARMISD::CMP";
283 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
284 case ARMISD::CMPFP: return "ARMISD::CMPFP";
285 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
286 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
287 case ARMISD::CMOV: return "ARMISD::CMOV";
288 case ARMISD::CNEG: return "ARMISD::CNEG";
290 case ARMISD::FTOSI: return "ARMISD::FTOSI";
291 case ARMISD::FTOUI: return "ARMISD::FTOUI";
292 case ARMISD::SITOF: return "ARMISD::SITOF";
293 case ARMISD::UITOF: return "ARMISD::UITOF";
295 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
296 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
297 case ARMISD::RRX: return "ARMISD::RRX";
299 case ARMISD::FMRRD: return "ARMISD::FMRRD";
300 case ARMISD::FMDRR: return "ARMISD::FMDRR";
302 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
306 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
311 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
312 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
314 default: assert(0 && "Unknown condition code!");
315 case ISD::SETNE: return ARMCC::NE;
316 case ISD::SETEQ: return ARMCC::EQ;
317 case ISD::SETGT: return ARMCC::GT;
318 case ISD::SETGE: return ARMCC::GE;
319 case ISD::SETLT: return ARMCC::LT;
320 case ISD::SETLE: return ARMCC::LE;
321 case ISD::SETUGT: return ARMCC::HI;
322 case ISD::SETUGE: return ARMCC::HS;
323 case ISD::SETULT: return ARMCC::LO;
324 case ISD::SETULE: return ARMCC::LS;
328 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
329 /// returns true if the operands should be inverted to form the proper
331 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
332 ARMCC::CondCodes &CondCode2) {
334 CondCode2 = ARMCC::AL;
336 default: assert(0 && "Unknown FP condition!");
338 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
340 case ISD::SETOGT: CondCode = ARMCC::GT; break;
342 case ISD::SETOGE: CondCode = ARMCC::GE; break;
343 case ISD::SETOLT: CondCode = ARMCC::MI; break;
344 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
345 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
346 case ISD::SETO: CondCode = ARMCC::VC; break;
347 case ISD::SETUO: CondCode = ARMCC::VS; break;
348 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
349 case ISD::SETUGT: CondCode = ARMCC::HI; break;
350 case ISD::SETUGE: CondCode = ARMCC::PL; break;
352 case ISD::SETULT: CondCode = ARMCC::LT; break;
354 case ISD::SETULE: CondCode = ARMCC::LE; break;
356 case ISD::SETUNE: CondCode = ARMCC::NE; break;
362 HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
363 unsigned StackOffset, unsigned &NeededGPRs,
364 unsigned &NeededStackSize, unsigned &GPRPad,
365 unsigned &StackPad, ISD::ArgFlagsTy Flags) {
370 unsigned align = Flags.getOrigAlign();
371 GPRPad = NumGPRs % ((align + 3)/4);
372 StackPad = StackOffset % align;
373 unsigned firstGPR = NumGPRs + GPRPad;
374 switch (ObjectVT.getSimpleVT()) {
375 default: assert(0 && "Unhandled argument type!");
387 else if (firstGPR == 3) {
395 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
396 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
398 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
399 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
400 MVT RetVT = TheCall->getRetValType(0);
401 SDValue Chain = TheCall->getChain();
402 assert((TheCall->getCallingConv() == CallingConv::C ||
403 TheCall->getCallingConv() == CallingConv::Fast) &&
404 "unknown calling convention");
405 SDValue Callee = TheCall->getCallee();
406 unsigned NumOps = TheCall->getNumArgs();
407 DebugLoc dl = TheCall->getDebugLoc();
408 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
409 unsigned NumGPRs = 0; // GPRs used for parameter passing.
411 // Count how many bytes are to be pushed on the stack.
412 unsigned NumBytes = 0;
414 // Add up all the space actually used.
415 for (unsigned i = 0; i < NumOps; ++i) {
420 MVT ObjectVT = TheCall->getArg(i).getValueType();
421 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
422 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
423 GPRPad, StackPad, Flags);
424 NumBytes += ObjSize + StackPad;
425 NumGPRs += ObjGPRs + GPRPad;
428 // Adjust the stack pointer for the new arguments...
429 // These operations are automatically eliminated by the prolog/epilog pass
430 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
432 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
434 static const unsigned GPRArgRegs[] = {
435 ARM::R0, ARM::R1, ARM::R2, ARM::R3
439 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
440 std::vector<SDValue> MemOpChains;
441 for (unsigned i = 0; i != NumOps; ++i) {
442 SDValue Arg = TheCall->getArg(i);
443 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
444 MVT ArgVT = Arg.getValueType();
450 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
451 ObjSize, GPRPad, StackPad, Flags);
453 ArgOffset += StackPad;
455 switch (ArgVT.getSimpleVT()) {
456 default: assert(0 && "Unexpected ValueType for argument!");
458 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
461 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
462 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg)));
465 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
466 DAG.getConstant(0, getPointerTy()));
467 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
468 DAG.getConstant(1, getPointerTy()));
469 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
471 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
473 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
474 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
475 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, NULL, 0));
480 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
481 DAG.getVTList(MVT::i32, MVT::i32),
483 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
485 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
488 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
489 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
490 MemOpChains.push_back(DAG.getStore(Chain, dl, Cvt.getValue(1), PtrOff,
497 assert(ObjSize != 0);
498 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
499 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
500 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
504 ArgOffset += ObjSize;
507 if (!MemOpChains.empty())
508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
509 &MemOpChains[0], MemOpChains.size());
511 // Build a sequence of copy-to-reg nodes chained together with token chain
512 // and flag operands which copy the outgoing args into the appropriate regs.
514 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
515 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
516 RegsToPass[i].second, InFlag);
517 InFlag = Chain.getValue(1);
520 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
521 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
522 // node so that legalize doesn't hack it.
523 bool isDirect = false;
524 bool isARMFunc = false;
525 bool isLocalARMFunc = false;
526 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
527 GlobalValue *GV = G->getGlobal();
529 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
530 GV->hasLinkOnceLinkage());
531 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
532 getTargetMachine().getRelocationModel() != Reloc::Static;
533 isARMFunc = !Subtarget->isThumb() || isStub;
534 // ARM call to a local ARM function is predicable.
535 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
536 // tBX takes a register source operand.
537 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
538 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
540 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
541 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
542 Callee = DAG.getLoad(getPointerTy(), dl,
543 DAG.getEntryNode(), CPAddr, NULL, 0);
544 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
545 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
546 getPointerTy(), Callee, PICLabel);
548 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
549 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
551 bool isStub = Subtarget->isTargetDarwin() &&
552 getTargetMachine().getRelocationModel() != Reloc::Static;
553 isARMFunc = !Subtarget->isThumb() || isStub;
554 // tBX takes a register source operand.
555 const char *Sym = S->getSymbol();
556 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
557 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
559 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
560 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
561 Callee = DAG.getLoad(getPointerTy(), dl,
562 DAG.getEntryNode(), CPAddr, NULL, 0);
563 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
564 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
565 getPointerTy(), Callee, PICLabel);
567 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
570 // FIXME: handle tail calls differently.
572 if (Subtarget->isThumb()) {
573 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
574 CallOpc = ARMISD::CALL_NOLINK;
576 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
578 CallOpc = (isDirect || Subtarget->hasV5TOps())
579 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
580 : ARMISD::CALL_NOLINK;
582 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
583 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
584 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR,
585 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
586 InFlag = Chain.getValue(1);
589 std::vector<SDValue> Ops;
590 Ops.push_back(Chain);
591 Ops.push_back(Callee);
593 // Add argument registers to the end of the list so that they are known live
595 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
596 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
597 RegsToPass[i].second.getValueType()));
599 if (InFlag.getNode())
600 Ops.push_back(InFlag);
601 // Returns a chain and a flag for retval copy to use.
602 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
603 &Ops[0], Ops.size());
604 InFlag = Chain.getValue(1);
606 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
607 DAG.getIntPtrConstant(0, true), InFlag);
608 if (RetVT != MVT::Other)
609 InFlag = Chain.getValue(1);
611 std::vector<SDValue> ResultVals;
613 // If the call has results, copy the values out of the ret val registers.
614 switch (RetVT.getSimpleVT()) {
615 default: assert(0 && "Unexpected ret value!");
619 Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0,
620 MVT::i32, InFlag).getValue(1);
621 ResultVals.push_back(Chain.getValue(0));
622 if (TheCall->getNumRetVals() > 1 &&
623 TheCall->getRetValType(1) == MVT::i32) {
624 // Returns a i64 value.
625 Chain = DAG.getCopyFromReg(Chain, dl, ARM::R1, MVT::i32,
626 Chain.getValue(2)).getValue(1);
627 ResultVals.push_back(Chain.getValue(0));
631 Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0,
632 MVT::i32, InFlag).getValue(1);
633 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32,
637 SDValue Lo = DAG.getCopyFromReg(Chain, dl, ARM::R0, MVT::i32, InFlag);
638 SDValue Hi = DAG.getCopyFromReg(Lo, dl, ARM::R1, MVT::i32, Lo.getValue(2));
639 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi));
644 if (ResultVals.empty())
647 ResultVals.push_back(Chain);
648 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
649 return Res.getValue(Op.getResNo());
652 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
654 SDValue Chain = Op.getOperand(0);
655 DebugLoc dl = Op.getDebugLoc();
656 switch(Op.getNumOperands()) {
658 assert(0 && "Do not know how to return this many arguments!");
661 SDValue LR = DAG.getRegister(ARM::LR, MVT::i32);
662 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
665 Op = Op.getOperand(1);
666 if (Op.getValueType() == MVT::f32) {
667 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
668 } else if (Op.getValueType() == MVT::f64) {
669 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
671 Op = DAG.getNode(ARMISD::FMRRD, dl,
672 DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
673 SDValue Sign = DAG.getConstant(0, MVT::i32);
674 return DAG.getNode(ISD::RET, dl, MVT::Other, Chain, Op, Sign,
675 Op.getValue(1), Sign);
677 Copy = DAG.getCopyToReg(Chain, dl, ARM::R0, Op, SDValue());
678 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
679 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
682 Copy = DAG.getCopyToReg(Chain, dl, ARM::R1, Op.getOperand(3), SDValue());
683 Copy = DAG.getCopyToReg(Copy, dl, ARM::R0, Op.getOperand(1),
685 // If we haven't noted the R0+R1 are live out, do so now.
686 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
687 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
688 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
691 case 9: // i128 -> 4 regs
692 Copy = DAG.getCopyToReg(Chain, dl, ARM::R3, Op.getOperand(7), SDValue());
693 Copy = DAG.getCopyToReg(Copy , dl, ARM::R2, Op.getOperand(5),
695 Copy = DAG.getCopyToReg(Copy , dl, ARM::R1, Op.getOperand(3),
697 Copy = DAG.getCopyToReg(Copy , dl, ARM::R0, Op.getOperand(1),
699 // If we haven't noted the R0+R1 are live out, do so now.
700 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
701 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
702 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
703 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2);
704 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3);
710 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
711 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Copy, Copy.getValue(1));
714 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
715 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
716 // one of the above mentioned nodes. It has to be wrapped because otherwise
717 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
718 // be used to form addressing mode. These wrapped nodes will be selected
720 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
721 MVT PtrVT = Op.getValueType();
722 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
724 if (CP->isMachineConstantPoolEntry())
725 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
728 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
730 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
733 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
735 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
737 DebugLoc dl = GA->getDebugLoc();
738 MVT PtrVT = getPointerTy();
739 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
740 ARMConstantPoolValue *CPV =
741 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
742 PCAdj, "tlsgd", true);
743 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
744 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
745 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
746 SDValue Chain = Argument.getValue(1);
748 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
749 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
751 // call __tls_get_addr.
754 Entry.Node = Argument;
755 Entry.Ty = (const Type *) Type::Int32Ty;
756 Args.push_back(Entry);
757 // FIXME: is there useful debug info available here?
758 std::pair<SDValue, SDValue> CallResult =
759 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
760 CallingConv::C, false,
761 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
762 return CallResult.first;
765 // Lower ISD::GlobalTLSAddress using the "initial exec" or
766 // "local exec" model.
768 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
770 GlobalValue *GV = GA->getGlobal();
771 DebugLoc dl = GA->getDebugLoc();
773 SDValue Chain = DAG.getEntryNode();
774 MVT PtrVT = getPointerTy();
775 // Get the Thread Pointer
776 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
778 if (GV->isDeclaration()){
779 // initial exec model
780 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
781 ARMConstantPoolValue *CPV =
782 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
783 PCAdj, "gottpoff", true);
784 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
785 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
786 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
787 Chain = Offset.getValue(1);
789 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
790 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
792 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
795 ARMConstantPoolValue *CPV =
796 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
797 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
798 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
799 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
802 // The address of the thread local variable is the add of the thread
803 // pointer with the offset of the variable.
804 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
808 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
809 // TODO: implement the "local dynamic" model
810 assert(Subtarget->isTargetELF() &&
811 "TLS not implemented for non-ELF targets");
812 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
813 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
814 // otherwise use the "Local Exec" TLS Model
815 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
816 return LowerToTLSGeneralDynamicModel(GA, DAG);
818 return LowerToTLSExecModels(GA, DAG);
821 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
823 MVT PtrVT = getPointerTy();
824 DebugLoc dl = Op.getDebugLoc();
825 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
826 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
827 if (RelocM == Reloc::PIC_) {
828 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
829 ARMConstantPoolValue *CPV =
830 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
831 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
832 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
833 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
835 SDValue Chain = Result.getValue(1);
836 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
837 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
839 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
842 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
843 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
844 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
848 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
849 /// even in non-static mode.
850 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
851 // If symbol visibility is hidden, the extra load is not needed if
852 // the symbol is definitely defined in the current translation unit.
853 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
854 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
856 return RelocM != Reloc::Static && (isDecl || GV->mayBeOverridden());
859 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
861 MVT PtrVT = getPointerTy();
862 DebugLoc dl = Op.getDebugLoc();
863 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
864 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
865 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
867 if (RelocM == Reloc::Static)
868 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
870 unsigned PCAdj = (RelocM != Reloc::PIC_)
871 ? 0 : (Subtarget->isThumb() ? 4 : 8);
872 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
874 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
876 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
878 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
880 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
881 SDValue Chain = Result.getValue(1);
883 if (RelocM == Reloc::PIC_) {
884 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
885 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
888 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
893 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
895 assert(Subtarget->isTargetELF() &&
896 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
897 MVT PtrVT = getPointerTy();
898 DebugLoc dl = Op.getDebugLoc();
899 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
900 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
902 ARMCP::CPValue, PCAdj);
903 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
904 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
905 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
906 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
907 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
910 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
911 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
912 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
914 default: return SDValue(); // Don't custom lower most intrinsics.
915 case Intrinsic::arm_thread_pointer:
916 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
920 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
921 unsigned VarArgsFrameIndex) {
922 // vastart just stores the address of the VarArgsFrameIndex slot into the
923 // memory location argument.
924 DebugLoc dl = Op.getDebugLoc();
925 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
926 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
927 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
928 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
931 static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG,
932 unsigned ArgNo, unsigned &NumGPRs,
933 unsigned &ArgOffset, DebugLoc dl) {
934 MachineFunction &MF = DAG.getMachineFunction();
935 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
936 SDValue Root = Op.getOperand(0);
937 MachineRegisterInfo &RegInfo = MF.getRegInfo();
939 static const unsigned GPRArgRegs[] = {
940 ARM::R0, ARM::R1, ARM::R2, ARM::R3
947 ISD::ArgFlagsTy Flags =
948 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags();
949 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
950 ObjSize, GPRPad, StackPad, Flags);
952 ArgOffset += StackPad;
956 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
957 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
958 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
959 if (ObjectVT == MVT::f32)
960 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
961 } else if (ObjGPRs == 2) {
962 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
963 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
964 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
966 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
967 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
968 SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
970 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
971 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
976 MachineFrameInfo *MFI = MF.getFrameInfo();
977 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
978 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
980 ArgValue = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
982 SDValue ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
983 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
984 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
987 ArgOffset += ObjSize; // Move on to the next argument.
994 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
995 std::vector<SDValue> ArgValues;
996 SDValue Root = Op.getOperand(0);
997 DebugLoc dl = Op.getDebugLoc();
998 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
999 unsigned NumGPRs = 0; // GPRs used for parameter passing.
1001 unsigned NumArgs = Op.getNode()->getNumValues()-1;
1002 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
1003 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
1004 NumGPRs, ArgOffset, dl));
1006 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1008 static const unsigned GPRArgRegs[] = {
1009 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1012 MachineFunction &MF = DAG.getMachineFunction();
1013 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1014 MachineFrameInfo *MFI = MF.getFrameInfo();
1015 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1016 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1017 unsigned VARegSize = (4 - NumGPRs) * 4;
1018 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1019 if (VARegSaveSize) {
1020 // If this function is vararg, store any remaining integer argument regs
1021 // to their spots on the stack so that they may be loaded by deferencing
1022 // the result of va_next.
1023 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1024 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1025 VARegSaveSize - VARegSize);
1026 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1028 SmallVector<SDValue, 4> MemOps;
1029 for (; NumGPRs < 4; ++NumGPRs) {
1030 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1031 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1032 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1033 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1034 MemOps.push_back(Store);
1035 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1036 DAG.getConstant(4, getPointerTy()));
1038 if (!MemOps.empty())
1039 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1040 &MemOps[0], MemOps.size());
1042 // This will point to the next argument passed via stack.
1043 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1046 ArgValues.push_back(Root);
1048 // Return the new list of results.
1049 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1050 &ArgValues[0], ArgValues.size());
1053 /// isFloatingPointZero - Return true if this is +0.0.
1054 static bool isFloatingPointZero(SDValue Op) {
1055 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1056 return CFP->getValueAPF().isPosZero();
1057 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1058 // Maybe this has already been legalized into the constant pool?
1059 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1060 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1061 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1062 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1063 return CFP->getValueAPF().isPosZero();
1069 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1070 return ( isThumb && (C & ~255U) == 0) ||
1071 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1074 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1075 /// the given operands.
1076 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1077 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1079 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1080 unsigned C = RHSC->getZExtValue();
1081 if (!isLegalCmpImmediate(C, isThumb)) {
1082 // Constant does not fit, try adjusting it by one?
1087 if (isLegalCmpImmediate(C-1, isThumb)) {
1088 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1089 RHS = DAG.getConstant(C-1, MVT::i32);
1094 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1095 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1096 RHS = DAG.getConstant(C-1, MVT::i32);
1101 if (isLegalCmpImmediate(C+1, isThumb)) {
1102 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1103 RHS = DAG.getConstant(C+1, MVT::i32);
1108 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1109 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1110 RHS = DAG.getConstant(C+1, MVT::i32);
1117 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1118 ARMISD::NodeType CompareType;
1121 CompareType = ARMISD::CMP;
1127 // Uses only N and Z Flags
1128 CompareType = ARMISD::CMPNZ;
1131 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1132 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1135 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1136 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1139 if (!isFloatingPointZero(RHS))
1140 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1142 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1143 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1146 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1147 const ARMSubtarget *ST) {
1148 MVT VT = Op.getValueType();
1149 SDValue LHS = Op.getOperand(0);
1150 SDValue RHS = Op.getOperand(1);
1151 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1152 SDValue TrueVal = Op.getOperand(2);
1153 SDValue FalseVal = Op.getOperand(3);
1154 DebugLoc dl = Op.getDebugLoc();
1156 if (LHS.getValueType() == MVT::i32) {
1158 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1159 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1160 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1163 ARMCC::CondCodes CondCode, CondCode2;
1164 if (FPCCToARMCC(CC, CondCode, CondCode2))
1165 std::swap(TrueVal, FalseVal);
1167 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1168 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1169 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1170 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1172 if (CondCode2 != ARMCC::AL) {
1173 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1174 // FIXME: Needs another CMP because flag can have but one use.
1175 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1176 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1177 Result, TrueVal, ARMCC2, CCR, Cmp2);
1182 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1183 const ARMSubtarget *ST) {
1184 SDValue Chain = Op.getOperand(0);
1185 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1186 SDValue LHS = Op.getOperand(2);
1187 SDValue RHS = Op.getOperand(3);
1188 SDValue Dest = Op.getOperand(4);
1189 DebugLoc dl = Op.getDebugLoc();
1191 if (LHS.getValueType() == MVT::i32) {
1193 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1194 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1195 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1196 Chain, Dest, ARMCC, CCR,Cmp);
1199 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1200 ARMCC::CondCodes CondCode, CondCode2;
1201 if (FPCCToARMCC(CC, CondCode, CondCode2))
1202 // Swap the LHS/RHS of the comparison if needed.
1203 std::swap(LHS, RHS);
1205 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1206 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1207 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1208 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1209 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1210 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1211 if (CondCode2 != ARMCC::AL) {
1212 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1213 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1214 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1219 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1220 SDValue Chain = Op.getOperand(0);
1221 SDValue Table = Op.getOperand(1);
1222 SDValue Index = Op.getOperand(2);
1223 DebugLoc dl = Op.getDebugLoc();
1225 MVT PTy = getPointerTy();
1226 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1227 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1228 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1229 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1230 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1231 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1232 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1233 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1234 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1235 Chain, Addr, NULL, 0);
1236 Chain = Addr.getValue(1);
1238 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1239 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1242 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1243 DebugLoc dl = Op.getDebugLoc();
1245 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1246 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1247 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1250 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1251 MVT VT = Op.getValueType();
1252 DebugLoc dl = Op.getDebugLoc();
1254 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1256 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1257 return DAG.getNode(Opc, dl, VT, Op);
1260 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1261 // Implement fcopysign with a fabs and a conditional fneg.
1262 SDValue Tmp0 = Op.getOperand(0);
1263 SDValue Tmp1 = Op.getOperand(1);
1264 DebugLoc dl = Op.getDebugLoc();
1265 MVT VT = Op.getValueType();
1266 MVT SrcVT = Tmp1.getValueType();
1267 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1268 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1269 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1270 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1271 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1275 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1277 SDValue Dst, SDValue Src,
1278 SDValue Size, unsigned Align,
1280 const Value *DstSV, uint64_t DstSVOff,
1281 const Value *SrcSV, uint64_t SrcSVOff){
1282 // Do repeated 4-byte loads and stores. To be improved.
1283 // This requires 4-byte alignment.
1284 if ((Align & 3) != 0)
1286 // This requires the copy size to be a constant, preferrably
1287 // within a subtarget-specific limit.
1288 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1291 uint64_t SizeVal = ConstantSize->getZExtValue();
1292 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1295 unsigned BytesLeft = SizeVal & 3;
1296 unsigned NumMemOps = SizeVal >> 2;
1297 unsigned EmittedNumMemOps = 0;
1299 unsigned VTSize = 4;
1301 const unsigned MAX_LOADS_IN_LDM = 6;
1302 SDValue TFOps[MAX_LOADS_IN_LDM];
1303 SDValue Loads[MAX_LOADS_IN_LDM];
1304 uint64_t SrcOff = 0, DstOff = 0;
1306 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1307 // same number of stores. The loads and stores will get combined into
1308 // ldm/stm later on.
1309 while (EmittedNumMemOps < NumMemOps) {
1311 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1312 Loads[i] = DAG.getLoad(VT, dl, Chain,
1313 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1314 DAG.getConstant(SrcOff, MVT::i32)),
1315 SrcSV, SrcSVOff + SrcOff);
1316 TFOps[i] = Loads[i].getValue(1);
1319 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1322 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1323 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1324 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1325 DAG.getConstant(DstOff, MVT::i32)),
1326 DstSV, DstSVOff + DstOff);
1329 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1331 EmittedNumMemOps += i;
1337 // Issue loads / stores for the trailing (1 - 3) bytes.
1338 unsigned BytesLeftSave = BytesLeft;
1341 if (BytesLeft >= 2) {
1349 Loads[i] = DAG.getLoad(VT, dl, Chain,
1350 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1351 DAG.getConstant(SrcOff, MVT::i32)),
1352 SrcSV, SrcSVOff + SrcOff);
1353 TFOps[i] = Loads[i].getValue(1);
1356 BytesLeft -= VTSize;
1358 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1361 BytesLeft = BytesLeftSave;
1363 if (BytesLeft >= 2) {
1371 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1372 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1373 DAG.getConstant(DstOff, MVT::i32)),
1374 DstSV, DstSVOff + DstOff);
1377 BytesLeft -= VTSize;
1379 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1382 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1383 SDValue Op = N->getOperand(0);
1384 DebugLoc dl = N->getDebugLoc();
1385 if (N->getValueType(0) == MVT::f64) {
1386 // Turn i64->f64 into FMDRR.
1387 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1388 DAG.getConstant(0, MVT::i32));
1389 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1390 DAG.getConstant(1, MVT::i32));
1391 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1394 // Turn f64->i64 into FMRRD.
1395 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1396 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1398 // Merge the pieces into a single i64 value.
1399 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1402 static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1403 assert(N->getValueType(0) == MVT::i64 &&
1404 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1405 "Unknown shift to lower!");
1407 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1408 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1409 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1412 // If we are in thumb mode, we don't have RRX.
1413 if (ST->isThumb()) return SDValue();
1415 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1416 DebugLoc dl = N->getDebugLoc();
1417 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1418 DAG.getConstant(0, MVT::i32));
1419 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1420 DAG.getConstant(1, MVT::i32));
1422 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1423 // captures the result into a carry flag.
1424 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1425 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1427 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1428 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1430 // Merge the pieces into a single i64 value.
1431 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1435 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1436 switch (Op.getOpcode()) {
1437 default: assert(0 && "Don't know how to custom lower this!"); abort();
1438 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1439 case ISD::GlobalAddress:
1440 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1441 LowerGlobalAddressELF(Op, DAG);
1442 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1443 case ISD::CALL: return LowerCALL(Op, DAG);
1444 case ISD::RET: return LowerRET(Op, DAG);
1445 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1446 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1447 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1448 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1449 case ISD::SINT_TO_FP:
1450 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1451 case ISD::FP_TO_SINT:
1452 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1453 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1454 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1455 case ISD::RETURNADDR: break;
1456 case ISD::FRAMEADDR: break;
1457 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1458 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1459 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
1461 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget);
1467 /// ReplaceNodeResults - Replace the results of node with an illegal result
1468 /// type with new values built out of custom code.
1470 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
1471 SmallVectorImpl<SDValue>&Results,
1472 SelectionDAG &DAG) {
1473 switch (N->getOpcode()) {
1475 assert(0 && "Don't know how to custom expand this!");
1477 case ISD::BIT_CONVERT:
1478 Results.push_back(ExpandBIT_CONVERT(N, DAG));
1482 SDValue Res = ExpandSRx(N, DAG, Subtarget);
1484 Results.push_back(Res);
1491 //===----------------------------------------------------------------------===//
1492 // ARM Scheduler Hooks
1493 //===----------------------------------------------------------------------===//
1496 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1497 MachineBasicBlock *BB) {
1498 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1499 switch (MI->getOpcode()) {
1500 default: assert(false && "Unexpected instr type to insert");
1501 case ARM::tMOVCCr: {
1502 // To "insert" a SELECT_CC instruction, we actually have to insert the
1503 // diamond control-flow pattern. The incoming instruction knows the
1504 // destination vreg to set, the condition code register to branch on, the
1505 // true/false values to select between, and a branch opcode to use.
1506 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1507 MachineFunction::iterator It = BB;
1513 // cmpTY ccX, r1, r2
1515 // fallthrough --> copy0MBB
1516 MachineBasicBlock *thisMBB = BB;
1517 MachineFunction *F = BB->getParent();
1518 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1519 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1520 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1521 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1522 F->insert(It, copy0MBB);
1523 F->insert(It, sinkMBB);
1524 // Update machine-CFG edges by first adding all successors of the current
1525 // block to the new block which will contain the Phi node for the select.
1526 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1527 e = BB->succ_end(); i != e; ++i)
1528 sinkMBB->addSuccessor(*i);
1529 // Next, remove all successors of the current block, and add the true
1530 // and fallthrough blocks as its successors.
1531 while(!BB->succ_empty())
1532 BB->removeSuccessor(BB->succ_begin());
1533 BB->addSuccessor(copy0MBB);
1534 BB->addSuccessor(sinkMBB);
1537 // %FalseValue = ...
1538 // # fallthrough to sinkMBB
1541 // Update machine-CFG edges
1542 BB->addSuccessor(sinkMBB);
1545 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1548 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1549 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1550 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1552 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1558 //===----------------------------------------------------------------------===//
1559 // ARM Optimization Hooks
1560 //===----------------------------------------------------------------------===//
1562 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1563 static SDValue PerformFMRRDCombine(SDNode *N,
1564 TargetLowering::DAGCombinerInfo &DCI) {
1565 // fmrrd(fmdrr x, y) -> x,y
1566 SDValue InDouble = N->getOperand(0);
1567 if (InDouble.getOpcode() == ARMISD::FMDRR)
1568 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1572 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1573 DAGCombinerInfo &DCI) const {
1574 switch (N->getOpcode()) {
1576 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1583 /// isLegalAddressImmediate - Return true if the integer value can be used
1584 /// as the offset of the target addressing mode for load / store of the
1586 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1587 const ARMSubtarget *Subtarget) {
1591 if (Subtarget->isThumb()) {
1596 switch (VT.getSimpleVT()) {
1597 default: return false;
1612 if ((V & (Scale - 1)) != 0)
1615 return V == (V & ((1LL << 5) - 1));
1620 switch (VT.getSimpleVT()) {
1621 default: return false;
1626 return V == (V & ((1LL << 12) - 1));
1629 return V == (V & ((1LL << 8) - 1));
1632 if (!Subtarget->hasVFP2())
1637 return V == (V & ((1LL << 8) - 1));
1641 /// isLegalAddressingMode - Return true if the addressing mode represented
1642 /// by AM is legal for this target, for a load/store of the specified type.
1643 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1644 const Type *Ty) const {
1645 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget))
1648 // Can never fold addr of global into load/store.
1653 case 0: // no scale reg, must be "r+i" or "r", or "i".
1656 if (Subtarget->isThumb())
1660 // ARM doesn't support any R+R*scale+imm addr modes.
1664 int Scale = AM.Scale;
1665 switch (getValueType(Ty).getSimpleVT()) {
1666 default: return false;
1671 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1672 // ldrd / strd are used, then its address mode is same as i16.
1674 if (Scale < 0) Scale = -Scale;
1678 return isPowerOf2_32(Scale & ~1);
1681 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1686 // Note, we allow "void" uses (basically, uses that aren't loads or
1687 // stores), because arm allows folding a scale into many arithmetic
1688 // operations. This should be made more precise and revisited later.
1690 // Allow r << imm, but the imm has to be a multiple of two.
1691 if (AM.Scale & 1) return false;
1692 return isPowerOf2_32(AM.Scale);
1700 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1701 bool isSEXTLoad, SDValue &Base,
1702 SDValue &Offset, bool &isInc,
1703 SelectionDAG &DAG) {
1704 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1707 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1709 Base = Ptr->getOperand(0);
1710 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1711 int RHSC = (int)RHS->getZExtValue();
1712 if (RHSC < 0 && RHSC > -256) {
1714 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1718 isInc = (Ptr->getOpcode() == ISD::ADD);
1719 Offset = Ptr->getOperand(1);
1721 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1723 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1724 int RHSC = (int)RHS->getZExtValue();
1725 if (RHSC < 0 && RHSC > -0x1000) {
1727 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1728 Base = Ptr->getOperand(0);
1733 if (Ptr->getOpcode() == ISD::ADD) {
1735 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1736 if (ShOpcVal != ARM_AM::no_shift) {
1737 Base = Ptr->getOperand(1);
1738 Offset = Ptr->getOperand(0);
1740 Base = Ptr->getOperand(0);
1741 Offset = Ptr->getOperand(1);
1746 isInc = (Ptr->getOpcode() == ISD::ADD);
1747 Base = Ptr->getOperand(0);
1748 Offset = Ptr->getOperand(1);
1752 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1756 /// getPreIndexedAddressParts - returns true by value, base pointer and
1757 /// offset pointer and addressing mode by reference if the node's address
1758 /// can be legally represented as pre-indexed load / store address.
1760 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1762 ISD::MemIndexedMode &AM,
1763 SelectionDAG &DAG) const {
1764 if (Subtarget->isThumb())
1769 bool isSEXTLoad = false;
1770 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1771 Ptr = LD->getBasePtr();
1772 VT = LD->getMemoryVT();
1773 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1774 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1775 Ptr = ST->getBasePtr();
1776 VT = ST->getMemoryVT();
1781 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
1784 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1790 /// getPostIndexedAddressParts - returns true by value, base pointer and
1791 /// offset pointer and addressing mode by reference if this node can be
1792 /// combined with a load / store to form a post-indexed load / store.
1793 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1796 ISD::MemIndexedMode &AM,
1797 SelectionDAG &DAG) const {
1798 if (Subtarget->isThumb())
1803 bool isSEXTLoad = false;
1804 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1805 VT = LD->getMemoryVT();
1806 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1807 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1808 VT = ST->getMemoryVT();
1813 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1816 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1822 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1826 const SelectionDAG &DAG,
1827 unsigned Depth) const {
1828 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1829 switch (Op.getOpcode()) {
1831 case ARMISD::CMOV: {
1832 // Bits are known zero/one if known on the LHS and RHS.
1833 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1834 if (KnownZero == 0 && KnownOne == 0) return;
1836 APInt KnownZeroRHS, KnownOneRHS;
1837 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1838 KnownZeroRHS, KnownOneRHS, Depth+1);
1839 KnownZero &= KnownZeroRHS;
1840 KnownOne &= KnownOneRHS;
1846 //===----------------------------------------------------------------------===//
1847 // ARM Inline Assembly Support
1848 //===----------------------------------------------------------------------===//
1850 /// getConstraintType - Given a constraint letter, return the type of
1851 /// constraint it is for this target.
1852 ARMTargetLowering::ConstraintType
1853 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1854 if (Constraint.size() == 1) {
1855 switch (Constraint[0]) {
1857 case 'l': return C_RegisterClass;
1858 case 'w': return C_RegisterClass;
1861 return TargetLowering::getConstraintType(Constraint);
1864 std::pair<unsigned, const TargetRegisterClass*>
1865 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1867 if (Constraint.size() == 1) {
1868 // GCC RS6000 Constraint Letters
1869 switch (Constraint[0]) {
1871 // FIXME: in thumb mode, 'l' is only low-regs.
1874 return std::make_pair(0U, ARM::GPRRegisterClass);
1877 return std::make_pair(0U, ARM::SPRRegisterClass);
1879 return std::make_pair(0U, ARM::DPRRegisterClass);
1883 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1886 std::vector<unsigned> ARMTargetLowering::
1887 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1889 if (Constraint.size() != 1)
1890 return std::vector<unsigned>();
1892 switch (Constraint[0]) { // GCC ARM Constraint Letters
1896 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1897 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1898 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1899 ARM::R12, ARM::LR, 0);
1902 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1903 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1904 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1905 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1906 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1907 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1908 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1909 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1911 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1912 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1913 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1914 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1918 return std::vector<unsigned>();