1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
76 class ARMCCState : public CCState {
78 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
79 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
80 LLVMContext &C, ParmContext PC)
81 : CCState(CC, isVarArg, MF, TM, locs, C) {
82 assert(((PC == Call) || (PC == Prologue)) &&
83 "ARMCCState users must specify whether their context is call"
84 "or prologue generation.");
90 // The APCS parameter registers.
91 static const unsigned GPRArgRegs[] = {
92 ARM::R0, ARM::R1, ARM::R2, ARM::R3
95 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
96 EVT PromotedBitwiseVT) {
97 if (VT != PromotedLdStVT) {
98 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
99 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
100 PromotedLdStVT.getSimpleVT());
102 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
103 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
104 PromotedLdStVT.getSimpleVT());
107 EVT ElemTy = VT.getVectorElementType();
108 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
109 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
112 if (ElemTy == MVT::i32) {
113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom);
114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Custom);
115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
118 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
121 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
123 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
125 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
126 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
127 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand);
130 if (VT.isInteger()) {
131 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
132 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
133 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
136 // Promote all bit-wise operations.
137 if (VT.isInteger() && VT != PromotedBitwiseVT) {
138 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
139 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
140 PromotedBitwiseVT.getSimpleVT());
141 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
142 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
143 PromotedBitwiseVT.getSimpleVT());
144 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
145 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
146 PromotedBitwiseVT.getSimpleVT());
149 // Neon does not support vector divide/remainder operations.
150 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
151 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
158 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
159 addRegisterClass(VT, ARM::DPRRegisterClass);
160 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
163 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
164 addRegisterClass(VT, ARM::QPRRegisterClass);
165 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
168 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
169 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
170 return new TargetLoweringObjectFileMachO();
172 return new ARMElfTargetObjectFile();
175 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
176 : TargetLowering(TM, createTLOF(TM)) {
177 Subtarget = &TM.getSubtarget<ARMSubtarget>();
178 RegInfo = TM.getRegisterInfo();
179 Itins = TM.getInstrItineraryData();
181 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
183 if (Subtarget->isTargetDarwin()) {
184 // Uses VFP for Thumb libfuncs if available.
185 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
186 // Single-precision floating-point arithmetic.
187 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
188 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
189 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
190 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
192 // Double-precision floating-point arithmetic.
193 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
194 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
195 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
196 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
198 // Single-precision comparisons.
199 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
200 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
201 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
202 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
203 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
204 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
205 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
206 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
208 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
217 // Double-precision comparisons.
218 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
219 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
220 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
221 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
222 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
223 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
224 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
225 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
227 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
233 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
234 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
236 // Floating-point to integer conversions.
237 // i64 conversions are done via library routines even when generating VFP
238 // instructions, so use the same ones.
239 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
240 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
241 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
242 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
244 // Conversions between floating types.
245 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
246 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
248 // Integer to floating-point conversions.
249 // i64 conversions are done via library routines even when generating VFP
250 // instructions, so use the same ones.
251 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
252 // e.g., __floatunsidf vs. __floatunssidfvfp.
253 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
254 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
255 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
256 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
260 // These libcalls are not available in 32-bit.
261 setLibcallName(RTLIB::SHL_I128, 0);
262 setLibcallName(RTLIB::SRL_I128, 0);
263 setLibcallName(RTLIB::SRA_I128, 0);
265 if (Subtarget->isAAPCS_ABI()) {
266 // Double-precision floating-point arithmetic helper functions
267 // RTABI chapter 4.1.2, Table 2
268 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
269 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
270 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
271 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
272 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
277 // Double-precision floating-point comparison helper functions
278 // RTABI chapter 4.1.2, Table 3
279 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
280 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
281 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
282 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
283 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
284 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
285 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
286 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
287 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
288 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
289 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
290 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
291 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
292 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
293 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
294 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
295 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
301 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
302 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
304 // Single-precision floating-point arithmetic helper functions
305 // RTABI chapter 4.1.2, Table 4
306 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
307 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
308 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
309 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
310 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
315 // Single-precision floating-point comparison helper functions
316 // RTABI chapter 4.1.2, Table 5
317 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
318 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
319 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
320 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
321 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
322 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
323 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
324 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
325 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
326 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
327 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
328 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
329 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
330 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
331 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
332 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
333 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
342 // Floating-point to integer conversions.
343 // RTABI chapter 4.1.2, Table 6
344 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
345 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
346 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
347 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
348 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
349 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
350 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
351 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
352 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
361 // Conversions between floating types.
362 // RTABI chapter 4.1.2, Table 7
363 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
364 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
365 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
366 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
368 // Integer to floating-point conversions.
369 // RTABI chapter 4.1.2, Table 8
370 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
371 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
372 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
373 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
374 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
375 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
376 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
377 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
378 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
384 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
385 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
387 // Long long helper functions
388 // RTABI chapter 4.2, Table 9
389 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
390 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
391 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
392 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
393 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
394 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
395 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
399 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
400 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
402 // Integer division functions
403 // RTABI chapter 4.3.1
404 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
405 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
406 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
407 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
408 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
409 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
410 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
414 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
415 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
418 // RTABI chapter 4.3.4
419 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
420 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
421 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
424 // Use divmod compiler-rt calls for iOS 5.0 and later.
425 if (Subtarget->getTargetTriple().getOS() == Triple::IOS &&
426 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
427 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
428 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
431 if (Subtarget->isThumb1Only())
432 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
434 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
435 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
436 !Subtarget->isThumb1Only()) {
437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
438 if (!Subtarget->isFPOnlySP())
439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
441 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
444 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
445 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
446 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
447 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
448 setTruncStoreAction((MVT::SimpleValueType)VT,
449 (MVT::SimpleValueType)InnerVT, Expand);
450 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
451 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
452 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
455 if (Subtarget->hasNEON()) {
456 addDRTypeForNEON(MVT::v2f32);
457 addDRTypeForNEON(MVT::v8i8);
458 addDRTypeForNEON(MVT::v4i16);
459 addDRTypeForNEON(MVT::v2i32);
460 addDRTypeForNEON(MVT::v1i64);
462 addQRTypeForNEON(MVT::v4f32);
463 addQRTypeForNEON(MVT::v2f64);
464 addQRTypeForNEON(MVT::v16i8);
465 addQRTypeForNEON(MVT::v8i16);
466 addQRTypeForNEON(MVT::v4i32);
467 addQRTypeForNEON(MVT::v2i64);
469 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
470 // neither Neon nor VFP support any arithmetic operations on it.
471 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
472 // supported for v4f32.
473 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
474 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
475 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
476 // FIXME: Code duplication: FDIV and FREM are expanded always, see
477 // ARMTargetLowering::addTypeForNEON method for details.
478 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
479 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
480 // FIXME: Create unittest.
481 // In another words, find a way when "copysign" appears in DAG with vector
483 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
484 // FIXME: Code duplication: SETCC has custom operation action, see
485 // ARMTargetLowering::addTypeForNEON method for details.
486 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
487 // FIXME: Create unittest for FNEG and for FABS.
488 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
489 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
490 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
491 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
492 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
493 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
494 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
495 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
496 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
497 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
498 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
499 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
500 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
501 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
502 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
503 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
504 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
505 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
507 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
508 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
509 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
510 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
511 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
512 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
513 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
514 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
515 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
516 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
518 // Neon does not support some operations on v1i64 and v2i64 types.
519 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // Custom handling for some quad-vector types to detect VMULL.
521 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
522 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
523 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
524 // Custom handling for some vector types to avoid expensive expansions
525 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
526 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
527 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
528 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
529 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
530 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
531 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
532 // a destination type that is wider than the source.
533 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
534 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
536 setTargetDAGCombine(ISD::INTRINSIC_VOID);
537 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
538 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
539 setTargetDAGCombine(ISD::SHL);
540 setTargetDAGCombine(ISD::SRL);
541 setTargetDAGCombine(ISD::SRA);
542 setTargetDAGCombine(ISD::SIGN_EXTEND);
543 setTargetDAGCombine(ISD::ZERO_EXTEND);
544 setTargetDAGCombine(ISD::ANY_EXTEND);
545 setTargetDAGCombine(ISD::SELECT_CC);
546 setTargetDAGCombine(ISD::BUILD_VECTOR);
547 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
548 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
549 setTargetDAGCombine(ISD::STORE);
550 setTargetDAGCombine(ISD::FP_TO_SINT);
551 setTargetDAGCombine(ISD::FP_TO_UINT);
552 setTargetDAGCombine(ISD::FDIV);
554 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
557 computeRegisterProperties();
559 // ARM does not have f32 extending load.
560 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
562 // ARM does not have i1 sign extending load.
563 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
565 // ARM supports all 4 flavors of integer indexed load / store.
566 if (!Subtarget->isThumb1Only()) {
567 for (unsigned im = (unsigned)ISD::PRE_INC;
568 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
569 setIndexedLoadAction(im, MVT::i1, Legal);
570 setIndexedLoadAction(im, MVT::i8, Legal);
571 setIndexedLoadAction(im, MVT::i16, Legal);
572 setIndexedLoadAction(im, MVT::i32, Legal);
573 setIndexedStoreAction(im, MVT::i1, Legal);
574 setIndexedStoreAction(im, MVT::i8, Legal);
575 setIndexedStoreAction(im, MVT::i16, Legal);
576 setIndexedStoreAction(im, MVT::i32, Legal);
580 // i64 operation support.
581 setOperationAction(ISD::MUL, MVT::i64, Expand);
582 setOperationAction(ISD::MULHU, MVT::i32, Expand);
583 if (Subtarget->isThumb1Only()) {
584 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
585 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
587 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
588 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
589 setOperationAction(ISD::MULHS, MVT::i32, Expand);
591 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
592 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
593 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
594 setOperationAction(ISD::SRL, MVT::i64, Custom);
595 setOperationAction(ISD::SRA, MVT::i64, Custom);
597 if (!Subtarget->isThumb1Only()) {
598 // FIXME: We should do this for Thumb1 as well.
599 setOperationAction(ISD::ADDC, MVT::i32, Custom);
600 setOperationAction(ISD::ADDE, MVT::i32, Custom);
601 setOperationAction(ISD::SUBC, MVT::i32, Custom);
602 setOperationAction(ISD::SUBE, MVT::i32, Custom);
605 // ARM does not have ROTL.
606 setOperationAction(ISD::ROTL, MVT::i32, Expand);
607 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
608 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
609 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
610 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
612 // Only ARMv6 has BSWAP.
613 if (!Subtarget->hasV6Ops())
614 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
616 // These are expanded into libcalls.
617 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
618 // v7M has a hardware divider
619 setOperationAction(ISD::SDIV, MVT::i32, Expand);
620 setOperationAction(ISD::UDIV, MVT::i32, Expand);
622 setOperationAction(ISD::SREM, MVT::i32, Expand);
623 setOperationAction(ISD::UREM, MVT::i32, Expand);
624 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
625 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
627 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
628 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
629 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
630 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
631 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
633 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 // Use the default implementation.
636 setOperationAction(ISD::VASTART, MVT::Other, Custom);
637 setOperationAction(ISD::VAARG, MVT::Other, Expand);
638 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
639 setOperationAction(ISD::VAEND, MVT::Other, Expand);
640 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
641 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
642 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
643 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
644 setExceptionPointerRegister(ARM::R0);
645 setExceptionSelectorRegister(ARM::R1);
647 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
648 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
649 // the default expansion.
650 // FIXME: This should be checking for v6k, not just v6.
651 if (Subtarget->hasDataBarrier() ||
652 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
653 // membarrier needs custom lowering; the rest are legal and handled
655 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
656 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
657 // Custom lowering for 64-bit ops
658 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
659 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
660 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
661 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
662 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
663 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
664 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
665 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
666 setInsertFencesForAtomic(true);
668 // Set them all for expansion, which will force libcalls.
669 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
670 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
671 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
672 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
673 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
674 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
675 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
676 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
677 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
678 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
679 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
680 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
681 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
682 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
683 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
684 // Unordered/Monotonic case.
685 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
686 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
687 // Since the libcalls include locking, fold in the fences
688 setShouldFoldAtomicFences(true);
691 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
693 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
694 if (!Subtarget->hasV6Ops()) {
695 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
696 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
698 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
700 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
701 !Subtarget->isThumb1Only()) {
702 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
703 // iff target supports vfp2.
704 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
705 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
708 // We want to custom lower some of our intrinsics.
709 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
710 if (Subtarget->isTargetDarwin()) {
711 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
712 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
713 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
716 setOperationAction(ISD::SETCC, MVT::i32, Expand);
717 setOperationAction(ISD::SETCC, MVT::f32, Expand);
718 setOperationAction(ISD::SETCC, MVT::f64, Expand);
719 setOperationAction(ISD::SELECT, MVT::i32, Custom);
720 setOperationAction(ISD::SELECT, MVT::f32, Custom);
721 setOperationAction(ISD::SELECT, MVT::f64, Custom);
722 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
723 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
724 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
726 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
727 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
728 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
729 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
730 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
732 // We don't support sin/cos/fmod/copysign/pow
733 setOperationAction(ISD::FSIN, MVT::f64, Expand);
734 setOperationAction(ISD::FSIN, MVT::f32, Expand);
735 setOperationAction(ISD::FCOS, MVT::f32, Expand);
736 setOperationAction(ISD::FCOS, MVT::f64, Expand);
737 setOperationAction(ISD::FREM, MVT::f64, Expand);
738 setOperationAction(ISD::FREM, MVT::f32, Expand);
739 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
740 !Subtarget->isThumb1Only()) {
741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
744 setOperationAction(ISD::FPOW, MVT::f64, Expand);
745 setOperationAction(ISD::FPOW, MVT::f32, Expand);
747 setOperationAction(ISD::FMA, MVT::f64, Expand);
748 setOperationAction(ISD::FMA, MVT::f32, Expand);
750 // Various VFP goodness
751 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
752 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
753 if (Subtarget->hasVFP2()) {
754 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
755 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
756 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
757 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
759 // Special handling for half-precision FP.
760 if (!Subtarget->hasFP16()) {
761 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
762 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
766 // We have target-specific dag combine patterns for the following nodes:
767 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
768 setTargetDAGCombine(ISD::ADD);
769 setTargetDAGCombine(ISD::SUB);
770 setTargetDAGCombine(ISD::MUL);
772 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
773 setTargetDAGCombine(ISD::OR);
774 if (Subtarget->hasNEON())
775 setTargetDAGCombine(ISD::AND);
777 setStackPointerRegisterToSaveRestore(ARM::SP);
779 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
780 !Subtarget->hasVFP2())
781 setSchedulingPreference(Sched::RegPressure);
783 setSchedulingPreference(Sched::Hybrid);
785 //// temporary - rewrite interface to use type
786 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
787 maxStoresPerMemset = 16;
788 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
790 // On ARM arguments smaller than 4 bytes are extended, so all arguments
791 // are at least 4 bytes aligned.
792 setMinStackArgumentAlignment(4);
794 benefitFromCodePlacementOpt = true;
796 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
799 // FIXME: It might make sense to define the representative register class as the
800 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
801 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
802 // SPR's representative would be DPR_VFP2. This should work well if register
803 // pressure tracking were modified such that a register use would increment the
804 // pressure of the register class's representative and all of it's super
805 // classes' representatives transitively. We have not implemented this because
806 // of the difficulty prior to coalescing of modeling operand register classes
807 // due to the common occurrence of cross class copies and subregister insertions
809 std::pair<const TargetRegisterClass*, uint8_t>
810 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
811 const TargetRegisterClass *RRC = 0;
813 switch (VT.getSimpleVT().SimpleTy) {
815 return TargetLowering::findRepresentativeClass(VT);
816 // Use DPR as representative register class for all floating point
817 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
818 // the cost is 1 for both f32 and f64.
819 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
820 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
821 RRC = ARM::DPRRegisterClass;
822 // When NEON is used for SP, only half of the register file is available
823 // because operations that define both SP and DP results will be constrained
824 // to the VFP2 class (D0-D15). We currently model this constraint prior to
825 // coalescing by double-counting the SP regs. See the FIXME above.
826 if (Subtarget->useNEONForSinglePrecisionFP())
829 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
830 case MVT::v4f32: case MVT::v2f64:
831 RRC = ARM::DPRRegisterClass;
835 RRC = ARM::DPRRegisterClass;
839 RRC = ARM::DPRRegisterClass;
843 return std::make_pair(RRC, Cost);
846 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
849 case ARMISD::Wrapper: return "ARMISD::Wrapper";
850 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
851 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
852 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
853 case ARMISD::CALL: return "ARMISD::CALL";
854 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
855 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
856 case ARMISD::tCALL: return "ARMISD::tCALL";
857 case ARMISD::BRCOND: return "ARMISD::BRCOND";
858 case ARMISD::BR_JT: return "ARMISD::BR_JT";
859 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
860 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
861 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
862 case ARMISD::CMP: return "ARMISD::CMP";
863 case ARMISD::CMPZ: return "ARMISD::CMPZ";
864 case ARMISD::CMPFP: return "ARMISD::CMPFP";
865 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
866 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
867 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
868 case ARMISD::CMOV: return "ARMISD::CMOV";
870 case ARMISD::RBIT: return "ARMISD::RBIT";
872 case ARMISD::FTOSI: return "ARMISD::FTOSI";
873 case ARMISD::FTOUI: return "ARMISD::FTOUI";
874 case ARMISD::SITOF: return "ARMISD::SITOF";
875 case ARMISD::UITOF: return "ARMISD::UITOF";
877 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
878 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
879 case ARMISD::RRX: return "ARMISD::RRX";
881 case ARMISD::ADDC: return "ARMISD::ADDC";
882 case ARMISD::ADDE: return "ARMISD::ADDE";
883 case ARMISD::SUBC: return "ARMISD::SUBC";
884 case ARMISD::SUBE: return "ARMISD::SUBE";
886 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
887 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
889 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
890 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
892 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
894 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
896 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
898 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
899 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
901 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
903 case ARMISD::VCEQ: return "ARMISD::VCEQ";
904 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
905 case ARMISD::VCGE: return "ARMISD::VCGE";
906 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
907 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
908 case ARMISD::VCGEU: return "ARMISD::VCGEU";
909 case ARMISD::VCGT: return "ARMISD::VCGT";
910 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
911 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
912 case ARMISD::VCGTU: return "ARMISD::VCGTU";
913 case ARMISD::VTST: return "ARMISD::VTST";
915 case ARMISD::VSHL: return "ARMISD::VSHL";
916 case ARMISD::VSHRs: return "ARMISD::VSHRs";
917 case ARMISD::VSHRu: return "ARMISD::VSHRu";
918 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
919 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
920 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
921 case ARMISD::VSHRN: return "ARMISD::VSHRN";
922 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
923 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
924 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
925 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
926 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
927 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
928 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
929 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
930 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
931 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
932 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
933 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
934 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
935 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
936 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
937 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
938 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
939 case ARMISD::VDUP: return "ARMISD::VDUP";
940 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
941 case ARMISD::VEXT: return "ARMISD::VEXT";
942 case ARMISD::VREV64: return "ARMISD::VREV64";
943 case ARMISD::VREV32: return "ARMISD::VREV32";
944 case ARMISD::VREV16: return "ARMISD::VREV16";
945 case ARMISD::VZIP: return "ARMISD::VZIP";
946 case ARMISD::VUZP: return "ARMISD::VUZP";
947 case ARMISD::VTRN: return "ARMISD::VTRN";
948 case ARMISD::VTBL1: return "ARMISD::VTBL1";
949 case ARMISD::VTBL2: return "ARMISD::VTBL2";
950 case ARMISD::VMULLs: return "ARMISD::VMULLs";
951 case ARMISD::VMULLu: return "ARMISD::VMULLu";
952 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
953 case ARMISD::FMAX: return "ARMISD::FMAX";
954 case ARMISD::FMIN: return "ARMISD::FMIN";
955 case ARMISD::BFI: return "ARMISD::BFI";
956 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
957 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
958 case ARMISD::VBSL: return "ARMISD::VBSL";
959 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
960 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
961 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
962 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
963 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
964 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
965 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
966 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
967 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
968 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
969 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
970 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
971 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
972 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
973 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
974 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
975 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
976 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
977 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
978 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
982 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
983 if (!VT.isVector()) return getPointerTy();
984 return VT.changeVectorElementTypeToInteger();
987 /// getRegClassFor - Return the register class that should be used for the
988 /// specified value type.
989 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
990 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
991 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
992 // load / store 4 to 8 consecutive D registers.
993 if (Subtarget->hasNEON()) {
994 if (VT == MVT::v4i64)
995 return ARM::QQPRRegisterClass;
996 else if (VT == MVT::v8i64)
997 return ARM::QQQQPRRegisterClass;
999 return TargetLowering::getRegClassFor(VT);
1002 // Create a fast isel object.
1004 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
1005 return ARM::createFastISel(funcInfo);
1008 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1009 /// be used for loads / stores from the global.
1010 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1011 return (Subtarget->isThumb1Only() ? 127 : 4095);
1014 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1015 unsigned NumVals = N->getNumValues();
1017 return Sched::RegPressure;
1019 for (unsigned i = 0; i != NumVals; ++i) {
1020 EVT VT = N->getValueType(i);
1021 if (VT == MVT::Glue || VT == MVT::Other)
1023 if (VT.isFloatingPoint() || VT.isVector())
1027 if (!N->isMachineOpcode())
1028 return Sched::RegPressure;
1030 // Load are scheduled for latency even if there instruction itinerary
1031 // is not available.
1032 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1033 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1035 if (MCID.getNumDefs() == 0)
1036 return Sched::RegPressure;
1037 if (!Itins->isEmpty() &&
1038 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1041 return Sched::RegPressure;
1044 //===----------------------------------------------------------------------===//
1046 //===----------------------------------------------------------------------===//
1048 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1049 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1051 default: llvm_unreachable("Unknown condition code!");
1052 case ISD::SETNE: return ARMCC::NE;
1053 case ISD::SETEQ: return ARMCC::EQ;
1054 case ISD::SETGT: return ARMCC::GT;
1055 case ISD::SETGE: return ARMCC::GE;
1056 case ISD::SETLT: return ARMCC::LT;
1057 case ISD::SETLE: return ARMCC::LE;
1058 case ISD::SETUGT: return ARMCC::HI;
1059 case ISD::SETUGE: return ARMCC::HS;
1060 case ISD::SETULT: return ARMCC::LO;
1061 case ISD::SETULE: return ARMCC::LS;
1065 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1066 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1067 ARMCC::CondCodes &CondCode2) {
1068 CondCode2 = ARMCC::AL;
1070 default: llvm_unreachable("Unknown FP condition!");
1072 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1074 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1076 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1077 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1078 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1079 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1080 case ISD::SETO: CondCode = ARMCC::VC; break;
1081 case ISD::SETUO: CondCode = ARMCC::VS; break;
1082 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1083 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1084 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1086 case ISD::SETULT: CondCode = ARMCC::LT; break;
1088 case ISD::SETULE: CondCode = ARMCC::LE; break;
1090 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1094 //===----------------------------------------------------------------------===//
1095 // Calling Convention Implementation
1096 //===----------------------------------------------------------------------===//
1098 #include "ARMGenCallingConv.inc"
1100 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1101 /// given CallingConvention value.
1102 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1104 bool isVarArg) const {
1107 llvm_unreachable("Unsupported calling convention");
1108 case CallingConv::Fast:
1109 if (Subtarget->hasVFP2() && !isVarArg) {
1110 if (!Subtarget->isAAPCS_ABI())
1111 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1112 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1113 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1116 case CallingConv::C: {
1117 // Use target triple & subtarget features to do actual dispatch.
1118 if (!Subtarget->isAAPCS_ABI())
1119 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1120 else if (Subtarget->hasVFP2() &&
1121 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1123 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1124 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1126 case CallingConv::ARM_AAPCS_VFP:
1127 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1128 case CallingConv::ARM_AAPCS:
1129 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1130 case CallingConv::ARM_APCS:
1131 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1135 /// LowerCallResult - Lower the result values of a call into the
1136 /// appropriate copies out of appropriate physical registers.
1138 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1139 CallingConv::ID CallConv, bool isVarArg,
1140 const SmallVectorImpl<ISD::InputArg> &Ins,
1141 DebugLoc dl, SelectionDAG &DAG,
1142 SmallVectorImpl<SDValue> &InVals) const {
1144 // Assign locations to each value returned by this call.
1145 SmallVector<CCValAssign, 16> RVLocs;
1146 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1147 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1148 CCInfo.AnalyzeCallResult(Ins,
1149 CCAssignFnForNode(CallConv, /* Return*/ true,
1152 // Copy all of the result registers out of their specified physreg.
1153 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1154 CCValAssign VA = RVLocs[i];
1157 if (VA.needsCustom()) {
1158 // Handle f64 or half of a v2f64.
1159 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1161 Chain = Lo.getValue(1);
1162 InFlag = Lo.getValue(2);
1163 VA = RVLocs[++i]; // skip ahead to next loc
1164 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1166 Chain = Hi.getValue(1);
1167 InFlag = Hi.getValue(2);
1168 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1170 if (VA.getLocVT() == MVT::v2f64) {
1171 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1172 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1173 DAG.getConstant(0, MVT::i32));
1175 VA = RVLocs[++i]; // skip ahead to next loc
1176 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1177 Chain = Lo.getValue(1);
1178 InFlag = Lo.getValue(2);
1179 VA = RVLocs[++i]; // skip ahead to next loc
1180 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1181 Chain = Hi.getValue(1);
1182 InFlag = Hi.getValue(2);
1183 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1184 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1185 DAG.getConstant(1, MVT::i32));
1188 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1190 Chain = Val.getValue(1);
1191 InFlag = Val.getValue(2);
1194 switch (VA.getLocInfo()) {
1195 default: llvm_unreachable("Unknown loc info!");
1196 case CCValAssign::Full: break;
1197 case CCValAssign::BCvt:
1198 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1202 InVals.push_back(Val);
1208 /// LowerMemOpCallTo - Store the argument to the stack.
1210 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1211 SDValue StackPtr, SDValue Arg,
1212 DebugLoc dl, SelectionDAG &DAG,
1213 const CCValAssign &VA,
1214 ISD::ArgFlagsTy Flags) const {
1215 unsigned LocMemOffset = VA.getLocMemOffset();
1216 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1217 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1218 return DAG.getStore(Chain, dl, Arg, PtrOff,
1219 MachinePointerInfo::getStack(LocMemOffset),
1223 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1224 SDValue Chain, SDValue &Arg,
1225 RegsToPassVector &RegsToPass,
1226 CCValAssign &VA, CCValAssign &NextVA,
1228 SmallVector<SDValue, 8> &MemOpChains,
1229 ISD::ArgFlagsTy Flags) const {
1231 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1232 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1233 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1235 if (NextVA.isRegLoc())
1236 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1238 assert(NextVA.isMemLoc());
1239 if (StackPtr.getNode() == 0)
1240 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1242 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1248 /// LowerCall - Lowering a call into a callseq_start <-
1249 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1252 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1253 CallingConv::ID CallConv, bool isVarArg,
1255 const SmallVectorImpl<ISD::OutputArg> &Outs,
1256 const SmallVectorImpl<SDValue> &OutVals,
1257 const SmallVectorImpl<ISD::InputArg> &Ins,
1258 DebugLoc dl, SelectionDAG &DAG,
1259 SmallVectorImpl<SDValue> &InVals) const {
1260 MachineFunction &MF = DAG.getMachineFunction();
1261 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1262 bool IsSibCall = false;
1263 // Disable tail calls if they're not supported.
1264 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1267 // Check if it's really possible to do a tail call.
1268 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1269 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1270 Outs, OutVals, Ins, DAG);
1271 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1272 // detected sibcalls.
1279 // Analyze operands of the call, assigning locations to each operand.
1280 SmallVector<CCValAssign, 16> ArgLocs;
1281 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1282 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1283 CCInfo.AnalyzeCallOperands(Outs,
1284 CCAssignFnForNode(CallConv, /* Return*/ false,
1287 // Get a count of how many bytes are to be pushed on the stack.
1288 unsigned NumBytes = CCInfo.getNextStackOffset();
1290 // For tail calls, memory operands are available in our caller's stack.
1294 // Adjust the stack pointer for the new arguments...
1295 // These operations are automatically eliminated by the prolog/epilog pass
1297 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1299 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1301 RegsToPassVector RegsToPass;
1302 SmallVector<SDValue, 8> MemOpChains;
1304 // Walk the register/memloc assignments, inserting copies/loads. In the case
1305 // of tail call optimization, arguments are handled later.
1306 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1308 ++i, ++realArgIdx) {
1309 CCValAssign &VA = ArgLocs[i];
1310 SDValue Arg = OutVals[realArgIdx];
1311 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1312 bool isByVal = Flags.isByVal();
1314 // Promote the value if needed.
1315 switch (VA.getLocInfo()) {
1316 default: llvm_unreachable("Unknown loc info!");
1317 case CCValAssign::Full: break;
1318 case CCValAssign::SExt:
1319 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1321 case CCValAssign::ZExt:
1322 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1324 case CCValAssign::AExt:
1325 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1327 case CCValAssign::BCvt:
1328 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1332 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1333 if (VA.needsCustom()) {
1334 if (VA.getLocVT() == MVT::v2f64) {
1335 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1336 DAG.getConstant(0, MVT::i32));
1337 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1338 DAG.getConstant(1, MVT::i32));
1340 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1341 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1343 VA = ArgLocs[++i]; // skip ahead to next loc
1344 if (VA.isRegLoc()) {
1345 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1346 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1348 assert(VA.isMemLoc());
1350 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1351 dl, DAG, VA, Flags));
1354 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1355 StackPtr, MemOpChains, Flags);
1357 } else if (VA.isRegLoc()) {
1358 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1359 } else if (isByVal) {
1360 assert(VA.isMemLoc());
1361 unsigned offset = 0;
1363 // True if this byval aggregate will be split between registers
1365 if (CCInfo.isFirstByValRegValid()) {
1366 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1368 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1369 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1370 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1371 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1372 MachinePointerInfo(),
1373 false, false, false, 0);
1374 MemOpChains.push_back(Load.getValue(1));
1375 RegsToPass.push_back(std::make_pair(j, Load));
1377 offset = ARM::R4 - CCInfo.getFirstByValReg();
1378 CCInfo.clearFirstByValReg();
1381 unsigned LocMemOffset = VA.getLocMemOffset();
1382 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1383 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1385 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1386 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1387 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1389 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1390 Flags.getByValAlign(),
1391 /*isVolatile=*/false,
1392 /*AlwaysInline=*/false,
1393 MachinePointerInfo(0),
1394 MachinePointerInfo(0)));
1396 } else if (!IsSibCall) {
1397 assert(VA.isMemLoc());
1399 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1400 dl, DAG, VA, Flags));
1404 if (!MemOpChains.empty())
1405 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1406 &MemOpChains[0], MemOpChains.size());
1408 // Build a sequence of copy-to-reg nodes chained together with token chain
1409 // and flag operands which copy the outgoing args into the appropriate regs.
1411 // Tail call byval lowering might overwrite argument registers so in case of
1412 // tail call optimization the copies to registers are lowered later.
1414 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1415 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1416 RegsToPass[i].second, InFlag);
1417 InFlag = Chain.getValue(1);
1420 // For tail calls lower the arguments to the 'real' stack slot.
1422 // Force all the incoming stack arguments to be loaded from the stack
1423 // before any new outgoing arguments are stored to the stack, because the
1424 // outgoing stack slots may alias the incoming argument stack slots, and
1425 // the alias isn't otherwise explicit. This is slightly more conservative
1426 // than necessary, because it means that each store effectively depends
1427 // on every argument instead of just those arguments it would clobber.
1429 // Do not flag preceding copytoreg stuff together with the following stuff.
1431 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1432 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1433 RegsToPass[i].second, InFlag);
1434 InFlag = Chain.getValue(1);
1439 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1440 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1441 // node so that legalize doesn't hack it.
1442 bool isDirect = false;
1443 bool isARMFunc = false;
1444 bool isLocalARMFunc = false;
1445 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1447 if (EnableARMLongCalls) {
1448 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1449 && "long-calls with non-static relocation model!");
1450 // Handle a global address or an external symbol. If it's not one of
1451 // those, the target's already in a register, so we don't need to do
1453 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1454 const GlobalValue *GV = G->getGlobal();
1455 // Create a constant pool entry for the callee address
1456 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1457 ARMConstantPoolValue *CPV =
1458 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1460 // Get the address of the callee into a register
1461 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1462 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1463 Callee = DAG.getLoad(getPointerTy(), dl,
1464 DAG.getEntryNode(), CPAddr,
1465 MachinePointerInfo::getConstantPool(),
1466 false, false, false, 0);
1467 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1468 const char *Sym = S->getSymbol();
1470 // Create a constant pool entry for the callee address
1471 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1472 ARMConstantPoolValue *CPV =
1473 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1474 ARMPCLabelIndex, 0);
1475 // Get the address of the callee into a register
1476 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1477 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1478 Callee = DAG.getLoad(getPointerTy(), dl,
1479 DAG.getEntryNode(), CPAddr,
1480 MachinePointerInfo::getConstantPool(),
1481 false, false, false, 0);
1483 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1484 const GlobalValue *GV = G->getGlobal();
1486 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1487 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1488 getTargetMachine().getRelocationModel() != Reloc::Static;
1489 isARMFunc = !Subtarget->isThumb() || isStub;
1490 // ARM call to a local ARM function is predicable.
1491 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1492 // tBX takes a register source operand.
1493 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1494 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1495 ARMConstantPoolValue *CPV =
1496 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1497 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1498 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1499 Callee = DAG.getLoad(getPointerTy(), dl,
1500 DAG.getEntryNode(), CPAddr,
1501 MachinePointerInfo::getConstantPool(),
1502 false, false, false, 0);
1503 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1504 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1505 getPointerTy(), Callee, PICLabel);
1507 // On ELF targets for PIC code, direct calls should go through the PLT
1508 unsigned OpFlags = 0;
1509 if (Subtarget->isTargetELF() &&
1510 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1511 OpFlags = ARMII::MO_PLT;
1512 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1514 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1516 bool isStub = Subtarget->isTargetDarwin() &&
1517 getTargetMachine().getRelocationModel() != Reloc::Static;
1518 isARMFunc = !Subtarget->isThumb() || isStub;
1519 // tBX takes a register source operand.
1520 const char *Sym = S->getSymbol();
1521 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1522 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1523 ARMConstantPoolValue *CPV =
1524 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1525 ARMPCLabelIndex, 4);
1526 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1527 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1528 Callee = DAG.getLoad(getPointerTy(), dl,
1529 DAG.getEntryNode(), CPAddr,
1530 MachinePointerInfo::getConstantPool(),
1531 false, false, false, 0);
1532 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1533 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1534 getPointerTy(), Callee, PICLabel);
1536 unsigned OpFlags = 0;
1537 // On ELF targets for PIC code, direct calls should go through the PLT
1538 if (Subtarget->isTargetELF() &&
1539 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1540 OpFlags = ARMII::MO_PLT;
1541 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1545 // FIXME: handle tail calls differently.
1547 if (Subtarget->isThumb()) {
1548 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1549 CallOpc = ARMISD::CALL_NOLINK;
1551 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1553 CallOpc = (isDirect || Subtarget->hasV5TOps())
1554 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1555 : ARMISD::CALL_NOLINK;
1558 std::vector<SDValue> Ops;
1559 Ops.push_back(Chain);
1560 Ops.push_back(Callee);
1562 // Add argument registers to the end of the list so that they are known live
1564 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1565 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1566 RegsToPass[i].second.getValueType()));
1568 if (InFlag.getNode())
1569 Ops.push_back(InFlag);
1571 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1573 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1575 // Returns a chain and a flag for retval copy to use.
1576 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1577 InFlag = Chain.getValue(1);
1579 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1580 DAG.getIntPtrConstant(0, true), InFlag);
1582 InFlag = Chain.getValue(1);
1584 // Handle result values, copying them out of physregs into vregs that we
1586 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1590 /// HandleByVal - Every parameter *after* a byval parameter is passed
1591 /// on the stack. Remember the next parameter register to allocate,
1592 /// and then confiscate the rest of the parameter registers to insure
1595 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1596 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1597 assert((State->getCallOrPrologue() == Prologue ||
1598 State->getCallOrPrologue() == Call) &&
1599 "unhandled ParmContext");
1600 if ((!State->isFirstByValRegValid()) &&
1601 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1602 State->setFirstByValReg(reg);
1603 // At a call site, a byval parameter that is split between
1604 // registers and memory needs its size truncated here. In a
1605 // function prologue, such byval parameters are reassembled in
1606 // memory, and are not truncated.
1607 if (State->getCallOrPrologue() == Call) {
1608 unsigned excess = 4 * (ARM::R4 - reg);
1609 assert(size >= excess && "expected larger existing stack allocation");
1613 // Confiscate any remaining parameter registers to preclude their
1614 // assignment to subsequent parameters.
1615 while (State->AllocateReg(GPRArgRegs, 4))
1619 /// MatchingStackOffset - Return true if the given stack call argument is
1620 /// already available in the same position (relatively) of the caller's
1621 /// incoming argument stack.
1623 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1624 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1625 const ARMInstrInfo *TII) {
1626 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1628 if (Arg.getOpcode() == ISD::CopyFromReg) {
1629 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1630 if (!TargetRegisterInfo::isVirtualRegister(VR))
1632 MachineInstr *Def = MRI->getVRegDef(VR);
1635 if (!Flags.isByVal()) {
1636 if (!TII->isLoadFromStackSlot(Def, FI))
1641 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1642 if (Flags.isByVal())
1643 // ByVal argument is passed in as a pointer but it's now being
1644 // dereferenced. e.g.
1645 // define @foo(%struct.X* %A) {
1646 // tail call @bar(%struct.X* byval %A)
1649 SDValue Ptr = Ld->getBasePtr();
1650 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1653 FI = FINode->getIndex();
1657 assert(FI != INT_MAX);
1658 if (!MFI->isFixedObjectIndex(FI))
1660 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1663 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1664 /// for tail call optimization. Targets which want to do tail call
1665 /// optimization should implement this function.
1667 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1668 CallingConv::ID CalleeCC,
1670 bool isCalleeStructRet,
1671 bool isCallerStructRet,
1672 const SmallVectorImpl<ISD::OutputArg> &Outs,
1673 const SmallVectorImpl<SDValue> &OutVals,
1674 const SmallVectorImpl<ISD::InputArg> &Ins,
1675 SelectionDAG& DAG) const {
1676 const Function *CallerF = DAG.getMachineFunction().getFunction();
1677 CallingConv::ID CallerCC = CallerF->getCallingConv();
1678 bool CCMatch = CallerCC == CalleeCC;
1680 // Look for obvious safe cases to perform tail call optimization that do not
1681 // require ABI changes. This is what gcc calls sibcall.
1683 // Do not sibcall optimize vararg calls unless the call site is not passing
1685 if (isVarArg && !Outs.empty())
1688 // Also avoid sibcall optimization if either caller or callee uses struct
1689 // return semantics.
1690 if (isCalleeStructRet || isCallerStructRet)
1693 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1694 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1695 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1696 // support in the assembler and linker to be used. This would need to be
1697 // fixed to fully support tail calls in Thumb1.
1699 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1700 // LR. This means if we need to reload LR, it takes an extra instructions,
1701 // which outweighs the value of the tail call; but here we don't know yet
1702 // whether LR is going to be used. Probably the right approach is to
1703 // generate the tail call here and turn it back into CALL/RET in
1704 // emitEpilogue if LR is used.
1706 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1707 // but we need to make sure there are enough registers; the only valid
1708 // registers are the 4 used for parameters. We don't currently do this
1710 if (Subtarget->isThumb1Only())
1713 // If the calling conventions do not match, then we'd better make sure the
1714 // results are returned in the same way as what the caller expects.
1716 SmallVector<CCValAssign, 16> RVLocs1;
1717 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1718 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1719 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1721 SmallVector<CCValAssign, 16> RVLocs2;
1722 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1723 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1724 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1726 if (RVLocs1.size() != RVLocs2.size())
1728 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1729 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1731 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1733 if (RVLocs1[i].isRegLoc()) {
1734 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1737 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1743 // If the callee takes no arguments then go on to check the results of the
1745 if (!Outs.empty()) {
1746 // Check if stack adjustment is needed. For now, do not do this if any
1747 // argument is passed on the stack.
1748 SmallVector<CCValAssign, 16> ArgLocs;
1749 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1750 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1751 CCInfo.AnalyzeCallOperands(Outs,
1752 CCAssignFnForNode(CalleeCC, false, isVarArg));
1753 if (CCInfo.getNextStackOffset()) {
1754 MachineFunction &MF = DAG.getMachineFunction();
1756 // Check if the arguments are already laid out in the right way as
1757 // the caller's fixed stack objects.
1758 MachineFrameInfo *MFI = MF.getFrameInfo();
1759 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1760 const ARMInstrInfo *TII =
1761 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1762 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1764 ++i, ++realArgIdx) {
1765 CCValAssign &VA = ArgLocs[i];
1766 EVT RegVT = VA.getLocVT();
1767 SDValue Arg = OutVals[realArgIdx];
1768 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1769 if (VA.getLocInfo() == CCValAssign::Indirect)
1771 if (VA.needsCustom()) {
1772 // f64 and vector types are split into multiple registers or
1773 // register/stack-slot combinations. The types will not match
1774 // the registers; give up on memory f64 refs until we figure
1775 // out what to do about this.
1778 if (!ArgLocs[++i].isRegLoc())
1780 if (RegVT == MVT::v2f64) {
1781 if (!ArgLocs[++i].isRegLoc())
1783 if (!ArgLocs[++i].isRegLoc())
1786 } else if (!VA.isRegLoc()) {
1787 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1799 ARMTargetLowering::LowerReturn(SDValue Chain,
1800 CallingConv::ID CallConv, bool isVarArg,
1801 const SmallVectorImpl<ISD::OutputArg> &Outs,
1802 const SmallVectorImpl<SDValue> &OutVals,
1803 DebugLoc dl, SelectionDAG &DAG) const {
1805 // CCValAssign - represent the assignment of the return value to a location.
1806 SmallVector<CCValAssign, 16> RVLocs;
1808 // CCState - Info about the registers and stack slots.
1809 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1810 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1812 // Analyze outgoing return values.
1813 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1816 // If this is the first return lowered for this function, add
1817 // the regs to the liveout set for the function.
1818 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1819 for (unsigned i = 0; i != RVLocs.size(); ++i)
1820 if (RVLocs[i].isRegLoc())
1821 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1826 // Copy the result values into the output registers.
1827 for (unsigned i = 0, realRVLocIdx = 0;
1829 ++i, ++realRVLocIdx) {
1830 CCValAssign &VA = RVLocs[i];
1831 assert(VA.isRegLoc() && "Can only return in registers!");
1833 SDValue Arg = OutVals[realRVLocIdx];
1835 switch (VA.getLocInfo()) {
1836 default: llvm_unreachable("Unknown loc info!");
1837 case CCValAssign::Full: break;
1838 case CCValAssign::BCvt:
1839 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1843 if (VA.needsCustom()) {
1844 if (VA.getLocVT() == MVT::v2f64) {
1845 // Extract the first half and return it in two registers.
1846 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1847 DAG.getConstant(0, MVT::i32));
1848 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1849 DAG.getVTList(MVT::i32, MVT::i32), Half);
1851 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1852 Flag = Chain.getValue(1);
1853 VA = RVLocs[++i]; // skip ahead to next loc
1854 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1855 HalfGPRs.getValue(1), Flag);
1856 Flag = Chain.getValue(1);
1857 VA = RVLocs[++i]; // skip ahead to next loc
1859 // Extract the 2nd half and fall through to handle it as an f64 value.
1860 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1861 DAG.getConstant(1, MVT::i32));
1863 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1865 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1866 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1867 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1868 Flag = Chain.getValue(1);
1869 VA = RVLocs[++i]; // skip ahead to next loc
1870 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1873 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1875 // Guarantee that all emitted copies are
1876 // stuck together, avoiding something bad.
1877 Flag = Chain.getValue(1);
1882 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1884 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1889 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1890 if (N->getNumValues() != 1)
1892 if (!N->hasNUsesOfValue(1, 0))
1895 unsigned NumCopies = 0;
1897 SDNode *Use = *N->use_begin();
1898 if (Use->getOpcode() == ISD::CopyToReg) {
1899 Copies[NumCopies++] = Use;
1900 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1901 // f64 returned in a pair of GPRs.
1902 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1904 if (UI->getOpcode() != ISD::CopyToReg)
1906 Copies[UI.getUse().getResNo()] = *UI;
1909 } else if (Use->getOpcode() == ISD::BITCAST) {
1910 // f32 returned in a single GPR.
1911 if (!Use->hasNUsesOfValue(1, 0))
1913 Use = *Use->use_begin();
1914 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1916 Copies[NumCopies++] = Use;
1921 if (NumCopies != 1 && NumCopies != 2)
1924 bool HasRet = false;
1925 for (unsigned i = 0; i < NumCopies; ++i) {
1926 SDNode *Copy = Copies[i];
1927 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1929 if (UI->getOpcode() == ISD::CopyToReg) {
1931 if (Use == Copies[0] || Use == Copies[1])
1935 if (UI->getOpcode() != ARMISD::RET_FLAG)
1944 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1945 if (!EnableARMTailCalls)
1948 if (!CI->isTailCall())
1951 return !Subtarget->isThumb1Only();
1954 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1955 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1956 // one of the above mentioned nodes. It has to be wrapped because otherwise
1957 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1958 // be used to form addressing mode. These wrapped nodes will be selected
1960 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1961 EVT PtrVT = Op.getValueType();
1962 // FIXME there is no actual debug info here
1963 DebugLoc dl = Op.getDebugLoc();
1964 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1966 if (CP->isMachineConstantPoolEntry())
1967 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1968 CP->getAlignment());
1970 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1971 CP->getAlignment());
1972 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1975 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1976 return MachineJumpTableInfo::EK_Inline;
1979 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1980 SelectionDAG &DAG) const {
1981 MachineFunction &MF = DAG.getMachineFunction();
1982 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1983 unsigned ARMPCLabelIndex = 0;
1984 DebugLoc DL = Op.getDebugLoc();
1985 EVT PtrVT = getPointerTy();
1986 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1987 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1989 if (RelocM == Reloc::Static) {
1990 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1992 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1993 ARMPCLabelIndex = AFI->createPICLabelUId();
1994 ARMConstantPoolValue *CPV =
1995 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
1996 ARMCP::CPBlockAddress, PCAdj);
1997 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1999 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2000 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2001 MachinePointerInfo::getConstantPool(),
2002 false, false, false, 0);
2003 if (RelocM == Reloc::Static)
2005 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2006 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2009 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2011 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2012 SelectionDAG &DAG) const {
2013 DebugLoc dl = GA->getDebugLoc();
2014 EVT PtrVT = getPointerTy();
2015 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2016 MachineFunction &MF = DAG.getMachineFunction();
2017 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2018 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2019 ARMConstantPoolValue *CPV =
2020 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2021 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2022 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2023 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2024 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2025 MachinePointerInfo::getConstantPool(),
2026 false, false, false, 0);
2027 SDValue Chain = Argument.getValue(1);
2029 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2030 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2032 // call __tls_get_addr.
2035 Entry.Node = Argument;
2036 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2037 Args.push_back(Entry);
2038 // FIXME: is there useful debug info available here?
2039 std::pair<SDValue, SDValue> CallResult =
2040 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
2041 false, false, false, false,
2042 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
2043 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2044 return CallResult.first;
2047 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2048 // "local exec" model.
2050 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2051 SelectionDAG &DAG) const {
2052 const GlobalValue *GV = GA->getGlobal();
2053 DebugLoc dl = GA->getDebugLoc();
2055 SDValue Chain = DAG.getEntryNode();
2056 EVT PtrVT = getPointerTy();
2057 // Get the Thread Pointer
2058 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2060 if (GV->isDeclaration()) {
2061 MachineFunction &MF = DAG.getMachineFunction();
2062 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2063 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2064 // Initial exec model.
2065 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2066 ARMConstantPoolValue *CPV =
2067 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2068 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2070 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2071 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2072 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2073 MachinePointerInfo::getConstantPool(),
2074 false, false, false, 0);
2075 Chain = Offset.getValue(1);
2077 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2078 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2080 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2081 MachinePointerInfo::getConstantPool(),
2082 false, false, false, 0);
2085 ARMConstantPoolValue *CPV =
2086 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2087 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2088 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2089 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2090 MachinePointerInfo::getConstantPool(),
2091 false, false, false, 0);
2094 // The address of the thread local variable is the add of the thread
2095 // pointer with the offset of the variable.
2096 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2100 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2101 // TODO: implement the "local dynamic" model
2102 assert(Subtarget->isTargetELF() &&
2103 "TLS not implemented for non-ELF targets");
2104 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2105 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2106 // otherwise use the "Local Exec" TLS Model
2107 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2108 return LowerToTLSGeneralDynamicModel(GA, DAG);
2110 return LowerToTLSExecModels(GA, DAG);
2113 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2114 SelectionDAG &DAG) const {
2115 EVT PtrVT = getPointerTy();
2116 DebugLoc dl = Op.getDebugLoc();
2117 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2118 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2119 if (RelocM == Reloc::PIC_) {
2120 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2121 ARMConstantPoolValue *CPV =
2122 ARMConstantPoolConstant::Create(GV,
2123 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2124 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2125 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2126 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2128 MachinePointerInfo::getConstantPool(),
2129 false, false, false, 0);
2130 SDValue Chain = Result.getValue(1);
2131 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2132 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2134 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2135 MachinePointerInfo::getGOT(),
2136 false, false, false, 0);
2140 // If we have T2 ops, we can materialize the address directly via movt/movw
2141 // pair. This is always cheaper.
2142 if (Subtarget->useMovt()) {
2144 // FIXME: Once remat is capable of dealing with instructions with register
2145 // operands, expand this into two nodes.
2146 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2147 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2149 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2150 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2151 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2152 MachinePointerInfo::getConstantPool(),
2153 false, false, false, 0);
2157 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2158 SelectionDAG &DAG) const {
2159 EVT PtrVT = getPointerTy();
2160 DebugLoc dl = Op.getDebugLoc();
2161 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2162 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2163 MachineFunction &MF = DAG.getMachineFunction();
2164 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2166 // FIXME: Enable this for static codegen when tool issues are fixed.
2167 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2169 // FIXME: Once remat is capable of dealing with instructions with register
2170 // operands, expand this into two nodes.
2171 if (RelocM == Reloc::Static)
2172 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2173 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2175 unsigned Wrapper = (RelocM == Reloc::PIC_)
2176 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2177 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2178 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2179 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2180 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2181 MachinePointerInfo::getGOT(),
2182 false, false, false, 0);
2186 unsigned ARMPCLabelIndex = 0;
2188 if (RelocM == Reloc::Static) {
2189 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2191 ARMPCLabelIndex = AFI->createPICLabelUId();
2192 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2193 ARMConstantPoolValue *CPV =
2194 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2196 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2198 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2200 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2201 MachinePointerInfo::getConstantPool(),
2202 false, false, false, 0);
2203 SDValue Chain = Result.getValue(1);
2205 if (RelocM == Reloc::PIC_) {
2206 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2207 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2210 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2211 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2212 false, false, false, 0);
2217 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2218 SelectionDAG &DAG) const {
2219 assert(Subtarget->isTargetELF() &&
2220 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2221 MachineFunction &MF = DAG.getMachineFunction();
2222 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2223 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2224 EVT PtrVT = getPointerTy();
2225 DebugLoc dl = Op.getDebugLoc();
2226 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2227 ARMConstantPoolValue *CPV =
2228 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2229 ARMPCLabelIndex, PCAdj);
2230 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2231 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2232 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2233 MachinePointerInfo::getConstantPool(),
2234 false, false, false, 0);
2235 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2236 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2240 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2241 DebugLoc dl = Op.getDebugLoc();
2242 SDValue Val = DAG.getConstant(0, MVT::i32);
2243 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2244 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2245 Op.getOperand(1), Val);
2249 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2250 DebugLoc dl = Op.getDebugLoc();
2251 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2252 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2256 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2257 const ARMSubtarget *Subtarget) const {
2258 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2259 DebugLoc dl = Op.getDebugLoc();
2261 default: return SDValue(); // Don't custom lower most intrinsics.
2262 case Intrinsic::arm_thread_pointer: {
2263 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2264 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2266 case Intrinsic::eh_sjlj_lsda: {
2267 MachineFunction &MF = DAG.getMachineFunction();
2268 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2269 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2270 EVT PtrVT = getPointerTy();
2271 DebugLoc dl = Op.getDebugLoc();
2272 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2274 unsigned PCAdj = (RelocM != Reloc::PIC_)
2275 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2276 ARMConstantPoolValue *CPV =
2277 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2278 ARMCP::CPLSDA, PCAdj);
2279 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2280 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2282 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2283 MachinePointerInfo::getConstantPool(),
2284 false, false, false, 0);
2286 if (RelocM == Reloc::PIC_) {
2287 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2288 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2292 case Intrinsic::arm_neon_vmulls:
2293 case Intrinsic::arm_neon_vmullu: {
2294 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2295 ? ARMISD::VMULLs : ARMISD::VMULLu;
2296 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2297 Op.getOperand(1), Op.getOperand(2));
2302 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2303 const ARMSubtarget *Subtarget) {
2304 DebugLoc dl = Op.getDebugLoc();
2305 if (!Subtarget->hasDataBarrier()) {
2306 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2307 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2309 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2310 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2311 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2312 DAG.getConstant(0, MVT::i32));
2315 SDValue Op5 = Op.getOperand(5);
2316 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2317 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2318 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2319 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2321 ARM_MB::MemBOpt DMBOpt;
2322 if (isDeviceBarrier)
2323 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2325 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2326 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2327 DAG.getConstant(DMBOpt, MVT::i32));
2331 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2332 const ARMSubtarget *Subtarget) {
2333 // FIXME: handle "fence singlethread" more efficiently.
2334 DebugLoc dl = Op.getDebugLoc();
2335 if (!Subtarget->hasDataBarrier()) {
2336 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2337 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2339 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2340 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2341 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2342 DAG.getConstant(0, MVT::i32));
2345 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2346 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2349 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2350 const ARMSubtarget *Subtarget) {
2351 // ARM pre v5TE and Thumb1 does not have preload instructions.
2352 if (!(Subtarget->isThumb2() ||
2353 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2354 // Just preserve the chain.
2355 return Op.getOperand(0);
2357 DebugLoc dl = Op.getDebugLoc();
2358 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2360 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2361 // ARMv7 with MP extension has PLDW.
2362 return Op.getOperand(0);
2364 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2365 if (Subtarget->isThumb()) {
2367 isRead = ~isRead & 1;
2368 isData = ~isData & 1;
2371 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2372 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2373 DAG.getConstant(isData, MVT::i32));
2376 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2377 MachineFunction &MF = DAG.getMachineFunction();
2378 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2380 // vastart just stores the address of the VarArgsFrameIndex slot into the
2381 // memory location argument.
2382 DebugLoc dl = Op.getDebugLoc();
2383 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2384 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2385 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2386 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2387 MachinePointerInfo(SV), false, false, 0);
2391 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2392 SDValue &Root, SelectionDAG &DAG,
2393 DebugLoc dl) const {
2394 MachineFunction &MF = DAG.getMachineFunction();
2395 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2397 TargetRegisterClass *RC;
2398 if (AFI->isThumb1OnlyFunction())
2399 RC = ARM::tGPRRegisterClass;
2401 RC = ARM::GPRRegisterClass;
2403 // Transform the arguments stored in physical registers into virtual ones.
2404 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2405 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2408 if (NextVA.isMemLoc()) {
2409 MachineFrameInfo *MFI = MF.getFrameInfo();
2410 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2412 // Create load node to retrieve arguments from the stack.
2413 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2414 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2415 MachinePointerInfo::getFixedStack(FI),
2416 false, false, false, 0);
2418 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2419 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2422 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2426 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2427 unsigned &VARegSize, unsigned &VARegSaveSize)
2430 if (CCInfo.isFirstByValRegValid())
2431 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2433 unsigned int firstUnalloced;
2434 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2435 sizeof(GPRArgRegs) /
2436 sizeof(GPRArgRegs[0]));
2437 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2440 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2441 VARegSize = NumGPRs * 4;
2442 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2445 // The remaining GPRs hold either the beginning of variable-argument
2446 // data, or the beginning of an aggregate passed by value (usuall
2447 // byval). Either way, we allocate stack slots adjacent to the data
2448 // provided by our caller, and store the unallocated registers there.
2449 // If this is a variadic function, the va_list pointer will begin with
2450 // these values; otherwise, this reassembles a (byval) structure that
2451 // was split between registers and memory.
2453 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2454 DebugLoc dl, SDValue &Chain,
2455 unsigned ArgOffset) const {
2456 MachineFunction &MF = DAG.getMachineFunction();
2457 MachineFrameInfo *MFI = MF.getFrameInfo();
2458 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2459 unsigned firstRegToSaveIndex;
2460 if (CCInfo.isFirstByValRegValid())
2461 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2463 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2464 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2467 unsigned VARegSize, VARegSaveSize;
2468 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2469 if (VARegSaveSize) {
2470 // If this function is vararg, store any remaining integer argument regs
2471 // to their spots on the stack so that they may be loaded by deferencing
2472 // the result of va_next.
2473 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2474 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2475 ArgOffset + VARegSaveSize
2478 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2481 SmallVector<SDValue, 4> MemOps;
2482 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2483 TargetRegisterClass *RC;
2484 if (AFI->isThumb1OnlyFunction())
2485 RC = ARM::tGPRRegisterClass;
2487 RC = ARM::GPRRegisterClass;
2489 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2490 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2492 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2493 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2495 MemOps.push_back(Store);
2496 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2497 DAG.getConstant(4, getPointerTy()));
2499 if (!MemOps.empty())
2500 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2501 &MemOps[0], MemOps.size());
2503 // This will point to the next argument passed via stack.
2504 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2508 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2509 CallingConv::ID CallConv, bool isVarArg,
2510 const SmallVectorImpl<ISD::InputArg>
2512 DebugLoc dl, SelectionDAG &DAG,
2513 SmallVectorImpl<SDValue> &InVals)
2515 MachineFunction &MF = DAG.getMachineFunction();
2516 MachineFrameInfo *MFI = MF.getFrameInfo();
2518 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2520 // Assign locations to all of the incoming arguments.
2521 SmallVector<CCValAssign, 16> ArgLocs;
2522 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2523 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2524 CCInfo.AnalyzeFormalArguments(Ins,
2525 CCAssignFnForNode(CallConv, /* Return*/ false,
2528 SmallVector<SDValue, 16> ArgValues;
2529 int lastInsIndex = -1;
2532 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2533 CCValAssign &VA = ArgLocs[i];
2535 // Arguments stored in registers.
2536 if (VA.isRegLoc()) {
2537 EVT RegVT = VA.getLocVT();
2539 if (VA.needsCustom()) {
2540 // f64 and vector types are split up into multiple registers or
2541 // combinations of registers and stack slots.
2542 if (VA.getLocVT() == MVT::v2f64) {
2543 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2545 VA = ArgLocs[++i]; // skip ahead to next loc
2547 if (VA.isMemLoc()) {
2548 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2549 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2550 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2551 MachinePointerInfo::getFixedStack(FI),
2552 false, false, false, 0);
2554 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2557 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2558 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2559 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2560 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2561 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2563 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2566 TargetRegisterClass *RC;
2568 if (RegVT == MVT::f32)
2569 RC = ARM::SPRRegisterClass;
2570 else if (RegVT == MVT::f64)
2571 RC = ARM::DPRRegisterClass;
2572 else if (RegVT == MVT::v2f64)
2573 RC = ARM::QPRRegisterClass;
2574 else if (RegVT == MVT::i32)
2575 RC = (AFI->isThumb1OnlyFunction() ?
2576 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2578 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2580 // Transform the arguments in physical registers into virtual ones.
2581 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2582 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2585 // If this is an 8 or 16-bit value, it is really passed promoted
2586 // to 32 bits. Insert an assert[sz]ext to capture this, then
2587 // truncate to the right size.
2588 switch (VA.getLocInfo()) {
2589 default: llvm_unreachable("Unknown loc info!");
2590 case CCValAssign::Full: break;
2591 case CCValAssign::BCvt:
2592 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2594 case CCValAssign::SExt:
2595 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2596 DAG.getValueType(VA.getValVT()));
2597 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2599 case CCValAssign::ZExt:
2600 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2601 DAG.getValueType(VA.getValVT()));
2602 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2606 InVals.push_back(ArgValue);
2608 } else { // VA.isRegLoc()
2611 assert(VA.isMemLoc());
2612 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2614 int index = ArgLocs[i].getValNo();
2616 // Some Ins[] entries become multiple ArgLoc[] entries.
2617 // Process them only once.
2618 if (index != lastInsIndex)
2620 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2621 // FIXME: For now, all byval parameter objects are marked mutable.
2622 // This can be changed with more analysis.
2623 // In case of tail call optimization mark all arguments mutable.
2624 // Since they could be overwritten by lowering of arguments in case of
2626 if (Flags.isByVal()) {
2627 unsigned VARegSize, VARegSaveSize;
2628 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2629 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2630 unsigned Bytes = Flags.getByValSize() - VARegSize;
2631 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2632 int FI = MFI->CreateFixedObject(Bytes,
2633 VA.getLocMemOffset(), false);
2634 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2636 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2637 VA.getLocMemOffset(), true);
2639 // Create load nodes to retrieve arguments from the stack.
2640 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2641 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2642 MachinePointerInfo::getFixedStack(FI),
2643 false, false, false, 0));
2645 lastInsIndex = index;
2652 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2657 /// isFloatingPointZero - Return true if this is +0.0.
2658 static bool isFloatingPointZero(SDValue Op) {
2659 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2660 return CFP->getValueAPF().isPosZero();
2661 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2662 // Maybe this has already been legalized into the constant pool?
2663 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2664 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2665 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2666 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2667 return CFP->getValueAPF().isPosZero();
2673 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2674 /// the given operands.
2676 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2677 SDValue &ARMcc, SelectionDAG &DAG,
2678 DebugLoc dl) const {
2679 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2680 unsigned C = RHSC->getZExtValue();
2681 if (!isLegalICmpImmediate(C)) {
2682 // Constant does not fit, try adjusting it by one?
2687 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2688 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2689 RHS = DAG.getConstant(C-1, MVT::i32);
2694 if (C != 0 && isLegalICmpImmediate(C-1)) {
2695 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2696 RHS = DAG.getConstant(C-1, MVT::i32);
2701 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2702 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2703 RHS = DAG.getConstant(C+1, MVT::i32);
2708 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2709 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2710 RHS = DAG.getConstant(C+1, MVT::i32);
2717 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2718 ARMISD::NodeType CompareType;
2721 CompareType = ARMISD::CMP;
2726 CompareType = ARMISD::CMPZ;
2729 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2730 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2733 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2735 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2736 DebugLoc dl) const {
2738 if (!isFloatingPointZero(RHS))
2739 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2741 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2742 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2745 /// duplicateCmp - Glue values can have only one use, so this function
2746 /// duplicates a comparison node.
2748 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2749 unsigned Opc = Cmp.getOpcode();
2750 DebugLoc DL = Cmp.getDebugLoc();
2751 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2752 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2754 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2755 Cmp = Cmp.getOperand(0);
2756 Opc = Cmp.getOpcode();
2757 if (Opc == ARMISD::CMPFP)
2758 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2760 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2761 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2763 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2766 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2767 SDValue Cond = Op.getOperand(0);
2768 SDValue SelectTrue = Op.getOperand(1);
2769 SDValue SelectFalse = Op.getOperand(2);
2770 DebugLoc dl = Op.getDebugLoc();
2774 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2775 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2777 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2778 const ConstantSDNode *CMOVTrue =
2779 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2780 const ConstantSDNode *CMOVFalse =
2781 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2783 if (CMOVTrue && CMOVFalse) {
2784 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2785 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2789 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2791 False = SelectFalse;
2792 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2797 if (True.getNode() && False.getNode()) {
2798 EVT VT = Op.getValueType();
2799 SDValue ARMcc = Cond.getOperand(2);
2800 SDValue CCR = Cond.getOperand(3);
2801 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2802 assert(True.getValueType() == VT);
2803 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2808 return DAG.getSelectCC(dl, Cond,
2809 DAG.getConstant(0, Cond.getValueType()),
2810 SelectTrue, SelectFalse, ISD::SETNE);
2813 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2814 EVT VT = Op.getValueType();
2815 SDValue LHS = Op.getOperand(0);
2816 SDValue RHS = Op.getOperand(1);
2817 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2818 SDValue TrueVal = Op.getOperand(2);
2819 SDValue FalseVal = Op.getOperand(3);
2820 DebugLoc dl = Op.getDebugLoc();
2822 if (LHS.getValueType() == MVT::i32) {
2824 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2825 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2826 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2829 ARMCC::CondCodes CondCode, CondCode2;
2830 FPCCToARMCC(CC, CondCode, CondCode2);
2832 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2833 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2834 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2835 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2837 if (CondCode2 != ARMCC::AL) {
2838 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2839 // FIXME: Needs another CMP because flag can have but one use.
2840 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2841 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2842 Result, TrueVal, ARMcc2, CCR, Cmp2);
2847 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2848 /// to morph to an integer compare sequence.
2849 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2850 const ARMSubtarget *Subtarget) {
2851 SDNode *N = Op.getNode();
2852 if (!N->hasOneUse())
2853 // Otherwise it requires moving the value from fp to integer registers.
2855 if (!N->getNumValues())
2857 EVT VT = Op.getValueType();
2858 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2859 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2860 // vmrs are very slow, e.g. cortex-a8.
2863 if (isFloatingPointZero(Op)) {
2867 return ISD::isNormalLoad(N);
2870 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2871 if (isFloatingPointZero(Op))
2872 return DAG.getConstant(0, MVT::i32);
2874 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2875 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2876 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2877 Ld->isVolatile(), Ld->isNonTemporal(),
2878 Ld->isInvariant(), Ld->getAlignment());
2880 llvm_unreachable("Unknown VFP cmp argument!");
2883 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2884 SDValue &RetVal1, SDValue &RetVal2) {
2885 if (isFloatingPointZero(Op)) {
2886 RetVal1 = DAG.getConstant(0, MVT::i32);
2887 RetVal2 = DAG.getConstant(0, MVT::i32);
2891 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2892 SDValue Ptr = Ld->getBasePtr();
2893 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2894 Ld->getChain(), Ptr,
2895 Ld->getPointerInfo(),
2896 Ld->isVolatile(), Ld->isNonTemporal(),
2897 Ld->isInvariant(), Ld->getAlignment());
2899 EVT PtrType = Ptr.getValueType();
2900 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2901 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2902 PtrType, Ptr, DAG.getConstant(4, PtrType));
2903 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2904 Ld->getChain(), NewPtr,
2905 Ld->getPointerInfo().getWithOffset(4),
2906 Ld->isVolatile(), Ld->isNonTemporal(),
2907 Ld->isInvariant(), NewAlign);
2911 llvm_unreachable("Unknown VFP cmp argument!");
2914 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2915 /// f32 and even f64 comparisons to integer ones.
2917 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2918 SDValue Chain = Op.getOperand(0);
2919 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2920 SDValue LHS = Op.getOperand(2);
2921 SDValue RHS = Op.getOperand(3);
2922 SDValue Dest = Op.getOperand(4);
2923 DebugLoc dl = Op.getDebugLoc();
2925 bool SeenZero = false;
2926 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2927 canChangeToInt(RHS, SeenZero, Subtarget) &&
2928 // If one of the operand is zero, it's safe to ignore the NaN case since
2929 // we only care about equality comparisons.
2930 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2931 // If unsafe fp math optimization is enabled and there are no other uses of
2932 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2933 // to an integer comparison.
2934 if (CC == ISD::SETOEQ)
2936 else if (CC == ISD::SETUNE)
2940 if (LHS.getValueType() == MVT::f32) {
2941 LHS = bitcastf32Toi32(LHS, DAG);
2942 RHS = bitcastf32Toi32(RHS, DAG);
2943 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2944 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2945 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2946 Chain, Dest, ARMcc, CCR, Cmp);
2951 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2952 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2953 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2954 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2955 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2956 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2957 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2963 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2964 SDValue Chain = Op.getOperand(0);
2965 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2966 SDValue LHS = Op.getOperand(2);
2967 SDValue RHS = Op.getOperand(3);
2968 SDValue Dest = Op.getOperand(4);
2969 DebugLoc dl = Op.getDebugLoc();
2971 if (LHS.getValueType() == MVT::i32) {
2973 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2974 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2975 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2976 Chain, Dest, ARMcc, CCR, Cmp);
2979 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2981 if (getTargetMachine().Options.UnsafeFPMath &&
2982 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2983 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2984 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2985 if (Result.getNode())
2989 ARMCC::CondCodes CondCode, CondCode2;
2990 FPCCToARMCC(CC, CondCode, CondCode2);
2992 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2993 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2994 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2995 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2996 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2997 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2998 if (CondCode2 != ARMCC::AL) {
2999 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3000 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3001 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3006 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3007 SDValue Chain = Op.getOperand(0);
3008 SDValue Table = Op.getOperand(1);
3009 SDValue Index = Op.getOperand(2);
3010 DebugLoc dl = Op.getDebugLoc();
3012 EVT PTy = getPointerTy();
3013 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3014 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3015 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3016 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3017 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3018 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3019 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3020 if (Subtarget->isThumb2()) {
3021 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3022 // which does another jump to the destination. This also makes it easier
3023 // to translate it to TBB / TBH later.
3024 // FIXME: This might not work if the function is extremely large.
3025 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3026 Addr, Op.getOperand(2), JTI, UId);
3028 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3029 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3030 MachinePointerInfo::getJumpTable(),
3031 false, false, false, 0);
3032 Chain = Addr.getValue(1);
3033 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3034 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3036 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3037 MachinePointerInfo::getJumpTable(),
3038 false, false, false, 0);
3039 Chain = Addr.getValue(1);
3040 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3044 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3045 EVT VT = Op.getValueType();
3046 assert(VT.getVectorElementType() == MVT::i32 && "Unexpected custom lowering");
3048 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3050 return DAG.UnrollVectorOp(Op.getNode());
3053 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3054 EVT VT = Op.getValueType();
3056 return LowerVectorFP_TO_INT(Op, DAG);
3058 DebugLoc dl = Op.getDebugLoc();
3061 switch (Op.getOpcode()) {
3063 assert(0 && "Invalid opcode!");
3064 case ISD::FP_TO_SINT:
3065 Opc = ARMISD::FTOSI;
3067 case ISD::FP_TO_UINT:
3068 Opc = ARMISD::FTOUI;
3071 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3072 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3075 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3076 EVT VT = Op.getValueType();
3077 DebugLoc dl = Op.getDebugLoc();
3079 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3080 if (VT.getVectorElementType() == MVT::f32)
3082 return DAG.UnrollVectorOp(Op.getNode());
3085 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3086 "Invalid type for custom lowering!");
3087 if (VT != MVT::v4f32)
3088 return DAG.UnrollVectorOp(Op.getNode());
3092 switch (Op.getOpcode()) {
3094 assert(0 && "Invalid opcode!");
3095 case ISD::SINT_TO_FP:
3096 CastOpc = ISD::SIGN_EXTEND;
3097 Opc = ISD::SINT_TO_FP;
3099 case ISD::UINT_TO_FP:
3100 CastOpc = ISD::ZERO_EXTEND;
3101 Opc = ISD::UINT_TO_FP;
3105 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3106 return DAG.getNode(Opc, dl, VT, Op);
3109 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3110 EVT VT = Op.getValueType();
3112 return LowerVectorINT_TO_FP(Op, DAG);
3114 DebugLoc dl = Op.getDebugLoc();
3117 switch (Op.getOpcode()) {
3119 assert(0 && "Invalid opcode!");
3120 case ISD::SINT_TO_FP:
3121 Opc = ARMISD::SITOF;
3123 case ISD::UINT_TO_FP:
3124 Opc = ARMISD::UITOF;
3128 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3129 return DAG.getNode(Opc, dl, VT, Op);
3132 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3133 // Implement fcopysign with a fabs and a conditional fneg.
3134 SDValue Tmp0 = Op.getOperand(0);
3135 SDValue Tmp1 = Op.getOperand(1);
3136 DebugLoc dl = Op.getDebugLoc();
3137 EVT VT = Op.getValueType();
3138 EVT SrcVT = Tmp1.getValueType();
3139 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3140 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3141 bool UseNEON = !InGPR && Subtarget->hasNEON();
3144 // Use VBSL to copy the sign bit.
3145 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3146 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3147 DAG.getTargetConstant(EncodedVal, MVT::i32));
3148 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3150 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3151 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3152 DAG.getConstant(32, MVT::i32));
3153 else /*if (VT == MVT::f32)*/
3154 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3155 if (SrcVT == MVT::f32) {
3156 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3158 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3159 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3160 DAG.getConstant(32, MVT::i32));
3161 } else if (VT == MVT::f32)
3162 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3163 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3164 DAG.getConstant(32, MVT::i32));
3165 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3166 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3168 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3170 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3171 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3172 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3174 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3175 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3176 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3177 if (VT == MVT::f32) {
3178 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3179 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3180 DAG.getConstant(0, MVT::i32));
3182 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3188 // Bitcast operand 1 to i32.
3189 if (SrcVT == MVT::f64)
3190 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3191 &Tmp1, 1).getValue(1);
3192 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3194 // Or in the signbit with integer operations.
3195 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3196 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3197 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3198 if (VT == MVT::f32) {
3199 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3200 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3201 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3202 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3205 // f64: Or the high part with signbit and then combine two parts.
3206 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3208 SDValue Lo = Tmp0.getValue(0);
3209 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3210 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3211 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3214 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3215 MachineFunction &MF = DAG.getMachineFunction();
3216 MachineFrameInfo *MFI = MF.getFrameInfo();
3217 MFI->setReturnAddressIsTaken(true);
3219 EVT VT = Op.getValueType();
3220 DebugLoc dl = Op.getDebugLoc();
3221 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3223 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3224 SDValue Offset = DAG.getConstant(4, MVT::i32);
3225 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3226 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3227 MachinePointerInfo(), false, false, false, 0);
3230 // Return LR, which contains the return address. Mark it an implicit live-in.
3231 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3232 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3235 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3236 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3237 MFI->setFrameAddressIsTaken(true);
3239 EVT VT = Op.getValueType();
3240 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3241 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3242 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3243 ? ARM::R7 : ARM::R11;
3244 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3246 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3247 MachinePointerInfo(),
3248 false, false, false, 0);
3252 /// ExpandBITCAST - If the target supports VFP, this function is called to
3253 /// expand a bit convert where either the source or destination type is i64 to
3254 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3255 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3256 /// vectors), since the legalizer won't know what to do with that.
3257 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3259 DebugLoc dl = N->getDebugLoc();
3260 SDValue Op = N->getOperand(0);
3262 // This function is only supposed to be called for i64 types, either as the
3263 // source or destination of the bit convert.
3264 EVT SrcVT = Op.getValueType();
3265 EVT DstVT = N->getValueType(0);
3266 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3267 "ExpandBITCAST called for non-i64 type");
3269 // Turn i64->f64 into VMOVDRR.
3270 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3271 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3272 DAG.getConstant(0, MVT::i32));
3273 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3274 DAG.getConstant(1, MVT::i32));
3275 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3276 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3279 // Turn f64->i64 into VMOVRRD.
3280 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3281 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3282 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3283 // Merge the pieces into a single i64 value.
3284 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3290 /// getZeroVector - Returns a vector of specified type with all zero elements.
3291 /// Zero vectors are used to represent vector negation and in those cases
3292 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3293 /// not support i64 elements, so sometimes the zero vectors will need to be
3294 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3296 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3297 assert(VT.isVector() && "Expected a vector type");
3298 // The canonical modified immediate encoding of a zero vector is....0!
3299 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3300 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3301 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3302 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3305 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3306 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3307 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3308 SelectionDAG &DAG) const {
3309 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3310 EVT VT = Op.getValueType();
3311 unsigned VTBits = VT.getSizeInBits();
3312 DebugLoc dl = Op.getDebugLoc();
3313 SDValue ShOpLo = Op.getOperand(0);
3314 SDValue ShOpHi = Op.getOperand(1);
3315 SDValue ShAmt = Op.getOperand(2);
3317 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3319 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3321 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3322 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3323 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3324 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3325 DAG.getConstant(VTBits, MVT::i32));
3326 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3327 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3328 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3330 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3331 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3333 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3334 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3337 SDValue Ops[2] = { Lo, Hi };
3338 return DAG.getMergeValues(Ops, 2, dl);
3341 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3342 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3343 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3344 SelectionDAG &DAG) const {
3345 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3346 EVT VT = Op.getValueType();
3347 unsigned VTBits = VT.getSizeInBits();
3348 DebugLoc dl = Op.getDebugLoc();
3349 SDValue ShOpLo = Op.getOperand(0);
3350 SDValue ShOpHi = Op.getOperand(1);
3351 SDValue ShAmt = Op.getOperand(2);
3354 assert(Op.getOpcode() == ISD::SHL_PARTS);
3355 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3356 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3357 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3358 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3359 DAG.getConstant(VTBits, MVT::i32));
3360 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3361 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3363 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3364 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3365 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3367 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3368 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3371 SDValue Ops[2] = { Lo, Hi };
3372 return DAG.getMergeValues(Ops, 2, dl);
3375 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3376 SelectionDAG &DAG) const {
3377 // The rounding mode is in bits 23:22 of the FPSCR.
3378 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3379 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3380 // so that the shift + and get folded into a bitfield extract.
3381 DebugLoc dl = Op.getDebugLoc();
3382 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3383 DAG.getConstant(Intrinsic::arm_get_fpscr,
3385 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3386 DAG.getConstant(1U << 22, MVT::i32));
3387 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3388 DAG.getConstant(22, MVT::i32));
3389 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3390 DAG.getConstant(3, MVT::i32));
3393 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3394 const ARMSubtarget *ST) {
3395 EVT VT = N->getValueType(0);
3396 DebugLoc dl = N->getDebugLoc();
3398 if (!ST->hasV6T2Ops())
3401 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3402 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3405 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3406 const ARMSubtarget *ST) {
3407 EVT VT = N->getValueType(0);
3408 DebugLoc dl = N->getDebugLoc();
3413 // Lower vector shifts on NEON to use VSHL.
3414 assert(ST->hasNEON() && "unexpected vector shift");
3416 // Left shifts translate directly to the vshiftu intrinsic.
3417 if (N->getOpcode() == ISD::SHL)
3418 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3419 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3420 N->getOperand(0), N->getOperand(1));
3422 assert((N->getOpcode() == ISD::SRA ||
3423 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3425 // NEON uses the same intrinsics for both left and right shifts. For
3426 // right shifts, the shift amounts are negative, so negate the vector of
3428 EVT ShiftVT = N->getOperand(1).getValueType();
3429 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3430 getZeroVector(ShiftVT, DAG, dl),
3432 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3433 Intrinsic::arm_neon_vshifts :
3434 Intrinsic::arm_neon_vshiftu);
3435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3436 DAG.getConstant(vshiftInt, MVT::i32),
3437 N->getOperand(0), NegatedCount);
3440 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3441 const ARMSubtarget *ST) {
3442 EVT VT = N->getValueType(0);
3443 DebugLoc dl = N->getDebugLoc();
3445 // We can get here for a node like i32 = ISD::SHL i32, i64
3449 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3450 "Unknown shift to lower!");
3452 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3453 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3454 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3457 // If we are in thumb mode, we don't have RRX.
3458 if (ST->isThumb1Only()) return SDValue();
3460 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3461 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3462 DAG.getConstant(0, MVT::i32));
3463 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3464 DAG.getConstant(1, MVT::i32));
3466 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3467 // captures the result into a carry flag.
3468 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3469 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3471 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3472 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3474 // Merge the pieces into a single i64 value.
3475 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3478 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3479 SDValue TmpOp0, TmpOp1;
3480 bool Invert = false;
3484 SDValue Op0 = Op.getOperand(0);
3485 SDValue Op1 = Op.getOperand(1);
3486 SDValue CC = Op.getOperand(2);
3487 EVT VT = Op.getValueType();
3488 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3489 DebugLoc dl = Op.getDebugLoc();
3491 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3492 switch (SetCCOpcode) {
3493 default: llvm_unreachable("Illegal FP comparison"); break;
3495 case ISD::SETNE: Invert = true; // Fallthrough
3497 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3499 case ISD::SETLT: Swap = true; // Fallthrough
3501 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3503 case ISD::SETLE: Swap = true; // Fallthrough
3505 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3506 case ISD::SETUGE: Swap = true; // Fallthrough
3507 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3508 case ISD::SETUGT: Swap = true; // Fallthrough
3509 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3510 case ISD::SETUEQ: Invert = true; // Fallthrough
3512 // Expand this to (OLT | OGT).
3516 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3517 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3519 case ISD::SETUO: Invert = true; // Fallthrough
3521 // Expand this to (OLT | OGE).
3525 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3526 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3530 // Integer comparisons.
3531 switch (SetCCOpcode) {
3532 default: llvm_unreachable("Illegal integer comparison"); break;
3533 case ISD::SETNE: Invert = true;
3534 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3535 case ISD::SETLT: Swap = true;
3536 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3537 case ISD::SETLE: Swap = true;
3538 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3539 case ISD::SETULT: Swap = true;
3540 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3541 case ISD::SETULE: Swap = true;
3542 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3545 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3546 if (Opc == ARMISD::VCEQ) {
3549 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3551 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3554 // Ignore bitconvert.
3555 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3556 AndOp = AndOp.getOperand(0);
3558 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3560 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3561 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3568 std::swap(Op0, Op1);
3570 // If one of the operands is a constant vector zero, attempt to fold the
3571 // comparison to a specialized compare-against-zero form.
3573 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3575 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3576 if (Opc == ARMISD::VCGE)
3577 Opc = ARMISD::VCLEZ;
3578 else if (Opc == ARMISD::VCGT)
3579 Opc = ARMISD::VCLTZ;
3584 if (SingleOp.getNode()) {
3587 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3589 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3591 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3593 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3595 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3597 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3600 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3604 Result = DAG.getNOT(dl, Result, VT);
3609 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3610 /// valid vector constant for a NEON instruction with a "modified immediate"
3611 /// operand (e.g., VMOV). If so, return the encoded value.
3612 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3613 unsigned SplatBitSize, SelectionDAG &DAG,
3614 EVT &VT, bool is128Bits, NEONModImmType type) {
3615 unsigned OpCmode, Imm;
3617 // SplatBitSize is set to the smallest size that splats the vector, so a
3618 // zero vector will always have SplatBitSize == 8. However, NEON modified
3619 // immediate instructions others than VMOV do not support the 8-bit encoding
3620 // of a zero vector, and the default encoding of zero is supposed to be the
3625 switch (SplatBitSize) {
3627 if (type != VMOVModImm)
3629 // Any 1-byte value is OK. Op=0, Cmode=1110.
3630 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3633 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3637 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3638 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3639 if ((SplatBits & ~0xff) == 0) {
3640 // Value = 0x00nn: Op=x, Cmode=100x.
3645 if ((SplatBits & ~0xff00) == 0) {
3646 // Value = 0xnn00: Op=x, Cmode=101x.
3648 Imm = SplatBits >> 8;
3654 // NEON's 32-bit VMOV supports splat values where:
3655 // * only one byte is nonzero, or
3656 // * the least significant byte is 0xff and the second byte is nonzero, or
3657 // * the least significant 2 bytes are 0xff and the third is nonzero.
3658 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3659 if ((SplatBits & ~0xff) == 0) {
3660 // Value = 0x000000nn: Op=x, Cmode=000x.
3665 if ((SplatBits & ~0xff00) == 0) {
3666 // Value = 0x0000nn00: Op=x, Cmode=001x.
3668 Imm = SplatBits >> 8;
3671 if ((SplatBits & ~0xff0000) == 0) {
3672 // Value = 0x00nn0000: Op=x, Cmode=010x.
3674 Imm = SplatBits >> 16;
3677 if ((SplatBits & ~0xff000000) == 0) {
3678 // Value = 0xnn000000: Op=x, Cmode=011x.
3680 Imm = SplatBits >> 24;
3684 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3685 if (type == OtherModImm) return SDValue();
3687 if ((SplatBits & ~0xffff) == 0 &&
3688 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3689 // Value = 0x0000nnff: Op=x, Cmode=1100.
3691 Imm = SplatBits >> 8;
3696 if ((SplatBits & ~0xffffff) == 0 &&
3697 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3698 // Value = 0x00nnffff: Op=x, Cmode=1101.
3700 Imm = SplatBits >> 16;
3701 SplatBits |= 0xffff;
3705 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3706 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3707 // VMOV.I32. A (very) minor optimization would be to replicate the value
3708 // and fall through here to test for a valid 64-bit splat. But, then the
3709 // caller would also need to check and handle the change in size.
3713 if (type != VMOVModImm)
3715 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3716 uint64_t BitMask = 0xff;
3718 unsigned ImmMask = 1;
3720 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3721 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3724 } else if ((SplatBits & BitMask) != 0) {
3730 // Op=1, Cmode=1110.
3733 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3738 llvm_unreachable("unexpected size for isNEONModifiedImm");
3742 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3743 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3746 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3747 bool &ReverseVEXT, unsigned &Imm) {
3748 unsigned NumElts = VT.getVectorNumElements();
3749 ReverseVEXT = false;
3751 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3757 // If this is a VEXT shuffle, the immediate value is the index of the first
3758 // element. The other shuffle indices must be the successive elements after
3760 unsigned ExpectedElt = Imm;
3761 for (unsigned i = 1; i < NumElts; ++i) {
3762 // Increment the expected index. If it wraps around, it may still be
3763 // a VEXT but the source vectors must be swapped.
3765 if (ExpectedElt == NumElts * 2) {
3770 if (M[i] < 0) continue; // ignore UNDEF indices
3771 if (ExpectedElt != static_cast<unsigned>(M[i]))
3775 // Adjust the index value if the source operands will be swapped.
3782 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3783 /// instruction with the specified blocksize. (The order of the elements
3784 /// within each block of the vector is reversed.)
3785 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3786 unsigned BlockSize) {
3787 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3788 "Only possible block sizes for VREV are: 16, 32, 64");
3790 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3794 unsigned NumElts = VT.getVectorNumElements();
3795 unsigned BlockElts = M[0] + 1;
3796 // If the first shuffle index is UNDEF, be optimistic.
3798 BlockElts = BlockSize / EltSz;
3800 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3803 for (unsigned i = 0; i < NumElts; ++i) {
3804 if (M[i] < 0) continue; // ignore UNDEF indices
3805 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3812 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3813 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3814 // range, then 0 is placed into the resulting vector. So pretty much any mask
3815 // of 8 elements can work here.
3816 return VT == MVT::v8i8 && M.size() == 8;
3819 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3820 unsigned &WhichResult) {
3821 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3825 unsigned NumElts = VT.getVectorNumElements();
3826 WhichResult = (M[0] == 0 ? 0 : 1);
3827 for (unsigned i = 0; i < NumElts; i += 2) {
3828 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3829 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3835 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3836 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3837 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3838 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3839 unsigned &WhichResult) {
3840 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3844 unsigned NumElts = VT.getVectorNumElements();
3845 WhichResult = (M[0] == 0 ? 0 : 1);
3846 for (unsigned i = 0; i < NumElts; i += 2) {
3847 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3848 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3854 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3855 unsigned &WhichResult) {
3856 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3860 unsigned NumElts = VT.getVectorNumElements();
3861 WhichResult = (M[0] == 0 ? 0 : 1);
3862 for (unsigned i = 0; i != NumElts; ++i) {
3863 if (M[i] < 0) continue; // ignore UNDEF indices
3864 if ((unsigned) M[i] != 2 * i + WhichResult)
3868 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3869 if (VT.is64BitVector() && EltSz == 32)
3875 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3876 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3877 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3878 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3879 unsigned &WhichResult) {
3880 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3884 unsigned Half = VT.getVectorNumElements() / 2;
3885 WhichResult = (M[0] == 0 ? 0 : 1);
3886 for (unsigned j = 0; j != 2; ++j) {
3887 unsigned Idx = WhichResult;
3888 for (unsigned i = 0; i != Half; ++i) {
3889 int MIdx = M[i + j * Half];
3890 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3896 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3897 if (VT.is64BitVector() && EltSz == 32)
3903 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3904 unsigned &WhichResult) {
3905 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3909 unsigned NumElts = VT.getVectorNumElements();
3910 WhichResult = (M[0] == 0 ? 0 : 1);
3911 unsigned Idx = WhichResult * NumElts / 2;
3912 for (unsigned i = 0; i != NumElts; i += 2) {
3913 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3914 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3919 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3920 if (VT.is64BitVector() && EltSz == 32)
3926 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3927 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3928 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3929 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3930 unsigned &WhichResult) {
3931 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3935 unsigned NumElts = VT.getVectorNumElements();
3936 WhichResult = (M[0] == 0 ? 0 : 1);
3937 unsigned Idx = WhichResult * NumElts / 2;
3938 for (unsigned i = 0; i != NumElts; i += 2) {
3939 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3940 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3945 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3946 if (VT.is64BitVector() && EltSz == 32)
3952 // If N is an integer constant that can be moved into a register in one
3953 // instruction, return an SDValue of such a constant (will become a MOV
3954 // instruction). Otherwise return null.
3955 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3956 const ARMSubtarget *ST, DebugLoc dl) {
3958 if (!isa<ConstantSDNode>(N))
3960 Val = cast<ConstantSDNode>(N)->getZExtValue();
3962 if (ST->isThumb1Only()) {
3963 if (Val <= 255 || ~Val <= 255)
3964 return DAG.getConstant(Val, MVT::i32);
3966 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3967 return DAG.getConstant(Val, MVT::i32);
3972 // If this is a case we can't handle, return null and let the default
3973 // expansion code take care of it.
3974 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3975 const ARMSubtarget *ST) const {
3976 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3977 DebugLoc dl = Op.getDebugLoc();
3978 EVT VT = Op.getValueType();
3980 APInt SplatBits, SplatUndef;
3981 unsigned SplatBitSize;
3983 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3984 if (SplatBitSize <= 64) {
3985 // Check if an immediate VMOV works.
3987 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3988 SplatUndef.getZExtValue(), SplatBitSize,
3989 DAG, VmovVT, VT.is128BitVector(),
3991 if (Val.getNode()) {
3992 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3993 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3996 // Try an immediate VMVN.
3997 uint64_t NegatedImm = (~SplatBits).getZExtValue();
3998 Val = isNEONModifiedImm(NegatedImm,
3999 SplatUndef.getZExtValue(), SplatBitSize,
4000 DAG, VmovVT, VT.is128BitVector(),
4002 if (Val.getNode()) {
4003 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4004 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4007 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4008 if (VT == MVT::v2f32 || VT == MVT::v4f32) {
4009 ConstantFPSDNode *C = cast<ConstantFPSDNode>(Op.getOperand(0));
4010 int ImmVal = ARM_AM::getFP32Imm(C->getValueAPF());
4012 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4013 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4019 // Scan through the operands to see if only one value is used.
4020 unsigned NumElts = VT.getVectorNumElements();
4021 bool isOnlyLowElement = true;
4022 bool usesOnlyOneValue = true;
4023 bool isConstant = true;
4025 for (unsigned i = 0; i < NumElts; ++i) {
4026 SDValue V = Op.getOperand(i);
4027 if (V.getOpcode() == ISD::UNDEF)
4030 isOnlyLowElement = false;
4031 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4034 if (!Value.getNode())
4036 else if (V != Value)
4037 usesOnlyOneValue = false;
4040 if (!Value.getNode())
4041 return DAG.getUNDEF(VT);
4043 if (isOnlyLowElement)
4044 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4046 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4048 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
4049 // i32 and try again.
4050 if (usesOnlyOneValue && EltSize <= 32) {
4052 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4053 if (VT.getVectorElementType().isFloatingPoint()) {
4054 SmallVector<SDValue, 8> Ops;
4055 for (unsigned i = 0; i < NumElts; ++i)
4056 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4058 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4059 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4060 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4062 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4064 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4066 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4069 // If all elements are constants and the case above didn't get hit, fall back
4070 // to the default expansion, which will generate a load from the constant
4075 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4077 SDValue shuffle = ReconstructShuffle(Op, DAG);
4078 if (shuffle != SDValue())
4082 // Vectors with 32- or 64-bit elements can be built by directly assigning
4083 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4084 // will be legalized.
4085 if (EltSize >= 32) {
4086 // Do the expansion with floating-point types, since that is what the VFP
4087 // registers are defined to use, and since i64 is not legal.
4088 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4089 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4090 SmallVector<SDValue, 8> Ops;
4091 for (unsigned i = 0; i < NumElts; ++i)
4092 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4093 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4094 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4100 // Gather data to see if the operation can be modelled as a
4101 // shuffle in combination with VEXTs.
4102 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4103 SelectionDAG &DAG) const {
4104 DebugLoc dl = Op.getDebugLoc();
4105 EVT VT = Op.getValueType();
4106 unsigned NumElts = VT.getVectorNumElements();
4108 SmallVector<SDValue, 2> SourceVecs;
4109 SmallVector<unsigned, 2> MinElts;
4110 SmallVector<unsigned, 2> MaxElts;
4112 for (unsigned i = 0; i < NumElts; ++i) {
4113 SDValue V = Op.getOperand(i);
4114 if (V.getOpcode() == ISD::UNDEF)
4116 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4117 // A shuffle can only come from building a vector from various
4118 // elements of other vectors.
4120 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4121 VT.getVectorElementType()) {
4122 // This code doesn't know how to handle shuffles where the vector
4123 // element types do not match (this happens because type legalization
4124 // promotes the return type of EXTRACT_VECTOR_ELT).
4125 // FIXME: It might be appropriate to extend this code to handle
4126 // mismatched types.
4130 // Record this extraction against the appropriate vector if possible...
4131 SDValue SourceVec = V.getOperand(0);
4132 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4133 bool FoundSource = false;
4134 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4135 if (SourceVecs[j] == SourceVec) {
4136 if (MinElts[j] > EltNo)
4138 if (MaxElts[j] < EltNo)
4145 // Or record a new source if not...
4147 SourceVecs.push_back(SourceVec);
4148 MinElts.push_back(EltNo);
4149 MaxElts.push_back(EltNo);
4153 // Currently only do something sane when at most two source vectors
4155 if (SourceVecs.size() > 2)
4158 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4159 int VEXTOffsets[2] = {0, 0};
4161 // This loop extracts the usage patterns of the source vectors
4162 // and prepares appropriate SDValues for a shuffle if possible.
4163 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4164 if (SourceVecs[i].getValueType() == VT) {
4165 // No VEXT necessary
4166 ShuffleSrcs[i] = SourceVecs[i];
4169 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4170 // It probably isn't worth padding out a smaller vector just to
4171 // break it down again in a shuffle.
4175 // Since only 64-bit and 128-bit vectors are legal on ARM and
4176 // we've eliminated the other cases...
4177 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4178 "unexpected vector sizes in ReconstructShuffle");
4180 if (MaxElts[i] - MinElts[i] >= NumElts) {
4181 // Span too large for a VEXT to cope
4185 if (MinElts[i] >= NumElts) {
4186 // The extraction can just take the second half
4187 VEXTOffsets[i] = NumElts;
4188 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4190 DAG.getIntPtrConstant(NumElts));
4191 } else if (MaxElts[i] < NumElts) {
4192 // The extraction can just take the first half
4194 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4196 DAG.getIntPtrConstant(0));
4198 // An actual VEXT is needed
4199 VEXTOffsets[i] = MinElts[i];
4200 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4202 DAG.getIntPtrConstant(0));
4203 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4205 DAG.getIntPtrConstant(NumElts));
4206 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4207 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4211 SmallVector<int, 8> Mask;
4213 for (unsigned i = 0; i < NumElts; ++i) {
4214 SDValue Entry = Op.getOperand(i);
4215 if (Entry.getOpcode() == ISD::UNDEF) {
4220 SDValue ExtractVec = Entry.getOperand(0);
4221 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4222 .getOperand(1))->getSExtValue();
4223 if (ExtractVec == SourceVecs[0]) {
4224 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4226 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4230 // Final check before we try to produce nonsense...
4231 if (isShuffleMaskLegal(Mask, VT))
4232 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4238 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4239 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4240 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4241 /// are assumed to be legal.
4243 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4245 if (VT.getVectorNumElements() == 4 &&
4246 (VT.is128BitVector() || VT.is64BitVector())) {
4247 unsigned PFIndexes[4];
4248 for (unsigned i = 0; i != 4; ++i) {
4252 PFIndexes[i] = M[i];
4255 // Compute the index in the perfect shuffle table.
4256 unsigned PFTableIndex =
4257 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4258 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4259 unsigned Cost = (PFEntry >> 30);
4266 unsigned Imm, WhichResult;
4268 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4269 return (EltSize >= 32 ||
4270 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4271 isVREVMask(M, VT, 64) ||
4272 isVREVMask(M, VT, 32) ||
4273 isVREVMask(M, VT, 16) ||
4274 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4275 isVTBLMask(M, VT) ||
4276 isVTRNMask(M, VT, WhichResult) ||
4277 isVUZPMask(M, VT, WhichResult) ||
4278 isVZIPMask(M, VT, WhichResult) ||
4279 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4280 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4281 isVZIP_v_undef_Mask(M, VT, WhichResult));
4284 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4285 /// the specified operations to build the shuffle.
4286 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4287 SDValue RHS, SelectionDAG &DAG,
4289 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4290 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4291 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4294 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4303 OP_VUZPL, // VUZP, left result
4304 OP_VUZPR, // VUZP, right result
4305 OP_VZIPL, // VZIP, left result
4306 OP_VZIPR, // VZIP, right result
4307 OP_VTRNL, // VTRN, left result
4308 OP_VTRNR // VTRN, right result
4311 if (OpNum == OP_COPY) {
4312 if (LHSID == (1*9+2)*9+3) return LHS;
4313 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4317 SDValue OpLHS, OpRHS;
4318 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4319 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4320 EVT VT = OpLHS.getValueType();
4323 default: llvm_unreachable("Unknown shuffle opcode!");
4325 // VREV divides the vector in half and swaps within the half.
4326 if (VT.getVectorElementType() == MVT::i32 ||
4327 VT.getVectorElementType() == MVT::f32)
4328 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4329 // vrev <4 x i16> -> VREV32
4330 if (VT.getVectorElementType() == MVT::i16)
4331 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4332 // vrev <4 x i8> -> VREV16
4333 assert(VT.getVectorElementType() == MVT::i8);
4334 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4339 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4340 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4344 return DAG.getNode(ARMISD::VEXT, dl, VT,
4346 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4349 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4350 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4353 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4354 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4357 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4358 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4362 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4363 SmallVectorImpl<int> &ShuffleMask,
4364 SelectionDAG &DAG) {
4365 // Check to see if we can use the VTBL instruction.
4366 SDValue V1 = Op.getOperand(0);
4367 SDValue V2 = Op.getOperand(1);
4368 DebugLoc DL = Op.getDebugLoc();
4370 SmallVector<SDValue, 8> VTBLMask;
4371 for (SmallVectorImpl<int>::iterator
4372 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4373 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4375 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4376 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4377 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4380 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4381 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4385 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4386 SDValue V1 = Op.getOperand(0);
4387 SDValue V2 = Op.getOperand(1);
4388 DebugLoc dl = Op.getDebugLoc();
4389 EVT VT = Op.getValueType();
4390 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4391 SmallVector<int, 8> ShuffleMask;
4393 // Convert shuffles that are directly supported on NEON to target-specific
4394 // DAG nodes, instead of keeping them as shuffles and matching them again
4395 // during code selection. This is more efficient and avoids the possibility
4396 // of inconsistencies between legalization and selection.
4397 // FIXME: floating-point vectors should be canonicalized to integer vectors
4398 // of the same time so that they get CSEd properly.
4399 SVN->getMask(ShuffleMask);
4401 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4402 if (EltSize <= 32) {
4403 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4404 int Lane = SVN->getSplatIndex();
4405 // If this is undef splat, generate it via "just" vdup, if possible.
4406 if (Lane == -1) Lane = 0;
4408 // Test if V1 is a SCALAR_TO_VECTOR.
4409 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4410 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4412 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
4413 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
4415 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4416 !isa<ConstantSDNode>(V1.getOperand(0))) {
4417 bool IsScalarToVector = true;
4418 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
4419 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
4420 IsScalarToVector = false;
4423 if (IsScalarToVector)
4424 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4426 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4427 DAG.getConstant(Lane, MVT::i32));
4432 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4435 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4436 DAG.getConstant(Imm, MVT::i32));
4439 if (isVREVMask(ShuffleMask, VT, 64))
4440 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4441 if (isVREVMask(ShuffleMask, VT, 32))
4442 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4443 if (isVREVMask(ShuffleMask, VT, 16))
4444 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4446 // Check for Neon shuffles that modify both input vectors in place.
4447 // If both results are used, i.e., if there are two shuffles with the same
4448 // source operands and with masks corresponding to both results of one of
4449 // these operations, DAG memoization will ensure that a single node is
4450 // used for both shuffles.
4451 unsigned WhichResult;
4452 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4453 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4454 V1, V2).getValue(WhichResult);
4455 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4456 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4457 V1, V2).getValue(WhichResult);
4458 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4459 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4460 V1, V2).getValue(WhichResult);
4462 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4463 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4464 V1, V1).getValue(WhichResult);
4465 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4466 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4467 V1, V1).getValue(WhichResult);
4468 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4469 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4470 V1, V1).getValue(WhichResult);
4473 // If the shuffle is not directly supported and it has 4 elements, use
4474 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4475 unsigned NumElts = VT.getVectorNumElements();
4477 unsigned PFIndexes[4];
4478 for (unsigned i = 0; i != 4; ++i) {
4479 if (ShuffleMask[i] < 0)
4482 PFIndexes[i] = ShuffleMask[i];
4485 // Compute the index in the perfect shuffle table.
4486 unsigned PFTableIndex =
4487 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4488 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4489 unsigned Cost = (PFEntry >> 30);
4492 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4495 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4496 if (EltSize >= 32) {
4497 // Do the expansion with floating-point types, since that is what the VFP
4498 // registers are defined to use, and since i64 is not legal.
4499 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4500 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4501 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4502 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4503 SmallVector<SDValue, 8> Ops;
4504 for (unsigned i = 0; i < NumElts; ++i) {
4505 if (ShuffleMask[i] < 0)
4506 Ops.push_back(DAG.getUNDEF(EltVT));
4508 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4509 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4510 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4513 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4514 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4517 if (VT == MVT::v8i8) {
4518 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4519 if (NewOp.getNode())
4526 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4527 // INSERT_VECTOR_ELT is legal only for immediate indexes.
4528 SDValue Lane = Op.getOperand(2);
4529 if (!isa<ConstantSDNode>(Lane))
4535 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4536 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4537 SDValue Lane = Op.getOperand(1);
4538 if (!isa<ConstantSDNode>(Lane))
4541 SDValue Vec = Op.getOperand(0);
4542 if (Op.getValueType() == MVT::i32 &&
4543 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4544 DebugLoc dl = Op.getDebugLoc();
4545 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4551 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4552 // The only time a CONCAT_VECTORS operation can have legal types is when
4553 // two 64-bit vectors are concatenated to a 128-bit vector.
4554 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4555 "unexpected CONCAT_VECTORS");
4556 DebugLoc dl = Op.getDebugLoc();
4557 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4558 SDValue Op0 = Op.getOperand(0);
4559 SDValue Op1 = Op.getOperand(1);
4560 if (Op0.getOpcode() != ISD::UNDEF)
4561 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4562 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4563 DAG.getIntPtrConstant(0));
4564 if (Op1.getOpcode() != ISD::UNDEF)
4565 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4566 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4567 DAG.getIntPtrConstant(1));
4568 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4571 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4572 /// element has been zero/sign-extended, depending on the isSigned parameter,
4573 /// from an integer type half its size.
4574 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4576 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4577 EVT VT = N->getValueType(0);
4578 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4579 SDNode *BVN = N->getOperand(0).getNode();
4580 if (BVN->getValueType(0) != MVT::v4i32 ||
4581 BVN->getOpcode() != ISD::BUILD_VECTOR)
4583 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4584 unsigned HiElt = 1 - LoElt;
4585 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4586 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4587 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4588 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4589 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4592 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4593 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4596 if (Hi0->isNullValue() && Hi1->isNullValue())
4602 if (N->getOpcode() != ISD::BUILD_VECTOR)
4605 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4606 SDNode *Elt = N->getOperand(i).getNode();
4607 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4608 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4609 unsigned HalfSize = EltSize / 2;
4611 if (!isIntN(HalfSize, C->getSExtValue()))
4614 if (!isUIntN(HalfSize, C->getZExtValue()))
4625 /// isSignExtended - Check if a node is a vector value that is sign-extended
4626 /// or a constant BUILD_VECTOR with sign-extended elements.
4627 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4628 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4630 if (isExtendedBUILD_VECTOR(N, DAG, true))
4635 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4636 /// or a constant BUILD_VECTOR with zero-extended elements.
4637 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4638 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4640 if (isExtendedBUILD_VECTOR(N, DAG, false))
4645 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4646 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4647 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4648 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4649 return N->getOperand(0);
4650 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4651 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4652 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4653 LD->isNonTemporal(), LD->isInvariant(),
4654 LD->getAlignment());
4655 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4656 // have been legalized as a BITCAST from v4i32.
4657 if (N->getOpcode() == ISD::BITCAST) {
4658 SDNode *BVN = N->getOperand(0).getNode();
4659 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4660 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4661 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4662 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4663 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4665 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4666 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4667 EVT VT = N->getValueType(0);
4668 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4669 unsigned NumElts = VT.getVectorNumElements();
4670 MVT TruncVT = MVT::getIntegerVT(EltSize);
4671 SmallVector<SDValue, 8> Ops;
4672 for (unsigned i = 0; i != NumElts; ++i) {
4673 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4674 const APInt &CInt = C->getAPIntValue();
4675 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4677 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4678 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4681 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4682 unsigned Opcode = N->getOpcode();
4683 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4684 SDNode *N0 = N->getOperand(0).getNode();
4685 SDNode *N1 = N->getOperand(1).getNode();
4686 return N0->hasOneUse() && N1->hasOneUse() &&
4687 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4692 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4693 unsigned Opcode = N->getOpcode();
4694 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4695 SDNode *N0 = N->getOperand(0).getNode();
4696 SDNode *N1 = N->getOperand(1).getNode();
4697 return N0->hasOneUse() && N1->hasOneUse() &&
4698 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4703 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4704 // Multiplications are only custom-lowered for 128-bit vectors so that
4705 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4706 EVT VT = Op.getValueType();
4707 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4708 SDNode *N0 = Op.getOperand(0).getNode();
4709 SDNode *N1 = Op.getOperand(1).getNode();
4710 unsigned NewOpc = 0;
4712 bool isN0SExt = isSignExtended(N0, DAG);
4713 bool isN1SExt = isSignExtended(N1, DAG);
4714 if (isN0SExt && isN1SExt)
4715 NewOpc = ARMISD::VMULLs;
4717 bool isN0ZExt = isZeroExtended(N0, DAG);
4718 bool isN1ZExt = isZeroExtended(N1, DAG);
4719 if (isN0ZExt && isN1ZExt)
4720 NewOpc = ARMISD::VMULLu;
4721 else if (isN1SExt || isN1ZExt) {
4722 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4723 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4724 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4725 NewOpc = ARMISD::VMULLs;
4727 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4728 NewOpc = ARMISD::VMULLu;
4730 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4732 NewOpc = ARMISD::VMULLu;
4738 if (VT == MVT::v2i64)
4739 // Fall through to expand this. It is not legal.
4742 // Other vector multiplications are legal.
4747 // Legalize to a VMULL instruction.
4748 DebugLoc DL = Op.getDebugLoc();
4750 SDValue Op1 = SkipExtension(N1, DAG);
4752 Op0 = SkipExtension(N0, DAG);
4753 assert(Op0.getValueType().is64BitVector() &&
4754 Op1.getValueType().is64BitVector() &&
4755 "unexpected types for extended operands to VMULL");
4756 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4759 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4760 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4767 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4768 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4769 EVT Op1VT = Op1.getValueType();
4770 return DAG.getNode(N0->getOpcode(), DL, VT,
4771 DAG.getNode(NewOpc, DL, VT,
4772 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4773 DAG.getNode(NewOpc, DL, VT,
4774 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4778 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4780 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4781 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4782 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4783 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4784 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4785 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4786 // Get reciprocal estimate.
4787 // float4 recip = vrecpeq_f32(yf);
4788 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4789 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4790 // Because char has a smaller range than uchar, we can actually get away
4791 // without any newton steps. This requires that we use a weird bias
4792 // of 0xb000, however (again, this has been exhaustively tested).
4793 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4794 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4795 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4796 Y = DAG.getConstant(0xb000, MVT::i32);
4797 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4798 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4799 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4800 // Convert back to short.
4801 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4802 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4807 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4809 // Convert to float.
4810 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4811 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4812 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4813 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4814 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4815 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4817 // Use reciprocal estimate and one refinement step.
4818 // float4 recip = vrecpeq_f32(yf);
4819 // recip *= vrecpsq_f32(yf, recip);
4820 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4821 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4822 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4823 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4825 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4826 // Because short has a smaller range than ushort, we can actually get away
4827 // with only a single newton step. This requires that we use a weird bias
4828 // of 89, however (again, this has been exhaustively tested).
4829 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4830 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4831 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4832 N1 = DAG.getConstant(0x89, MVT::i32);
4833 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4834 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4835 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4836 // Convert back to integer and return.
4837 // return vmovn_s32(vcvt_s32_f32(result));
4838 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4839 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4843 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4844 EVT VT = Op.getValueType();
4845 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4846 "unexpected type for custom-lowering ISD::SDIV");
4848 DebugLoc dl = Op.getDebugLoc();
4849 SDValue N0 = Op.getOperand(0);
4850 SDValue N1 = Op.getOperand(1);
4853 if (VT == MVT::v8i8) {
4854 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4855 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4857 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4858 DAG.getIntPtrConstant(4));
4859 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4860 DAG.getIntPtrConstant(4));
4861 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4862 DAG.getIntPtrConstant(0));
4863 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4864 DAG.getIntPtrConstant(0));
4866 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4867 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4869 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4870 N0 = LowerCONCAT_VECTORS(N0, DAG);
4872 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4875 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4878 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4879 EVT VT = Op.getValueType();
4880 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4881 "unexpected type for custom-lowering ISD::UDIV");
4883 DebugLoc dl = Op.getDebugLoc();
4884 SDValue N0 = Op.getOperand(0);
4885 SDValue N1 = Op.getOperand(1);
4888 if (VT == MVT::v8i8) {
4889 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4890 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4892 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4893 DAG.getIntPtrConstant(4));
4894 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4895 DAG.getIntPtrConstant(4));
4896 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4897 DAG.getIntPtrConstant(0));
4898 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4899 DAG.getIntPtrConstant(0));
4901 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4902 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4904 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4905 N0 = LowerCONCAT_VECTORS(N0, DAG);
4907 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4908 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4913 // v4i16 sdiv ... Convert to float.
4914 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4915 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4916 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4917 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4918 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4919 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4921 // Use reciprocal estimate and two refinement steps.
4922 // float4 recip = vrecpeq_f32(yf);
4923 // recip *= vrecpsq_f32(yf, recip);
4924 // recip *= vrecpsq_f32(yf, recip);
4925 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4926 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4927 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4928 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4930 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4931 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4932 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4934 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4935 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4936 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4937 // and that it will never cause us to return an answer too large).
4938 // float4 result = as_float4(as_int4(xf*recip) + 2);
4939 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4940 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4941 N1 = DAG.getConstant(2, MVT::i32);
4942 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4943 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4944 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4945 // Convert back to integer and return.
4946 // return vmovn_u32(vcvt_s32_f32(result));
4947 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4948 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4952 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
4953 EVT VT = Op.getNode()->getValueType(0);
4954 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4957 bool ExtraOp = false;
4958 switch (Op.getOpcode()) {
4959 default: assert(0 && "Invalid code");
4960 case ISD::ADDC: Opc = ARMISD::ADDC; break;
4961 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
4962 case ISD::SUBC: Opc = ARMISD::SUBC; break;
4963 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
4967 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4969 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4970 Op.getOperand(1), Op.getOperand(2));
4973 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
4974 // Monotonic load/store is legal for all targets
4975 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
4978 // Aquire/Release load/store is not legal for targets without a
4979 // dmb or equivalent available.
4985 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
4986 SelectionDAG &DAG, unsigned NewOp) {
4987 DebugLoc dl = Node->getDebugLoc();
4988 assert (Node->getValueType(0) == MVT::i64 &&
4989 "Only know how to expand i64 atomics");
4991 SmallVector<SDValue, 6> Ops;
4992 Ops.push_back(Node->getOperand(0)); // Chain
4993 Ops.push_back(Node->getOperand(1)); // Ptr
4995 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4996 Node->getOperand(2), DAG.getIntPtrConstant(0)));
4997 // High part of Val1
4998 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4999 Node->getOperand(2), DAG.getIntPtrConstant(1)));
5000 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
5001 // High part of Val1
5002 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5003 Node->getOperand(3), DAG.getIntPtrConstant(0)));
5004 // High part of Val2
5005 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5006 Node->getOperand(3), DAG.getIntPtrConstant(1)));
5008 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
5010 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
5011 cast<MemSDNode>(Node)->getMemOperand());
5012 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
5013 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
5014 Results.push_back(Result.getValue(2));
5017 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5018 switch (Op.getOpcode()) {
5019 default: llvm_unreachable("Don't know how to custom lower this!");
5020 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5021 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5022 case ISD::GlobalAddress:
5023 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
5024 LowerGlobalAddressELF(Op, DAG);
5025 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5026 case ISD::SELECT: return LowerSELECT(Op, DAG);
5027 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5028 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
5029 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
5030 case ISD::VASTART: return LowerVASTART(Op, DAG);
5031 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
5032 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
5033 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
5034 case ISD::SINT_TO_FP:
5035 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5036 case ISD::FP_TO_SINT:
5037 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
5038 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5039 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5040 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5041 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
5042 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
5043 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
5044 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
5046 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
5049 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
5050 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
5051 case ISD::SRL_PARTS:
5052 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
5053 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
5054 case ISD::SETCC: return LowerVSETCC(Op, DAG);
5055 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
5056 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5057 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5058 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5059 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
5060 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5061 case ISD::MUL: return LowerMUL(Op, DAG);
5062 case ISD::SDIV: return LowerSDIV(Op, DAG);
5063 case ISD::UDIV: return LowerUDIV(Op, DAG);
5067 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
5068 case ISD::ATOMIC_LOAD:
5069 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
5074 /// ReplaceNodeResults - Replace the results of node with an illegal result
5075 /// type with new values built out of custom code.
5076 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
5077 SmallVectorImpl<SDValue>&Results,
5078 SelectionDAG &DAG) const {
5080 switch (N->getOpcode()) {
5082 llvm_unreachable("Don't know how to custom expand this!");
5085 Res = ExpandBITCAST(N, DAG);
5089 Res = Expand64BitShift(N, DAG, Subtarget);
5091 case ISD::ATOMIC_LOAD_ADD:
5092 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5094 case ISD::ATOMIC_LOAD_AND:
5095 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5097 case ISD::ATOMIC_LOAD_NAND:
5098 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5100 case ISD::ATOMIC_LOAD_OR:
5101 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5103 case ISD::ATOMIC_LOAD_SUB:
5104 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5106 case ISD::ATOMIC_LOAD_XOR:
5107 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5109 case ISD::ATOMIC_SWAP:
5110 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5112 case ISD::ATOMIC_CMP_SWAP:
5113 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5117 Results.push_back(Res);
5120 //===----------------------------------------------------------------------===//
5121 // ARM Scheduler Hooks
5122 //===----------------------------------------------------------------------===//
5125 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5126 MachineBasicBlock *BB,
5127 unsigned Size) const {
5128 unsigned dest = MI->getOperand(0).getReg();
5129 unsigned ptr = MI->getOperand(1).getReg();
5130 unsigned oldval = MI->getOperand(2).getReg();
5131 unsigned newval = MI->getOperand(3).getReg();
5132 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5133 DebugLoc dl = MI->getDebugLoc();
5134 bool isThumb2 = Subtarget->isThumb2();
5136 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5138 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
5139 : ARM::GPRRegisterClass);
5142 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5143 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
5144 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
5147 unsigned ldrOpc, strOpc;
5149 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5151 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5152 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5155 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5156 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5159 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5160 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5164 MachineFunction *MF = BB->getParent();
5165 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5166 MachineFunction::iterator It = BB;
5167 ++It; // insert the new blocks after the current block
5169 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5170 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5171 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5172 MF->insert(It, loop1MBB);
5173 MF->insert(It, loop2MBB);
5174 MF->insert(It, exitMBB);
5176 // Transfer the remainder of BB and its successor edges to exitMBB.
5177 exitMBB->splice(exitMBB->begin(), BB,
5178 llvm::next(MachineBasicBlock::iterator(MI)),
5180 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5184 // fallthrough --> loop1MBB
5185 BB->addSuccessor(loop1MBB);
5188 // ldrex dest, [ptr]
5192 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5193 if (ldrOpc == ARM::t2LDREX)
5195 AddDefaultPred(MIB);
5196 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5197 .addReg(dest).addReg(oldval));
5198 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5199 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5200 BB->addSuccessor(loop2MBB);
5201 BB->addSuccessor(exitMBB);
5204 // strex scratch, newval, [ptr]
5208 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5209 if (strOpc == ARM::t2STREX)
5211 AddDefaultPred(MIB);
5212 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5213 .addReg(scratch).addImm(0));
5214 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5215 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5216 BB->addSuccessor(loop1MBB);
5217 BB->addSuccessor(exitMBB);
5223 MI->eraseFromParent(); // The instruction is gone now.
5229 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5230 unsigned Size, unsigned BinOpcode) const {
5231 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5232 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5234 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5235 MachineFunction *MF = BB->getParent();
5236 MachineFunction::iterator It = BB;
5239 unsigned dest = MI->getOperand(0).getReg();
5240 unsigned ptr = MI->getOperand(1).getReg();
5241 unsigned incr = MI->getOperand(2).getReg();
5242 DebugLoc dl = MI->getDebugLoc();
5243 bool isThumb2 = Subtarget->isThumb2();
5245 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5247 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5248 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5251 unsigned ldrOpc, strOpc;
5253 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5255 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5256 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5259 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5260 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5263 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5264 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5268 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5269 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5270 MF->insert(It, loopMBB);
5271 MF->insert(It, exitMBB);
5273 // Transfer the remainder of BB and its successor edges to exitMBB.
5274 exitMBB->splice(exitMBB->begin(), BB,
5275 llvm::next(MachineBasicBlock::iterator(MI)),
5277 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5279 TargetRegisterClass *TRC =
5280 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5281 unsigned scratch = MRI.createVirtualRegister(TRC);
5282 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5286 // fallthrough --> loopMBB
5287 BB->addSuccessor(loopMBB);
5291 // <binop> scratch2, dest, incr
5292 // strex scratch, scratch2, ptr
5295 // fallthrough --> exitMBB
5297 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5298 if (ldrOpc == ARM::t2LDREX)
5300 AddDefaultPred(MIB);
5302 // operand order needs to go the other way for NAND
5303 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5304 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5305 addReg(incr).addReg(dest)).addReg(0);
5307 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5308 addReg(dest).addReg(incr)).addReg(0);
5311 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5312 if (strOpc == ARM::t2STREX)
5314 AddDefaultPred(MIB);
5315 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5316 .addReg(scratch).addImm(0));
5317 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5318 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5320 BB->addSuccessor(loopMBB);
5321 BB->addSuccessor(exitMBB);
5327 MI->eraseFromParent(); // The instruction is gone now.
5333 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5334 MachineBasicBlock *BB,
5337 ARMCC::CondCodes Cond) const {
5338 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5340 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5341 MachineFunction *MF = BB->getParent();
5342 MachineFunction::iterator It = BB;
5345 unsigned dest = MI->getOperand(0).getReg();
5346 unsigned ptr = MI->getOperand(1).getReg();
5347 unsigned incr = MI->getOperand(2).getReg();
5348 unsigned oldval = dest;
5349 DebugLoc dl = MI->getDebugLoc();
5350 bool isThumb2 = Subtarget->isThumb2();
5352 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5354 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5355 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5358 unsigned ldrOpc, strOpc, extendOpc;
5360 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5362 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5363 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5364 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5367 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5368 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5369 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5372 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5373 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5378 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5379 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5380 MF->insert(It, loopMBB);
5381 MF->insert(It, exitMBB);
5383 // Transfer the remainder of BB and its successor edges to exitMBB.
5384 exitMBB->splice(exitMBB->begin(), BB,
5385 llvm::next(MachineBasicBlock::iterator(MI)),
5387 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5389 TargetRegisterClass *TRC =
5390 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5391 unsigned scratch = MRI.createVirtualRegister(TRC);
5392 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5396 // fallthrough --> loopMBB
5397 BB->addSuccessor(loopMBB);
5401 // (sign extend dest, if required)
5403 // cmov.cond scratch2, dest, incr
5404 // strex scratch, scratch2, ptr
5407 // fallthrough --> exitMBB
5409 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5410 if (ldrOpc == ARM::t2LDREX)
5412 AddDefaultPred(MIB);
5414 // Sign extend the value, if necessary.
5415 if (signExtend && extendOpc) {
5416 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5417 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5422 // Build compare and cmov instructions.
5423 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5424 .addReg(oldval).addReg(incr));
5425 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5426 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5428 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5429 if (strOpc == ARM::t2STREX)
5431 AddDefaultPred(MIB);
5432 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5433 .addReg(scratch).addImm(0));
5434 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5435 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5437 BB->addSuccessor(loopMBB);
5438 BB->addSuccessor(exitMBB);
5444 MI->eraseFromParent(); // The instruction is gone now.
5450 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5451 unsigned Op1, unsigned Op2,
5452 bool NeedsCarry, bool IsCmpxchg) const {
5453 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5454 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5456 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5457 MachineFunction *MF = BB->getParent();
5458 MachineFunction::iterator It = BB;
5461 unsigned destlo = MI->getOperand(0).getReg();
5462 unsigned desthi = MI->getOperand(1).getReg();
5463 unsigned ptr = MI->getOperand(2).getReg();
5464 unsigned vallo = MI->getOperand(3).getReg();
5465 unsigned valhi = MI->getOperand(4).getReg();
5466 DebugLoc dl = MI->getDebugLoc();
5467 bool isThumb2 = Subtarget->isThumb2();
5469 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5471 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
5472 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
5473 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5476 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5477 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5479 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5480 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5482 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5483 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5485 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5486 MF->insert(It, loopMBB);
5488 MF->insert(It, contBB);
5489 MF->insert(It, cont2BB);
5491 MF->insert(It, exitMBB);
5493 // Transfer the remainder of BB and its successor edges to exitMBB.
5494 exitMBB->splice(exitMBB->begin(), BB,
5495 llvm::next(MachineBasicBlock::iterator(MI)),
5497 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5499 TargetRegisterClass *TRC =
5500 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5501 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5505 // fallthrough --> loopMBB
5506 BB->addSuccessor(loopMBB);
5509 // ldrexd r2, r3, ptr
5510 // <binopa> r0, r2, incr
5511 // <binopb> r1, r3, incr
5512 // strexd storesuccess, r0, r1, ptr
5513 // cmp storesuccess, #0
5515 // fallthrough --> exitMBB
5517 // Note that the registers are explicitly specified because there is not any
5518 // way to force the register allocator to allocate a register pair.
5520 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
5521 // need to properly enforce the restriction that the two output registers
5522 // for ldrexd must be different.
5525 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5526 .addReg(ARM::R2, RegState::Define)
5527 .addReg(ARM::R3, RegState::Define).addReg(ptr));
5528 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
5529 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5530 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5534 for (unsigned i = 0; i < 2; i++) {
5535 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5537 .addReg(i == 0 ? destlo : desthi)
5538 .addReg(i == 0 ? vallo : valhi));
5539 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5540 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5541 BB->addSuccessor(exitMBB);
5542 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5543 BB = (i == 0 ? contBB : cont2BB);
5546 // Copy to physregs for strexd
5547 unsigned setlo = MI->getOperand(5).getReg();
5548 unsigned sethi = MI->getOperand(6).getReg();
5549 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5550 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5552 // Perform binary operation
5553 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5554 .addReg(destlo).addReg(vallo))
5555 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
5556 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5557 .addReg(desthi).addReg(valhi)).addReg(0);
5559 // Copy to physregs for strexd
5560 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5561 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5565 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5566 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
5568 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5569 .addReg(storesuccess).addImm(0));
5570 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5571 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5573 BB->addSuccessor(loopMBB);
5574 BB->addSuccessor(exitMBB);
5580 MI->eraseFromParent(); // The instruction is gone now.
5585 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
5586 /// registers the function context.
5587 void ARMTargetLowering::
5588 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
5589 MachineBasicBlock *DispatchBB, int FI) const {
5590 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5591 DebugLoc dl = MI->getDebugLoc();
5592 MachineFunction *MF = MBB->getParent();
5593 MachineRegisterInfo *MRI = &MF->getRegInfo();
5594 MachineConstantPool *MCP = MF->getConstantPool();
5595 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5596 const Function *F = MF->getFunction();
5598 bool isThumb = Subtarget->isThumb();
5599 bool isThumb2 = Subtarget->isThumb2();
5601 unsigned PCLabelId = AFI->createPICLabelUId();
5602 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
5603 ARMConstantPoolValue *CPV =
5604 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
5605 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
5607 const TargetRegisterClass *TRC =
5608 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5610 // Grab constant pool and fixed stack memory operands.
5611 MachineMemOperand *CPMMO =
5612 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
5613 MachineMemOperand::MOLoad, 4, 4);
5615 MachineMemOperand *FIMMOSt =
5616 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5617 MachineMemOperand::MOStore, 4, 4);
5619 // Load the address of the dispatch MBB into the jump buffer.
5621 // Incoming value: jbuf
5622 // ldr.n r5, LCPI1_1
5625 // str r5, [$jbuf, #+4] ; &jbuf[1]
5626 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5627 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
5628 .addConstantPoolIndex(CPI)
5629 .addMemOperand(CPMMO));
5630 // Set the low bit because of thumb mode.
5631 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5633 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
5634 .addReg(NewVReg1, RegState::Kill)
5636 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5637 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
5638 .addReg(NewVReg2, RegState::Kill)
5640 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
5641 .addReg(NewVReg3, RegState::Kill)
5643 .addImm(36) // &jbuf[1] :: pc
5644 .addMemOperand(FIMMOSt));
5645 } else if (isThumb) {
5646 // Incoming value: jbuf
5647 // ldr.n r1, LCPI1_4
5651 // add r2, $jbuf, #+4 ; &jbuf[1]
5653 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5654 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
5655 .addConstantPoolIndex(CPI)
5656 .addMemOperand(CPMMO));
5657 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5658 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
5659 .addReg(NewVReg1, RegState::Kill)
5661 // Set the low bit because of thumb mode.
5662 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5663 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
5664 .addReg(ARM::CPSR, RegState::Define)
5666 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5667 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
5668 .addReg(ARM::CPSR, RegState::Define)
5669 .addReg(NewVReg2, RegState::Kill)
5670 .addReg(NewVReg3, RegState::Kill));
5671 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5672 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
5674 .addImm(36)); // &jbuf[1] :: pc
5675 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
5676 .addReg(NewVReg4, RegState::Kill)
5677 .addReg(NewVReg5, RegState::Kill)
5679 .addMemOperand(FIMMOSt));
5681 // Incoming value: jbuf
5684 // str r1, [$jbuf, #+4] ; &jbuf[1]
5685 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5686 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
5687 .addConstantPoolIndex(CPI)
5689 .addMemOperand(CPMMO));
5690 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5691 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
5692 .addReg(NewVReg1, RegState::Kill)
5693 .addImm(PCLabelId));
5694 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
5695 .addReg(NewVReg2, RegState::Kill)
5697 .addImm(36) // &jbuf[1] :: pc
5698 .addMemOperand(FIMMOSt));
5702 MachineBasicBlock *ARMTargetLowering::
5703 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5704 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5705 DebugLoc dl = MI->getDebugLoc();
5706 MachineFunction *MF = MBB->getParent();
5707 MachineRegisterInfo *MRI = &MF->getRegInfo();
5708 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5709 MachineFrameInfo *MFI = MF->getFrameInfo();
5710 int FI = MFI->getFunctionContextIndex();
5712 const TargetRegisterClass *TRC =
5713 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5715 // Get a mapping of the call site numbers to all of the landing pads they're
5717 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
5718 unsigned MaxCSNum = 0;
5719 MachineModuleInfo &MMI = MF->getMMI();
5720 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) {
5721 if (!BB->isLandingPad()) continue;
5723 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
5725 for (MachineBasicBlock::iterator
5726 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5727 if (!II->isEHLabel()) continue;
5729 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
5730 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
5732 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
5733 for (SmallVectorImpl<unsigned>::iterator
5734 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
5735 CSI != CSE; ++CSI) {
5736 CallSiteNumToLPad[*CSI].push_back(BB);
5737 MaxCSNum = std::max(MaxCSNum, *CSI);
5743 // Get an ordered list of the machine basic blocks for the jump table.
5744 std::vector<MachineBasicBlock*> LPadList;
5745 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
5746 LPadList.reserve(CallSiteNumToLPad.size());
5747 for (unsigned I = 1; I <= MaxCSNum; ++I) {
5748 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
5749 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5750 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
5751 LPadList.push_back(*II);
5752 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
5756 assert(!LPadList.empty() &&
5757 "No landing pad destinations for the dispatch jump table!");
5759 // Create the jump table and associated information.
5760 MachineJumpTableInfo *JTI =
5761 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
5762 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
5763 unsigned UId = AFI->createJumpTableUId();
5765 // Create the MBBs for the dispatch code.
5767 // Shove the dispatch's address into the return slot in the function context.
5768 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
5769 DispatchBB->setIsLandingPad();
5771 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
5772 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
5773 DispatchBB->addSuccessor(TrapBB);
5775 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
5776 DispatchBB->addSuccessor(DispContBB);
5779 MF->insert(MF->end(), DispatchBB);
5780 MF->insert(MF->end(), DispContBB);
5781 MF->insert(MF->end(), TrapBB);
5783 // Insert code into the entry block that creates and registers the function
5785 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
5787 MachineMemOperand *FIMMOLd =
5788 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5789 MachineMemOperand::MOLoad |
5790 MachineMemOperand::MOVolatile, 4, 4);
5792 BuildMI(DispatchBB, dl, TII->get(ARM::eh_sjlj_dispatchsetup));
5794 unsigned NumLPads = LPadList.size();
5795 if (Subtarget->isThumb2()) {
5796 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5797 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
5800 .addMemOperand(FIMMOLd));
5802 if (NumLPads < 256) {
5803 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
5805 .addImm(LPadList.size()));
5807 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5808 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
5809 .addImm(NumLPads & 0xFFFF));
5811 unsigned VReg2 = VReg1;
5812 if ((NumLPads & 0xFFFF0000) != 0) {
5813 VReg2 = MRI->createVirtualRegister(TRC);
5814 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
5816 .addImm(NumLPads >> 16));
5819 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
5824 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
5829 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5830 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
5831 .addJumpTableIndex(MJTI)
5834 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5837 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
5838 .addReg(NewVReg3, RegState::Kill)
5840 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5842 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
5843 .addReg(NewVReg4, RegState::Kill)
5845 .addJumpTableIndex(MJTI)
5847 } else if (Subtarget->isThumb()) {
5848 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5849 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
5852 .addMemOperand(FIMMOLd));
5854 if (NumLPads < 256) {
5855 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
5859 MachineConstantPool *ConstantPool = MF->getConstantPool();
5860 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
5861 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
5863 // MachineConstantPool wants an explicit alignment.
5864 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
5866 Align = getTargetData()->getTypeAllocSize(C->getType());
5867 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
5869 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5870 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
5871 .addReg(VReg1, RegState::Define)
5872 .addConstantPoolIndex(Idx));
5873 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
5878 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
5883 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5884 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
5885 .addReg(ARM::CPSR, RegState::Define)
5889 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5890 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
5891 .addJumpTableIndex(MJTI)
5894 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5895 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
5896 .addReg(ARM::CPSR, RegState::Define)
5897 .addReg(NewVReg2, RegState::Kill)
5900 MachineMemOperand *JTMMOLd =
5901 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5902 MachineMemOperand::MOLoad, 4, 4);
5904 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5905 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
5906 .addReg(NewVReg4, RegState::Kill)
5908 .addMemOperand(JTMMOLd));
5910 unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
5911 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
5912 .addReg(ARM::CPSR, RegState::Define)
5913 .addReg(NewVReg5, RegState::Kill)
5916 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
5917 .addReg(NewVReg6, RegState::Kill)
5918 .addJumpTableIndex(MJTI)
5921 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5922 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
5925 .addMemOperand(FIMMOLd));
5927 if (NumLPads < 256) {
5928 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
5931 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
5932 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5933 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
5934 .addImm(NumLPads & 0xFFFF));
5936 unsigned VReg2 = VReg1;
5937 if ((NumLPads & 0xFFFF0000) != 0) {
5938 VReg2 = MRI->createVirtualRegister(TRC);
5939 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
5941 .addImm(NumLPads >> 16));
5944 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
5948 MachineConstantPool *ConstantPool = MF->getConstantPool();
5949 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
5950 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
5952 // MachineConstantPool wants an explicit alignment.
5953 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
5955 Align = getTargetData()->getTypeAllocSize(C->getType());
5956 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
5958 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5959 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
5960 .addReg(VReg1, RegState::Define)
5961 .addConstantPoolIndex(Idx)
5963 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
5965 .addReg(VReg1, RegState::Kill));
5968 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
5973 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5975 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
5977 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5978 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5979 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
5980 .addJumpTableIndex(MJTI)
5983 MachineMemOperand *JTMMOLd =
5984 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5985 MachineMemOperand::MOLoad, 4, 4);
5986 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5988 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
5989 .addReg(NewVReg3, RegState::Kill)
5992 .addMemOperand(JTMMOLd));
5994 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
5995 .addReg(NewVReg5, RegState::Kill)
5997 .addJumpTableIndex(MJTI)
6001 // Add the jump table entries as successors to the MBB.
6002 MachineBasicBlock *PrevMBB = 0;
6003 for (std::vector<MachineBasicBlock*>::iterator
6004 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6005 MachineBasicBlock *CurMBB = *I;
6006 if (PrevMBB != CurMBB)
6007 DispContBB->addSuccessor(CurMBB);
6011 // N.B. the order the invoke BBs are processed in doesn't matter here.
6012 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6013 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6014 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF);
6015 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6016 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
6017 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6018 MachineBasicBlock *BB = *I;
6020 // Remove the landing pad successor from the invoke block and replace it
6021 // with the new dispatch block.
6022 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6024 while (!Successors.empty()) {
6025 MachineBasicBlock *SMBB = Successors.pop_back_val();
6026 if (SMBB->isLandingPad()) {
6027 BB->removeSuccessor(SMBB);
6028 MBBLPads.push_back(SMBB);
6032 BB->addSuccessor(DispatchBB);
6034 // Find the invoke call and mark all of the callee-saved registers as
6035 // 'implicit defined' so that they're spilled. This prevents code from
6036 // moving instructions to before the EH block, where they will never be
6038 for (MachineBasicBlock::reverse_iterator
6039 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6040 if (!II->isCall()) continue;
6042 DenseMap<unsigned, bool> DefRegs;
6043 for (MachineInstr::mop_iterator
6044 OI = II->operands_begin(), OE = II->operands_end();
6046 if (!OI->isReg()) continue;
6047 DefRegs[OI->getReg()] = true;
6050 MachineInstrBuilder MIB(&*II);
6052 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6053 unsigned Reg = SavedRegs[i];
6054 if (Subtarget->isThumb2() &&
6055 !ARM::tGPRRegisterClass->contains(Reg) &&
6056 !ARM::hGPRRegisterClass->contains(Reg))
6058 else if (Subtarget->isThumb1Only() &&
6059 !ARM::tGPRRegisterClass->contains(Reg))
6061 else if (!Subtarget->isThumb() &&
6062 !ARM::GPRRegisterClass->contains(Reg))
6065 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
6072 // Mark all former landing pads as non-landing pads. The dispatch is the only
6074 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6075 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6076 (*I)->setIsLandingPad(false);
6078 // The instruction is gone now.
6079 MI->eraseFromParent();
6085 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6086 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6087 E = MBB->succ_end(); I != E; ++I)
6090 llvm_unreachable("Expecting a BB with two successors!");
6094 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6095 MachineBasicBlock *BB) const {
6096 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6097 DebugLoc dl = MI->getDebugLoc();
6098 bool isThumb2 = Subtarget->isThumb2();
6099 switch (MI->getOpcode()) {
6102 llvm_unreachable("Unexpected instr type to insert");
6104 // The Thumb2 pre-indexed stores have the same MI operands, they just
6105 // define them differently in the .td files from the isel patterns, so
6106 // they need pseudos.
6107 case ARM::t2STR_preidx:
6108 MI->setDesc(TII->get(ARM::t2STR_PRE));
6110 case ARM::t2STRB_preidx:
6111 MI->setDesc(TII->get(ARM::t2STRB_PRE));
6113 case ARM::t2STRH_preidx:
6114 MI->setDesc(TII->get(ARM::t2STRH_PRE));
6117 case ARM::STRi_preidx:
6118 case ARM::STRBi_preidx: {
6119 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6120 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
6121 // Decode the offset.
6122 unsigned Offset = MI->getOperand(4).getImm();
6123 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
6124 Offset = ARM_AM::getAM2Offset(Offset);
6128 MachineMemOperand *MMO = *MI->memoperands_begin();
6129 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6130 .addOperand(MI->getOperand(0)) // Rn_wb
6131 .addOperand(MI->getOperand(1)) // Rt
6132 .addOperand(MI->getOperand(2)) // Rn
6133 .addImm(Offset) // offset (skip GPR==zero_reg)
6134 .addOperand(MI->getOperand(5)) // pred
6135 .addOperand(MI->getOperand(6))
6136 .addMemOperand(MMO);
6137 MI->eraseFromParent();
6140 case ARM::STRr_preidx:
6141 case ARM::STRBr_preidx:
6142 case ARM::STRH_preidx: {
6144 switch (MI->getOpcode()) {
6145 default: llvm_unreachable("unexpected opcode!");
6146 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
6147 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
6148 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
6150 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
6151 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
6152 MIB.addOperand(MI->getOperand(i));
6153 MI->eraseFromParent();
6156 case ARM::ATOMIC_LOAD_ADD_I8:
6157 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6158 case ARM::ATOMIC_LOAD_ADD_I16:
6159 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6160 case ARM::ATOMIC_LOAD_ADD_I32:
6161 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6163 case ARM::ATOMIC_LOAD_AND_I8:
6164 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6165 case ARM::ATOMIC_LOAD_AND_I16:
6166 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6167 case ARM::ATOMIC_LOAD_AND_I32:
6168 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6170 case ARM::ATOMIC_LOAD_OR_I8:
6171 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6172 case ARM::ATOMIC_LOAD_OR_I16:
6173 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6174 case ARM::ATOMIC_LOAD_OR_I32:
6175 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6177 case ARM::ATOMIC_LOAD_XOR_I8:
6178 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6179 case ARM::ATOMIC_LOAD_XOR_I16:
6180 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6181 case ARM::ATOMIC_LOAD_XOR_I32:
6182 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6184 case ARM::ATOMIC_LOAD_NAND_I8:
6185 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6186 case ARM::ATOMIC_LOAD_NAND_I16:
6187 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6188 case ARM::ATOMIC_LOAD_NAND_I32:
6189 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6191 case ARM::ATOMIC_LOAD_SUB_I8:
6192 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6193 case ARM::ATOMIC_LOAD_SUB_I16:
6194 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6195 case ARM::ATOMIC_LOAD_SUB_I32:
6196 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6198 case ARM::ATOMIC_LOAD_MIN_I8:
6199 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
6200 case ARM::ATOMIC_LOAD_MIN_I16:
6201 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
6202 case ARM::ATOMIC_LOAD_MIN_I32:
6203 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
6205 case ARM::ATOMIC_LOAD_MAX_I8:
6206 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
6207 case ARM::ATOMIC_LOAD_MAX_I16:
6208 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
6209 case ARM::ATOMIC_LOAD_MAX_I32:
6210 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
6212 case ARM::ATOMIC_LOAD_UMIN_I8:
6213 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
6214 case ARM::ATOMIC_LOAD_UMIN_I16:
6215 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
6216 case ARM::ATOMIC_LOAD_UMIN_I32:
6217 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
6219 case ARM::ATOMIC_LOAD_UMAX_I8:
6220 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
6221 case ARM::ATOMIC_LOAD_UMAX_I16:
6222 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
6223 case ARM::ATOMIC_LOAD_UMAX_I32:
6224 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
6226 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
6227 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
6228 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
6230 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
6231 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
6232 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
6235 case ARM::ATOMADD6432:
6236 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
6237 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
6238 /*NeedsCarry*/ true);
6239 case ARM::ATOMSUB6432:
6240 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6241 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6242 /*NeedsCarry*/ true);
6243 case ARM::ATOMOR6432:
6244 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
6245 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6246 case ARM::ATOMXOR6432:
6247 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
6248 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6249 case ARM::ATOMAND6432:
6250 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
6251 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6252 case ARM::ATOMSWAP6432:
6253 return EmitAtomicBinary64(MI, BB, 0, 0, false);
6254 case ARM::ATOMCMPXCHG6432:
6255 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6256 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6257 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
6259 case ARM::tMOVCCr_pseudo: {
6260 // To "insert" a SELECT_CC instruction, we actually have to insert the
6261 // diamond control-flow pattern. The incoming instruction knows the
6262 // destination vreg to set, the condition code register to branch on, the
6263 // true/false values to select between, and a branch opcode to use.
6264 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6265 MachineFunction::iterator It = BB;
6271 // cmpTY ccX, r1, r2
6273 // fallthrough --> copy0MBB
6274 MachineBasicBlock *thisMBB = BB;
6275 MachineFunction *F = BB->getParent();
6276 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6277 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6278 F->insert(It, copy0MBB);
6279 F->insert(It, sinkMBB);
6281 // Transfer the remainder of BB and its successor edges to sinkMBB.
6282 sinkMBB->splice(sinkMBB->begin(), BB,
6283 llvm::next(MachineBasicBlock::iterator(MI)),
6285 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6287 BB->addSuccessor(copy0MBB);
6288 BB->addSuccessor(sinkMBB);
6290 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
6291 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
6294 // %FalseValue = ...
6295 // # fallthrough to sinkMBB
6298 // Update machine-CFG edges
6299 BB->addSuccessor(sinkMBB);
6302 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6305 BuildMI(*BB, BB->begin(), dl,
6306 TII->get(ARM::PHI), MI->getOperand(0).getReg())
6307 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6308 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6310 MI->eraseFromParent(); // The pseudo instruction is gone now.
6315 case ARM::BCCZi64: {
6316 // If there is an unconditional branch to the other successor, remove it.
6317 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
6319 // Compare both parts that make up the double comparison separately for
6321 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6323 unsigned LHS1 = MI->getOperand(1).getReg();
6324 unsigned LHS2 = MI->getOperand(2).getReg();
6326 AddDefaultPred(BuildMI(BB, dl,
6327 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6328 .addReg(LHS1).addImm(0));
6329 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6330 .addReg(LHS2).addImm(0)
6331 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6333 unsigned RHS1 = MI->getOperand(3).getReg();
6334 unsigned RHS2 = MI->getOperand(4).getReg();
6335 AddDefaultPred(BuildMI(BB, dl,
6336 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6337 .addReg(LHS1).addReg(RHS1));
6338 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6339 .addReg(LHS2).addReg(RHS2)
6340 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6343 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
6344 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
6345 if (MI->getOperand(0).getImm() == ARMCC::NE)
6346 std::swap(destMBB, exitMBB);
6348 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6349 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
6351 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6353 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6355 MI->eraseFromParent(); // The pseudo instruction is gone now.
6359 case ARM::Int_eh_sjlj_setjmp:
6360 case ARM::Int_eh_sjlj_setjmp_nofp:
6361 case ARM::tInt_eh_sjlj_setjmp:
6362 case ARM::t2Int_eh_sjlj_setjmp:
6363 case ARM::t2Int_eh_sjlj_setjmp_nofp:
6364 EmitSjLjDispatchBlock(MI, BB);
6369 // To insert an ABS instruction, we have to insert the
6370 // diamond control-flow pattern. The incoming instruction knows the
6371 // source vreg to test against 0, the destination vreg to set,
6372 // the condition code register to branch on, the
6373 // true/false values to select between, and a branch opcode to use.
6378 // BCC (branch to SinkBB if V0 >= 0)
6379 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
6380 // SinkBB: V1 = PHI(V2, V3)
6381 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6382 MachineFunction::iterator BBI = BB;
6384 MachineFunction *Fn = BB->getParent();
6385 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6386 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6387 Fn->insert(BBI, RSBBB);
6388 Fn->insert(BBI, SinkBB);
6390 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
6391 unsigned int ABSDstReg = MI->getOperand(0).getReg();
6392 bool isThumb2 = Subtarget->isThumb2();
6393 MachineRegisterInfo &MRI = Fn->getRegInfo();
6394 // In Thumb mode S must not be specified if source register is the SP or
6395 // PC and if destination register is the SP, so restrict register class
6396 unsigned NewMovDstReg = MRI.createVirtualRegister(
6397 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6398 unsigned NewRsbDstReg = MRI.createVirtualRegister(
6399 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6401 // Transfer the remainder of BB and its successor edges to sinkMBB.
6402 SinkBB->splice(SinkBB->begin(), BB,
6403 llvm::next(MachineBasicBlock::iterator(MI)),
6405 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6407 BB->addSuccessor(RSBBB);
6408 BB->addSuccessor(SinkBB);
6410 // fall through to SinkMBB
6411 RSBBB->addSuccessor(SinkBB);
6413 // insert a movs at the end of BB
6414 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
6416 .addReg(ABSSrcReg, RegState::Kill)
6417 .addImm((unsigned)ARMCC::AL).addReg(0)
6418 .addReg(ARM::CPSR, RegState::Define);
6420 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6422 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
6423 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
6425 // insert rsbri in RSBBB
6426 // Note: BCC and rsbri will be converted into predicated rsbmi
6427 // by if-conversion pass
6428 BuildMI(*RSBBB, RSBBB->begin(), dl,
6429 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
6430 .addReg(NewMovDstReg, RegState::Kill)
6431 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
6433 // insert PHI in SinkBB,
6434 // reuse ABSDstReg to not change uses of ABS instruction
6435 BuildMI(*SinkBB, SinkBB->begin(), dl,
6436 TII->get(ARM::PHI), ABSDstReg)
6437 .addReg(NewRsbDstReg).addMBB(RSBBB)
6438 .addReg(NewMovDstReg).addMBB(BB);
6440 // remove ABS instruction
6441 MI->eraseFromParent();
6443 // return last added BB
6449 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
6450 SDNode *Node) const {
6451 if (!MI->hasPostISelHook()) {
6452 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6453 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
6457 const MCInstrDesc *MCID = &MI->getDesc();
6458 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
6459 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
6460 // operand is still set to noreg. If needed, set the optional operand's
6461 // register to CPSR, and remove the redundant implicit def.
6463 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
6465 // Rename pseudo opcodes.
6466 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
6468 const ARMBaseInstrInfo *TII =
6469 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
6470 MCID = &TII->get(NewOpc);
6472 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
6473 "converted opcode should be the same except for cc_out");
6477 // Add the optional cc_out operand
6478 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
6480 unsigned ccOutIdx = MCID->getNumOperands() - 1;
6482 // Any ARM instruction that sets the 's' bit should specify an optional
6483 // "cc_out" operand in the last operand position.
6484 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
6485 assert(!NewOpc && "Optional cc_out operand required");
6488 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
6489 // since we already have an optional CPSR def.
6490 bool definesCPSR = false;
6491 bool deadCPSR = false;
6492 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
6494 const MachineOperand &MO = MI->getOperand(i);
6495 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
6499 MI->RemoveOperand(i);
6504 assert(!NewOpc && "Optional cc_out operand required");
6507 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
6509 assert(!MI->getOperand(ccOutIdx).getReg() &&
6510 "expect uninitialized optional cc_out operand");
6514 // If this instruction was defined with an optional CPSR def and its dag node
6515 // had a live implicit CPSR def, then activate the optional CPSR def.
6516 MachineOperand &MO = MI->getOperand(ccOutIdx);
6517 MO.setReg(ARM::CPSR);
6521 //===----------------------------------------------------------------------===//
6522 // ARM Optimization Hooks
6523 //===----------------------------------------------------------------------===//
6526 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
6527 TargetLowering::DAGCombinerInfo &DCI) {
6528 SelectionDAG &DAG = DCI.DAG;
6529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6530 EVT VT = N->getValueType(0);
6531 unsigned Opc = N->getOpcode();
6532 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
6533 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
6534 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
6535 ISD::CondCode CC = ISD::SETCC_INVALID;
6538 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
6540 SDValue CCOp = Slct.getOperand(0);
6541 if (CCOp.getOpcode() == ISD::SETCC)
6542 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
6545 bool DoXform = false;
6547 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
6550 if (LHS.getOpcode() == ISD::Constant &&
6551 cast<ConstantSDNode>(LHS)->isNullValue()) {
6553 } else if (CC != ISD::SETCC_INVALID &&
6554 RHS.getOpcode() == ISD::Constant &&
6555 cast<ConstantSDNode>(RHS)->isNullValue()) {
6556 std::swap(LHS, RHS);
6557 SDValue Op0 = Slct.getOperand(0);
6558 EVT OpVT = isSlctCC ? Op0.getValueType() :
6559 Op0.getOperand(0).getValueType();
6560 bool isInt = OpVT.isInteger();
6561 CC = ISD::getSetCCInverse(CC, isInt);
6563 if (!TLI.isCondCodeLegal(CC, OpVT))
6564 return SDValue(); // Inverse operator isn't legal.
6571 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
6573 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
6574 Slct.getOperand(0), Slct.getOperand(1), CC);
6575 SDValue CCOp = Slct.getOperand(0);
6577 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
6578 CCOp.getOperand(0), CCOp.getOperand(1), CC);
6579 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
6580 CCOp, OtherOp, Result);
6585 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
6586 // (only after legalization).
6587 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6588 TargetLowering::DAGCombinerInfo &DCI,
6589 const ARMSubtarget *Subtarget) {
6591 // Only perform optimization if after legalize, and if NEON is available. We
6592 // also expected both operands to be BUILD_VECTORs.
6593 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
6594 || N0.getOpcode() != ISD::BUILD_VECTOR
6595 || N1.getOpcode() != ISD::BUILD_VECTOR)
6598 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
6599 EVT VT = N->getValueType(0);
6600 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
6603 // Check that the vector operands are of the right form.
6604 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6605 // operands, where N is the size of the formed vector.
6606 // Each EXTRACT_VECTOR should have the same input vector and odd or even
6607 // index such that we have a pair wise add pattern.
6609 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
6610 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6612 SDValue Vec = N0->getOperand(0)->getOperand(0);
6613 SDNode *V = Vec.getNode();
6614 unsigned nextIndex = 0;
6616 // For each operands to the ADD which are BUILD_VECTORs,
6617 // check to see if each of their operands are an EXTRACT_VECTOR with
6618 // the same vector and appropriate index.
6619 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6620 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6621 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6623 SDValue ExtVec0 = N0->getOperand(i);
6624 SDValue ExtVec1 = N1->getOperand(i);
6626 // First operand is the vector, verify its the same.
6627 if (V != ExtVec0->getOperand(0).getNode() ||
6628 V != ExtVec1->getOperand(0).getNode())
6631 // Second is the constant, verify its correct.
6632 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
6633 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
6635 // For the constant, we want to see all the even or all the odd.
6636 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
6637 || C1->getZExtValue() != nextIndex+1)
6646 // Create VPADDL node.
6647 SelectionDAG &DAG = DCI.DAG;
6648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6650 // Build operand list.
6651 SmallVector<SDValue, 8> Ops;
6652 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
6653 TLI.getPointerTy()));
6655 // Input is the vector.
6658 // Get widened type and narrowed type.
6660 unsigned numElem = VT.getVectorNumElements();
6661 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
6662 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
6663 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
6664 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
6666 assert(0 && "Invalid vector element type for padd optimization.");
6669 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6670 widenType, &Ops[0], Ops.size());
6671 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
6674 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
6675 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6676 /// called with the default operands, and if that fails, with commuted
6678 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6679 TargetLowering::DAGCombinerInfo &DCI,
6680 const ARMSubtarget *Subtarget){
6682 // Attempt to create vpaddl for this add.
6683 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6684 if (Result.getNode())
6687 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
6688 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6689 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6690 if (Result.getNode()) return Result;
6695 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
6697 static SDValue PerformADDCombine(SDNode *N,
6698 TargetLowering::DAGCombinerInfo &DCI,
6699 const ARMSubtarget *Subtarget) {
6700 SDValue N0 = N->getOperand(0);
6701 SDValue N1 = N->getOperand(1);
6703 // First try with the default operand order.
6704 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6705 if (Result.getNode())
6708 // If that didn't work, try again with the operands commuted.
6709 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6712 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
6714 static SDValue PerformSUBCombine(SDNode *N,
6715 TargetLowering::DAGCombinerInfo &DCI) {
6716 SDValue N0 = N->getOperand(0);
6717 SDValue N1 = N->getOperand(1);
6719 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
6720 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
6721 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6722 if (Result.getNode()) return Result;
6728 /// PerformVMULCombine
6729 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
6730 /// special multiplier accumulator forwarding.
6736 static SDValue PerformVMULCombine(SDNode *N,
6737 TargetLowering::DAGCombinerInfo &DCI,
6738 const ARMSubtarget *Subtarget) {
6739 if (!Subtarget->hasVMLxForwarding())
6742 SelectionDAG &DAG = DCI.DAG;
6743 SDValue N0 = N->getOperand(0);
6744 SDValue N1 = N->getOperand(1);
6745 unsigned Opcode = N0.getOpcode();
6746 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6747 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
6748 Opcode = N1.getOpcode();
6749 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6750 Opcode != ISD::FADD && Opcode != ISD::FSUB)
6755 EVT VT = N->getValueType(0);
6756 DebugLoc DL = N->getDebugLoc();
6757 SDValue N00 = N0->getOperand(0);
6758 SDValue N01 = N0->getOperand(1);
6759 return DAG.getNode(Opcode, DL, VT,
6760 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
6761 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
6764 static SDValue PerformMULCombine(SDNode *N,
6765 TargetLowering::DAGCombinerInfo &DCI,
6766 const ARMSubtarget *Subtarget) {
6767 SelectionDAG &DAG = DCI.DAG;
6769 if (Subtarget->isThumb1Only())
6772 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6775 EVT VT = N->getValueType(0);
6776 if (VT.is64BitVector() || VT.is128BitVector())
6777 return PerformVMULCombine(N, DCI, Subtarget);
6781 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
6785 uint64_t MulAmt = C->getZExtValue();
6786 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
6787 ShiftAmt = ShiftAmt & (32 - 1);
6788 SDValue V = N->getOperand(0);
6789 DebugLoc DL = N->getDebugLoc();
6792 MulAmt >>= ShiftAmt;
6793 if (isPowerOf2_32(MulAmt - 1)) {
6794 // (mul x, 2^N + 1) => (add (shl x, N), x)
6795 Res = DAG.getNode(ISD::ADD, DL, VT,
6796 V, DAG.getNode(ISD::SHL, DL, VT,
6797 V, DAG.getConstant(Log2_32(MulAmt-1),
6799 } else if (isPowerOf2_32(MulAmt + 1)) {
6800 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6801 Res = DAG.getNode(ISD::SUB, DL, VT,
6802 DAG.getNode(ISD::SHL, DL, VT,
6803 V, DAG.getConstant(Log2_32(MulAmt+1),
6810 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
6811 DAG.getConstant(ShiftAmt, MVT::i32));
6813 // Do not add new nodes to DAG combiner worklist.
6814 DCI.CombineTo(N, Res, false);
6818 static SDValue PerformANDCombine(SDNode *N,
6819 TargetLowering::DAGCombinerInfo &DCI) {
6821 // Attempt to use immediate-form VBIC
6822 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6823 DebugLoc dl = N->getDebugLoc();
6824 EVT VT = N->getValueType(0);
6825 SelectionDAG &DAG = DCI.DAG;
6827 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6830 APInt SplatBits, SplatUndef;
6831 unsigned SplatBitSize;
6834 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6835 if (SplatBitSize <= 64) {
6837 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
6838 SplatUndef.getZExtValue(), SplatBitSize,
6839 DAG, VbicVT, VT.is128BitVector(),
6841 if (Val.getNode()) {
6843 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
6844 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
6845 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
6853 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
6854 static SDValue PerformORCombine(SDNode *N,
6855 TargetLowering::DAGCombinerInfo &DCI,
6856 const ARMSubtarget *Subtarget) {
6857 // Attempt to use immediate-form VORR
6858 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6859 DebugLoc dl = N->getDebugLoc();
6860 EVT VT = N->getValueType(0);
6861 SelectionDAG &DAG = DCI.DAG;
6863 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6866 APInt SplatBits, SplatUndef;
6867 unsigned SplatBitSize;
6869 if (BVN && Subtarget->hasNEON() &&
6870 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6871 if (SplatBitSize <= 64) {
6873 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
6874 SplatUndef.getZExtValue(), SplatBitSize,
6875 DAG, VorrVT, VT.is128BitVector(),
6877 if (Val.getNode()) {
6879 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
6880 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
6881 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
6886 SDValue N0 = N->getOperand(0);
6887 if (N0.getOpcode() != ISD::AND)
6889 SDValue N1 = N->getOperand(1);
6891 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
6892 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
6893 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
6895 unsigned SplatBitSize;
6898 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
6900 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
6901 HasAnyUndefs) && !HasAnyUndefs) {
6902 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
6904 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
6905 HasAnyUndefs) && !HasAnyUndefs &&
6906 SplatBits0 == ~SplatBits1) {
6907 // Canonicalize the vector type to make instruction selection simpler.
6908 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
6909 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
6910 N0->getOperand(1), N0->getOperand(0),
6912 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
6917 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
6920 // BFI is only available on V6T2+
6921 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
6924 DebugLoc DL = N->getDebugLoc();
6925 // 1) or (and A, mask), val => ARMbfi A, val, mask
6926 // iff (val & mask) == val
6928 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6929 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
6930 // && mask == ~mask2
6931 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
6932 // && ~mask == mask2
6933 // (i.e., copy a bitfield value into another bitfield of the same width)
6938 SDValue N00 = N0.getOperand(0);
6940 // The value and the mask need to be constants so we can verify this is
6941 // actually a bitfield set. If the mask is 0xffff, we can do better
6942 // via a movt instruction, so don't use BFI in that case.
6943 SDValue MaskOp = N0.getOperand(1);
6944 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
6947 unsigned Mask = MaskC->getZExtValue();
6951 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
6952 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
6954 unsigned Val = N1C->getZExtValue();
6955 if ((Val & ~Mask) != Val)
6958 if (ARM::isBitFieldInvertedMask(Mask)) {
6959 Val >>= CountTrailingZeros_32(~Mask);
6961 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
6962 DAG.getConstant(Val, MVT::i32),
6963 DAG.getConstant(Mask, MVT::i32));
6965 // Do not add new nodes to DAG combiner worklist.
6966 DCI.CombineTo(N, Res, false);
6969 } else if (N1.getOpcode() == ISD::AND) {
6970 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6971 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6974 unsigned Mask2 = N11C->getZExtValue();
6976 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
6978 if (ARM::isBitFieldInvertedMask(Mask) &&
6980 // The pack halfword instruction works better for masks that fit it,
6981 // so use that when it's available.
6982 if (Subtarget->hasT2ExtractPack() &&
6983 (Mask == 0xffff || Mask == 0xffff0000))
6986 unsigned amt = CountTrailingZeros_32(Mask2);
6987 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
6988 DAG.getConstant(amt, MVT::i32));
6989 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
6990 DAG.getConstant(Mask, MVT::i32));
6991 // Do not add new nodes to DAG combiner worklist.
6992 DCI.CombineTo(N, Res, false);
6994 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
6996 // The pack halfword instruction works better for masks that fit it,
6997 // so use that when it's available.
6998 if (Subtarget->hasT2ExtractPack() &&
6999 (Mask2 == 0xffff || Mask2 == 0xffff0000))
7002 unsigned lsb = CountTrailingZeros_32(Mask);
7003 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
7004 DAG.getConstant(lsb, MVT::i32));
7005 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
7006 DAG.getConstant(Mask2, MVT::i32));
7007 // Do not add new nodes to DAG combiner worklist.
7008 DCI.CombineTo(N, Res, false);
7013 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
7014 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
7015 ARM::isBitFieldInvertedMask(~Mask)) {
7016 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
7017 // where lsb(mask) == #shamt and masked bits of B are known zero.
7018 SDValue ShAmt = N00.getOperand(1);
7019 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
7020 unsigned LSB = CountTrailingZeros_32(Mask);
7024 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
7025 DAG.getConstant(~Mask, MVT::i32));
7027 // Do not add new nodes to DAG combiner worklist.
7028 DCI.CombineTo(N, Res, false);
7034 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
7035 /// the bits being cleared by the AND are not demanded by the BFI.
7036 static SDValue PerformBFICombine(SDNode *N,
7037 TargetLowering::DAGCombinerInfo &DCI) {
7038 SDValue N1 = N->getOperand(1);
7039 if (N1.getOpcode() == ISD::AND) {
7040 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
7043 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
7044 unsigned LSB = CountTrailingZeros_32(~InvMask);
7045 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
7046 unsigned Mask = (1 << Width)-1;
7047 unsigned Mask2 = N11C->getZExtValue();
7048 if ((Mask & (~Mask2)) == 0)
7049 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
7050 N->getOperand(0), N1.getOperand(0),
7056 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
7057 /// ARMISD::VMOVRRD.
7058 static SDValue PerformVMOVRRDCombine(SDNode *N,
7059 TargetLowering::DAGCombinerInfo &DCI) {
7060 // vmovrrd(vmovdrr x, y) -> x,y
7061 SDValue InDouble = N->getOperand(0);
7062 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
7063 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
7065 // vmovrrd(load f64) -> (load i32), (load i32)
7066 SDNode *InNode = InDouble.getNode();
7067 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
7068 InNode->getValueType(0) == MVT::f64 &&
7069 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
7070 !cast<LoadSDNode>(InNode)->isVolatile()) {
7071 // TODO: Should this be done for non-FrameIndex operands?
7072 LoadSDNode *LD = cast<LoadSDNode>(InNode);
7074 SelectionDAG &DAG = DCI.DAG;
7075 DebugLoc DL = LD->getDebugLoc();
7076 SDValue BasePtr = LD->getBasePtr();
7077 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
7078 LD->getPointerInfo(), LD->isVolatile(),
7079 LD->isNonTemporal(), LD->isInvariant(),
7080 LD->getAlignment());
7082 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
7083 DAG.getConstant(4, MVT::i32));
7084 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
7085 LD->getPointerInfo(), LD->isVolatile(),
7086 LD->isNonTemporal(), LD->isInvariant(),
7087 std::min(4U, LD->getAlignment() / 2));
7089 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
7090 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
7091 DCI.RemoveFromWorklist(LD);
7099 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
7100 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
7101 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
7102 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
7103 SDValue Op0 = N->getOperand(0);
7104 SDValue Op1 = N->getOperand(1);
7105 if (Op0.getOpcode() == ISD::BITCAST)
7106 Op0 = Op0.getOperand(0);
7107 if (Op1.getOpcode() == ISD::BITCAST)
7108 Op1 = Op1.getOperand(0);
7109 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
7110 Op0.getNode() == Op1.getNode() &&
7111 Op0.getResNo() == 0 && Op1.getResNo() == 1)
7112 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
7113 N->getValueType(0), Op0.getOperand(0));
7117 /// PerformSTORECombine - Target-specific dag combine xforms for
7119 static SDValue PerformSTORECombine(SDNode *N,
7120 TargetLowering::DAGCombinerInfo &DCI) {
7121 // Bitcast an i64 store extracted from a vector to f64.
7122 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7123 StoreSDNode *St = cast<StoreSDNode>(N);
7124 SDValue StVal = St->getValue();
7125 if (!ISD::isNormalStore(St) || St->isVolatile())
7128 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
7129 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
7130 SelectionDAG &DAG = DCI.DAG;
7131 DebugLoc DL = St->getDebugLoc();
7132 SDValue BasePtr = St->getBasePtr();
7133 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
7134 StVal.getNode()->getOperand(0), BasePtr,
7135 St->getPointerInfo(), St->isVolatile(),
7136 St->isNonTemporal(), St->getAlignment());
7138 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
7139 DAG.getConstant(4, MVT::i32));
7140 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
7141 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
7142 St->isNonTemporal(),
7143 std::min(4U, St->getAlignment() / 2));
7146 if (StVal.getValueType() != MVT::i64 ||
7147 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7150 SelectionDAG &DAG = DCI.DAG;
7151 DebugLoc dl = StVal.getDebugLoc();
7152 SDValue IntVec = StVal.getOperand(0);
7153 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7154 IntVec.getValueType().getVectorNumElements());
7155 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
7156 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7157 Vec, StVal.getOperand(1));
7158 dl = N->getDebugLoc();
7159 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
7160 // Make the DAGCombiner fold the bitcasts.
7161 DCI.AddToWorklist(Vec.getNode());
7162 DCI.AddToWorklist(ExtElt.getNode());
7163 DCI.AddToWorklist(V.getNode());
7164 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
7165 St->getPointerInfo(), St->isVolatile(),
7166 St->isNonTemporal(), St->getAlignment(),
7170 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
7171 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
7172 /// i64 vector to have f64 elements, since the value can then be loaded
7173 /// directly into a VFP register.
7174 static bool hasNormalLoadOperand(SDNode *N) {
7175 unsigned NumElts = N->getValueType(0).getVectorNumElements();
7176 for (unsigned i = 0; i < NumElts; ++i) {
7177 SDNode *Elt = N->getOperand(i).getNode();
7178 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
7184 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
7185 /// ISD::BUILD_VECTOR.
7186 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
7187 TargetLowering::DAGCombinerInfo &DCI){
7188 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
7189 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
7190 // into a pair of GPRs, which is fine when the value is used as a scalar,
7191 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
7192 SelectionDAG &DAG = DCI.DAG;
7193 if (N->getNumOperands() == 2) {
7194 SDValue RV = PerformVMOVDRRCombine(N, DAG);
7199 // Load i64 elements as f64 values so that type legalization does not split
7200 // them up into i32 values.
7201 EVT VT = N->getValueType(0);
7202 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
7204 DebugLoc dl = N->getDebugLoc();
7205 SmallVector<SDValue, 8> Ops;
7206 unsigned NumElts = VT.getVectorNumElements();
7207 for (unsigned i = 0; i < NumElts; ++i) {
7208 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
7210 // Make the DAGCombiner fold the bitcast.
7211 DCI.AddToWorklist(V.getNode());
7213 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
7214 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
7215 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
7218 /// PerformInsertEltCombine - Target-specific dag combine xforms for
7219 /// ISD::INSERT_VECTOR_ELT.
7220 static SDValue PerformInsertEltCombine(SDNode *N,
7221 TargetLowering::DAGCombinerInfo &DCI) {
7222 // Bitcast an i64 load inserted into a vector to f64.
7223 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7224 EVT VT = N->getValueType(0);
7225 SDNode *Elt = N->getOperand(1).getNode();
7226 if (VT.getVectorElementType() != MVT::i64 ||
7227 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
7230 SelectionDAG &DAG = DCI.DAG;
7231 DebugLoc dl = N->getDebugLoc();
7232 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7233 VT.getVectorNumElements());
7234 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
7235 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
7236 // Make the DAGCombiner fold the bitcasts.
7237 DCI.AddToWorklist(Vec.getNode());
7238 DCI.AddToWorklist(V.getNode());
7239 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
7240 Vec, V, N->getOperand(2));
7241 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
7244 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
7245 /// ISD::VECTOR_SHUFFLE.
7246 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
7247 // The LLVM shufflevector instruction does not require the shuffle mask
7248 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
7249 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
7250 // operands do not match the mask length, they are extended by concatenating
7251 // them with undef vectors. That is probably the right thing for other
7252 // targets, but for NEON it is better to concatenate two double-register
7253 // size vector operands into a single quad-register size vector. Do that
7254 // transformation here:
7255 // shuffle(concat(v1, undef), concat(v2, undef)) ->
7256 // shuffle(concat(v1, v2), undef)
7257 SDValue Op0 = N->getOperand(0);
7258 SDValue Op1 = N->getOperand(1);
7259 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
7260 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
7261 Op0.getNumOperands() != 2 ||
7262 Op1.getNumOperands() != 2)
7264 SDValue Concat0Op1 = Op0.getOperand(1);
7265 SDValue Concat1Op1 = Op1.getOperand(1);
7266 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
7267 Concat1Op1.getOpcode() != ISD::UNDEF)
7269 // Skip the transformation if any of the types are illegal.
7270 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7271 EVT VT = N->getValueType(0);
7272 if (!TLI.isTypeLegal(VT) ||
7273 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
7274 !TLI.isTypeLegal(Concat1Op1.getValueType()))
7277 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7278 Op0.getOperand(0), Op1.getOperand(0));
7279 // Translate the shuffle mask.
7280 SmallVector<int, 16> NewMask;
7281 unsigned NumElts = VT.getVectorNumElements();
7282 unsigned HalfElts = NumElts/2;
7283 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7284 for (unsigned n = 0; n < NumElts; ++n) {
7285 int MaskElt = SVN->getMaskElt(n);
7287 if (MaskElt < (int)HalfElts)
7289 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
7290 NewElt = HalfElts + MaskElt - NumElts;
7291 NewMask.push_back(NewElt);
7293 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
7294 DAG.getUNDEF(VT), NewMask.data());
7297 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
7298 /// NEON load/store intrinsics to merge base address updates.
7299 static SDValue CombineBaseUpdate(SDNode *N,
7300 TargetLowering::DAGCombinerInfo &DCI) {
7301 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7304 SelectionDAG &DAG = DCI.DAG;
7305 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
7306 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
7307 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
7308 SDValue Addr = N->getOperand(AddrOpIdx);
7310 // Search for a use of the address operand that is an increment.
7311 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7312 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7314 if (User->getOpcode() != ISD::ADD ||
7315 UI.getUse().getResNo() != Addr.getResNo())
7318 // Check that the add is independent of the load/store. Otherwise, folding
7319 // it would create a cycle.
7320 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7323 // Find the new opcode for the updating load/store.
7325 bool isLaneOp = false;
7326 unsigned NewOpc = 0;
7327 unsigned NumVecs = 0;
7329 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7331 default: assert(0 && "unexpected intrinsic for Neon base update");
7332 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
7334 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
7336 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
7338 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
7340 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
7341 NumVecs = 2; isLaneOp = true; break;
7342 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
7343 NumVecs = 3; isLaneOp = true; break;
7344 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
7345 NumVecs = 4; isLaneOp = true; break;
7346 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
7347 NumVecs = 1; isLoad = false; break;
7348 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
7349 NumVecs = 2; isLoad = false; break;
7350 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
7351 NumVecs = 3; isLoad = false; break;
7352 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
7353 NumVecs = 4; isLoad = false; break;
7354 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
7355 NumVecs = 2; isLoad = false; isLaneOp = true; break;
7356 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
7357 NumVecs = 3; isLoad = false; isLaneOp = true; break;
7358 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
7359 NumVecs = 4; isLoad = false; isLaneOp = true; break;
7363 switch (N->getOpcode()) {
7364 default: assert(0 && "unexpected opcode for Neon base update");
7365 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
7366 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
7367 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
7371 // Find the size of memory referenced by the load/store.
7374 VecTy = N->getValueType(0);
7376 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
7377 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7379 NumBytes /= VecTy.getVectorNumElements();
7381 // If the increment is a constant, it must match the memory ref size.
7382 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7383 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7384 uint64_t IncVal = CInc->getZExtValue();
7385 if (IncVal != NumBytes)
7387 } else if (NumBytes >= 3 * 16) {
7388 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
7389 // separate instructions that make it harder to use a non-constant update.
7393 // Create the new updating load/store node.
7395 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
7397 for (n = 0; n < NumResultVecs; ++n)
7399 Tys[n++] = MVT::i32;
7400 Tys[n] = MVT::Other;
7401 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
7402 SmallVector<SDValue, 8> Ops;
7403 Ops.push_back(N->getOperand(0)); // incoming chain
7404 Ops.push_back(N->getOperand(AddrOpIdx));
7406 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
7407 Ops.push_back(N->getOperand(i));
7409 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7410 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
7411 Ops.data(), Ops.size(),
7412 MemInt->getMemoryVT(),
7413 MemInt->getMemOperand());
7416 std::vector<SDValue> NewResults;
7417 for (unsigned i = 0; i < NumResultVecs; ++i) {
7418 NewResults.push_back(SDValue(UpdN.getNode(), i));
7420 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
7421 DCI.CombineTo(N, NewResults);
7422 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7429 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
7430 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
7431 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
7433 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
7434 SelectionDAG &DAG = DCI.DAG;
7435 EVT VT = N->getValueType(0);
7436 // vldN-dup instructions only support 64-bit vectors for N > 1.
7437 if (!VT.is64BitVector())
7440 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
7441 SDNode *VLD = N->getOperand(0).getNode();
7442 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
7444 unsigned NumVecs = 0;
7445 unsigned NewOpc = 0;
7446 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
7447 if (IntNo == Intrinsic::arm_neon_vld2lane) {
7449 NewOpc = ARMISD::VLD2DUP;
7450 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
7452 NewOpc = ARMISD::VLD3DUP;
7453 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
7455 NewOpc = ARMISD::VLD4DUP;
7460 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
7461 // numbers match the load.
7462 unsigned VLDLaneNo =
7463 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
7464 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7466 // Ignore uses of the chain result.
7467 if (UI.getUse().getResNo() == NumVecs)
7470 if (User->getOpcode() != ARMISD::VDUPLANE ||
7471 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
7475 // Create the vldN-dup node.
7478 for (n = 0; n < NumVecs; ++n)
7480 Tys[n] = MVT::Other;
7481 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
7482 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
7483 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
7484 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
7485 Ops, 2, VLDMemInt->getMemoryVT(),
7486 VLDMemInt->getMemOperand());
7489 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7491 unsigned ResNo = UI.getUse().getResNo();
7492 // Ignore uses of the chain result.
7493 if (ResNo == NumVecs)
7496 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
7499 // Now the vldN-lane intrinsic is dead except for its chain result.
7500 // Update uses of the chain.
7501 std::vector<SDValue> VLDDupResults;
7502 for (unsigned n = 0; n < NumVecs; ++n)
7503 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
7504 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
7505 DCI.CombineTo(VLD, VLDDupResults);
7510 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
7511 /// ARMISD::VDUPLANE.
7512 static SDValue PerformVDUPLANECombine(SDNode *N,
7513 TargetLowering::DAGCombinerInfo &DCI) {
7514 SDValue Op = N->getOperand(0);
7516 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
7517 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
7518 if (CombineVLDDUP(N, DCI))
7519 return SDValue(N, 0);
7521 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
7522 // redundant. Ignore bit_converts for now; element sizes are checked below.
7523 while (Op.getOpcode() == ISD::BITCAST)
7524 Op = Op.getOperand(0);
7525 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
7528 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
7529 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
7530 // The canonical VMOV for a zero vector uses a 32-bit element size.
7531 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7533 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
7535 EVT VT = N->getValueType(0);
7536 if (EltSize > VT.getVectorElementType().getSizeInBits())
7539 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
7542 // isConstVecPow2 - Return true if each vector element is a power of 2, all
7543 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
7544 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
7548 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
7550 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
7555 APFloat APF = C->getValueAPF();
7556 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
7557 != APFloat::opOK || !isExact)
7560 c0 = (I == 0) ? cN : c0;
7561 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
7568 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
7569 /// can replace combinations of VMUL and VCVT (floating-point to integer)
7570 /// when the VMUL has a constant operand that is a power of 2.
7572 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7573 /// vmul.f32 d16, d17, d16
7574 /// vcvt.s32.f32 d16, d16
7576 /// vcvt.s32.f32 d16, d16, #3
7577 static SDValue PerformVCVTCombine(SDNode *N,
7578 TargetLowering::DAGCombinerInfo &DCI,
7579 const ARMSubtarget *Subtarget) {
7580 SelectionDAG &DAG = DCI.DAG;
7581 SDValue Op = N->getOperand(0);
7583 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
7584 Op.getOpcode() != ISD::FMUL)
7588 SDValue N0 = Op->getOperand(0);
7589 SDValue ConstVec = Op->getOperand(1);
7590 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
7592 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7593 !isConstVecPow2(ConstVec, isSigned, C))
7596 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
7597 Intrinsic::arm_neon_vcvtfp2fxu;
7598 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7600 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
7601 DAG.getConstant(Log2_64(C), MVT::i32));
7604 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
7605 /// can replace combinations of VCVT (integer to floating-point) and VDIV
7606 /// when the VDIV has a constant operand that is a power of 2.
7608 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7609 /// vcvt.f32.s32 d16, d16
7610 /// vdiv.f32 d16, d17, d16
7612 /// vcvt.f32.s32 d16, d16, #3
7613 static SDValue PerformVDIVCombine(SDNode *N,
7614 TargetLowering::DAGCombinerInfo &DCI,
7615 const ARMSubtarget *Subtarget) {
7616 SelectionDAG &DAG = DCI.DAG;
7617 SDValue Op = N->getOperand(0);
7618 unsigned OpOpcode = Op.getNode()->getOpcode();
7620 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
7621 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
7625 SDValue ConstVec = N->getOperand(1);
7626 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
7628 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7629 !isConstVecPow2(ConstVec, isSigned, C))
7632 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
7633 Intrinsic::arm_neon_vcvtfxu2fp;
7634 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7636 DAG.getConstant(IntrinsicOpcode, MVT::i32),
7637 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
7640 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
7641 /// operand of a vector shift operation, where all the elements of the
7642 /// build_vector must have the same constant integer value.
7643 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
7644 // Ignore bit_converts.
7645 while (Op.getOpcode() == ISD::BITCAST)
7646 Op = Op.getOperand(0);
7647 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7648 APInt SplatBits, SplatUndef;
7649 unsigned SplatBitSize;
7651 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
7652 HasAnyUndefs, ElementBits) ||
7653 SplatBitSize > ElementBits)
7655 Cnt = SplatBits.getSExtValue();
7659 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
7660 /// operand of a vector shift left operation. That value must be in the range:
7661 /// 0 <= Value < ElementBits for a left shift; or
7662 /// 0 <= Value <= ElementBits for a long left shift.
7663 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
7664 assert(VT.isVector() && "vector shift count is not a vector type");
7665 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7666 if (! getVShiftImm(Op, ElementBits, Cnt))
7668 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
7671 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
7672 /// operand of a vector shift right operation. For a shift opcode, the value
7673 /// is positive, but for an intrinsic the value count must be negative. The
7674 /// absolute value must be in the range:
7675 /// 1 <= |Value| <= ElementBits for a right shift; or
7676 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
7677 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
7679 assert(VT.isVector() && "vector shift count is not a vector type");
7680 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7681 if (! getVShiftImm(Op, ElementBits, Cnt))
7685 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
7688 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
7689 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
7690 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
7693 // Don't do anything for most intrinsics.
7696 // Vector shifts: check for immediate versions and lower them.
7697 // Note: This is done during DAG combining instead of DAG legalizing because
7698 // the build_vectors for 64-bit vector element shift counts are generally
7699 // not legal, and it is hard to see their values after they get legalized to
7700 // loads from a constant pool.
7701 case Intrinsic::arm_neon_vshifts:
7702 case Intrinsic::arm_neon_vshiftu:
7703 case Intrinsic::arm_neon_vshiftls:
7704 case Intrinsic::arm_neon_vshiftlu:
7705 case Intrinsic::arm_neon_vshiftn:
7706 case Intrinsic::arm_neon_vrshifts:
7707 case Intrinsic::arm_neon_vrshiftu:
7708 case Intrinsic::arm_neon_vrshiftn:
7709 case Intrinsic::arm_neon_vqshifts:
7710 case Intrinsic::arm_neon_vqshiftu:
7711 case Intrinsic::arm_neon_vqshiftsu:
7712 case Intrinsic::arm_neon_vqshiftns:
7713 case Intrinsic::arm_neon_vqshiftnu:
7714 case Intrinsic::arm_neon_vqshiftnsu:
7715 case Intrinsic::arm_neon_vqrshiftns:
7716 case Intrinsic::arm_neon_vqrshiftnu:
7717 case Intrinsic::arm_neon_vqrshiftnsu: {
7718 EVT VT = N->getOperand(1).getValueType();
7720 unsigned VShiftOpc = 0;
7723 case Intrinsic::arm_neon_vshifts:
7724 case Intrinsic::arm_neon_vshiftu:
7725 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
7726 VShiftOpc = ARMISD::VSHL;
7729 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
7730 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
7731 ARMISD::VSHRs : ARMISD::VSHRu);
7736 case Intrinsic::arm_neon_vshiftls:
7737 case Intrinsic::arm_neon_vshiftlu:
7738 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
7740 llvm_unreachable("invalid shift count for vshll intrinsic");
7742 case Intrinsic::arm_neon_vrshifts:
7743 case Intrinsic::arm_neon_vrshiftu:
7744 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
7748 case Intrinsic::arm_neon_vqshifts:
7749 case Intrinsic::arm_neon_vqshiftu:
7750 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7754 case Intrinsic::arm_neon_vqshiftsu:
7755 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7757 llvm_unreachable("invalid shift count for vqshlu intrinsic");
7759 case Intrinsic::arm_neon_vshiftn:
7760 case Intrinsic::arm_neon_vrshiftn:
7761 case Intrinsic::arm_neon_vqshiftns:
7762 case Intrinsic::arm_neon_vqshiftnu:
7763 case Intrinsic::arm_neon_vqshiftnsu:
7764 case Intrinsic::arm_neon_vqrshiftns:
7765 case Intrinsic::arm_neon_vqrshiftnu:
7766 case Intrinsic::arm_neon_vqrshiftnsu:
7767 // Narrowing shifts require an immediate right shift.
7768 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
7770 llvm_unreachable("invalid shift count for narrowing vector shift "
7774 llvm_unreachable("unhandled vector shift");
7778 case Intrinsic::arm_neon_vshifts:
7779 case Intrinsic::arm_neon_vshiftu:
7780 // Opcode already set above.
7782 case Intrinsic::arm_neon_vshiftls:
7783 case Intrinsic::arm_neon_vshiftlu:
7784 if (Cnt == VT.getVectorElementType().getSizeInBits())
7785 VShiftOpc = ARMISD::VSHLLi;
7787 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
7788 ARMISD::VSHLLs : ARMISD::VSHLLu);
7790 case Intrinsic::arm_neon_vshiftn:
7791 VShiftOpc = ARMISD::VSHRN; break;
7792 case Intrinsic::arm_neon_vrshifts:
7793 VShiftOpc = ARMISD::VRSHRs; break;
7794 case Intrinsic::arm_neon_vrshiftu:
7795 VShiftOpc = ARMISD::VRSHRu; break;
7796 case Intrinsic::arm_neon_vrshiftn:
7797 VShiftOpc = ARMISD::VRSHRN; break;
7798 case Intrinsic::arm_neon_vqshifts:
7799 VShiftOpc = ARMISD::VQSHLs; break;
7800 case Intrinsic::arm_neon_vqshiftu:
7801 VShiftOpc = ARMISD::VQSHLu; break;
7802 case Intrinsic::arm_neon_vqshiftsu:
7803 VShiftOpc = ARMISD::VQSHLsu; break;
7804 case Intrinsic::arm_neon_vqshiftns:
7805 VShiftOpc = ARMISD::VQSHRNs; break;
7806 case Intrinsic::arm_neon_vqshiftnu:
7807 VShiftOpc = ARMISD::VQSHRNu; break;
7808 case Intrinsic::arm_neon_vqshiftnsu:
7809 VShiftOpc = ARMISD::VQSHRNsu; break;
7810 case Intrinsic::arm_neon_vqrshiftns:
7811 VShiftOpc = ARMISD::VQRSHRNs; break;
7812 case Intrinsic::arm_neon_vqrshiftnu:
7813 VShiftOpc = ARMISD::VQRSHRNu; break;
7814 case Intrinsic::arm_neon_vqrshiftnsu:
7815 VShiftOpc = ARMISD::VQRSHRNsu; break;
7818 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7819 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
7822 case Intrinsic::arm_neon_vshiftins: {
7823 EVT VT = N->getOperand(1).getValueType();
7825 unsigned VShiftOpc = 0;
7827 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
7828 VShiftOpc = ARMISD::VSLI;
7829 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
7830 VShiftOpc = ARMISD::VSRI;
7832 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
7835 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7836 N->getOperand(1), N->getOperand(2),
7837 DAG.getConstant(Cnt, MVT::i32));
7840 case Intrinsic::arm_neon_vqrshifts:
7841 case Intrinsic::arm_neon_vqrshiftu:
7842 // No immediate versions of these to check for.
7849 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
7850 /// lowers them. As with the vector shift intrinsics, this is done during DAG
7851 /// combining instead of DAG legalizing because the build_vectors for 64-bit
7852 /// vector element shift counts are generally not legal, and it is hard to see
7853 /// their values after they get legalized to loads from a constant pool.
7854 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
7855 const ARMSubtarget *ST) {
7856 EVT VT = N->getValueType(0);
7858 // Nothing to be done for scalar shifts.
7859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7860 if (!VT.isVector() || !TLI.isTypeLegal(VT))
7863 assert(ST->hasNEON() && "unexpected vector shift");
7866 switch (N->getOpcode()) {
7867 default: llvm_unreachable("unexpected shift opcode");
7870 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
7871 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
7872 DAG.getConstant(Cnt, MVT::i32));
7877 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
7878 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
7879 ARMISD::VSHRs : ARMISD::VSHRu);
7880 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
7881 DAG.getConstant(Cnt, MVT::i32));
7887 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
7888 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
7889 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
7890 const ARMSubtarget *ST) {
7891 SDValue N0 = N->getOperand(0);
7893 // Check for sign- and zero-extensions of vector extract operations of 8-
7894 // and 16-bit vector elements. NEON supports these directly. They are
7895 // handled during DAG combining because type legalization will promote them
7896 // to 32-bit types and it is messy to recognize the operations after that.
7897 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7898 SDValue Vec = N0.getOperand(0);
7899 SDValue Lane = N0.getOperand(1);
7900 EVT VT = N->getValueType(0);
7901 EVT EltVT = N0.getValueType();
7902 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7904 if (VT == MVT::i32 &&
7905 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
7906 TLI.isTypeLegal(Vec.getValueType()) &&
7907 isa<ConstantSDNode>(Lane)) {
7910 switch (N->getOpcode()) {
7911 default: llvm_unreachable("unexpected opcode");
7912 case ISD::SIGN_EXTEND:
7913 Opc = ARMISD::VGETLANEs;
7915 case ISD::ZERO_EXTEND:
7916 case ISD::ANY_EXTEND:
7917 Opc = ARMISD::VGETLANEu;
7920 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
7927 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
7928 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
7929 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
7930 const ARMSubtarget *ST) {
7931 // If the target supports NEON, try to use vmax/vmin instructions for f32
7932 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
7933 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
7934 // a NaN; only do the transformation when it matches that behavior.
7936 // For now only do this when using NEON for FP operations; if using VFP, it
7937 // is not obvious that the benefit outweighs the cost of switching to the
7939 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
7940 N->getValueType(0) != MVT::f32)
7943 SDValue CondLHS = N->getOperand(0);
7944 SDValue CondRHS = N->getOperand(1);
7945 SDValue LHS = N->getOperand(2);
7946 SDValue RHS = N->getOperand(3);
7947 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
7949 unsigned Opcode = 0;
7951 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
7952 IsReversed = false; // x CC y ? x : y
7953 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
7954 IsReversed = true ; // x CC y ? y : x
7968 // If LHS is NaN, an ordered comparison will be false and the result will
7969 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
7970 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7971 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
7972 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7974 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
7975 // will return -0, so vmin can only be used for unsafe math or if one of
7976 // the operands is known to be nonzero.
7977 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
7978 !DAG.getTarget().Options.UnsafeFPMath &&
7979 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7981 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
7990 // If LHS is NaN, an ordered comparison will be false and the result will
7991 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
7992 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7993 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
7994 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7996 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
7997 // will return +0, so vmax can only be used for unsafe math or if one of
7998 // the operands is known to be nonzero.
7999 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
8000 !DAG.getTarget().Options.UnsafeFPMath &&
8001 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8003 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
8009 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
8012 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
8014 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
8015 SDValue Cmp = N->getOperand(4);
8016 if (Cmp.getOpcode() != ARMISD::CMPZ)
8017 // Only looking at EQ and NE cases.
8020 EVT VT = N->getValueType(0);
8021 DebugLoc dl = N->getDebugLoc();
8022 SDValue LHS = Cmp.getOperand(0);
8023 SDValue RHS = Cmp.getOperand(1);
8024 SDValue FalseVal = N->getOperand(0);
8025 SDValue TrueVal = N->getOperand(1);
8026 SDValue ARMcc = N->getOperand(2);
8027 ARMCC::CondCodes CC =
8028 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
8046 /// FIXME: Turn this into a target neutral optimization?
8048 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
8049 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
8050 N->getOperand(3), Cmp);
8051 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
8053 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
8054 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
8055 N->getOperand(3), NewCmp);
8058 if (Res.getNode()) {
8059 APInt KnownZero, KnownOne;
8060 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
8061 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
8062 // Capture demanded bits information that would be otherwise lost.
8063 if (KnownZero == 0xfffffffe)
8064 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
8065 DAG.getValueType(MVT::i1));
8066 else if (KnownZero == 0xffffff00)
8067 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
8068 DAG.getValueType(MVT::i8));
8069 else if (KnownZero == 0xffff0000)
8070 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
8071 DAG.getValueType(MVT::i16));
8077 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
8078 DAGCombinerInfo &DCI) const {
8079 switch (N->getOpcode()) {
8081 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
8082 case ISD::SUB: return PerformSUBCombine(N, DCI);
8083 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
8084 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
8085 case ISD::AND: return PerformANDCombine(N, DCI);
8086 case ARMISD::BFI: return PerformBFICombine(N, DCI);
8087 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
8088 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
8089 case ISD::STORE: return PerformSTORECombine(N, DCI);
8090 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
8091 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
8092 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
8093 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
8094 case ISD::FP_TO_SINT:
8095 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
8096 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
8097 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
8100 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
8101 case ISD::SIGN_EXTEND:
8102 case ISD::ZERO_EXTEND:
8103 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
8104 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
8105 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
8106 case ARMISD::VLD2DUP:
8107 case ARMISD::VLD3DUP:
8108 case ARMISD::VLD4DUP:
8109 return CombineBaseUpdate(N, DCI);
8110 case ISD::INTRINSIC_VOID:
8111 case ISD::INTRINSIC_W_CHAIN:
8112 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8113 case Intrinsic::arm_neon_vld1:
8114 case Intrinsic::arm_neon_vld2:
8115 case Intrinsic::arm_neon_vld3:
8116 case Intrinsic::arm_neon_vld4:
8117 case Intrinsic::arm_neon_vld2lane:
8118 case Intrinsic::arm_neon_vld3lane:
8119 case Intrinsic::arm_neon_vld4lane:
8120 case Intrinsic::arm_neon_vst1:
8121 case Intrinsic::arm_neon_vst2:
8122 case Intrinsic::arm_neon_vst3:
8123 case Intrinsic::arm_neon_vst4:
8124 case Intrinsic::arm_neon_vst2lane:
8125 case Intrinsic::arm_neon_vst3lane:
8126 case Intrinsic::arm_neon_vst4lane:
8127 return CombineBaseUpdate(N, DCI);
8135 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
8137 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
8140 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
8141 if (!Subtarget->allowsUnalignedMem())
8144 switch (VT.getSimpleVT().SimpleTy) {
8151 // FIXME: VLD1 etc with standard alignment is legal.
8155 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
8156 unsigned AlignCheck) {
8157 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
8158 (DstAlign == 0 || DstAlign % AlignCheck == 0));
8161 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
8162 unsigned DstAlign, unsigned SrcAlign,
8165 MachineFunction &MF) const {
8166 const Function *F = MF.getFunction();
8168 // See if we can use NEON instructions for this...
8170 !F->hasFnAttr(Attribute::NoImplicitFloat) &&
8171 Subtarget->hasNEON()) {
8172 if (memOpAlign(SrcAlign, DstAlign, 16) && Size >= 16) {
8174 } else if (memOpAlign(SrcAlign, DstAlign, 8) && Size >= 8) {
8179 // Lowering to i32/i16 if the size permits.
8182 } else if (Size >= 2) {
8186 // Let the target-independent logic figure it out.
8190 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
8195 switch (VT.getSimpleVT().SimpleTy) {
8196 default: return false;
8211 if ((V & (Scale - 1)) != 0)
8214 return V == (V & ((1LL << 5) - 1));
8217 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
8218 const ARMSubtarget *Subtarget) {
8225 switch (VT.getSimpleVT().SimpleTy) {
8226 default: return false;
8231 // + imm12 or - imm8
8233 return V == (V & ((1LL << 8) - 1));
8234 return V == (V & ((1LL << 12) - 1));
8237 // Same as ARM mode. FIXME: NEON?
8238 if (!Subtarget->hasVFP2())
8243 return V == (V & ((1LL << 8) - 1));
8247 /// isLegalAddressImmediate - Return true if the integer value can be used
8248 /// as the offset of the target addressing mode for load / store of the
8250 static bool isLegalAddressImmediate(int64_t V, EVT VT,
8251 const ARMSubtarget *Subtarget) {
8258 if (Subtarget->isThumb1Only())
8259 return isLegalT1AddressImmediate(V, VT);
8260 else if (Subtarget->isThumb2())
8261 return isLegalT2AddressImmediate(V, VT, Subtarget);
8266 switch (VT.getSimpleVT().SimpleTy) {
8267 default: return false;
8272 return V == (V & ((1LL << 12) - 1));
8275 return V == (V & ((1LL << 8) - 1));
8278 if (!Subtarget->hasVFP2()) // FIXME: NEON?
8283 return V == (V & ((1LL << 8) - 1));
8287 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
8289 int Scale = AM.Scale;
8293 switch (VT.getSimpleVT().SimpleTy) {
8294 default: return false;
8303 return Scale == 2 || Scale == 4 || Scale == 8;
8306 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8310 // Note, we allow "void" uses (basically, uses that aren't loads or
8311 // stores), because arm allows folding a scale into many arithmetic
8312 // operations. This should be made more precise and revisited later.
8314 // Allow r << imm, but the imm has to be a multiple of two.
8315 if (Scale & 1) return false;
8316 return isPowerOf2_32(Scale);
8320 /// isLegalAddressingMode - Return true if the addressing mode represented
8321 /// by AM is legal for this target, for a load/store of the specified type.
8322 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8324 EVT VT = getValueType(Ty, true);
8325 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
8328 // Can never fold addr of global into load/store.
8333 case 0: // no scale reg, must be "r+i" or "r", or "i".
8336 if (Subtarget->isThumb1Only())
8340 // ARM doesn't support any R+R*scale+imm addr modes.
8347 if (Subtarget->isThumb2())
8348 return isLegalT2ScaledAddressingMode(AM, VT);
8350 int Scale = AM.Scale;
8351 switch (VT.getSimpleVT().SimpleTy) {
8352 default: return false;
8356 if (Scale < 0) Scale = -Scale;
8360 return isPowerOf2_32(Scale & ~1);
8364 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8369 // Note, we allow "void" uses (basically, uses that aren't loads or
8370 // stores), because arm allows folding a scale into many arithmetic
8371 // operations. This should be made more precise and revisited later.
8373 // Allow r << imm, but the imm has to be a multiple of two.
8374 if (Scale & 1) return false;
8375 return isPowerOf2_32(Scale);
8382 /// isLegalICmpImmediate - Return true if the specified immediate is legal
8383 /// icmp immediate, that is the target has icmp instructions which can compare
8384 /// a register against the immediate without having to materialize the
8385 /// immediate into a register.
8386 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8387 if (!Subtarget->isThumb())
8388 return ARM_AM::getSOImmVal(Imm) != -1;
8389 if (Subtarget->isThumb2())
8390 return ARM_AM::getT2SOImmVal(Imm) != -1;
8391 return Imm >= 0 && Imm <= 255;
8394 /// isLegalAddImmediate - Return true if the specified immediate is legal
8395 /// add immediate, that is the target has add instructions which can add
8396 /// a register with the immediate without having to materialize the
8397 /// immediate into a register.
8398 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8399 return ARM_AM::getSOImmVal(Imm) != -1;
8402 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
8403 bool isSEXTLoad, SDValue &Base,
8404 SDValue &Offset, bool &isInc,
8405 SelectionDAG &DAG) {
8406 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8409 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
8411 Base = Ptr->getOperand(0);
8412 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8413 int RHSC = (int)RHS->getZExtValue();
8414 if (RHSC < 0 && RHSC > -256) {
8415 assert(Ptr->getOpcode() == ISD::ADD);
8417 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8421 isInc = (Ptr->getOpcode() == ISD::ADD);
8422 Offset = Ptr->getOperand(1);
8424 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
8426 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8427 int RHSC = (int)RHS->getZExtValue();
8428 if (RHSC < 0 && RHSC > -0x1000) {
8429 assert(Ptr->getOpcode() == ISD::ADD);
8431 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8432 Base = Ptr->getOperand(0);
8437 if (Ptr->getOpcode() == ISD::ADD) {
8439 ARM_AM::ShiftOpc ShOpcVal=
8440 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
8441 if (ShOpcVal != ARM_AM::no_shift) {
8442 Base = Ptr->getOperand(1);
8443 Offset = Ptr->getOperand(0);
8445 Base = Ptr->getOperand(0);
8446 Offset = Ptr->getOperand(1);
8451 isInc = (Ptr->getOpcode() == ISD::ADD);
8452 Base = Ptr->getOperand(0);
8453 Offset = Ptr->getOperand(1);
8457 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
8461 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
8462 bool isSEXTLoad, SDValue &Base,
8463 SDValue &Offset, bool &isInc,
8464 SelectionDAG &DAG) {
8465 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8468 Base = Ptr->getOperand(0);
8469 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8470 int RHSC = (int)RHS->getZExtValue();
8471 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
8472 assert(Ptr->getOpcode() == ISD::ADD);
8474 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8476 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
8477 isInc = Ptr->getOpcode() == ISD::ADD;
8478 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
8486 /// getPreIndexedAddressParts - returns true by value, base pointer and
8487 /// offset pointer and addressing mode by reference if the node's address
8488 /// can be legally represented as pre-indexed load / store address.
8490 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8492 ISD::MemIndexedMode &AM,
8493 SelectionDAG &DAG) const {
8494 if (Subtarget->isThumb1Only())
8499 bool isSEXTLoad = false;
8500 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8501 Ptr = LD->getBasePtr();
8502 VT = LD->getMemoryVT();
8503 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8504 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8505 Ptr = ST->getBasePtr();
8506 VT = ST->getMemoryVT();
8511 bool isLegal = false;
8512 if (Subtarget->isThumb2())
8513 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8514 Offset, isInc, DAG);
8516 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8517 Offset, isInc, DAG);
8521 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
8525 /// getPostIndexedAddressParts - returns true by value, base pointer and
8526 /// offset pointer and addressing mode by reference if this node can be
8527 /// combined with a load / store to form a post-indexed load / store.
8528 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
8531 ISD::MemIndexedMode &AM,
8532 SelectionDAG &DAG) const {
8533 if (Subtarget->isThumb1Only())
8538 bool isSEXTLoad = false;
8539 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8540 VT = LD->getMemoryVT();
8541 Ptr = LD->getBasePtr();
8542 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8543 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8544 VT = ST->getMemoryVT();
8545 Ptr = ST->getBasePtr();
8550 bool isLegal = false;
8551 if (Subtarget->isThumb2())
8552 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8555 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8561 // Swap base ptr and offset to catch more post-index load / store when
8562 // it's legal. In Thumb2 mode, offset must be an immediate.
8563 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
8564 !Subtarget->isThumb2())
8565 std::swap(Base, Offset);
8567 // Post-indexed load / store update the base pointer.
8572 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
8576 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8580 const SelectionDAG &DAG,
8581 unsigned Depth) const {
8582 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
8583 switch (Op.getOpcode()) {
8585 case ARMISD::CMOV: {
8586 // Bits are known zero/one if known on the LHS and RHS.
8587 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
8588 if (KnownZero == 0 && KnownOne == 0) return;
8590 APInt KnownZeroRHS, KnownOneRHS;
8591 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
8592 KnownZeroRHS, KnownOneRHS, Depth+1);
8593 KnownZero &= KnownZeroRHS;
8594 KnownOne &= KnownOneRHS;
8600 //===----------------------------------------------------------------------===//
8601 // ARM Inline Assembly Support
8602 //===----------------------------------------------------------------------===//
8604 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
8605 // Looking for "rev" which is V6+.
8606 if (!Subtarget->hasV6Ops())
8609 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8610 std::string AsmStr = IA->getAsmString();
8611 SmallVector<StringRef, 4> AsmPieces;
8612 SplitString(AsmStr, AsmPieces, ";\n");
8614 switch (AsmPieces.size()) {
8615 default: return false;
8617 AsmStr = AsmPieces[0];
8619 SplitString(AsmStr, AsmPieces, " \t,");
8622 if (AsmPieces.size() == 3 &&
8623 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
8624 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
8625 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8626 if (Ty && Ty->getBitWidth() == 32)
8627 return IntrinsicLowering::LowerToByteSwap(CI);
8635 /// getConstraintType - Given a constraint letter, return the type of
8636 /// constraint it is for this target.
8637 ARMTargetLowering::ConstraintType
8638 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
8639 if (Constraint.size() == 1) {
8640 switch (Constraint[0]) {
8642 case 'l': return C_RegisterClass;
8643 case 'w': return C_RegisterClass;
8644 case 'h': return C_RegisterClass;
8645 case 'x': return C_RegisterClass;
8646 case 't': return C_RegisterClass;
8647 case 'j': return C_Other; // Constant for movw.
8648 // An address with a single base register. Due to the way we
8649 // currently handle addresses it is the same as an 'r' memory constraint.
8650 case 'Q': return C_Memory;
8652 } else if (Constraint.size() == 2) {
8653 switch (Constraint[0]) {
8655 // All 'U+' constraints are addresses.
8656 case 'U': return C_Memory;
8659 return TargetLowering::getConstraintType(Constraint);
8662 /// Examine constraint type and operand type and determine a weight value.
8663 /// This object must already have been set up with the operand type
8664 /// and the current alternative constraint selected.
8665 TargetLowering::ConstraintWeight
8666 ARMTargetLowering::getSingleConstraintMatchWeight(
8667 AsmOperandInfo &info, const char *constraint) const {
8668 ConstraintWeight weight = CW_Invalid;
8669 Value *CallOperandVal = info.CallOperandVal;
8670 // If we don't have a value, we can't do a match,
8671 // but allow it at the lowest weight.
8672 if (CallOperandVal == NULL)
8674 Type *type = CallOperandVal->getType();
8675 // Look at the constraint type.
8676 switch (*constraint) {
8678 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8681 if (type->isIntegerTy()) {
8682 if (Subtarget->isThumb())
8683 weight = CW_SpecificReg;
8685 weight = CW_Register;
8689 if (type->isFloatingPointTy())
8690 weight = CW_Register;
8696 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
8698 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8700 if (Constraint.size() == 1) {
8701 // GCC ARM Constraint Letters
8702 switch (Constraint[0]) {
8703 case 'l': // Low regs or general regs.
8704 if (Subtarget->isThumb())
8705 return RCPair(0U, ARM::tGPRRegisterClass);
8707 return RCPair(0U, ARM::GPRRegisterClass);
8708 case 'h': // High regs or no regs.
8709 if (Subtarget->isThumb())
8710 return RCPair(0U, ARM::hGPRRegisterClass);
8713 return RCPair(0U, ARM::GPRRegisterClass);
8716 return RCPair(0U, ARM::SPRRegisterClass);
8717 if (VT.getSizeInBits() == 64)
8718 return RCPair(0U, ARM::DPRRegisterClass);
8719 if (VT.getSizeInBits() == 128)
8720 return RCPair(0U, ARM::QPRRegisterClass);
8724 return RCPair(0U, ARM::SPR_8RegisterClass);
8725 if (VT.getSizeInBits() == 64)
8726 return RCPair(0U, ARM::DPR_8RegisterClass);
8727 if (VT.getSizeInBits() == 128)
8728 return RCPair(0U, ARM::QPR_8RegisterClass);
8732 return RCPair(0U, ARM::SPRRegisterClass);
8736 if (StringRef("{cc}").equals_lower(Constraint))
8737 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
8739 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8742 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8743 /// vector. If it is invalid, don't add anything to Ops.
8744 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8745 std::string &Constraint,
8746 std::vector<SDValue>&Ops,
8747 SelectionDAG &DAG) const {
8748 SDValue Result(0, 0);
8750 // Currently only support length 1 constraints.
8751 if (Constraint.length() != 1) return;
8753 char ConstraintLetter = Constraint[0];
8754 switch (ConstraintLetter) {
8757 case 'I': case 'J': case 'K': case 'L':
8758 case 'M': case 'N': case 'O':
8759 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
8763 int64_t CVal64 = C->getSExtValue();
8764 int CVal = (int) CVal64;
8765 // None of these constraints allow values larger than 32 bits. Check
8766 // that the value fits in an int.
8770 switch (ConstraintLetter) {
8772 // Constant suitable for movw, must be between 0 and
8774 if (Subtarget->hasV6T2Ops())
8775 if (CVal >= 0 && CVal <= 65535)
8779 if (Subtarget->isThumb1Only()) {
8780 // This must be a constant between 0 and 255, for ADD
8782 if (CVal >= 0 && CVal <= 255)
8784 } else if (Subtarget->isThumb2()) {
8785 // A constant that can be used as an immediate value in a
8786 // data-processing instruction.
8787 if (ARM_AM::getT2SOImmVal(CVal) != -1)
8790 // A constant that can be used as an immediate value in a
8791 // data-processing instruction.
8792 if (ARM_AM::getSOImmVal(CVal) != -1)
8798 if (Subtarget->isThumb()) { // FIXME thumb2
8799 // This must be a constant between -255 and -1, for negated ADD
8800 // immediates. This can be used in GCC with an "n" modifier that
8801 // prints the negated value, for use with SUB instructions. It is
8802 // not useful otherwise but is implemented for compatibility.
8803 if (CVal >= -255 && CVal <= -1)
8806 // This must be a constant between -4095 and 4095. It is not clear
8807 // what this constraint is intended for. Implemented for
8808 // compatibility with GCC.
8809 if (CVal >= -4095 && CVal <= 4095)
8815 if (Subtarget->isThumb1Only()) {
8816 // A 32-bit value where only one byte has a nonzero value. Exclude
8817 // zero to match GCC. This constraint is used by GCC internally for
8818 // constants that can be loaded with a move/shift combination.
8819 // It is not useful otherwise but is implemented for compatibility.
8820 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
8822 } else if (Subtarget->isThumb2()) {
8823 // A constant whose bitwise inverse can be used as an immediate
8824 // value in a data-processing instruction. This can be used in GCC
8825 // with a "B" modifier that prints the inverted value, for use with
8826 // BIC and MVN instructions. It is not useful otherwise but is
8827 // implemented for compatibility.
8828 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
8831 // A constant whose bitwise inverse can be used as an immediate
8832 // value in a data-processing instruction. This can be used in GCC
8833 // with a "B" modifier that prints the inverted value, for use with
8834 // BIC and MVN instructions. It is not useful otherwise but is
8835 // implemented for compatibility.
8836 if (ARM_AM::getSOImmVal(~CVal) != -1)
8842 if (Subtarget->isThumb1Only()) {
8843 // This must be a constant between -7 and 7,
8844 // for 3-operand ADD/SUB immediate instructions.
8845 if (CVal >= -7 && CVal < 7)
8847 } else if (Subtarget->isThumb2()) {
8848 // A constant whose negation can be used as an immediate value in a
8849 // data-processing instruction. This can be used in GCC with an "n"
8850 // modifier that prints the negated value, for use with SUB
8851 // instructions. It is not useful otherwise but is implemented for
8853 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
8856 // A constant whose negation can be used as an immediate value in a
8857 // data-processing instruction. This can be used in GCC with an "n"
8858 // modifier that prints the negated value, for use with SUB
8859 // instructions. It is not useful otherwise but is implemented for
8861 if (ARM_AM::getSOImmVal(-CVal) != -1)
8867 if (Subtarget->isThumb()) { // FIXME thumb2
8868 // This must be a multiple of 4 between 0 and 1020, for
8869 // ADD sp + immediate.
8870 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
8873 // A power of two or a constant between 0 and 32. This is used in
8874 // GCC for the shift amount on shifted register operands, but it is
8875 // useful in general for any shift amounts.
8876 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
8882 if (Subtarget->isThumb()) { // FIXME thumb2
8883 // This must be a constant between 0 and 31, for shift amounts.
8884 if (CVal >= 0 && CVal <= 31)
8890 if (Subtarget->isThumb()) { // FIXME thumb2
8891 // This must be a multiple of 4 between -508 and 508, for
8892 // ADD/SUB sp = sp + immediate.
8893 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
8898 Result = DAG.getTargetConstant(CVal, Op.getValueType());
8902 if (Result.getNode()) {
8903 Ops.push_back(Result);
8906 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8910 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8911 // The ARM target isn't yet aware of offsets.
8915 bool ARM::isBitFieldInvertedMask(unsigned v) {
8916 if (v == 0xffffffff)
8918 // there can be 1's on either or both "outsides", all the "inside"
8920 unsigned int lsb = 0, msb = 31;
8921 while (v & (1 << msb)) --msb;
8922 while (v & (1 << lsb)) ++lsb;
8923 for (unsigned int i = lsb; i <= msb; ++i) {
8930 /// isFPImmLegal - Returns true if the target can instruction select the
8931 /// specified FP immediate natively. If false, the legalizer will
8932 /// materialize the FP immediate as a load from a constant pool.
8933 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
8934 if (!Subtarget->hasVFP3())
8937 return ARM_AM::getFP32Imm(Imm) != -1;
8939 return ARM_AM::getFP64Imm(Imm) != -1;
8943 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
8944 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
8945 /// specified in the intrinsic calls.
8946 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
8948 unsigned Intrinsic) const {
8949 switch (Intrinsic) {
8950 case Intrinsic::arm_neon_vld1:
8951 case Intrinsic::arm_neon_vld2:
8952 case Intrinsic::arm_neon_vld3:
8953 case Intrinsic::arm_neon_vld4:
8954 case Intrinsic::arm_neon_vld2lane:
8955 case Intrinsic::arm_neon_vld3lane:
8956 case Intrinsic::arm_neon_vld4lane: {
8957 Info.opc = ISD::INTRINSIC_W_CHAIN;
8958 // Conservatively set memVT to the entire set of vectors loaded.
8959 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
8960 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8961 Info.ptrVal = I.getArgOperand(0);
8963 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8964 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8965 Info.vol = false; // volatile loads with NEON intrinsics not supported
8966 Info.readMem = true;
8967 Info.writeMem = false;
8970 case Intrinsic::arm_neon_vst1:
8971 case Intrinsic::arm_neon_vst2:
8972 case Intrinsic::arm_neon_vst3:
8973 case Intrinsic::arm_neon_vst4:
8974 case Intrinsic::arm_neon_vst2lane:
8975 case Intrinsic::arm_neon_vst3lane:
8976 case Intrinsic::arm_neon_vst4lane: {
8977 Info.opc = ISD::INTRINSIC_VOID;
8978 // Conservatively set memVT to the entire set of vectors stored.
8979 unsigned NumElts = 0;
8980 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
8981 Type *ArgTy = I.getArgOperand(ArgI)->getType();
8982 if (!ArgTy->isVectorTy())
8984 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
8986 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8987 Info.ptrVal = I.getArgOperand(0);
8989 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8990 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8991 Info.vol = false; // volatile stores with NEON intrinsics not supported
8992 Info.readMem = false;
8993 Info.writeMem = true;
8996 case Intrinsic::arm_strexd: {
8997 Info.opc = ISD::INTRINSIC_W_CHAIN;
8998 Info.memVT = MVT::i64;
8999 Info.ptrVal = I.getArgOperand(2);
9003 Info.readMem = false;
9004 Info.writeMem = true;
9007 case Intrinsic::arm_ldrexd: {
9008 Info.opc = ISD::INTRINSIC_W_CHAIN;
9009 Info.memVT = MVT::i64;
9010 Info.ptrVal = I.getArgOperand(0);
9014 Info.readMem = true;
9015 Info.writeMem = false;