1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
35 //===--------------------------------------------------------------------===//
36 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
37 /// instructions for SelectionDAG operations.
40 class ARMDAGToDAGISel : public SelectionDAGISel {
43 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
44 /// make the right decision when generating code for different targets.
45 const ARMSubtarget *Subtarget;
48 explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
49 : SelectionDAGISel(tm), TM(tm),
50 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
53 virtual const char *getPassName() const {
54 return "ARM Instruction Selection";
57 /// getI32Imm - Return a target constant with the specified value, of type i32.
58 inline SDValue getI32Imm(unsigned Imm) {
59 return CurDAG->getTargetConstant(Imm, MVT::i32);
62 SDNode *Select(SDValue Op);
63 virtual void InstructionSelect();
64 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
65 SDValue &Offset, SDValue &Opc);
66 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
67 SDValue &Offset, SDValue &Opc);
68 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
69 SDValue &Offset, SDValue &Opc);
70 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
71 SDValue &Offset, SDValue &Opc);
72 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
75 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
78 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
80 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
81 SDValue &Base, SDValue &OffImm,
83 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
84 SDValue &OffImm, SDValue &Offset);
85 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
86 SDValue &OffImm, SDValue &Offset);
87 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
88 SDValue &OffImm, SDValue &Offset);
89 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
92 bool SelectShifterOperand(SDValue Op, SDValue N,
93 SDValue &BaseReg, SDValue &Opc);
95 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
96 SDValue &B, SDValue &C);
98 // Include the pieces autogenerated from the target description.
99 #include "ARMGenDAGISel.inc"
102 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
103 /// inline asm expressions.
104 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
106 std::vector<SDValue> &OutOps);
110 void ARMDAGToDAGISel::InstructionSelect() {
114 CurDAG->RemoveDeadNodes();
117 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
118 SDValue &Base, SDValue &Offset,
120 if (N.getOpcode() == ISD::MUL) {
121 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
122 // X * [3,5,9] -> X + X * [2,4,8] etc.
123 int RHSC = (int)RHS->getZExtValue();
126 ARM_AM::AddrOpc AddSub = ARM_AM::add;
128 AddSub = ARM_AM::sub;
131 if (isPowerOf2_32(RHSC)) {
132 unsigned ShAmt = Log2_32(RHSC);
133 Base = Offset = N.getOperand(0);
134 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
143 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
145 if (N.getOpcode() == ISD::FrameIndex) {
146 int FI = cast<FrameIndexSDNode>(N)->getIndex();
147 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
148 } else if (N.getOpcode() == ARMISD::Wrapper) {
149 Base = N.getOperand(0);
151 Offset = CurDAG->getRegister(0, MVT::i32);
152 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
158 // Match simple R +/- imm12 operands.
159 if (N.getOpcode() == ISD::ADD)
160 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
161 int RHSC = (int)RHS->getZExtValue();
162 if ((RHSC >= 0 && RHSC < 0x1000) ||
163 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
164 Base = N.getOperand(0);
165 if (Base.getOpcode() == ISD::FrameIndex) {
166 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
167 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
169 Offset = CurDAG->getRegister(0, MVT::i32);
171 ARM_AM::AddrOpc AddSub = ARM_AM::add;
173 AddSub = ARM_AM::sub;
176 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
183 // Otherwise this is R +/- [possibly shifted] R
184 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
185 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
188 Base = N.getOperand(0);
189 Offset = N.getOperand(1);
191 if (ShOpcVal != ARM_AM::no_shift) {
192 // Check to see if the RHS of the shift is a constant, if not, we can't fold
194 if (ConstantSDNode *Sh =
195 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
196 ShAmt = Sh->getZExtValue();
197 Offset = N.getOperand(1).getOperand(0);
199 ShOpcVal = ARM_AM::no_shift;
203 // Try matching (R shl C) + (R).
204 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
205 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
206 if (ShOpcVal != ARM_AM::no_shift) {
207 // Check to see if the RHS of the shift is a constant, if not, we can't
209 if (ConstantSDNode *Sh =
210 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
211 ShAmt = Sh->getZExtValue();
212 Offset = N.getOperand(0).getOperand(0);
213 Base = N.getOperand(1);
215 ShOpcVal = ARM_AM::no_shift;
220 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
225 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
226 SDValue &Offset, SDValue &Opc) {
227 unsigned Opcode = Op.getOpcode();
228 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
229 ? cast<LoadSDNode>(Op)->getAddressingMode()
230 : cast<StoreSDNode>(Op)->getAddressingMode();
231 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
232 ? ARM_AM::add : ARM_AM::sub;
233 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
234 int Val = (int)C->getZExtValue();
235 if (Val >= 0 && Val < 0x1000) { // 12 bits.
236 Offset = CurDAG->getRegister(0, MVT::i32);
237 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
245 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
247 if (ShOpcVal != ARM_AM::no_shift) {
248 // Check to see if the RHS of the shift is a constant, if not, we can't fold
250 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
251 ShAmt = Sh->getZExtValue();
252 Offset = N.getOperand(0);
254 ShOpcVal = ARM_AM::no_shift;
258 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
264 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
265 SDValue &Base, SDValue &Offset,
267 if (N.getOpcode() == ISD::SUB) {
268 // X - C is canonicalize to X + -C, no need to handle it here.
269 Base = N.getOperand(0);
270 Offset = N.getOperand(1);
271 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
275 if (N.getOpcode() != ISD::ADD) {
277 if (N.getOpcode() == ISD::FrameIndex) {
278 int FI = cast<FrameIndexSDNode>(N)->getIndex();
279 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
281 Offset = CurDAG->getRegister(0, MVT::i32);
282 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
286 // If the RHS is +/- imm8, fold into addr mode.
287 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
288 int RHSC = (int)RHS->getZExtValue();
289 if ((RHSC >= 0 && RHSC < 256) ||
290 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
291 Base = N.getOperand(0);
292 if (Base.getOpcode() == ISD::FrameIndex) {
293 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
294 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
296 Offset = CurDAG->getRegister(0, MVT::i32);
298 ARM_AM::AddrOpc AddSub = ARM_AM::add;
300 AddSub = ARM_AM::sub;
303 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
308 Base = N.getOperand(0);
309 Offset = N.getOperand(1);
310 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
314 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
315 SDValue &Offset, SDValue &Opc) {
316 unsigned Opcode = Op.getOpcode();
317 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
318 ? cast<LoadSDNode>(Op)->getAddressingMode()
319 : cast<StoreSDNode>(Op)->getAddressingMode();
320 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
321 ? ARM_AM::add : ARM_AM::sub;
322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
323 int Val = (int)C->getZExtValue();
324 if (Val >= 0 && Val < 256) {
325 Offset = CurDAG->getRegister(0, MVT::i32);
326 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
332 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
337 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
338 SDValue &Base, SDValue &Offset) {
339 if (N.getOpcode() != ISD::ADD) {
341 if (N.getOpcode() == ISD::FrameIndex) {
342 int FI = cast<FrameIndexSDNode>(N)->getIndex();
343 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
344 } else if (N.getOpcode() == ARMISD::Wrapper) {
345 Base = N.getOperand(0);
347 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
352 // If the RHS is +/- imm8, fold into addr mode.
353 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
354 int RHSC = (int)RHS->getZExtValue();
355 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
357 if ((RHSC >= 0 && RHSC < 256) ||
358 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
359 Base = N.getOperand(0);
360 if (Base.getOpcode() == ISD::FrameIndex) {
361 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
362 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
365 ARM_AM::AddrOpc AddSub = ARM_AM::add;
367 AddSub = ARM_AM::sub;
370 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
378 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
383 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
384 SDValue &Offset, SDValue &Label) {
385 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
386 Offset = N.getOperand(0);
387 SDValue N1 = N.getOperand(1);
388 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
395 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
396 SDValue &Base, SDValue &Offset){
397 // FIXME dl should come from the parent load or store, not the address
398 DebugLoc dl = Op.getDebugLoc();
399 if (N.getOpcode() != ISD::ADD) {
401 // We must materialize a zero in a reg! Returning a constant here
402 // wouldn't work without additional code to position the node within
403 // ISel's topological ordering in a place where ISel will process it
404 // normally. Instead, just explicitly issue a tMOVri8 node!
405 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32,
406 CurDAG->getTargetConstant(0, MVT::i32)), 0);
410 Base = N.getOperand(0);
411 Offset = N.getOperand(1);
416 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
417 unsigned Scale, SDValue &Base,
418 SDValue &OffImm, SDValue &Offset) {
420 SDValue TmpBase, TmpOffImm;
421 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
422 return false; // We want to select tLDRspi / tSTRspi instead.
423 if (N.getOpcode() == ARMISD::Wrapper &&
424 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
425 return false; // We want to select tLDRpci instead.
428 if (N.getOpcode() != ISD::ADD) {
429 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
430 Offset = CurDAG->getRegister(0, MVT::i32);
431 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
435 // Thumb does not have [sp, r] address mode.
436 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
437 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
438 if ((LHSR && LHSR->getReg() == ARM::SP) ||
439 (RHSR && RHSR->getReg() == ARM::SP)) {
441 Offset = CurDAG->getRegister(0, MVT::i32);
442 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
446 // If the RHS is + imm5 * scale, fold into addr mode.
447 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
448 int RHSC = (int)RHS->getZExtValue();
449 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
451 if (RHSC >= 0 && RHSC < 32) {
452 Base = N.getOperand(0);
453 Offset = CurDAG->getRegister(0, MVT::i32);
454 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
460 Base = N.getOperand(0);
461 Offset = N.getOperand(1);
462 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
466 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
467 SDValue &Base, SDValue &OffImm,
469 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
472 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
473 SDValue &Base, SDValue &OffImm,
475 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
478 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
479 SDValue &Base, SDValue &OffImm,
481 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
484 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
485 SDValue &Base, SDValue &OffImm) {
486 if (N.getOpcode() == ISD::FrameIndex) {
487 int FI = cast<FrameIndexSDNode>(N)->getIndex();
488 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
489 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
493 if (N.getOpcode() != ISD::ADD)
496 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
497 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
498 (LHSR && LHSR->getReg() == ARM::SP)) {
499 // If the RHS is + imm8 * scale, fold into addr mode.
500 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
501 int RHSC = (int)RHS->getZExtValue();
502 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
504 if (RHSC >= 0 && RHSC < 256) {
505 Base = N.getOperand(0);
506 if (Base.getOpcode() == ISD::FrameIndex) {
507 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
508 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
510 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
520 bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op,
524 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
526 // Don't match base register only case. That is matched to a separate
527 // lower complexity pattern with explicit register operand.
528 if (ShOpcVal == ARM_AM::no_shift) return false;
530 BaseReg = N.getOperand(0);
531 unsigned ShImmVal = 0;
532 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)))
533 ShImmVal = RHS->getZExtValue() & 31;
537 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
542 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
547 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
549 // Don't match base register only case. That is matched to a separate
550 // lower complexity pattern with explicit register operand.
551 if (ShOpcVal == ARM_AM::no_shift) return false;
553 BaseReg = N.getOperand(0);
554 unsigned ShImmVal = 0;
555 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
556 ShReg = CurDAG->getRegister(0, MVT::i32);
557 ShImmVal = RHS->getZExtValue() & 31;
559 ShReg = N.getOperand(1);
561 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
566 /// getAL - Returns a ARMCC::AL immediate node.
567 static inline SDValue getAL(SelectionDAG *CurDAG) {
568 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
572 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
573 SDNode *N = Op.getNode();
574 DebugLoc dl = N->getDebugLoc();
576 if (N->isMachineOpcode())
577 return NULL; // Already selected.
579 switch (N->getOpcode()) {
581 case ISD::Constant: {
582 // ARMv6T2 and later should materialize imms via MOV / MOVT pair.
583 if (Subtarget->hasV6T2Ops() || Subtarget->hasThumb2())
586 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
588 if (Subtarget->isThumb())
589 UseCP = (Val > 255 && // MOV
590 ~Val > 255 && // MOV + MVN
591 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
593 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
594 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
595 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
598 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
602 if (Subtarget->isThumb())
603 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
604 CPIdx, CurDAG->getEntryNode());
608 CurDAG->getRegister(0, MVT::i32),
609 CurDAG->getTargetConstant(0, MVT::i32),
611 CurDAG->getRegister(0, MVT::i32),
612 CurDAG->getEntryNode()
614 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
617 ReplaceUses(Op, SDValue(ResNode, 0));
621 // Other cases are autogenerated.
624 case ISD::FrameIndex: {
625 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
626 int FI = cast<FrameIndexSDNode>(N)->getIndex();
627 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
628 if (Subtarget->isThumb()) {
629 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
630 CurDAG->getTargetConstant(0, MVT::i32));
632 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
633 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
634 CurDAG->getRegister(0, MVT::i32) };
635 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
639 if (!Subtarget->isThumb())
641 // Select add sp, c to tADDhirr.
642 SDValue N0 = Op.getOperand(0);
643 SDValue N1 = Op.getOperand(1);
644 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
645 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
646 if (LHSR && LHSR->getReg() == ARM::SP) {
648 std::swap(LHSR, RHSR);
650 if (RHSR && RHSR->getReg() == ARM::SP) {
651 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
652 Op.getValueType(), N0, N0), 0);
653 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
658 if (Subtarget->isThumb())
660 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
661 unsigned RHSV = C->getZExtValue();
663 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
664 SDValue V = Op.getOperand(0);
665 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
666 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
667 CurDAG->getTargetConstant(ShImm, MVT::i32),
668 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
669 CurDAG->getRegister(0, MVT::i32) };
670 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
672 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
673 SDValue V = Op.getOperand(0);
674 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
675 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
676 CurDAG->getTargetConstant(ShImm, MVT::i32),
677 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
678 CurDAG->getRegister(0, MVT::i32) };
679 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
684 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
685 Op.getOperand(0), getAL(CurDAG),
686 CurDAG->getRegister(0, MVT::i32));
687 case ISD::UMUL_LOHI: {
688 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
689 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
690 CurDAG->getRegister(0, MVT::i32) };
691 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
693 case ISD::SMUL_LOHI: {
694 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
695 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
696 CurDAG->getRegister(0, MVT::i32) };
697 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
700 LoadSDNode *LD = cast<LoadSDNode>(Op);
701 ISD::MemIndexedMode AM = LD->getAddressingMode();
702 MVT LoadedVT = LD->getMemoryVT();
703 if (AM != ISD::UNINDEXED) {
704 SDValue Offset, AMOpc;
705 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
708 if (LoadedVT == MVT::i32 &&
709 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
710 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
712 } else if (LoadedVT == MVT::i16 &&
713 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
715 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
716 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
717 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
718 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
719 if (LD->getExtensionType() == ISD::SEXTLOAD) {
720 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
722 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
725 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
727 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
733 SDValue Chain = LD->getChain();
734 SDValue Base = LD->getBasePtr();
735 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
736 CurDAG->getRegister(0, MVT::i32), Chain };
737 return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32,
741 // Other cases are autogenerated.
744 case ARMISD::BRCOND: {
745 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
746 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
747 // Pattern complexity = 6 cost = 1 size = 0
749 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
750 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
751 // Pattern complexity = 6 cost = 1 size = 0
753 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
754 SDValue Chain = Op.getOperand(0);
755 SDValue N1 = Op.getOperand(1);
756 SDValue N2 = Op.getOperand(2);
757 SDValue N3 = Op.getOperand(3);
758 SDValue InFlag = Op.getOperand(4);
759 assert(N1.getOpcode() == ISD::BasicBlock);
760 assert(N2.getOpcode() == ISD::Constant);
761 assert(N3.getOpcode() == ISD::Register);
763 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
764 cast<ConstantSDNode>(N2)->getZExtValue()),
766 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
767 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
769 Chain = SDValue(ResNode, 0);
770 if (Op.getNode()->getNumValues() == 2) {
771 InFlag = SDValue(ResNode, 1);
772 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
774 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
778 bool isThumb = Subtarget->isThumb();
779 MVT VT = Op.getValueType();
780 SDValue N0 = Op.getOperand(0);
781 SDValue N1 = Op.getOperand(1);
782 SDValue N2 = Op.getOperand(2);
783 SDValue N3 = Op.getOperand(3);
784 SDValue InFlag = Op.getOperand(4);
785 assert(N2.getOpcode() == ISD::Constant);
786 assert(N3.getOpcode() == ISD::Register);
788 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
789 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
790 // Pattern complexity = 18 cost = 1 size = 0
794 if (!isThumb && VT == MVT::i32 &&
795 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
796 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
797 cast<ConstantSDNode>(N2)->getZExtValue()),
799 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
800 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
803 // Pattern: (ARMcmov:i32 GPR:i32:$false,
804 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
806 // Emits: (MOVCCi:i32 GPR:i32:$false,
807 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
808 // Pattern complexity = 10 cost = 1 size = 0
809 if (VT == MVT::i32 &&
810 N3.getOpcode() == ISD::Constant &&
811 Predicate_so_imm(N3.getNode())) {
812 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
813 cast<ConstantSDNode>(N1)->getZExtValue()),
815 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
816 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
817 cast<ConstantSDNode>(N2)->getZExtValue()),
819 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
820 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
823 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
824 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
825 // Pattern complexity = 6 cost = 1 size = 0
827 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
828 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
829 // Pattern complexity = 6 cost = 11 size = 0
831 // Also FCPYScc and FCPYDcc.
832 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
833 cast<ConstantSDNode>(N2)->getZExtValue()),
835 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
837 switch (VT.getSimpleVT()) {
838 default: assert(false && "Illegal conditional move type!");
841 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
850 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
853 MVT VT = Op.getValueType();
854 SDValue N0 = Op.getOperand(0);
855 SDValue N1 = Op.getOperand(1);
856 SDValue N2 = Op.getOperand(2);
857 SDValue N3 = Op.getOperand(3);
858 SDValue InFlag = Op.getOperand(4);
859 assert(N2.getOpcode() == ISD::Constant);
860 assert(N3.getOpcode() == ISD::Register);
862 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
863 cast<ConstantSDNode>(N2)->getZExtValue()),
865 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
867 switch (VT.getSimpleVT()) {
868 default: assert(false && "Illegal conditional move type!");
877 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
881 SDValue Chain = Op.getOperand(0);
882 SDValue N1 = Op.getOperand(1);
883 SDValue N2 = Op.getOperand(2);
884 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
885 // FIXME: handle VLAs.
887 ReplaceUses(Op.getValue(0), Chain);
890 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
891 N2 = N2.getOperand(0);
892 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
894 ReplaceUses(Op.getValue(0), Chain);
897 SDValue BasePtr = Ld->getBasePtr();
898 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
899 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
900 "llvm.dbg.variable should be a constantpool node");
901 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
903 if (CP->isMachineConstantPoolEntry()) {
904 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
907 GV = dyn_cast<GlobalValue>(CP->getConstVal());
909 ReplaceUses(Op.getValue(0), Chain);
913 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
915 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
916 SDValue Ops[] = { Tmp1, Tmp2, Chain };
917 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
922 return SelectCode(Op);
925 bool ARMDAGToDAGISel::
926 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
927 std::vector<SDValue> &OutOps) {
928 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
930 SDValue Base, Offset, Opc;
931 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
934 OutOps.push_back(Base);
935 OutOps.push_back(Offset);
936 OutOps.push_back(Opc);
940 /// createARMISelDag - This pass converts a legalized DAG into a
941 /// ARM-specific DAG, ready for instruction scheduling.
943 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
944 return new ARMDAGToDAGISel(TM);