1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
35 //===--------------------------------------------------------------------===//
36 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
37 /// instructions for SelectionDAG operations.
40 class ARMDAGToDAGISel : public SelectionDAGISel {
43 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
44 /// make the right decision when generating code for different targets.
45 const ARMSubtarget *Subtarget;
48 explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
49 : SelectionDAGISel(tm), TM(tm),
50 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
53 virtual const char *getPassName() const {
54 return "ARM Instruction Selection";
57 SDNode *Select(SDValue Op);
58 virtual void InstructionSelect();
59 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
60 SDValue &Offset, SDValue &Opc);
61 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
62 SDValue &Offset, SDValue &Opc);
63 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
64 SDValue &Offset, SDValue &Opc);
65 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
66 SDValue &Offset, SDValue &Opc);
67 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
70 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
73 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
75 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
76 SDValue &Base, SDValue &OffImm,
78 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
79 SDValue &OffImm, SDValue &Offset);
80 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
81 SDValue &OffImm, SDValue &Offset);
82 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
83 SDValue &OffImm, SDValue &Offset);
84 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
87 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
88 SDValue &B, SDValue &C);
90 // Include the pieces autogenerated from the target description.
91 #include "ARMGenDAGISel.inc"
95 void ARMDAGToDAGISel::InstructionSelect() {
99 CurDAG->RemoveDeadNodes();
102 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
103 SDValue &Base, SDValue &Offset,
105 if (N.getOpcode() == ISD::MUL) {
106 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
107 // X * [3,5,9] -> X + X * [2,4,8] etc.
108 int RHSC = (int)RHS->getZExtValue();
111 ARM_AM::AddrOpc AddSub = ARM_AM::add;
113 AddSub = ARM_AM::sub;
116 if (isPowerOf2_32(RHSC)) {
117 unsigned ShAmt = Log2_32(RHSC);
118 Base = Offset = N.getOperand(0);
119 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
128 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
130 if (N.getOpcode() == ISD::FrameIndex) {
131 int FI = cast<FrameIndexSDNode>(N)->getIndex();
132 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
133 } else if (N.getOpcode() == ARMISD::Wrapper) {
134 Base = N.getOperand(0);
136 Offset = CurDAG->getRegister(0, MVT::i32);
137 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
143 // Match simple R +/- imm12 operands.
144 if (N.getOpcode() == ISD::ADD)
145 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
146 int RHSC = (int)RHS->getZExtValue();
147 if ((RHSC >= 0 && RHSC < 0x1000) ||
148 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
149 Base = N.getOperand(0);
150 if (Base.getOpcode() == ISD::FrameIndex) {
151 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
152 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
154 Offset = CurDAG->getRegister(0, MVT::i32);
156 ARM_AM::AddrOpc AddSub = ARM_AM::add;
158 AddSub = ARM_AM::sub;
161 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
168 // Otherwise this is R +/- [possibly shifted] R
169 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
170 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
173 Base = N.getOperand(0);
174 Offset = N.getOperand(1);
176 if (ShOpcVal != ARM_AM::no_shift) {
177 // Check to see if the RHS of the shift is a constant, if not, we can't fold
179 if (ConstantSDNode *Sh =
180 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
181 ShAmt = Sh->getZExtValue();
182 Offset = N.getOperand(1).getOperand(0);
184 ShOpcVal = ARM_AM::no_shift;
188 // Try matching (R shl C) + (R).
189 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
190 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
191 if (ShOpcVal != ARM_AM::no_shift) {
192 // Check to see if the RHS of the shift is a constant, if not, we can't
194 if (ConstantSDNode *Sh =
195 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
196 ShAmt = Sh->getZExtValue();
197 Offset = N.getOperand(0).getOperand(0);
198 Base = N.getOperand(1);
200 ShOpcVal = ARM_AM::no_shift;
205 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
210 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
211 SDValue &Offset, SDValue &Opc) {
212 unsigned Opcode = Op.getOpcode();
213 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
214 ? cast<LoadSDNode>(Op)->getAddressingMode()
215 : cast<StoreSDNode>(Op)->getAddressingMode();
216 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
217 ? ARM_AM::add : ARM_AM::sub;
218 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
219 int Val = (int)C->getZExtValue();
220 if (Val >= 0 && Val < 0x1000) { // 12 bits.
221 Offset = CurDAG->getRegister(0, MVT::i32);
222 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
230 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
232 if (ShOpcVal != ARM_AM::no_shift) {
233 // Check to see if the RHS of the shift is a constant, if not, we can't fold
235 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
236 ShAmt = Sh->getZExtValue();
237 Offset = N.getOperand(0);
239 ShOpcVal = ARM_AM::no_shift;
243 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
249 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
250 SDValue &Base, SDValue &Offset,
252 if (N.getOpcode() == ISD::SUB) {
253 // X - C is canonicalize to X + -C, no need to handle it here.
254 Base = N.getOperand(0);
255 Offset = N.getOperand(1);
256 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
260 if (N.getOpcode() != ISD::ADD) {
262 if (N.getOpcode() == ISD::FrameIndex) {
263 int FI = cast<FrameIndexSDNode>(N)->getIndex();
264 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
266 Offset = CurDAG->getRegister(0, MVT::i32);
267 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
271 // If the RHS is +/- imm8, fold into addr mode.
272 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
273 int RHSC = (int)RHS->getZExtValue();
274 if ((RHSC >= 0 && RHSC < 256) ||
275 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
276 Base = N.getOperand(0);
277 if (Base.getOpcode() == ISD::FrameIndex) {
278 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
279 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
281 Offset = CurDAG->getRegister(0, MVT::i32);
283 ARM_AM::AddrOpc AddSub = ARM_AM::add;
285 AddSub = ARM_AM::sub;
288 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
293 Base = N.getOperand(0);
294 Offset = N.getOperand(1);
295 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
299 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
300 SDValue &Offset, SDValue &Opc) {
301 unsigned Opcode = Op.getOpcode();
302 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
303 ? cast<LoadSDNode>(Op)->getAddressingMode()
304 : cast<StoreSDNode>(Op)->getAddressingMode();
305 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
306 ? ARM_AM::add : ARM_AM::sub;
307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
308 int Val = (int)C->getZExtValue();
309 if (Val >= 0 && Val < 256) {
310 Offset = CurDAG->getRegister(0, MVT::i32);
311 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
317 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
322 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
323 SDValue &Base, SDValue &Offset) {
324 if (N.getOpcode() != ISD::ADD) {
326 if (N.getOpcode() == ISD::FrameIndex) {
327 int FI = cast<FrameIndexSDNode>(N)->getIndex();
328 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
329 } else if (N.getOpcode() == ARMISD::Wrapper) {
330 Base = N.getOperand(0);
332 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
337 // If the RHS is +/- imm8, fold into addr mode.
338 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
339 int RHSC = (int)RHS->getZExtValue();
340 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
342 if ((RHSC >= 0 && RHSC < 256) ||
343 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
344 Base = N.getOperand(0);
345 if (Base.getOpcode() == ISD::FrameIndex) {
346 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
347 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
350 ARM_AM::AddrOpc AddSub = ARM_AM::add;
352 AddSub = ARM_AM::sub;
355 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
363 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
368 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
369 SDValue &Offset, SDValue &Label) {
370 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
371 Offset = N.getOperand(0);
372 SDValue N1 = N.getOperand(1);
373 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
380 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
381 SDValue &Base, SDValue &Offset){
382 if (N.getOpcode() != ISD::ADD) {
384 // We must materialize a zero in a reg! Returning a constant here
385 // wouldn't work without additional code to position the node within
386 // ISel's topological ordering in a place where ISel will process it
387 // normally. Instead, just explicitly issue a tMOVri8 node!
388 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
389 CurDAG->getTargetConstant(0, MVT::i32)), 0);
393 Base = N.getOperand(0);
394 Offset = N.getOperand(1);
399 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
400 unsigned Scale, SDValue &Base,
401 SDValue &OffImm, SDValue &Offset) {
403 SDValue TmpBase, TmpOffImm;
404 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
405 return false; // We want to select tLDRspi / tSTRspi instead.
406 if (N.getOpcode() == ARMISD::Wrapper &&
407 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
408 return false; // We want to select tLDRpci instead.
411 if (N.getOpcode() != ISD::ADD) {
412 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
413 Offset = CurDAG->getRegister(0, MVT::i32);
414 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
418 // Thumb does not have [sp, r] address mode.
419 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
420 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
421 if ((LHSR && LHSR->getReg() == ARM::SP) ||
422 (RHSR && RHSR->getReg() == ARM::SP)) {
424 Offset = CurDAG->getRegister(0, MVT::i32);
425 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
429 // If the RHS is + imm5 * scale, fold into addr mode.
430 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
431 int RHSC = (int)RHS->getZExtValue();
432 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
434 if (RHSC >= 0 && RHSC < 32) {
435 Base = N.getOperand(0);
436 Offset = CurDAG->getRegister(0, MVT::i32);
437 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
443 Base = N.getOperand(0);
444 Offset = N.getOperand(1);
445 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
449 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
450 SDValue &Base, SDValue &OffImm,
452 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
455 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
456 SDValue &Base, SDValue &OffImm,
458 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
461 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
462 SDValue &Base, SDValue &OffImm,
464 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
467 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
468 SDValue &Base, SDValue &OffImm) {
469 if (N.getOpcode() == ISD::FrameIndex) {
470 int FI = cast<FrameIndexSDNode>(N)->getIndex();
471 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
472 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
476 if (N.getOpcode() != ISD::ADD)
479 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
480 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
481 (LHSR && LHSR->getReg() == ARM::SP)) {
482 // If the RHS is + imm8 * scale, fold into addr mode.
483 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
484 int RHSC = (int)RHS->getZExtValue();
485 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
487 if (RHSC >= 0 && RHSC < 256) {
488 Base = N.getOperand(0);
489 if (Base.getOpcode() == ISD::FrameIndex) {
490 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
491 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
493 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
503 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
508 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
510 // Don't match base register only case. That is matched to a separate
511 // lower complexity pattern with explicit register operand.
512 if (ShOpcVal == ARM_AM::no_shift) return false;
514 BaseReg = N.getOperand(0);
515 unsigned ShImmVal = 0;
516 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
517 ShReg = CurDAG->getRegister(0, MVT::i32);
518 ShImmVal = RHS->getZExtValue() & 31;
520 ShReg = N.getOperand(1);
522 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
527 /// getAL - Returns a ARMCC::AL immediate node.
528 static inline SDValue getAL(SelectionDAG *CurDAG) {
529 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
533 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
534 SDNode *N = Op.getNode();
536 if (N->isMachineOpcode())
537 return NULL; // Already selected.
539 switch (N->getOpcode()) {
541 case ISD::Constant: {
542 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
544 if (Subtarget->isThumb())
545 UseCP = (Val > 255 && // MOV
546 ~Val > 255 && // MOV + MVN
547 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
549 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
550 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
551 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
554 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
558 if (Subtarget->isThumb())
559 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
560 CPIdx, CurDAG->getEntryNode());
564 CurDAG->getRegister(0, MVT::i32),
565 CurDAG->getTargetConstant(0, MVT::i32),
567 CurDAG->getRegister(0, MVT::i32),
568 CurDAG->getEntryNode()
570 ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
572 ReplaceUses(Op, SDValue(ResNode, 0));
576 // Other cases are autogenerated.
579 case ISD::FrameIndex: {
580 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
581 int FI = cast<FrameIndexSDNode>(N)->getIndex();
582 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
583 if (Subtarget->isThumb())
584 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
585 CurDAG->getTargetConstant(0, MVT::i32));
587 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
588 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
589 CurDAG->getRegister(0, MVT::i32) };
590 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
594 // Select add sp, c to tADDhirr.
595 SDValue N0 = Op.getOperand(0);
596 SDValue N1 = Op.getOperand(1);
597 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
598 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
599 if (LHSR && LHSR->getReg() == ARM::SP) {
601 std::swap(LHSR, RHSR);
603 if (RHSR && RHSR->getReg() == ARM::SP) {
604 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
609 if (Subtarget->isThumb())
611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
612 unsigned RHSV = C->getZExtValue();
614 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
615 SDValue V = Op.getOperand(0);
616 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
617 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
618 CurDAG->getTargetConstant(ShImm, MVT::i32),
619 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
620 CurDAG->getRegister(0, MVT::i32) };
621 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
623 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
624 SDValue V = Op.getOperand(0);
625 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
626 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
627 CurDAG->getTargetConstant(ShImm, MVT::i32),
628 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
629 CurDAG->getRegister(0, MVT::i32) };
630 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
635 return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
636 Op.getOperand(0), getAL(CurDAG),
637 CurDAG->getRegister(0, MVT::i32));
638 case ISD::UMUL_LOHI: {
639 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
640 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
641 CurDAG->getRegister(0, MVT::i32) };
642 return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
644 case ISD::SMUL_LOHI: {
645 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
646 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
647 CurDAG->getRegister(0, MVT::i32) };
648 return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
651 LoadSDNode *LD = cast<LoadSDNode>(Op);
652 ISD::MemIndexedMode AM = LD->getAddressingMode();
653 MVT LoadedVT = LD->getMemoryVT();
654 if (AM != ISD::UNINDEXED) {
655 SDValue Offset, AMOpc;
656 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
659 if (LoadedVT == MVT::i32 &&
660 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
661 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
663 } else if (LoadedVT == MVT::i16 &&
664 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
666 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
667 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
668 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
669 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
670 if (LD->getExtensionType() == ISD::SEXTLOAD) {
671 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
673 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
676 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
678 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
684 SDValue Chain = LD->getChain();
685 SDValue Base = LD->getBasePtr();
686 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
687 CurDAG->getRegister(0, MVT::i32), Chain };
688 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
692 // Other cases are autogenerated.
695 case ARMISD::BRCOND: {
696 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
697 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
698 // Pattern complexity = 6 cost = 1 size = 0
700 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
701 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
702 // Pattern complexity = 6 cost = 1 size = 0
704 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
705 SDValue Chain = Op.getOperand(0);
706 SDValue N1 = Op.getOperand(1);
707 SDValue N2 = Op.getOperand(2);
708 SDValue N3 = Op.getOperand(3);
709 SDValue InFlag = Op.getOperand(4);
710 assert(N1.getOpcode() == ISD::BasicBlock);
711 assert(N2.getOpcode() == ISD::Constant);
712 assert(N3.getOpcode() == ISD::Register);
714 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
715 cast<ConstantSDNode>(N2)->getZExtValue()),
717 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
718 SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
719 Chain = SDValue(ResNode, 0);
720 if (Op.getNode()->getNumValues() == 2) {
721 InFlag = SDValue(ResNode, 1);
722 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
724 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
728 bool isThumb = Subtarget->isThumb();
729 MVT VT = Op.getValueType();
730 SDValue N0 = Op.getOperand(0);
731 SDValue N1 = Op.getOperand(1);
732 SDValue N2 = Op.getOperand(2);
733 SDValue N3 = Op.getOperand(3);
734 SDValue InFlag = Op.getOperand(4);
735 assert(N2.getOpcode() == ISD::Constant);
736 assert(N3.getOpcode() == ISD::Register);
738 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
739 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
740 // Pattern complexity = 18 cost = 1 size = 0
744 if (!isThumb && VT == MVT::i32 &&
745 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
746 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
747 cast<ConstantSDNode>(N2)->getZExtValue()),
749 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
750 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
753 // Pattern: (ARMcmov:i32 GPR:i32:$false,
754 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
756 // Emits: (MOVCCi:i32 GPR:i32:$false,
757 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
758 // Pattern complexity = 10 cost = 1 size = 0
759 if (VT == MVT::i32 &&
760 N3.getOpcode() == ISD::Constant &&
761 Predicate_so_imm(N3.getNode())) {
762 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
763 cast<ConstantSDNode>(N1)->getZExtValue()),
765 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
766 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
767 cast<ConstantSDNode>(N2)->getZExtValue()),
769 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
770 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
773 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
774 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
775 // Pattern complexity = 6 cost = 1 size = 0
777 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
778 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
779 // Pattern complexity = 6 cost = 11 size = 0
781 // Also FCPYScc and FCPYDcc.
782 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
783 cast<ConstantSDNode>(N2)->getZExtValue()),
785 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
787 switch (VT.getSimpleVT()) {
788 default: assert(false && "Illegal conditional move type!");
791 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
800 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
803 MVT VT = Op.getValueType();
804 SDValue N0 = Op.getOperand(0);
805 SDValue N1 = Op.getOperand(1);
806 SDValue N2 = Op.getOperand(2);
807 SDValue N3 = Op.getOperand(3);
808 SDValue InFlag = Op.getOperand(4);
809 assert(N2.getOpcode() == ISD::Constant);
810 assert(N3.getOpcode() == ISD::Register);
812 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
813 cast<ConstantSDNode>(N2)->getZExtValue()),
815 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
817 switch (VT.getSimpleVT()) {
818 default: assert(false && "Illegal conditional move type!");
827 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
831 SDValue Chain = Op.getOperand(0);
832 SDValue N1 = Op.getOperand(1);
833 SDValue N2 = Op.getOperand(2);
834 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
837 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
838 N2 = N2.getOperand(0);
839 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
842 SDValue BasePtr = Ld->getBasePtr();
843 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
844 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
845 "llvm.dbg.variable should be a constantpool node");
846 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
848 if (CP->isMachineConstantPoolEntry()) {
849 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
852 GV = dyn_cast<GlobalValue>(CP->getConstVal());
854 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
856 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
857 SDValue Ops[] = { Tmp1, Tmp2, Chain };
858 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
865 return SelectCode(Op);
868 /// createARMISelDag - This pass converts a legalized DAG into a
869 /// ARM-specific DAG, ready for instruction scheduling.
871 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
872 return new ARMDAGToDAGISel(TM);