1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
33 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
39 class ARMTargetLowering : public TargetLowering {
41 ARMTargetLowering(TargetMachine &TM);
42 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
44 virtual std::pair<SDOperand, SDOperand>
45 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
47 bool isTailCall, SDOperand Callee, ArgListTy &Args,
54 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
55 : TargetLowering(TM) {
56 setOperationAction(ISD::RET, MVT::Other, Custom);
59 std::pair<SDOperand, SDOperand>
60 ARMTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
61 bool isVarArg, unsigned CC,
62 bool isTailCall, SDOperand Callee,
63 ArgListTy &Args, SelectionDAG &DAG) {
64 assert(0 && "Not implemented");
67 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
69 switch(Op.getNumOperands()) {
71 assert(0 && "Do not know how to return this many arguments!");
74 return SDOperand(); // ret void is legal
76 Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
80 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
83 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
84 switch (Op.getOpcode()) {
86 assert(0 && "Should not custom lower this!");
88 return LowerRET(Op, DAG);
92 //===----------------------------------------------------------------------===//
93 // Instruction Selector Implementation
94 //===----------------------------------------------------------------------===//
96 //===--------------------------------------------------------------------===//
97 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
98 /// instructions for SelectionDAG operations.
101 class ARMDAGToDAGISel : public SelectionDAGISel {
102 ARMTargetLowering Lowering;
105 ARMDAGToDAGISel(TargetMachine &TM)
106 : SelectionDAGISel(Lowering), Lowering(TM) {
109 void Select(SDOperand &Result, SDOperand Op);
110 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
112 // Include the pieces autogenerated from the target description.
113 #include "ARMGenDAGISel.inc"
116 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
119 DAG.setRoot(SelectRoot(DAG.getRoot()));
121 DAG.RemoveDeadNodes();
123 ScheduleAndEmitDAG(DAG);
126 void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
127 SelectCode(Result, Op);
130 } // end anonymous namespace
132 /// createARMISelDag - This pass converts a legalized DAG into a
133 /// ARM-specific DAG, ready for instruction scheduling.
135 FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
136 return new ARMDAGToDAGISel(TM);