1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Support/Debug.h"
34 //===--------------------------------------------------------------------===//
35 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
36 /// instructions for SelectionDAG operations.
39 class ARMDAGToDAGISel : public SelectionDAGISel {
40 ARMTargetLowering Lowering;
42 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
43 /// make the right decision when generating code for different targets.
44 const ARMSubtarget *Subtarget;
47 ARMDAGToDAGISel(ARMTargetMachine &TM)
48 : SelectionDAGISel(Lowering), Lowering(TM),
49 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
52 virtual const char *getPassName() const {
53 return "ARM Instruction Selection";
56 SDNode *Select(SDOperand Op);
57 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
58 bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
59 SDOperand &Offset, SDOperand &Opc);
60 bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
61 SDOperand &Offset, SDOperand &Opc);
62 bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base,
63 SDOperand &Offset, SDOperand &Opc);
64 bool SelectAddrMode3Offset(SDOperand Op, SDOperand N,
65 SDOperand &Offset, SDOperand &Opc);
66 bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base,
69 bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset,
72 bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
74 bool SelectThumbAddrModeRI5_1(SDOperand Op, SDOperand N, SDOperand &Base,
76 bool SelectThumbAddrModeRI5_2(SDOperand Op, SDOperand N, SDOperand &Base,
78 bool SelectThumbAddrModeRI5_4(SDOperand Op, SDOperand N, SDOperand &Base,
80 bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
83 bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A,
84 SDOperand &B, SDOperand &C);
86 // Include the pieces autogenerated from the target description.
87 #include "ARMGenDAGISel.inc"
91 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
94 DAG.setRoot(SelectRoot(DAG.getRoot()));
95 DAG.RemoveDeadNodes();
97 ScheduleAndEmitDAG(DAG);
100 bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
101 SDOperand &Base, SDOperand &Offset,
103 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
105 if (N.getOpcode() == ISD::FrameIndex) {
106 int FI = cast<FrameIndexSDNode>(N)->getIndex();
107 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
108 } else if (N.getOpcode() == ARMISD::Wrapper) {
109 Base = N.getOperand(0);
111 Offset = CurDAG->getRegister(0, MVT::i32);
112 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
118 // Match simple R +/- imm12 operands.
119 if (N.getOpcode() == ISD::ADD)
120 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
121 int RHSC = (int)RHS->getValue();
122 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
123 Base = N.getOperand(0);
124 Offset = CurDAG->getRegister(0, MVT::i32);
125 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, RHSC,
129 } else if (RHSC < 0 && RHSC > -0x1000) {
130 Base = N.getOperand(0);
131 Offset = CurDAG->getRegister(0, MVT::i32);
132 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::sub, -RHSC,
139 // Otherwise this is R +/- [possibly shifted] R
140 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
141 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
144 Base = N.getOperand(0);
145 Offset = N.getOperand(1);
147 if (ShOpcVal != ARM_AM::no_shift) {
148 // Check to see if the RHS of the shift is a constant, if not, we can't fold
150 if (ConstantSDNode *Sh =
151 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
152 ShAmt = Sh->getValue();
153 Offset = N.getOperand(1).getOperand(0);
155 ShOpcVal = ARM_AM::no_shift;
159 // Try matching (R shl C) + (R).
160 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
161 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
162 if (ShOpcVal != ARM_AM::no_shift) {
163 // Check to see if the RHS of the shift is a constant, if not, we can't
165 if (ConstantSDNode *Sh =
166 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
167 ShAmt = Sh->getValue();
168 Offset = N.getOperand(0).getOperand(0);
169 Base = N.getOperand(1);
171 ShOpcVal = ARM_AM::no_shift;
176 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
181 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
182 SDOperand &Offset, SDOperand &Opc) {
183 unsigned Opcode = Op.getOpcode();
184 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
185 ? cast<LoadSDNode>(Op)->getAddressingMode()
186 : cast<StoreSDNode>(Op)->getAddressingMode();
187 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
188 ? ARM_AM::add : ARM_AM::sub;
189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
190 int Val = (int)C->getValue();
191 if (Val >= 0 && Val < 0x1000) { // 12 bits.
192 Offset = CurDAG->getRegister(0, MVT::i32);
193 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
201 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
203 if (ShOpcVal != ARM_AM::no_shift) {
204 // Check to see if the RHS of the shift is a constant, if not, we can't fold
206 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
207 ShAmt = Sh->getValue();
208 Offset = N.getOperand(0);
210 ShOpcVal = ARM_AM::no_shift;
214 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
220 bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
221 SDOperand &Base, SDOperand &Offset,
223 if (N.getOpcode() == ISD::SUB) {
224 // X - C is canonicalize to X + -C, no need to handle it here.
225 Base = N.getOperand(0);
226 Offset = N.getOperand(1);
227 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
231 if (N.getOpcode() != ISD::ADD) {
233 if (N.getOpcode() == ISD::FrameIndex) {
234 int FI = cast<FrameIndexSDNode>(N)->getIndex();
235 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
237 Offset = CurDAG->getRegister(0, MVT::i32);
238 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
242 // If the RHS is +/- imm8, fold into addr mode.
243 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
244 int RHSC = (int)RHS->getValue();
245 if (RHSC >= 0 && RHSC < 256) {
246 Base = N.getOperand(0);
247 Offset = CurDAG->getRegister(0, MVT::i32);
248 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, RHSC),
251 } else if (RHSC < 0 && RHSC > -256) { // note -256 itself isn't allowed.
252 Base = N.getOperand(0);
253 Offset = CurDAG->getRegister(0, MVT::i32);
254 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, -RHSC),
260 Base = N.getOperand(0);
261 Offset = N.getOperand(1);
262 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
266 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
267 SDOperand &Offset, SDOperand &Opc) {
268 unsigned Opcode = Op.getOpcode();
269 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
270 ? cast<LoadSDNode>(Op)->getAddressingMode()
271 : cast<StoreSDNode>(Op)->getAddressingMode();
272 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
273 ? ARM_AM::add : ARM_AM::sub;
274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
275 int Val = (int)C->getValue();
276 if (Val >= 0 && Val < 256) {
277 Offset = CurDAG->getRegister(0, MVT::i32);
278 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
284 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
289 bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
290 SDOperand &Base, SDOperand &Offset) {
291 if (N.getOpcode() != ISD::ADD) {
293 if (N.getOpcode() == ISD::FrameIndex) {
294 int FI = cast<FrameIndexSDNode>(N)->getIndex();
295 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
296 } else if (N.getOpcode() == ARMISD::Wrapper) {
297 Base = N.getOperand(0);
299 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
304 // If the RHS is +/- imm8, fold into addr mode.
305 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
306 int RHSC = (int)RHS->getValue();
307 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
309 if (RHSC >= 0 && RHSC < 256) {
310 Base = N.getOperand(0);
311 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, RHSC),
314 } else if (RHSC < 0 && RHSC > -256) { // note -256 itself isn't allowed.
315 Base = N.getOperand(0);
316 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::sub,-RHSC),
324 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
329 bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
330 SDOperand &Offset, SDOperand &Label) {
331 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
332 Offset = N.getOperand(0);
333 SDOperand N1 = N.getOperand(1);
334 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
341 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
342 SDOperand &Base, SDOperand &Offset){
343 if (N.getOpcode() != ISD::ADD)
345 Base = N.getOperand(0);
346 Offset = N.getOperand(1);
350 static bool SelectThumbAddrModeRI5(SDOperand N, unsigned Scale,
351 TargetLowering &TLI, SelectionDAG *CurDAG,
352 SDOperand &Base, SDOperand &Offset) {
353 if (N.getOpcode() == ISD::FrameIndex)
356 if (N.getOpcode() != ISD::ADD) {
357 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
358 Offset = CurDAG->getTargetConstant(0, MVT::i32);
362 // If the RHS is + imm5 * scale, fold into addr mode.
363 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
364 int RHSC = (int)RHS->getValue();
365 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
367 if (RHSC >= 0 && RHSC < 32) {
368 Base = N.getOperand(0);
369 Offset = CurDAG->getTargetConstant(RHSC, MVT::i32);
378 bool ARMDAGToDAGISel::SelectThumbAddrModeRI5_1(SDOperand Op, SDOperand N,
379 SDOperand &Base, SDOperand &Offset){
380 return SelectThumbAddrModeRI5(N, 1, TLI, CurDAG, Base, Offset);
383 bool ARMDAGToDAGISel::SelectThumbAddrModeRI5_2(SDOperand Op, SDOperand N,
384 SDOperand &Base, SDOperand &Offset){
385 return SelectThumbAddrModeRI5(N, 2, TLI, CurDAG, Base, Offset);
388 bool ARMDAGToDAGISel::SelectThumbAddrModeRI5_4(SDOperand Op, SDOperand N,
389 SDOperand &Base, SDOperand &Offset){
390 return SelectThumbAddrModeRI5(N, 4, TLI, CurDAG, Base, Offset);
393 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
394 SDOperand &Base, SDOperand &Offset) {
395 if (N.getOpcode() == ISD::FrameIndex) {
396 int FI = cast<FrameIndexSDNode>(N)->getIndex();
397 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
398 Offset = CurDAG->getTargetConstant(0, MVT::i32);
405 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
410 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
412 // Don't match base register only case. That is matched to a separate
413 // lower complexity pattern with explicit register operand.
414 if (ShOpcVal == ARM_AM::no_shift) return false;
416 BaseReg = N.getOperand(0);
417 unsigned ShImmVal = 0;
418 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
419 ShReg = CurDAG->getRegister(0, MVT::i32);
420 ShImmVal = RHS->getValue() & 31;
422 ShReg = N.getOperand(1);
424 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
430 SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
432 unsigned Opcode = N->getOpcode();
434 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < ARMISD::FIRST_NUMBER)
435 return NULL; // Already selected.
437 switch (N->getOpcode()) {
439 case ISD::Constant: {
440 unsigned Val = cast<ConstantSDNode>(N)->getValue();
442 if (Subtarget->isThumb())
443 UseCP = (Val > 255 && // MOV
444 ~Val > 255 && // MOV + MVN
445 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
447 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
448 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
449 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
452 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
456 CurDAG->getRegister(0, MVT::i32),
457 CurDAG->getTargetConstant(0, MVT::i32),
458 CurDAG->getEntryNode()
461 CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
462 ReplaceUses(Op, SDOperand(ResNode, 0));
466 // Other cases are autogenerated.
469 case ISD::FrameIndex: {
470 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
471 int FI = cast<FrameIndexSDNode>(N)->getIndex();
472 unsigned Opc = Subtarget->isThumb() ? ARM::tADDrSPi : ARM::ADDri;
473 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
474 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, TFI,
475 CurDAG->getTargetConstant(0, MVT::i32));
478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
479 unsigned RHSV = C->getValue();
481 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
482 SDOperand V = Op.getOperand(0);
484 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
485 SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
486 CurDAG->getTargetConstant(ShImm, MVT::i32)
488 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 4);
490 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
491 SDOperand V = Op.getOperand(0);
493 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
494 SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
495 CurDAG->getTargetConstant(ShImm, MVT::i32)
497 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 4);
502 AddToISelQueue(Op.getOperand(0));
503 return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
505 case ARMISD::MULHILOU:
506 AddToISelQueue(Op.getOperand(0));
507 AddToISelQueue(Op.getOperand(1));
508 return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32,
509 Op.getOperand(0), Op.getOperand(1));
510 case ARMISD::MULHILOS:
511 AddToISelQueue(Op.getOperand(0));
512 AddToISelQueue(Op.getOperand(1));
513 return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32,
514 Op.getOperand(0), Op.getOperand(1));
516 LoadSDNode *LD = cast<LoadSDNode>(Op);
517 ISD::MemIndexedMode AM = LD->getAddressingMode();
518 MVT::ValueType LoadedVT = LD->getLoadedVT();
519 if (AM != ISD::UNINDEXED) {
520 SDOperand Offset, AMOpc;
521 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
524 if (LoadedVT == MVT::i32 &&
525 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
526 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
528 } else if (LoadedVT == MVT::i16 &&
529 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
531 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
532 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
533 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
534 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
535 if (LD->getExtensionType() == ISD::SEXTLOAD) {
536 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
538 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
541 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
543 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
549 SDOperand Chain = LD->getChain();
550 SDOperand Base = LD->getBasePtr();
551 AddToISelQueue(Chain);
552 AddToISelQueue(Base);
553 AddToISelQueue(Offset);
554 SDOperand Ops[] = { Base, Offset, AMOpc, Chain };
555 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
559 // Other cases are autogenerated.
564 return SelectCode(Op);
567 /// createARMISelDag - This pass converts a legalized DAG into a
568 /// ARM-specific DAG, ready for instruction scheduling.
570 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
571 return new ARMDAGToDAGISel(TM);