1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
35 static const unsigned arm_dsubreg_0 = 5;
36 static const unsigned arm_dsubreg_1 = 6;
38 //===--------------------------------------------------------------------===//
39 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
40 /// instructions for SelectionDAG operations.
43 class ARMDAGToDAGISel : public SelectionDAGISel {
46 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47 /// make the right decision when generating code for different targets.
48 const ARMSubtarget *Subtarget;
51 explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
52 : SelectionDAGISel(tm), TM(tm),
53 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
56 virtual const char *getPassName() const {
57 return "ARM Instruction Selection";
60 /// getI32Imm - Return a target constant with the specified value, of type i32.
61 inline SDValue getI32Imm(unsigned Imm) {
62 return CurDAG->getTargetConstant(Imm, MVT::i32);
65 SDNode *Select(SDValue Op);
66 virtual void InstructionSelect();
67 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
68 SDValue &Offset, SDValue &Opc);
69 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
70 SDValue &Offset, SDValue &Opc);
71 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
78 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
81 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
84 SDValue &Base, SDValue &OffImm,
86 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
87 SDValue &OffImm, SDValue &Offset);
88 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
89 SDValue &OffImm, SDValue &Offset);
90 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
91 SDValue &OffImm, SDValue &Offset);
92 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
95 bool SelectShifterOperand(SDValue Op, SDValue N,
96 SDValue &BaseReg, SDValue &Opc);
98 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
99 SDValue &B, SDValue &C);
101 // Include the pieces autogenerated from the target description.
102 #include "ARMGenDAGISel.inc"
105 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
106 /// inline asm expressions.
107 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
109 std::vector<SDValue> &OutOps);
113 void ARMDAGToDAGISel::InstructionSelect() {
117 CurDAG->RemoveDeadNodes();
120 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
121 SDValue &Base, SDValue &Offset,
123 if (N.getOpcode() == ISD::MUL) {
124 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
125 // X * [3,5,9] -> X + X * [2,4,8] etc.
126 int RHSC = (int)RHS->getZExtValue();
129 ARM_AM::AddrOpc AddSub = ARM_AM::add;
131 AddSub = ARM_AM::sub;
134 if (isPowerOf2_32(RHSC)) {
135 unsigned ShAmt = Log2_32(RHSC);
136 Base = Offset = N.getOperand(0);
137 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
146 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
148 if (N.getOpcode() == ISD::FrameIndex) {
149 int FI = cast<FrameIndexSDNode>(N)->getIndex();
150 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
151 } else if (N.getOpcode() == ARMISD::Wrapper) {
152 Base = N.getOperand(0);
154 Offset = CurDAG->getRegister(0, MVT::i32);
155 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
161 // Match simple R +/- imm12 operands.
162 if (N.getOpcode() == ISD::ADD)
163 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
164 int RHSC = (int)RHS->getZExtValue();
165 if ((RHSC >= 0 && RHSC < 0x1000) ||
166 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
167 Base = N.getOperand(0);
168 if (Base.getOpcode() == ISD::FrameIndex) {
169 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
170 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
172 Offset = CurDAG->getRegister(0, MVT::i32);
174 ARM_AM::AddrOpc AddSub = ARM_AM::add;
176 AddSub = ARM_AM::sub;
179 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
186 // Otherwise this is R +/- [possibly shifted] R
187 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
188 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
191 Base = N.getOperand(0);
192 Offset = N.getOperand(1);
194 if (ShOpcVal != ARM_AM::no_shift) {
195 // Check to see if the RHS of the shift is a constant, if not, we can't fold
197 if (ConstantSDNode *Sh =
198 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
199 ShAmt = Sh->getZExtValue();
200 Offset = N.getOperand(1).getOperand(0);
202 ShOpcVal = ARM_AM::no_shift;
206 // Try matching (R shl C) + (R).
207 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
208 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
209 if (ShOpcVal != ARM_AM::no_shift) {
210 // Check to see if the RHS of the shift is a constant, if not, we can't
212 if (ConstantSDNode *Sh =
213 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
214 ShAmt = Sh->getZExtValue();
215 Offset = N.getOperand(0).getOperand(0);
216 Base = N.getOperand(1);
218 ShOpcVal = ARM_AM::no_shift;
223 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
228 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
229 SDValue &Offset, SDValue &Opc) {
230 unsigned Opcode = Op.getOpcode();
231 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
232 ? cast<LoadSDNode>(Op)->getAddressingMode()
233 : cast<StoreSDNode>(Op)->getAddressingMode();
234 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
235 ? ARM_AM::add : ARM_AM::sub;
236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
237 int Val = (int)C->getZExtValue();
238 if (Val >= 0 && Val < 0x1000) { // 12 bits.
239 Offset = CurDAG->getRegister(0, MVT::i32);
240 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
248 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
250 if (ShOpcVal != ARM_AM::no_shift) {
251 // Check to see if the RHS of the shift is a constant, if not, we can't fold
253 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
254 ShAmt = Sh->getZExtValue();
255 Offset = N.getOperand(0);
257 ShOpcVal = ARM_AM::no_shift;
261 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
267 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
268 SDValue &Base, SDValue &Offset,
270 if (N.getOpcode() == ISD::SUB) {
271 // X - C is canonicalize to X + -C, no need to handle it here.
272 Base = N.getOperand(0);
273 Offset = N.getOperand(1);
274 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
278 if (N.getOpcode() != ISD::ADD) {
280 if (N.getOpcode() == ISD::FrameIndex) {
281 int FI = cast<FrameIndexSDNode>(N)->getIndex();
282 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
284 Offset = CurDAG->getRegister(0, MVT::i32);
285 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
289 // If the RHS is +/- imm8, fold into addr mode.
290 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
291 int RHSC = (int)RHS->getZExtValue();
292 if ((RHSC >= 0 && RHSC < 256) ||
293 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
294 Base = N.getOperand(0);
295 if (Base.getOpcode() == ISD::FrameIndex) {
296 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
297 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
299 Offset = CurDAG->getRegister(0, MVT::i32);
301 ARM_AM::AddrOpc AddSub = ARM_AM::add;
303 AddSub = ARM_AM::sub;
306 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
311 Base = N.getOperand(0);
312 Offset = N.getOperand(1);
313 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
317 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
318 SDValue &Offset, SDValue &Opc) {
319 unsigned Opcode = Op.getOpcode();
320 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
321 ? cast<LoadSDNode>(Op)->getAddressingMode()
322 : cast<StoreSDNode>(Op)->getAddressingMode();
323 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
324 ? ARM_AM::add : ARM_AM::sub;
325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
326 int Val = (int)C->getZExtValue();
327 if (Val >= 0 && Val < 256) {
328 Offset = CurDAG->getRegister(0, MVT::i32);
329 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
335 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
340 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
341 SDValue &Base, SDValue &Offset) {
342 if (N.getOpcode() != ISD::ADD) {
344 if (N.getOpcode() == ISD::FrameIndex) {
345 int FI = cast<FrameIndexSDNode>(N)->getIndex();
346 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
347 } else if (N.getOpcode() == ARMISD::Wrapper) {
348 Base = N.getOperand(0);
350 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
355 // If the RHS is +/- imm8, fold into addr mode.
356 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
357 int RHSC = (int)RHS->getZExtValue();
358 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
360 if ((RHSC >= 0 && RHSC < 256) ||
361 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
362 Base = N.getOperand(0);
363 if (Base.getOpcode() == ISD::FrameIndex) {
364 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
365 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
368 ARM_AM::AddrOpc AddSub = ARM_AM::add;
370 AddSub = ARM_AM::sub;
373 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
381 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
386 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
387 SDValue &Offset, SDValue &Label) {
388 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
389 Offset = N.getOperand(0);
390 SDValue N1 = N.getOperand(1);
391 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
398 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
399 SDValue &Base, SDValue &Offset){
400 // FIXME dl should come from the parent load or store, not the address
401 DebugLoc dl = Op.getDebugLoc();
402 if (N.getOpcode() != ISD::ADD) {
404 // We must materialize a zero in a reg! Returning a constant here
405 // wouldn't work without additional code to position the node within
406 // ISel's topological ordering in a place where ISel will process it
407 // normally. Instead, just explicitly issue a tMOVri8 node!
408 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32,
409 CurDAG->getTargetConstant(0, MVT::i32)), 0);
413 Base = N.getOperand(0);
414 Offset = N.getOperand(1);
419 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
420 unsigned Scale, SDValue &Base,
421 SDValue &OffImm, SDValue &Offset) {
423 SDValue TmpBase, TmpOffImm;
424 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
425 return false; // We want to select tLDRspi / tSTRspi instead.
426 if (N.getOpcode() == ARMISD::Wrapper &&
427 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
428 return false; // We want to select tLDRpci instead.
431 if (N.getOpcode() != ISD::ADD) {
432 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
433 Offset = CurDAG->getRegister(0, MVT::i32);
434 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
438 // Thumb does not have [sp, r] address mode.
439 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
440 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
441 if ((LHSR && LHSR->getReg() == ARM::SP) ||
442 (RHSR && RHSR->getReg() == ARM::SP)) {
444 Offset = CurDAG->getRegister(0, MVT::i32);
445 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
449 // If the RHS is + imm5 * scale, fold into addr mode.
450 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
451 int RHSC = (int)RHS->getZExtValue();
452 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
454 if (RHSC >= 0 && RHSC < 32) {
455 Base = N.getOperand(0);
456 Offset = CurDAG->getRegister(0, MVT::i32);
457 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
463 Base = N.getOperand(0);
464 Offset = N.getOperand(1);
465 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
469 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
470 SDValue &Base, SDValue &OffImm,
472 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
475 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
476 SDValue &Base, SDValue &OffImm,
478 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
481 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
482 SDValue &Base, SDValue &OffImm,
484 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
487 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
488 SDValue &Base, SDValue &OffImm) {
489 if (N.getOpcode() == ISD::FrameIndex) {
490 int FI = cast<FrameIndexSDNode>(N)->getIndex();
491 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
492 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
496 if (N.getOpcode() != ISD::ADD)
499 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
500 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
501 (LHSR && LHSR->getReg() == ARM::SP)) {
502 // If the RHS is + imm8 * scale, fold into addr mode.
503 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
504 int RHSC = (int)RHS->getZExtValue();
505 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
507 if (RHSC >= 0 && RHSC < 256) {
508 Base = N.getOperand(0);
509 if (Base.getOpcode() == ISD::FrameIndex) {
510 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
511 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
513 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
523 bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op,
527 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
529 // Don't match base register only case. That is matched to a separate
530 // lower complexity pattern with explicit register operand.
531 if (ShOpcVal == ARM_AM::no_shift) return false;
533 BaseReg = N.getOperand(0);
534 unsigned ShImmVal = 0;
535 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)))
536 ShImmVal = RHS->getZExtValue() & 31;
540 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
545 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
550 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
552 // Don't match base register only case. That is matched to a separate
553 // lower complexity pattern with explicit register operand.
554 if (ShOpcVal == ARM_AM::no_shift) return false;
556 BaseReg = N.getOperand(0);
557 unsigned ShImmVal = 0;
558 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
559 ShReg = CurDAG->getRegister(0, MVT::i32);
560 ShImmVal = RHS->getZExtValue() & 31;
562 ShReg = N.getOperand(1);
564 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
569 /// getAL - Returns a ARMCC::AL immediate node.
570 static inline SDValue getAL(SelectionDAG *CurDAG) {
571 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
575 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
576 SDNode *N = Op.getNode();
577 DebugLoc dl = N->getDebugLoc();
579 if (N->isMachineOpcode())
580 return NULL; // Already selected.
582 switch (N->getOpcode()) {
584 case ISD::Constant: {
585 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
587 if (Subtarget->isThumb()) {
588 if (Subtarget->hasThumb2())
589 // Thumb2 has the MOVT instruction, so all immediates can
590 // be done with MOV + MOVT, at worst.
593 UseCP = (Val > 255 && // MOV
594 ~Val > 255 && // MOV + MVN
595 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
597 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
598 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
599 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
602 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
606 if (Subtarget->isThumb())
607 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
608 CPIdx, CurDAG->getEntryNode());
612 CurDAG->getRegister(0, MVT::i32),
613 CurDAG->getTargetConstant(0, MVT::i32),
615 CurDAG->getRegister(0, MVT::i32),
616 CurDAG->getEntryNode()
618 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
621 ReplaceUses(Op, SDValue(ResNode, 0));
625 // Other cases are autogenerated.
628 case ISD::FrameIndex: {
629 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
630 int FI = cast<FrameIndexSDNode>(N)->getIndex();
631 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
632 if (Subtarget->isThumb()) {
633 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
634 CurDAG->getTargetConstant(0, MVT::i32));
636 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
637 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
638 CurDAG->getRegister(0, MVT::i32) };
639 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
643 if (!Subtarget->isThumb())
645 // Select add sp, c to tADDhirr.
646 SDValue N0 = Op.getOperand(0);
647 SDValue N1 = Op.getOperand(1);
648 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
649 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
650 if (LHSR && LHSR->getReg() == ARM::SP) {
652 std::swap(LHSR, RHSR);
654 if (RHSR && RHSR->getReg() == ARM::SP) {
655 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
656 Op.getValueType(), N0, N0), 0);
657 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
662 if (Subtarget->isThumb())
664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
665 unsigned RHSV = C->getZExtValue();
667 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
668 SDValue V = Op.getOperand(0);
669 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
670 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
671 CurDAG->getTargetConstant(ShImm, MVT::i32),
672 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
673 CurDAG->getRegister(0, MVT::i32) };
674 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
676 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
677 SDValue V = Op.getOperand(0);
678 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
679 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
680 CurDAG->getTargetConstant(ShImm, MVT::i32),
681 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
682 CurDAG->getRegister(0, MVT::i32) };
683 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
688 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
689 Op.getOperand(0), getAL(CurDAG),
690 CurDAG->getRegister(0, MVT::i32));
691 case ISD::UMUL_LOHI: {
692 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
693 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
694 CurDAG->getRegister(0, MVT::i32) };
695 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
697 case ISD::SMUL_LOHI: {
698 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
699 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
700 CurDAG->getRegister(0, MVT::i32) };
701 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
704 LoadSDNode *LD = cast<LoadSDNode>(Op);
705 ISD::MemIndexedMode AM = LD->getAddressingMode();
706 MVT LoadedVT = LD->getMemoryVT();
707 if (AM != ISD::UNINDEXED) {
708 SDValue Offset, AMOpc;
709 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
712 if (LoadedVT == MVT::i32 &&
713 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
714 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
716 } else if (LoadedVT == MVT::i16 &&
717 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
719 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
720 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
721 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
722 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
723 if (LD->getExtensionType() == ISD::SEXTLOAD) {
724 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
726 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
729 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
731 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
737 SDValue Chain = LD->getChain();
738 SDValue Base = LD->getBasePtr();
739 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
740 CurDAG->getRegister(0, MVT::i32), Chain };
741 return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32,
745 // Other cases are autogenerated.
748 case ARMISD::BRCOND: {
749 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
750 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
751 // Pattern complexity = 6 cost = 1 size = 0
753 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
754 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
755 // Pattern complexity = 6 cost = 1 size = 0
757 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
758 SDValue Chain = Op.getOperand(0);
759 SDValue N1 = Op.getOperand(1);
760 SDValue N2 = Op.getOperand(2);
761 SDValue N3 = Op.getOperand(3);
762 SDValue InFlag = Op.getOperand(4);
763 assert(N1.getOpcode() == ISD::BasicBlock);
764 assert(N2.getOpcode() == ISD::Constant);
765 assert(N3.getOpcode() == ISD::Register);
767 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
768 cast<ConstantSDNode>(N2)->getZExtValue()),
770 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
771 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
773 Chain = SDValue(ResNode, 0);
774 if (Op.getNode()->getNumValues() == 2) {
775 InFlag = SDValue(ResNode, 1);
776 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
778 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
782 bool isThumb = Subtarget->isThumb();
783 MVT VT = Op.getValueType();
784 SDValue N0 = Op.getOperand(0);
785 SDValue N1 = Op.getOperand(1);
786 SDValue N2 = Op.getOperand(2);
787 SDValue N3 = Op.getOperand(3);
788 SDValue InFlag = Op.getOperand(4);
789 assert(N2.getOpcode() == ISD::Constant);
790 assert(N3.getOpcode() == ISD::Register);
792 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
793 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
794 // Pattern complexity = 18 cost = 1 size = 0
798 if (!isThumb && VT == MVT::i32 &&
799 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
800 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
801 cast<ConstantSDNode>(N2)->getZExtValue()),
803 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
804 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
807 // Pattern: (ARMcmov:i32 GPR:i32:$false,
808 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
810 // Emits: (MOVCCi:i32 GPR:i32:$false,
811 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
812 // Pattern complexity = 10 cost = 1 size = 0
813 if (VT == MVT::i32 &&
814 N3.getOpcode() == ISD::Constant &&
815 Predicate_so_imm(N3.getNode())) {
816 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
817 cast<ConstantSDNode>(N1)->getZExtValue()),
819 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
820 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
821 cast<ConstantSDNode>(N2)->getZExtValue()),
823 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
824 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
827 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
828 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
829 // Pattern complexity = 6 cost = 1 size = 0
831 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
832 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
833 // Pattern complexity = 6 cost = 11 size = 0
835 // Also FCPYScc and FCPYDcc.
836 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
837 cast<ConstantSDNode>(N2)->getZExtValue()),
839 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
841 switch (VT.getSimpleVT()) {
842 default: assert(false && "Illegal conditional move type!");
845 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
854 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
857 MVT VT = Op.getValueType();
858 SDValue N0 = Op.getOperand(0);
859 SDValue N1 = Op.getOperand(1);
860 SDValue N2 = Op.getOperand(2);
861 SDValue N3 = Op.getOperand(3);
862 SDValue InFlag = Op.getOperand(4);
863 assert(N2.getOpcode() == ISD::Constant);
864 assert(N3.getOpcode() == ISD::Register);
866 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
867 cast<ConstantSDNode>(N2)->getZExtValue()),
869 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
871 switch (VT.getSimpleVT()) {
872 default: assert(false && "Illegal conditional move type!");
881 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
885 SDValue Chain = Op.getOperand(0);
886 SDValue N1 = Op.getOperand(1);
887 SDValue N2 = Op.getOperand(2);
888 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
889 // FIXME: handle VLAs.
891 ReplaceUses(Op.getValue(0), Chain);
894 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
895 N2 = N2.getOperand(0);
896 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
898 ReplaceUses(Op.getValue(0), Chain);
901 SDValue BasePtr = Ld->getBasePtr();
902 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
903 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
904 "llvm.dbg.variable should be a constantpool node");
905 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
907 if (CP->isMachineConstantPoolEntry()) {
908 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
911 GV = dyn_cast<GlobalValue>(CP->getConstVal());
913 ReplaceUses(Op.getValue(0), Chain);
917 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
919 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
920 SDValue Ops[] = { Tmp1, Tmp2, Chain };
921 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
925 case ISD::CONCAT_VECTORS: {
926 MVT VT = Op.getValueType();
927 assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
928 "unexpected CONCAT_VECTORS");
929 SDValue N0 = Op.getOperand(0);
930 SDValue N1 = Op.getOperand(1);
932 CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
933 if (N0.getOpcode() != ISD::UNDEF)
934 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
935 SDValue(Result, 0), N0,
936 CurDAG->getTargetConstant(arm_dsubreg_0,
938 if (N1.getOpcode() != ISD::UNDEF)
939 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
940 SDValue(Result, 0), N1,
941 CurDAG->getTargetConstant(arm_dsubreg_1,
946 case ISD::VECTOR_SHUFFLE: {
947 MVT VT = Op.getValueType();
949 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
950 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
951 // transformed first into a lane number and then to both a subregister
952 // index and an adjusted lane number.) If the source operand is a
953 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
954 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
955 if (VT.is128BitVector() && SVOp->isSplat() &&
956 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
957 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
958 unsigned LaneVal = SVOp->getSplatIndex();
962 switch (VT.getVectorElementType().getSimpleVT()) {
963 default: assert(false && "unhandled VDUP splat type");
964 case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
965 case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
966 case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
967 case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
970 // The source operand needs to be changed to a subreg of the original
971 // 128-bit operand, and the lane number needs to be adjusted accordingly.
972 unsigned NumElts = VT.getVectorNumElements() / 2;
973 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
974 SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
975 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
976 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
977 dl, HalfVT, N->getOperand(0), SR);
978 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
985 return SelectCode(Op);
988 bool ARMDAGToDAGISel::
989 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
990 std::vector<SDValue> &OutOps) {
991 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
993 SDValue Base, Offset, Opc;
994 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
997 OutOps.push_back(Base);
998 OutOps.push_back(Offset);
999 OutOps.push_back(Opc);
1003 /// createARMISelDag - This pass converts a legalized DAG into a
1004 /// ARM-specific DAG, ready for instruction scheduling.
1006 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
1007 return new ARMDAGToDAGISel(TM);