1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
41 /// instructions for SelectionDAG operations.
44 class ARMDAGToDAGISel : public SelectionDAGISel {
45 ARMBaseTargetMachine &TM;
47 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const ARMSubtarget *Subtarget;
52 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
53 : SelectionDAGISel(tm), TM(tm),
54 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
57 virtual const char *getPassName() const {
58 return "ARM Instruction Selection";
61 /// getI32Imm - Return a target constant with the specified value, of type i32.
62 inline SDValue getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 SDNode *Select(SDValue Op);
67 virtual void InstructionSelect();
68 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
69 SDValue &B, SDValue &C);
70 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
71 SDValue &Offset, SDValue &Opc);
72 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
73 SDValue &Offset, SDValue &Opc);
74 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
75 SDValue &Offset, SDValue &Opc);
76 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
77 SDValue &Offset, SDValue &Opc);
78 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
80 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
82 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
85 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
88 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
90 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
91 SDValue &Base, SDValue &OffImm,
93 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
94 SDValue &OffImm, SDValue &Offset);
95 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
96 SDValue &OffImm, SDValue &Offset);
97 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
98 SDValue &OffImm, SDValue &Offset);
99 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
102 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
103 SDValue &BaseReg, SDValue &Opc);
104 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
106 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
108 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
110 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
112 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
113 SDValue &OffReg, SDValue &ShImm);
115 // Include the pieces autogenerated from the target description.
116 #include "ARMGenDAGISel.inc"
119 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
121 SDNode *SelectARMIndexedLoad(SDValue Op);
122 SDNode *SelectT2IndexedLoad(SDValue Op);
124 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
125 SDNode *SelectDYN_ALLOC(SDValue Op);
127 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
128 /// inline asm expressions.
129 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
131 std::vector<SDValue> &OutOps);
135 void ARMDAGToDAGISel::InstructionSelect() {
139 CurDAG->RemoveDeadNodes();
142 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
147 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
149 // Don't match base register only case. That is matched to a separate
150 // lower complexity pattern with explicit register operand.
151 if (ShOpcVal == ARM_AM::no_shift) return false;
153 BaseReg = N.getOperand(0);
154 unsigned ShImmVal = 0;
155 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
156 ShReg = CurDAG->getRegister(0, MVT::i32);
157 ShImmVal = RHS->getZExtValue() & 31;
159 ShReg = N.getOperand(1);
161 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
166 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
167 SDValue &Base, SDValue &Offset,
169 if (N.getOpcode() == ISD::MUL) {
170 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
171 // X * [3,5,9] -> X + X * [2,4,8] etc.
172 int RHSC = (int)RHS->getZExtValue();
175 ARM_AM::AddrOpc AddSub = ARM_AM::add;
177 AddSub = ARM_AM::sub;
180 if (isPowerOf2_32(RHSC)) {
181 unsigned ShAmt = Log2_32(RHSC);
182 Base = Offset = N.getOperand(0);
183 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
192 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
194 if (N.getOpcode() == ISD::FrameIndex) {
195 int FI = cast<FrameIndexSDNode>(N)->getIndex();
196 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
197 } else if (N.getOpcode() == ARMISD::Wrapper) {
198 Base = N.getOperand(0);
200 Offset = CurDAG->getRegister(0, MVT::i32);
201 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
207 // Match simple R +/- imm12 operands.
208 if (N.getOpcode() == ISD::ADD)
209 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
210 int RHSC = (int)RHS->getZExtValue();
211 if ((RHSC >= 0 && RHSC < 0x1000) ||
212 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
213 Base = N.getOperand(0);
214 if (Base.getOpcode() == ISD::FrameIndex) {
215 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
216 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
218 Offset = CurDAG->getRegister(0, MVT::i32);
220 ARM_AM::AddrOpc AddSub = ARM_AM::add;
222 AddSub = ARM_AM::sub;
225 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
232 // Otherwise this is R +/- [possibly shifted] R
233 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
234 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
237 Base = N.getOperand(0);
238 Offset = N.getOperand(1);
240 if (ShOpcVal != ARM_AM::no_shift) {
241 // Check to see if the RHS of the shift is a constant, if not, we can't fold
243 if (ConstantSDNode *Sh =
244 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
245 ShAmt = Sh->getZExtValue();
246 Offset = N.getOperand(1).getOperand(0);
248 ShOpcVal = ARM_AM::no_shift;
252 // Try matching (R shl C) + (R).
253 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
254 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
255 if (ShOpcVal != ARM_AM::no_shift) {
256 // Check to see if the RHS of the shift is a constant, if not, we can't
258 if (ConstantSDNode *Sh =
259 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
260 ShAmt = Sh->getZExtValue();
261 Offset = N.getOperand(0).getOperand(0);
262 Base = N.getOperand(1);
264 ShOpcVal = ARM_AM::no_shift;
269 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
274 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
275 SDValue &Offset, SDValue &Opc) {
276 unsigned Opcode = Op.getOpcode();
277 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
278 ? cast<LoadSDNode>(Op)->getAddressingMode()
279 : cast<StoreSDNode>(Op)->getAddressingMode();
280 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
281 ? ARM_AM::add : ARM_AM::sub;
282 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
283 int Val = (int)C->getZExtValue();
284 if (Val >= 0 && Val < 0x1000) { // 12 bits.
285 Offset = CurDAG->getRegister(0, MVT::i32);
286 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
294 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
296 if (ShOpcVal != ARM_AM::no_shift) {
297 // Check to see if the RHS of the shift is a constant, if not, we can't fold
299 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
300 ShAmt = Sh->getZExtValue();
301 Offset = N.getOperand(0);
303 ShOpcVal = ARM_AM::no_shift;
307 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
313 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
314 SDValue &Base, SDValue &Offset,
316 if (N.getOpcode() == ISD::SUB) {
317 // X - C is canonicalize to X + -C, no need to handle it here.
318 Base = N.getOperand(0);
319 Offset = N.getOperand(1);
320 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
324 if (N.getOpcode() != ISD::ADD) {
326 if (N.getOpcode() == ISD::FrameIndex) {
327 int FI = cast<FrameIndexSDNode>(N)->getIndex();
328 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
330 Offset = CurDAG->getRegister(0, MVT::i32);
331 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
335 // If the RHS is +/- imm8, fold into addr mode.
336 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
337 int RHSC = (int)RHS->getZExtValue();
338 if ((RHSC >= 0 && RHSC < 256) ||
339 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
340 Base = N.getOperand(0);
341 if (Base.getOpcode() == ISD::FrameIndex) {
342 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
343 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
345 Offset = CurDAG->getRegister(0, MVT::i32);
347 ARM_AM::AddrOpc AddSub = ARM_AM::add;
349 AddSub = ARM_AM::sub;
352 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
357 Base = N.getOperand(0);
358 Offset = N.getOperand(1);
359 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
363 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
364 SDValue &Offset, SDValue &Opc) {
365 unsigned Opcode = Op.getOpcode();
366 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
367 ? cast<LoadSDNode>(Op)->getAddressingMode()
368 : cast<StoreSDNode>(Op)->getAddressingMode();
369 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
370 ? ARM_AM::add : ARM_AM::sub;
371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
372 int Val = (int)C->getZExtValue();
373 if (Val >= 0 && Val < 256) {
374 Offset = CurDAG->getRegister(0, MVT::i32);
375 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
381 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
385 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
386 SDValue &Addr, SDValue &Mode) {
388 Mode = CurDAG->getTargetConstant(0, MVT::i32);
392 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
393 SDValue &Base, SDValue &Offset) {
394 if (N.getOpcode() != ISD::ADD) {
396 if (N.getOpcode() == ISD::FrameIndex) {
397 int FI = cast<FrameIndexSDNode>(N)->getIndex();
398 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
399 } else if (N.getOpcode() == ARMISD::Wrapper) {
400 Base = N.getOperand(0);
402 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
407 // If the RHS is +/- imm8, fold into addr mode.
408 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
409 int RHSC = (int)RHS->getZExtValue();
410 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
412 if ((RHSC >= 0 && RHSC < 256) ||
413 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
414 Base = N.getOperand(0);
415 if (Base.getOpcode() == ISD::FrameIndex) {
416 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
417 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
420 ARM_AM::AddrOpc AddSub = ARM_AM::add;
422 AddSub = ARM_AM::sub;
425 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
433 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
438 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
439 SDValue &Addr, SDValue &Update,
442 // The optional writeback is handled in ARMLoadStoreOpt.
443 Update = CurDAG->getRegister(0, MVT::i32);
444 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
448 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
449 SDValue &Offset, SDValue &Label) {
450 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
451 Offset = N.getOperand(0);
452 SDValue N1 = N.getOperand(1);
453 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
460 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
461 SDValue &Base, SDValue &Offset){
462 // FIXME dl should come from the parent load or store, not the address
463 DebugLoc dl = Op.getDebugLoc();
464 if (N.getOpcode() != ISD::ADD) {
465 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
466 if (!NC || NC->getZExtValue() != 0)
473 Base = N.getOperand(0);
474 Offset = N.getOperand(1);
479 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
480 unsigned Scale, SDValue &Base,
481 SDValue &OffImm, SDValue &Offset) {
483 SDValue TmpBase, TmpOffImm;
484 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
485 return false; // We want to select tLDRspi / tSTRspi instead.
486 if (N.getOpcode() == ARMISD::Wrapper &&
487 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
488 return false; // We want to select tLDRpci instead.
491 if (N.getOpcode() != ISD::ADD) {
492 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
493 Offset = CurDAG->getRegister(0, MVT::i32);
494 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
498 // Thumb does not have [sp, r] address mode.
499 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
500 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
501 if ((LHSR && LHSR->getReg() == ARM::SP) ||
502 (RHSR && RHSR->getReg() == ARM::SP)) {
504 Offset = CurDAG->getRegister(0, MVT::i32);
505 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
509 // If the RHS is + imm5 * scale, fold into addr mode.
510 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
511 int RHSC = (int)RHS->getZExtValue();
512 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
514 if (RHSC >= 0 && RHSC < 32) {
515 Base = N.getOperand(0);
516 Offset = CurDAG->getRegister(0, MVT::i32);
517 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
523 Base = N.getOperand(0);
524 Offset = N.getOperand(1);
525 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
529 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
530 SDValue &Base, SDValue &OffImm,
532 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
535 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
536 SDValue &Base, SDValue &OffImm,
538 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
541 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
542 SDValue &Base, SDValue &OffImm,
544 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
547 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
548 SDValue &Base, SDValue &OffImm) {
549 if (N.getOpcode() == ISD::FrameIndex) {
550 int FI = cast<FrameIndexSDNode>(N)->getIndex();
551 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
552 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
556 if (N.getOpcode() != ISD::ADD)
559 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
560 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
561 (LHSR && LHSR->getReg() == ARM::SP)) {
562 // If the RHS is + imm8 * scale, fold into addr mode.
563 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
564 int RHSC = (int)RHS->getZExtValue();
565 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
567 if (RHSC >= 0 && RHSC < 256) {
568 Base = N.getOperand(0);
569 if (Base.getOpcode() == ISD::FrameIndex) {
570 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
571 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
573 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
583 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
586 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
588 // Don't match base register only case. That is matched to a separate
589 // lower complexity pattern with explicit register operand.
590 if (ShOpcVal == ARM_AM::no_shift) return false;
592 BaseReg = N.getOperand(0);
593 unsigned ShImmVal = 0;
594 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
595 ShImmVal = RHS->getZExtValue() & 31;
596 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
603 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
604 SDValue &Base, SDValue &OffImm) {
605 // Match simple R + imm12 operands.
608 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
609 if (N.getOpcode() == ISD::FrameIndex) {
610 // Match frame index...
611 int FI = cast<FrameIndexSDNode>(N)->getIndex();
612 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
613 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
615 } else if (N.getOpcode() == ARMISD::Wrapper) {
616 Base = N.getOperand(0);
617 if (Base.getOpcode() == ISD::TargetConstantPool)
618 return false; // We want to select t2LDRpci instead.
621 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
625 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
626 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
627 // Let t2LDRi8 handle (R - imm8).
630 int RHSC = (int)RHS->getZExtValue();
631 if (N.getOpcode() == ISD::SUB)
634 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
635 Base = N.getOperand(0);
636 if (Base.getOpcode() == ISD::FrameIndex) {
637 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
638 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
640 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
647 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
651 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
652 SDValue &Base, SDValue &OffImm) {
653 // Match simple R - imm8 operands.
654 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
655 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
656 int RHSC = (int)RHS->getSExtValue();
657 if (N.getOpcode() == ISD::SUB)
660 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
661 Base = N.getOperand(0);
662 if (Base.getOpcode() == ISD::FrameIndex) {
663 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
664 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
666 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
675 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
677 unsigned Opcode = Op.getOpcode();
678 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
679 ? cast<LoadSDNode>(Op)->getAddressingMode()
680 : cast<StoreSDNode>(Op)->getAddressingMode();
681 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
682 int RHSC = (int)RHS->getZExtValue();
683 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
684 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
685 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
686 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
694 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
695 SDValue &Base, SDValue &OffImm) {
696 if (N.getOpcode() == ISD::ADD) {
697 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
698 int RHSC = (int)RHS->getZExtValue();
699 if (((RHSC & 0x3) == 0) &&
700 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
701 Base = N.getOperand(0);
702 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
706 } else if (N.getOpcode() == ISD::SUB) {
707 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
708 int RHSC = (int)RHS->getZExtValue();
709 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
710 Base = N.getOperand(0);
711 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
720 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
722 SDValue &OffReg, SDValue &ShImm) {
723 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
724 if (N.getOpcode() != ISD::ADD)
727 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
728 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
729 int RHSC = (int)RHS->getZExtValue();
730 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
732 else if (RHSC < 0 && RHSC >= -255) // 8 bits
736 // Look for (R + R) or (R + (R << [1,2,3])).
738 Base = N.getOperand(0);
739 OffReg = N.getOperand(1);
741 // Swap if it is ((R << c) + R).
742 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
743 if (ShOpcVal != ARM_AM::lsl) {
744 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
745 if (ShOpcVal == ARM_AM::lsl)
746 std::swap(Base, OffReg);
749 if (ShOpcVal == ARM_AM::lsl) {
750 // Check to see if the RHS of the shift is a constant, if not, we can't fold
752 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
753 ShAmt = Sh->getZExtValue();
756 ShOpcVal = ARM_AM::no_shift;
758 OffReg = OffReg.getOperand(0);
760 ShOpcVal = ARM_AM::no_shift;
764 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
769 //===--------------------------------------------------------------------===//
771 /// getAL - Returns a ARMCC::AL immediate node.
772 static inline SDValue getAL(SelectionDAG *CurDAG) {
773 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
776 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
777 LoadSDNode *LD = cast<LoadSDNode>(Op);
778 ISD::MemIndexedMode AM = LD->getAddressingMode();
779 if (AM == ISD::UNINDEXED)
782 EVT LoadedVT = LD->getMemoryVT();
783 SDValue Offset, AMOpc;
784 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
787 if (LoadedVT == MVT::i32 &&
788 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
789 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
791 } else if (LoadedVT == MVT::i16 &&
792 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
794 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
795 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
796 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
797 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
798 if (LD->getExtensionType() == ISD::SEXTLOAD) {
799 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
801 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
804 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
806 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
812 SDValue Chain = LD->getChain();
813 SDValue Base = LD->getBasePtr();
814 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
815 CurDAG->getRegister(0, MVT::i32), Chain };
816 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
823 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
824 LoadSDNode *LD = cast<LoadSDNode>(Op);
825 ISD::MemIndexedMode AM = LD->getAddressingMode();
826 if (AM == ISD::UNINDEXED)
829 EVT LoadedVT = LD->getMemoryVT();
830 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
832 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
835 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
836 switch (LoadedVT.getSimpleVT().SimpleTy) {
838 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
842 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
844 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
849 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
851 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
860 SDValue Chain = LD->getChain();
861 SDValue Base = LD->getBasePtr();
862 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
863 CurDAG->getRegister(0, MVT::i32), Chain };
864 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
871 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
872 SDNode *N = Op.getNode();
873 DebugLoc dl = N->getDebugLoc();
874 EVT VT = Op.getValueType();
875 SDValue Chain = Op.getOperand(0);
876 SDValue Size = Op.getOperand(1);
877 SDValue Align = Op.getOperand(2);
878 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
879 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
881 // We need to align the stack. Use Thumb1 tAND which is the only thumb
882 // instruction that can read and write SP. This matches to a pseudo
883 // instruction that has a chain to ensure the result is written back to
884 // the stack pointer.
885 SP = SDValue(CurDAG->getTargetNode(ARM::tANDsp, dl, VT, SP, Align), 0);
887 bool isC = isa<ConstantSDNode>(Size);
888 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
889 // Handle the most common case for both Thumb1 and Thumb2:
890 // tSUBspi - immediate is between 0 ... 508 inclusive.
891 if (C <= 508 && ((C & 3) == 0))
892 // FIXME: tSUBspi encode scale 4 implicitly.
893 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
894 CurDAG->getTargetConstant(C/4, MVT::i32),
897 if (Subtarget->isThumb1Only()) {
898 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
899 // should have negated the size operand already. FIXME: We can't insert
900 // new target independent node at this stage so we are forced to negate
901 // it earlier. Is there a better solution?
902 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
904 } else if (Subtarget->isThumb2()) {
905 if (isC && Predicate_t2_so_imm(Size.getNode())) {
907 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
908 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
909 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
911 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
912 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
915 SDValue Ops[] = { SP, Size,
916 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
917 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
921 // FIXME: Add ADD / SUB sp instructions for ARM.
925 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
926 SDNode *N = Op.getNode();
927 DebugLoc dl = N->getDebugLoc();
929 if (N->isMachineOpcode())
930 return NULL; // Already selected.
932 switch (N->getOpcode()) {
934 case ISD::Constant: {
935 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
937 if (Subtarget->isThumb()) {
938 if (Subtarget->hasThumb2())
939 // Thumb2 has the MOVT instruction, so all immediates can
940 // be done with MOV + MOVT, at worst.
943 UseCP = (Val > 255 && // MOV
944 ~Val > 255 && // MOV + MVN
945 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
947 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
948 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
949 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
952 CurDAG->getTargetConstantPool(ConstantInt::get(
953 Type::getInt32Ty(*CurDAG->getContext()), Val),
957 if (Subtarget->isThumb1Only()) {
958 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
959 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
960 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
961 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
966 CurDAG->getRegister(0, MVT::i32),
967 CurDAG->getTargetConstant(0, MVT::i32),
969 CurDAG->getRegister(0, MVT::i32),
970 CurDAG->getEntryNode()
972 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
975 ReplaceUses(Op, SDValue(ResNode, 0));
979 // Other cases are autogenerated.
982 case ISD::FrameIndex: {
983 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
984 int FI = cast<FrameIndexSDNode>(N)->getIndex();
985 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
986 if (Subtarget->isThumb1Only()) {
987 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
988 CurDAG->getTargetConstant(0, MVT::i32));
990 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
991 ARM::t2ADDri : ARM::ADDri);
992 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
993 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
994 CurDAG->getRegister(0, MVT::i32) };
995 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
998 case ARMISD::DYN_ALLOC:
999 return SelectDYN_ALLOC(Op);
1001 if (Subtarget->isThumb1Only())
1003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1004 unsigned RHSV = C->getZExtValue();
1006 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1007 unsigned ShImm = Log2_32(RHSV-1);
1010 SDValue V = Op.getOperand(0);
1011 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1012 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1013 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1014 if (Subtarget->isThumb()) {
1015 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1016 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1018 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1019 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1022 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1023 unsigned ShImm = Log2_32(RHSV+1);
1026 SDValue V = Op.getOperand(0);
1027 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1028 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1029 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1030 if (Subtarget->isThumb()) {
1031 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1032 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1034 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1035 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1041 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
1042 Op.getOperand(0), getAL(CurDAG),
1043 CurDAG->getRegister(0, MVT::i32));
1044 case ISD::UMUL_LOHI: {
1045 if (Subtarget->isThumb1Only())
1047 if (Subtarget->isThumb()) {
1048 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1049 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1050 CurDAG->getRegister(0, MVT::i32) };
1051 return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1053 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1054 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1055 CurDAG->getRegister(0, MVT::i32) };
1056 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1059 case ISD::SMUL_LOHI: {
1060 if (Subtarget->isThumb1Only())
1062 if (Subtarget->isThumb()) {
1063 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1064 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1065 return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1067 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1068 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1069 CurDAG->getRegister(0, MVT::i32) };
1070 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1074 SDNode *ResNode = 0;
1075 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1076 ResNode = SelectT2IndexedLoad(Op);
1078 ResNode = SelectARMIndexedLoad(Op);
1081 // Other cases are autogenerated.
1084 case ARMISD::BRCOND: {
1085 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1086 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1087 // Pattern complexity = 6 cost = 1 size = 0
1089 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1090 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1091 // Pattern complexity = 6 cost = 1 size = 0
1093 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1094 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1095 // Pattern complexity = 6 cost = 1 size = 0
1097 unsigned Opc = Subtarget->isThumb() ?
1098 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1099 SDValue Chain = Op.getOperand(0);
1100 SDValue N1 = Op.getOperand(1);
1101 SDValue N2 = Op.getOperand(2);
1102 SDValue N3 = Op.getOperand(3);
1103 SDValue InFlag = Op.getOperand(4);
1104 assert(N1.getOpcode() == ISD::BasicBlock);
1105 assert(N2.getOpcode() == ISD::Constant);
1106 assert(N3.getOpcode() == ISD::Register);
1108 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1109 cast<ConstantSDNode>(N2)->getZExtValue()),
1111 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1112 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
1114 Chain = SDValue(ResNode, 0);
1115 if (Op.getNode()->getNumValues() == 2) {
1116 InFlag = SDValue(ResNode, 1);
1117 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1119 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1122 case ARMISD::CMOV: {
1123 EVT VT = Op.getValueType();
1124 SDValue N0 = Op.getOperand(0);
1125 SDValue N1 = Op.getOperand(1);
1126 SDValue N2 = Op.getOperand(2);
1127 SDValue N3 = Op.getOperand(3);
1128 SDValue InFlag = Op.getOperand(4);
1129 assert(N2.getOpcode() == ISD::Constant);
1130 assert(N3.getOpcode() == ISD::Register);
1132 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1133 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1134 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1135 // Pattern complexity = 18 cost = 1 size = 0
1139 if (Subtarget->isThumb()) {
1140 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1141 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1142 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1145 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1146 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1147 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1148 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1150 llvm_unreachable("Unknown so_reg opcode!");
1154 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1155 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1156 cast<ConstantSDNode>(N2)->getZExtValue()),
1158 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1159 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1162 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1163 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1164 cast<ConstantSDNode>(N2)->getZExtValue()),
1166 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1167 return CurDAG->SelectNodeTo(Op.getNode(),
1168 ARM::MOVCCs, MVT::i32, Ops, 7);
1172 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1173 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1175 // Emits: (MOVCCi:i32 GPR:i32:$false,
1176 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1177 // Pattern complexity = 10 cost = 1 size = 0
1178 if (N3.getOpcode() == ISD::Constant) {
1179 if (Subtarget->isThumb()) {
1180 if (Predicate_t2_so_imm(N3.getNode())) {
1181 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1182 cast<ConstantSDNode>(N1)->getZExtValue()),
1184 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1185 cast<ConstantSDNode>(N2)->getZExtValue()),
1187 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1188 return CurDAG->SelectNodeTo(Op.getNode(),
1189 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1192 if (Predicate_so_imm(N3.getNode())) {
1193 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1194 cast<ConstantSDNode>(N1)->getZExtValue()),
1196 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1197 cast<ConstantSDNode>(N2)->getZExtValue()),
1199 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1200 return CurDAG->SelectNodeTo(Op.getNode(),
1201 ARM::MOVCCi, MVT::i32, Ops, 5);
1207 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1208 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1209 // Pattern complexity = 6 cost = 1 size = 0
1211 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1212 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1213 // Pattern complexity = 6 cost = 11 size = 0
1215 // Also FCPYScc and FCPYDcc.
1216 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1217 cast<ConstantSDNode>(N2)->getZExtValue()),
1219 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1221 switch (VT.getSimpleVT().SimpleTy) {
1222 default: assert(false && "Illegal conditional move type!");
1225 Opc = Subtarget->isThumb()
1226 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1236 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1238 case ARMISD::CNEG: {
1239 EVT VT = Op.getValueType();
1240 SDValue N0 = Op.getOperand(0);
1241 SDValue N1 = Op.getOperand(1);
1242 SDValue N2 = Op.getOperand(2);
1243 SDValue N3 = Op.getOperand(3);
1244 SDValue InFlag = Op.getOperand(4);
1245 assert(N2.getOpcode() == ISD::Constant);
1246 assert(N3.getOpcode() == ISD::Register);
1248 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1249 cast<ConstantSDNode>(N2)->getZExtValue()),
1251 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1253 switch (VT.getSimpleVT().SimpleTy) {
1254 default: assert(false && "Illegal conditional move type!");
1263 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1266 case ARMISD::VZIP: {
1268 EVT VT = N->getValueType(0);
1269 switch (VT.getSimpleVT().SimpleTy) {
1270 default: return NULL;
1271 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1272 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1274 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1275 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1276 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1278 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1280 return CurDAG->getTargetNode(Opc, dl, VT, VT,
1281 N->getOperand(0), N->getOperand(1));
1283 case ARMISD::VUZP: {
1285 EVT VT = N->getValueType(0);
1286 switch (VT.getSimpleVT().SimpleTy) {
1287 default: return NULL;
1288 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1289 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1291 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1292 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1293 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1295 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1297 return CurDAG->getTargetNode(Opc, dl, VT, VT,
1298 N->getOperand(0), N->getOperand(1));
1300 case ARMISD::VTRN: {
1302 EVT VT = N->getValueType(0);
1303 switch (VT.getSimpleVT().SimpleTy) {
1304 default: return NULL;
1305 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1306 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1308 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1309 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1310 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1312 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1314 return CurDAG->getTargetNode(Opc, dl, VT, VT,
1315 N->getOperand(0), N->getOperand(1));
1318 case ISD::INTRINSIC_VOID:
1319 case ISD::INTRINSIC_W_CHAIN: {
1320 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1321 EVT VT = N->getValueType(0);
1328 case Intrinsic::arm_neon_vld2: {
1329 SDValue MemAddr, MemUpdate, MemOpc;
1330 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1332 switch (VT.getSimpleVT().SimpleTy) {
1333 default: llvm_unreachable("unhandled vld2 type");
1334 case MVT::v8i8: Opc = ARM::VLD2d8; break;
1335 case MVT::v4i16: Opc = ARM::VLD2d16; break;
1337 case MVT::v2i32: Opc = ARM::VLD2d32; break;
1339 SDValue Chain = N->getOperand(0);
1340 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1341 return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
1344 case Intrinsic::arm_neon_vld3: {
1345 SDValue MemAddr, MemUpdate, MemOpc;
1346 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1348 switch (VT.getSimpleVT().SimpleTy) {
1349 default: llvm_unreachable("unhandled vld3 type");
1350 case MVT::v8i8: Opc = ARM::VLD3d8; break;
1351 case MVT::v4i16: Opc = ARM::VLD3d16; break;
1353 case MVT::v2i32: Opc = ARM::VLD3d32; break;
1355 SDValue Chain = N->getOperand(0);
1356 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1357 return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
1360 case Intrinsic::arm_neon_vld4: {
1361 SDValue MemAddr, MemUpdate, MemOpc;
1362 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1364 switch (VT.getSimpleVT().SimpleTy) {
1365 default: llvm_unreachable("unhandled vld4 type");
1366 case MVT::v8i8: Opc = ARM::VLD4d8; break;
1367 case MVT::v4i16: Opc = ARM::VLD4d16; break;
1369 case MVT::v2i32: Opc = ARM::VLD4d32; break;
1371 SDValue Chain = N->getOperand(0);
1372 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1373 std::vector<EVT> ResTys(4, VT);
1374 ResTys.push_back(MVT::Other);
1375 return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
1378 case Intrinsic::arm_neon_vld2lane: {
1379 SDValue MemAddr, MemUpdate, MemOpc;
1380 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1382 switch (VT.getSimpleVT().SimpleTy) {
1383 default: llvm_unreachable("unhandled vld2lane type");
1384 case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
1385 case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
1387 case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
1389 SDValue Chain = N->getOperand(0);
1390 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1391 N->getOperand(3), N->getOperand(4),
1392 N->getOperand(5), Chain };
1393 return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
1396 case Intrinsic::arm_neon_vld3lane: {
1397 SDValue MemAddr, MemUpdate, MemOpc;
1398 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1400 switch (VT.getSimpleVT().SimpleTy) {
1401 default: llvm_unreachable("unhandled vld3lane type");
1402 case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
1403 case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
1405 case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
1407 SDValue Chain = N->getOperand(0);
1408 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1409 N->getOperand(3), N->getOperand(4),
1410 N->getOperand(5), N->getOperand(6), Chain };
1411 return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
1414 case Intrinsic::arm_neon_vld4lane: {
1415 SDValue MemAddr, MemUpdate, MemOpc;
1416 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1418 switch (VT.getSimpleVT().SimpleTy) {
1419 default: llvm_unreachable("unhandled vld4lane type");
1420 case MVT::v8i8: Opc = ARM::VLD4LNd8; break;
1421 case MVT::v4i16: Opc = ARM::VLD4LNd16; break;
1423 case MVT::v2i32: Opc = ARM::VLD4LNd32; break;
1425 SDValue Chain = N->getOperand(0);
1426 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1427 N->getOperand(3), N->getOperand(4),
1428 N->getOperand(5), N->getOperand(6),
1429 N->getOperand(7), Chain };
1430 std::vector<EVT> ResTys(4, VT);
1431 ResTys.push_back(MVT::Other);
1432 return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 9);
1435 case Intrinsic::arm_neon_vst2: {
1436 SDValue MemAddr, MemUpdate, MemOpc;
1437 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1439 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1440 default: llvm_unreachable("unhandled vst2 type");
1441 case MVT::v8i8: Opc = ARM::VST2d8; break;
1442 case MVT::v4i16: Opc = ARM::VST2d16; break;
1444 case MVT::v2i32: Opc = ARM::VST2d32; break;
1446 SDValue Chain = N->getOperand(0);
1447 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1448 N->getOperand(3), N->getOperand(4), Chain };
1449 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
1452 case Intrinsic::arm_neon_vst3: {
1453 SDValue MemAddr, MemUpdate, MemOpc;
1454 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1456 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1457 default: llvm_unreachable("unhandled vst3 type");
1458 case MVT::v8i8: Opc = ARM::VST3d8; break;
1459 case MVT::v4i16: Opc = ARM::VST3d16; break;
1461 case MVT::v2i32: Opc = ARM::VST3d32; break;
1463 SDValue Chain = N->getOperand(0);
1464 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1465 N->getOperand(3), N->getOperand(4),
1466 N->getOperand(5), Chain };
1467 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
1470 case Intrinsic::arm_neon_vst4: {
1471 SDValue MemAddr, MemUpdate, MemOpc;
1472 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1474 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1475 default: llvm_unreachable("unhandled vst4 type");
1476 case MVT::v8i8: Opc = ARM::VST4d8; break;
1477 case MVT::v4i16: Opc = ARM::VST4d16; break;
1479 case MVT::v2i32: Opc = ARM::VST4d32; break;
1481 SDValue Chain = N->getOperand(0);
1482 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1483 N->getOperand(3), N->getOperand(4),
1484 N->getOperand(5), N->getOperand(6), Chain };
1485 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
1488 case Intrinsic::arm_neon_vst2lane: {
1489 SDValue MemAddr, MemUpdate, MemOpc;
1490 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1492 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1493 default: llvm_unreachable("unhandled vst2lane type");
1494 case MVT::v8i8: Opc = ARM::VST2LNd8; break;
1495 case MVT::v4i16: Opc = ARM::VST2LNd16; break;
1497 case MVT::v2i32: Opc = ARM::VST2LNd32; break;
1499 SDValue Chain = N->getOperand(0);
1500 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1501 N->getOperand(3), N->getOperand(4),
1502 N->getOperand(5), Chain };
1503 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
1506 case Intrinsic::arm_neon_vst3lane: {
1507 SDValue MemAddr, MemUpdate, MemOpc;
1508 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1510 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1511 default: llvm_unreachable("unhandled vst3lane type");
1512 case MVT::v8i8: Opc = ARM::VST3LNd8; break;
1513 case MVT::v4i16: Opc = ARM::VST3LNd16; break;
1515 case MVT::v2i32: Opc = ARM::VST3LNd32; break;
1517 SDValue Chain = N->getOperand(0);
1518 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1519 N->getOperand(3), N->getOperand(4),
1520 N->getOperand(5), N->getOperand(6), Chain };
1521 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
1524 case Intrinsic::arm_neon_vst4lane: {
1525 SDValue MemAddr, MemUpdate, MemOpc;
1526 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1528 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1529 default: llvm_unreachable("unhandled vst4lane type");
1530 case MVT::v8i8: Opc = ARM::VST4LNd8; break;
1531 case MVT::v4i16: Opc = ARM::VST4LNd16; break;
1533 case MVT::v2i32: Opc = ARM::VST4LNd32; break;
1535 SDValue Chain = N->getOperand(0);
1536 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1537 N->getOperand(3), N->getOperand(4),
1538 N->getOperand(5), N->getOperand(6),
1539 N->getOperand(7), Chain };
1540 return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 9);
1546 return SelectCode(Op);
1549 bool ARMDAGToDAGISel::
1550 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1551 std::vector<SDValue> &OutOps) {
1552 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1554 SDValue Base, Offset, Opc;
1555 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1558 OutOps.push_back(Base);
1559 OutOps.push_back(Offset);
1560 OutOps.push_back(Opc);
1564 /// createARMISelDag - This pass converts a legalized DAG into a
1565 /// ARM-specific DAG, ready for instruction scheduling.
1567 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1568 return new ARMDAGToDAGISel(TM);