1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
35 static const unsigned arm_dsubreg_0 = 5;
36 static const unsigned arm_dsubreg_1 = 6;
38 //===--------------------------------------------------------------------===//
39 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
40 /// instructions for SelectionDAG operations.
43 class ARMDAGToDAGISel : public SelectionDAGISel {
44 ARMBaseTargetMachine &TM;
46 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47 /// make the right decision when generating code for different targets.
48 const ARMSubtarget *Subtarget;
51 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
52 : SelectionDAGISel(tm), TM(tm),
53 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
56 virtual const char *getPassName() const {
57 return "ARM Instruction Selection";
60 /// getI32Imm - Return a target constant with the specified value, of type i32.
61 inline SDValue getI32Imm(unsigned Imm) {
62 return CurDAG->getTargetConstant(Imm, MVT::i32);
65 SDNode *Select(SDValue Op);
66 virtual void InstructionSelect();
67 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
68 SDValue &B, SDValue &C);
69 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
70 SDValue &Offset, SDValue &Opc);
71 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
80 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
83 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
85 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
86 SDValue &Base, SDValue &OffImm,
88 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
89 SDValue &OffImm, SDValue &Offset);
90 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
91 SDValue &OffImm, SDValue &Offset);
92 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
93 SDValue &OffImm, SDValue &Offset);
94 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
97 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
98 SDValue &BaseReg, SDValue &Opc);
99 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
101 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
104 SDValue &OffReg, SDValue &ShImm);
107 // Include the pieces autogenerated from the target description.
108 #include "ARMGenDAGISel.inc"
111 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
112 /// inline asm expressions.
113 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
115 std::vector<SDValue> &OutOps);
119 void ARMDAGToDAGISel::InstructionSelect() {
123 CurDAG->RemoveDeadNodes();
126 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
131 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
133 // Don't match base register only case. That is matched to a separate
134 // lower complexity pattern with explicit register operand.
135 if (ShOpcVal == ARM_AM::no_shift) return false;
137 BaseReg = N.getOperand(0);
138 unsigned ShImmVal = 0;
139 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
140 ShReg = CurDAG->getRegister(0, MVT::i32);
141 ShImmVal = RHS->getZExtValue() & 31;
143 ShReg = N.getOperand(1);
145 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
150 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
151 SDValue &Base, SDValue &Offset,
153 if (N.getOpcode() == ISD::MUL) {
154 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
155 // X * [3,5,9] -> X + X * [2,4,8] etc.
156 int RHSC = (int)RHS->getZExtValue();
159 ARM_AM::AddrOpc AddSub = ARM_AM::add;
161 AddSub = ARM_AM::sub;
164 if (isPowerOf2_32(RHSC)) {
165 unsigned ShAmt = Log2_32(RHSC);
166 Base = Offset = N.getOperand(0);
167 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
176 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
178 if (N.getOpcode() == ISD::FrameIndex) {
179 int FI = cast<FrameIndexSDNode>(N)->getIndex();
180 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
181 } else if (N.getOpcode() == ARMISD::Wrapper) {
182 Base = N.getOperand(0);
184 Offset = CurDAG->getRegister(0, MVT::i32);
185 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
191 // Match simple R +/- imm12 operands.
192 if (N.getOpcode() == ISD::ADD)
193 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
194 int RHSC = (int)RHS->getZExtValue();
195 if ((RHSC >= 0 && RHSC < 0x1000) ||
196 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
197 Base = N.getOperand(0);
198 if (Base.getOpcode() == ISD::FrameIndex) {
199 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
200 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
202 Offset = CurDAG->getRegister(0, MVT::i32);
204 ARM_AM::AddrOpc AddSub = ARM_AM::add;
206 AddSub = ARM_AM::sub;
209 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
216 // Otherwise this is R +/- [possibly shifted] R
217 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
218 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
221 Base = N.getOperand(0);
222 Offset = N.getOperand(1);
224 if (ShOpcVal != ARM_AM::no_shift) {
225 // Check to see if the RHS of the shift is a constant, if not, we can't fold
227 if (ConstantSDNode *Sh =
228 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
229 ShAmt = Sh->getZExtValue();
230 Offset = N.getOperand(1).getOperand(0);
232 ShOpcVal = ARM_AM::no_shift;
236 // Try matching (R shl C) + (R).
237 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
238 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
239 if (ShOpcVal != ARM_AM::no_shift) {
240 // Check to see if the RHS of the shift is a constant, if not, we can't
242 if (ConstantSDNode *Sh =
243 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
244 ShAmt = Sh->getZExtValue();
245 Offset = N.getOperand(0).getOperand(0);
246 Base = N.getOperand(1);
248 ShOpcVal = ARM_AM::no_shift;
253 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
258 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
259 SDValue &Offset, SDValue &Opc) {
260 unsigned Opcode = Op.getOpcode();
261 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
262 ? cast<LoadSDNode>(Op)->getAddressingMode()
263 : cast<StoreSDNode>(Op)->getAddressingMode();
264 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
265 ? ARM_AM::add : ARM_AM::sub;
266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
267 int Val = (int)C->getZExtValue();
268 if (Val >= 0 && Val < 0x1000) { // 12 bits.
269 Offset = CurDAG->getRegister(0, MVT::i32);
270 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
278 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
280 if (ShOpcVal != ARM_AM::no_shift) {
281 // Check to see if the RHS of the shift is a constant, if not, we can't fold
283 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
284 ShAmt = Sh->getZExtValue();
285 Offset = N.getOperand(0);
287 ShOpcVal = ARM_AM::no_shift;
291 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
297 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
298 SDValue &Base, SDValue &Offset,
300 if (N.getOpcode() == ISD::SUB) {
301 // X - C is canonicalize to X + -C, no need to handle it here.
302 Base = N.getOperand(0);
303 Offset = N.getOperand(1);
304 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
308 if (N.getOpcode() != ISD::ADD) {
310 if (N.getOpcode() == ISD::FrameIndex) {
311 int FI = cast<FrameIndexSDNode>(N)->getIndex();
312 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
314 Offset = CurDAG->getRegister(0, MVT::i32);
315 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
319 // If the RHS is +/- imm8, fold into addr mode.
320 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
321 int RHSC = (int)RHS->getZExtValue();
322 if ((RHSC >= 0 && RHSC < 256) ||
323 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
324 Base = N.getOperand(0);
325 if (Base.getOpcode() == ISD::FrameIndex) {
326 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
327 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
329 Offset = CurDAG->getRegister(0, MVT::i32);
331 ARM_AM::AddrOpc AddSub = ARM_AM::add;
333 AddSub = ARM_AM::sub;
336 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
341 Base = N.getOperand(0);
342 Offset = N.getOperand(1);
343 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
347 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
348 SDValue &Offset, SDValue &Opc) {
349 unsigned Opcode = Op.getOpcode();
350 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
351 ? cast<LoadSDNode>(Op)->getAddressingMode()
352 : cast<StoreSDNode>(Op)->getAddressingMode();
353 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
354 ? ARM_AM::add : ARM_AM::sub;
355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
356 int Val = (int)C->getZExtValue();
357 if (Val >= 0 && Val < 256) {
358 Offset = CurDAG->getRegister(0, MVT::i32);
359 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
365 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
370 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
371 SDValue &Base, SDValue &Offset) {
372 if (N.getOpcode() != ISD::ADD) {
374 if (N.getOpcode() == ISD::FrameIndex) {
375 int FI = cast<FrameIndexSDNode>(N)->getIndex();
376 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
377 } else if (N.getOpcode() == ARMISD::Wrapper) {
378 Base = N.getOperand(0);
380 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
385 // If the RHS is +/- imm8, fold into addr mode.
386 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
387 int RHSC = (int)RHS->getZExtValue();
388 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
390 if ((RHSC >= 0 && RHSC < 256) ||
391 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
392 Base = N.getOperand(0);
393 if (Base.getOpcode() == ISD::FrameIndex) {
394 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
395 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
398 ARM_AM::AddrOpc AddSub = ARM_AM::add;
400 AddSub = ARM_AM::sub;
403 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
411 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
416 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
417 SDValue &Offset, SDValue &Label) {
418 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
419 Offset = N.getOperand(0);
420 SDValue N1 = N.getOperand(1);
421 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
428 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
429 SDValue &Base, SDValue &Offset){
430 // FIXME dl should come from the parent load or store, not the address
431 DebugLoc dl = Op.getDebugLoc();
432 if (N.getOpcode() != ISD::ADD) {
434 // We must materialize a zero in a reg! Returning a constant here
435 // wouldn't work without additional code to position the node within
436 // ISel's topological ordering in a place where ISel will process it
437 // normally. Instead, just explicitly issue a tMOVri8 node!
438 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32,
439 CurDAG->getTargetConstant(0, MVT::i32)), 0);
443 Base = N.getOperand(0);
444 Offset = N.getOperand(1);
449 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
450 unsigned Scale, SDValue &Base,
451 SDValue &OffImm, SDValue &Offset) {
453 SDValue TmpBase, TmpOffImm;
454 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
455 return false; // We want to select tLDRspi / tSTRspi instead.
456 if (N.getOpcode() == ARMISD::Wrapper &&
457 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
458 return false; // We want to select tLDRpci instead.
461 if (N.getOpcode() != ISD::ADD) {
462 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
463 Offset = CurDAG->getRegister(0, MVT::i32);
464 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
468 // Thumb does not have [sp, r] address mode.
469 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
470 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
471 if ((LHSR && LHSR->getReg() == ARM::SP) ||
472 (RHSR && RHSR->getReg() == ARM::SP)) {
474 Offset = CurDAG->getRegister(0, MVT::i32);
475 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
479 // If the RHS is + imm5 * scale, fold into addr mode.
480 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
481 int RHSC = (int)RHS->getZExtValue();
482 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
484 if (RHSC >= 0 && RHSC < 32) {
485 Base = N.getOperand(0);
486 Offset = CurDAG->getRegister(0, MVT::i32);
487 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
493 Base = N.getOperand(0);
494 Offset = N.getOperand(1);
495 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
499 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
500 SDValue &Base, SDValue &OffImm,
502 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
505 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
506 SDValue &Base, SDValue &OffImm,
508 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
511 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
512 SDValue &Base, SDValue &OffImm,
514 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
517 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
518 SDValue &Base, SDValue &OffImm) {
519 if (N.getOpcode() == ISD::FrameIndex) {
520 int FI = cast<FrameIndexSDNode>(N)->getIndex();
521 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
522 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
526 if (N.getOpcode() != ISD::ADD)
529 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
530 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
531 (LHSR && LHSR->getReg() == ARM::SP)) {
532 // If the RHS is + imm8 * scale, fold into addr mode.
533 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
534 int RHSC = (int)RHS->getZExtValue();
535 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
537 if (RHSC >= 0 && RHSC < 256) {
538 Base = N.getOperand(0);
539 if (Base.getOpcode() == ISD::FrameIndex) {
540 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
541 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
543 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
553 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
556 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
558 // Don't match base register only case. That is matched to a separate
559 // lower complexity pattern with explicit register operand.
560 if (ShOpcVal == ARM_AM::no_shift) return false;
562 BaseReg = N.getOperand(0);
563 unsigned ShImmVal = 0;
564 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
565 ShImmVal = RHS->getZExtValue() & 31;
566 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
573 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
574 SDValue &Base, SDValue &OffImm) {
575 // Match simple R + imm12 operands.
576 if (N.getOpcode() != ISD::ADD)
579 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
580 int RHSC = (int)RHS->getZExtValue();
581 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
582 Base = N.getOperand(0);
583 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
591 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
592 SDValue &Base, SDValue &OffImm) {
593 if (N.getOpcode() == ISD::ADD) {
594 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
595 int RHSC = (int)RHS->getZExtValue();
596 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
597 Base = N.getOperand(0);
598 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
602 } else if (N.getOpcode() == ISD::SUB) {
603 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
604 int RHSC = (int)RHS->getZExtValue();
605 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
606 Base = N.getOperand(0);
607 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
616 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
618 SDValue &OffReg, SDValue &ShImm) {
620 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
622 if (N.getOpcode() == ISD::FrameIndex) {
623 int FI = cast<FrameIndexSDNode>(N)->getIndex();
624 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
625 } else if (N.getOpcode() == ARMISD::Wrapper) {
626 Base = N.getOperand(0);
627 if (Base.getOpcode() == ISD::TargetConstantPool)
628 return false; // We want to select t2LDRpci instead.
630 OffReg = CurDAG->getRegister(0, MVT::i32);
631 ShImm = CurDAG->getTargetConstant(0, MVT::i32);
635 // Look for (R + R) or (R + (R << [1,2,3])).
637 Base = N.getOperand(0);
638 OffReg = N.getOperand(1);
640 // Swap if it is ((R << c) + R).
641 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
642 if (ShOpcVal != ARM_AM::lsl) {
643 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
644 if (ShOpcVal == ARM_AM::lsl)
645 std::swap(Base, OffReg);
648 if (ShOpcVal == ARM_AM::lsl) {
649 // Check to see if the RHS of the shift is a constant, if not, we can't fold
651 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
652 ShAmt = Sh->getZExtValue();
655 ShOpcVal = ARM_AM::no_shift;
657 OffReg = OffReg.getOperand(0);
659 ShOpcVal = ARM_AM::no_shift;
661 } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
662 SelectT2AddrModeImm8 (Op, N, Base, ShImm))
663 // Don't match if it's possible to match to one of the r +/- imm cases.
666 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
671 //===--------------------------------------------------------------------===//
673 /// getAL - Returns a ARMCC::AL immediate node.
674 static inline SDValue getAL(SelectionDAG *CurDAG) {
675 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
679 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
680 SDNode *N = Op.getNode();
681 DebugLoc dl = N->getDebugLoc();
683 if (N->isMachineOpcode())
684 return NULL; // Already selected.
686 switch (N->getOpcode()) {
688 case ISD::Constant: {
689 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
691 if (Subtarget->isThumb()) {
692 if (Subtarget->hasThumb2())
693 // Thumb2 has the MOVT instruction, so all immediates can
694 // be done with MOV + MOVT, at worst.
697 UseCP = (Val > 255 && // MOV
698 ~Val > 255 && // MOV + MVN
699 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
701 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
702 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
703 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
706 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
710 if (Subtarget->isThumb())
711 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
712 CPIdx, CurDAG->getEntryNode());
716 CurDAG->getRegister(0, MVT::i32),
717 CurDAG->getTargetConstant(0, MVT::i32),
719 CurDAG->getRegister(0, MVT::i32),
720 CurDAG->getEntryNode()
722 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
725 ReplaceUses(Op, SDValue(ResNode, 0));
729 // Other cases are autogenerated.
732 case ISD::FrameIndex: {
733 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
734 int FI = cast<FrameIndexSDNode>(N)->getIndex();
735 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
736 if (Subtarget->isThumb()) {
737 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
738 CurDAG->getTargetConstant(0, MVT::i32));
740 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
741 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
742 CurDAG->getRegister(0, MVT::i32) };
743 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
747 if (!Subtarget->isThumb())
749 // Select add sp, c to tADDhirr.
750 SDValue N0 = Op.getOperand(0);
751 SDValue N1 = Op.getOperand(1);
752 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
753 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
754 if (LHSR && LHSR->getReg() == ARM::SP) {
756 std::swap(LHSR, RHSR);
758 if (RHSR && RHSR->getReg() == ARM::SP) {
759 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
760 Op.getValueType(), N0, N0), 0);
761 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
766 if (Subtarget->isThumb())
768 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
769 unsigned RHSV = C->getZExtValue();
771 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
772 SDValue V = Op.getOperand(0);
773 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
774 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
775 CurDAG->getTargetConstant(ShImm, MVT::i32),
776 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
777 CurDAG->getRegister(0, MVT::i32) };
778 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
780 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
781 SDValue V = Op.getOperand(0);
782 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
783 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
784 CurDAG->getTargetConstant(ShImm, MVT::i32),
785 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
786 CurDAG->getRegister(0, MVT::i32) };
787 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
792 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
793 Op.getOperand(0), getAL(CurDAG),
794 CurDAG->getRegister(0, MVT::i32));
795 case ISD::UMUL_LOHI: {
796 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
797 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
798 CurDAG->getRegister(0, MVT::i32) };
799 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
801 case ISD::SMUL_LOHI: {
802 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
803 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
804 CurDAG->getRegister(0, MVT::i32) };
805 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
808 LoadSDNode *LD = cast<LoadSDNode>(Op);
809 ISD::MemIndexedMode AM = LD->getAddressingMode();
810 MVT LoadedVT = LD->getMemoryVT();
811 if (AM != ISD::UNINDEXED) {
812 SDValue Offset, AMOpc;
813 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
816 if (LoadedVT == MVT::i32 &&
817 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
818 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
820 } else if (LoadedVT == MVT::i16 &&
821 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
823 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
824 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
825 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
826 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
827 if (LD->getExtensionType() == ISD::SEXTLOAD) {
828 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
830 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
833 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
835 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
841 SDValue Chain = LD->getChain();
842 SDValue Base = LD->getBasePtr();
843 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
844 CurDAG->getRegister(0, MVT::i32), Chain };
845 return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32,
849 // Other cases are autogenerated.
852 case ARMISD::BRCOND: {
853 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
854 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
855 // Pattern complexity = 6 cost = 1 size = 0
857 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
858 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
859 // Pattern complexity = 6 cost = 1 size = 0
861 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
862 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
863 // Pattern complexity = 6 cost = 1 size = 0
865 unsigned Opc = Subtarget->isThumb() ?
866 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
867 SDValue Chain = Op.getOperand(0);
868 SDValue N1 = Op.getOperand(1);
869 SDValue N2 = Op.getOperand(2);
870 SDValue N3 = Op.getOperand(3);
871 SDValue InFlag = Op.getOperand(4);
872 assert(N1.getOpcode() == ISD::BasicBlock);
873 assert(N2.getOpcode() == ISD::Constant);
874 assert(N3.getOpcode() == ISD::Register);
876 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
877 cast<ConstantSDNode>(N2)->getZExtValue()),
879 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
880 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
882 Chain = SDValue(ResNode, 0);
883 if (Op.getNode()->getNumValues() == 2) {
884 InFlag = SDValue(ResNode, 1);
885 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
887 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
891 bool isThumb = Subtarget->isThumb();
892 MVT VT = Op.getValueType();
893 SDValue N0 = Op.getOperand(0);
894 SDValue N1 = Op.getOperand(1);
895 SDValue N2 = Op.getOperand(2);
896 SDValue N3 = Op.getOperand(3);
897 SDValue InFlag = Op.getOperand(4);
898 assert(N2.getOpcode() == ISD::Constant);
899 assert(N3.getOpcode() == ISD::Register);
901 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
902 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
903 // Pattern complexity = 18 cost = 1 size = 0
907 if (!isThumb && VT == MVT::i32 &&
908 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
909 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
910 cast<ConstantSDNode>(N2)->getZExtValue()),
912 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
913 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
916 // Pattern: (ARMcmov:i32 GPR:i32:$false,
917 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
919 // Emits: (MOVCCi:i32 GPR:i32:$false,
920 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
921 // Pattern complexity = 10 cost = 1 size = 0
922 if (VT == MVT::i32 &&
923 N3.getOpcode() == ISD::Constant &&
924 Predicate_so_imm(N3.getNode())) {
925 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
926 cast<ConstantSDNode>(N1)->getZExtValue()),
928 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
929 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
930 cast<ConstantSDNode>(N2)->getZExtValue()),
932 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
933 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
936 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
937 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
938 // Pattern complexity = 6 cost = 1 size = 0
940 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
941 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
942 // Pattern complexity = 6 cost = 11 size = 0
944 // Also FCPYScc and FCPYDcc.
945 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
946 cast<ConstantSDNode>(N2)->getZExtValue()),
948 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
950 switch (VT.getSimpleVT()) {
951 default: assert(false && "Illegal conditional move type!");
954 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
963 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
966 MVT VT = Op.getValueType();
967 SDValue N0 = Op.getOperand(0);
968 SDValue N1 = Op.getOperand(1);
969 SDValue N2 = Op.getOperand(2);
970 SDValue N3 = Op.getOperand(3);
971 SDValue InFlag = Op.getOperand(4);
972 assert(N2.getOpcode() == ISD::Constant);
973 assert(N3.getOpcode() == ISD::Register);
975 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
976 cast<ConstantSDNode>(N2)->getZExtValue()),
978 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
980 switch (VT.getSimpleVT()) {
981 default: assert(false && "Illegal conditional move type!");
990 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
994 SDValue Chain = Op.getOperand(0);
995 SDValue N1 = Op.getOperand(1);
996 SDValue N2 = Op.getOperand(2);
997 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
998 // FIXME: handle VLAs.
1000 ReplaceUses(Op.getValue(0), Chain);
1003 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1004 N2 = N2.getOperand(0);
1005 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1007 ReplaceUses(Op.getValue(0), Chain);
1010 SDValue BasePtr = Ld->getBasePtr();
1011 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1012 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1013 "llvm.dbg.variable should be a constantpool node");
1014 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1015 GlobalValue *GV = 0;
1016 if (CP->isMachineConstantPoolEntry()) {
1017 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1020 GV = dyn_cast<GlobalValue>(CP->getConstVal());
1022 ReplaceUses(Op.getValue(0), Chain);
1026 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1027 TLI.getPointerTy());
1028 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1029 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1030 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1031 MVT::Other, Ops, 3);
1034 case ISD::CONCAT_VECTORS: {
1035 MVT VT = Op.getValueType();
1036 assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
1037 "unexpected CONCAT_VECTORS");
1038 SDValue N0 = Op.getOperand(0);
1039 SDValue N1 = Op.getOperand(1);
1041 CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
1042 if (N0.getOpcode() != ISD::UNDEF)
1043 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1044 SDValue(Result, 0), N0,
1045 CurDAG->getTargetConstant(arm_dsubreg_0,
1047 if (N1.getOpcode() != ISD::UNDEF)
1048 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1049 SDValue(Result, 0), N1,
1050 CurDAG->getTargetConstant(arm_dsubreg_1,
1055 case ISD::VECTOR_SHUFFLE: {
1056 MVT VT = Op.getValueType();
1058 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
1059 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1060 // transformed first into a lane number and then to both a subregister
1061 // index and an adjusted lane number.) If the source operand is a
1062 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1063 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1064 if (VT.is128BitVector() && SVOp->isSplat() &&
1065 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1066 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1067 unsigned LaneVal = SVOp->getSplatIndex();
1071 switch (VT.getVectorElementType().getSimpleVT()) {
1072 default: assert(false && "unhandled VDUP splat type");
1073 case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
1074 case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
1075 case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
1076 case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
1079 // The source operand needs to be changed to a subreg of the original
1080 // 128-bit operand, and the lane number needs to be adjusted accordingly.
1081 unsigned NumElts = VT.getVectorNumElements() / 2;
1082 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1083 SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
1084 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
1085 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1086 dl, HalfVT, N->getOperand(0), SR);
1087 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1094 return SelectCode(Op);
1097 bool ARMDAGToDAGISel::
1098 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1099 std::vector<SDValue> &OutOps) {
1100 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1102 SDValue Base, Offset, Opc;
1103 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1106 OutOps.push_back(Base);
1107 OutOps.push_back(Offset);
1108 OutOps.push_back(Opc);
1112 /// createARMISelDag - This pass converts a legalized DAG into a
1113 /// ARM-specific DAG, ready for instruction scheduling.
1115 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1116 return new ARMDAGToDAGISel(TM);