1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
49 class ARMDAGToDAGISel : public SelectionDAGISel {
50 ARMBaseTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const ARMSubtarget *Subtarget;
57 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
58 CodeGenOpt::Level OptLevel)
59 : SelectionDAGISel(tm, OptLevel), TM(tm),
60 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
63 virtual const char *getPassName() const {
64 return "ARM Instruction Selection";
67 /// getI32Imm - Return a target constant of type i32 with the specified
69 inline SDValue getI32Imm(unsigned Imm) {
70 return CurDAG->getTargetConstant(Imm, MVT::i32);
73 SDNode *Select(SDNode *N);
75 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
76 SDValue &B, SDValue &C);
77 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
80 SDValue &Offset, SDValue &Opc);
81 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
82 SDValue &Offset, SDValue &Opc);
83 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
84 SDValue &Offset, SDValue &Opc);
85 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
87 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
89 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align);
91 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
94 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
96 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
97 SDValue &Base, SDValue &OffImm,
99 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
100 SDValue &OffImm, SDValue &Offset);
101 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
102 SDValue &OffImm, SDValue &Offset);
103 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
104 SDValue &OffImm, SDValue &Offset);
105 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
108 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
109 SDValue &BaseReg, SDValue &Opc);
110 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
112 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
114 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
116 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
117 SDValue &OffReg, SDValue &ShImm);
119 inline bool Pred_so_imm(SDNode *inN) const {
120 ConstantSDNode *N = cast<ConstantSDNode>(inN);
121 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
124 inline bool Pred_t2_so_imm(SDNode *inN) const {
125 ConstantSDNode *N = cast<ConstantSDNode>(inN);
126 return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1;
129 // Include the pieces autogenerated from the target description.
130 #include "ARMGenDAGISel.inc"
133 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
135 SDNode *SelectARMIndexedLoad(SDNode *N);
136 SDNode *SelectT2IndexedLoad(SDNode *N);
138 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
139 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
140 /// loads of D registers and even subregs and odd subregs of Q registers.
141 /// For NumVecs <= 2, QOpcodes1 is not used.
142 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
143 unsigned *QOpcodes0, unsigned *QOpcodes1);
145 /// SelectVST - Select NEON store intrinsics. NumVecs should
146 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
147 /// stores of D registers and even subregs and odd subregs of Q registers.
148 /// For NumVecs <= 2, QOpcodes1 is not used.
149 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
150 unsigned *QOpcodes0, unsigned *QOpcodes1);
152 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
153 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
154 /// load/store of D registers and even subregs and odd subregs of Q registers.
155 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
156 unsigned *DOpcodes, unsigned *QOpcodes0,
157 unsigned *QOpcodes1);
159 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
160 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
161 /// generated to force the table registers to be consecutive.
162 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
164 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
165 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
167 /// SelectCMOVOp - Select CMOV instructions for ARM.
168 SDNode *SelectCMOVOp(SDNode *N);
169 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
170 ARMCC::CondCodes CCVal, SDValue CCR,
172 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
173 ARMCC::CondCodes CCVal, SDValue CCR,
175 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
176 ARMCC::CondCodes CCVal, SDValue CCR,
178 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
179 ARMCC::CondCodes CCVal, SDValue CCR,
182 SDNode *SelectConcatVector(SDNode *N);
184 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
185 /// inline asm expressions.
186 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
188 std::vector<SDValue> &OutOps);
190 // Form pairs of consecutive S, D, or Q registers.
191 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
192 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
193 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
195 // Form sequences of 4 consecutive S, D, or Q registers.
196 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
197 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
198 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
200 // Form sequences of 8 consecutive D registers.
201 SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3,
202 SDValue V4, SDValue V5, SDValue V6, SDValue V7);
206 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
207 /// operand. If so Imm will receive the 32-bit value.
208 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
209 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
210 Imm = cast<ConstantSDNode>(N)->getZExtValue();
216 // isInt32Immediate - This method tests to see if a constant operand.
217 // If so Imm will receive the 32 bit value.
218 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
219 return isInt32Immediate(N.getNode(), Imm);
222 // isOpcWithIntImmediate - This method tests to see if the node is a specific
223 // opcode and that it has a immediate integer right operand.
224 // If so Imm will receive the 32 bit value.
225 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
226 return N->getOpcode() == Opc &&
227 isInt32Immediate(N->getOperand(1).getNode(), Imm);
231 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
236 if (DisableShifterOp)
239 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
241 // Don't match base register only case. That is matched to a separate
242 // lower complexity pattern with explicit register operand.
243 if (ShOpcVal == ARM_AM::no_shift) return false;
245 BaseReg = N.getOperand(0);
246 unsigned ShImmVal = 0;
247 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
248 ShReg = CurDAG->getRegister(0, MVT::i32);
249 ShImmVal = RHS->getZExtValue() & 31;
251 ShReg = N.getOperand(1);
253 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
258 bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
259 SDValue &Base, SDValue &Offset,
261 if (N.getOpcode() == ISD::MUL) {
262 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
263 // X * [3,5,9] -> X + X * [2,4,8] etc.
264 int RHSC = (int)RHS->getZExtValue();
267 ARM_AM::AddrOpc AddSub = ARM_AM::add;
269 AddSub = ARM_AM::sub;
272 if (isPowerOf2_32(RHSC)) {
273 unsigned ShAmt = Log2_32(RHSC);
274 Base = Offset = N.getOperand(0);
275 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
284 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
286 if (N.getOpcode() == ISD::FrameIndex) {
287 int FI = cast<FrameIndexSDNode>(N)->getIndex();
288 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
289 } else if (N.getOpcode() == ARMISD::Wrapper &&
290 !(Subtarget->useMovt() &&
291 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
292 Base = N.getOperand(0);
294 Offset = CurDAG->getRegister(0, MVT::i32);
295 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
301 // Match simple R +/- imm12 operands.
302 if (N.getOpcode() == ISD::ADD)
303 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
304 int RHSC = (int)RHS->getZExtValue();
305 if ((RHSC >= 0 && RHSC < 0x1000) ||
306 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
307 Base = N.getOperand(0);
308 if (Base.getOpcode() == ISD::FrameIndex) {
309 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
310 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
312 Offset = CurDAG->getRegister(0, MVT::i32);
314 ARM_AM::AddrOpc AddSub = ARM_AM::add;
316 AddSub = ARM_AM::sub;
319 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
326 // Otherwise this is R +/- [possibly shifted] R.
327 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
328 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
331 Base = N.getOperand(0);
332 Offset = N.getOperand(1);
334 if (ShOpcVal != ARM_AM::no_shift) {
335 // Check to see if the RHS of the shift is a constant, if not, we can't fold
337 if (ConstantSDNode *Sh =
338 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
339 ShAmt = Sh->getZExtValue();
340 Offset = N.getOperand(1).getOperand(0);
342 ShOpcVal = ARM_AM::no_shift;
346 // Try matching (R shl C) + (R).
347 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
348 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
349 if (ShOpcVal != ARM_AM::no_shift) {
350 // Check to see if the RHS of the shift is a constant, if not, we can't
352 if (ConstantSDNode *Sh =
353 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
354 ShAmt = Sh->getZExtValue();
355 Offset = N.getOperand(0).getOperand(0);
356 Base = N.getOperand(1);
358 ShOpcVal = ARM_AM::no_shift;
363 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
368 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
369 SDValue &Offset, SDValue &Opc) {
370 unsigned Opcode = Op->getOpcode();
371 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
372 ? cast<LoadSDNode>(Op)->getAddressingMode()
373 : cast<StoreSDNode>(Op)->getAddressingMode();
374 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
375 ? ARM_AM::add : ARM_AM::sub;
376 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
377 int Val = (int)C->getZExtValue();
378 if (Val >= 0 && Val < 0x1000) { // 12 bits.
379 Offset = CurDAG->getRegister(0, MVT::i32);
380 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
388 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
390 if (ShOpcVal != ARM_AM::no_shift) {
391 // Check to see if the RHS of the shift is a constant, if not, we can't fold
393 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
394 ShAmt = Sh->getZExtValue();
395 Offset = N.getOperand(0);
397 ShOpcVal = ARM_AM::no_shift;
401 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
407 bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
408 SDValue &Base, SDValue &Offset,
410 if (N.getOpcode() == ISD::SUB) {
411 // X - C is canonicalize to X + -C, no need to handle it here.
412 Base = N.getOperand(0);
413 Offset = N.getOperand(1);
414 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
418 if (N.getOpcode() != ISD::ADD) {
420 if (N.getOpcode() == ISD::FrameIndex) {
421 int FI = cast<FrameIndexSDNode>(N)->getIndex();
422 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
424 Offset = CurDAG->getRegister(0, MVT::i32);
425 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
429 // If the RHS is +/- imm8, fold into addr mode.
430 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
431 int RHSC = (int)RHS->getZExtValue();
432 if ((RHSC >= 0 && RHSC < 256) ||
433 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
434 Base = N.getOperand(0);
435 if (Base.getOpcode() == ISD::FrameIndex) {
436 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
437 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
439 Offset = CurDAG->getRegister(0, MVT::i32);
441 ARM_AM::AddrOpc AddSub = ARM_AM::add;
443 AddSub = ARM_AM::sub;
446 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
451 Base = N.getOperand(0);
452 Offset = N.getOperand(1);
453 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
457 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
458 SDValue &Offset, SDValue &Opc) {
459 unsigned Opcode = Op->getOpcode();
460 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
461 ? cast<LoadSDNode>(Op)->getAddressingMode()
462 : cast<StoreSDNode>(Op)->getAddressingMode();
463 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
464 ? ARM_AM::add : ARM_AM::sub;
465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
466 int Val = (int)C->getZExtValue();
467 if (Val >= 0 && Val < 256) {
468 Offset = CurDAG->getRegister(0, MVT::i32);
469 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
475 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
479 bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
480 SDValue &Addr, SDValue &Mode) {
482 Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
486 bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
487 SDValue &Base, SDValue &Offset) {
488 if (N.getOpcode() != ISD::ADD) {
490 if (N.getOpcode() == ISD::FrameIndex) {
491 int FI = cast<FrameIndexSDNode>(N)->getIndex();
492 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
493 } else if (N.getOpcode() == ARMISD::Wrapper &&
494 !(Subtarget->useMovt() &&
495 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
496 Base = N.getOperand(0);
498 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
503 // If the RHS is +/- imm8, fold into addr mode.
504 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
505 int RHSC = (int)RHS->getZExtValue();
506 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
508 if ((RHSC >= 0 && RHSC < 256) ||
509 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
510 Base = N.getOperand(0);
511 if (Base.getOpcode() == ISD::FrameIndex) {
512 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
513 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
516 ARM_AM::AddrOpc AddSub = ARM_AM::add;
518 AddSub = ARM_AM::sub;
521 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
529 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
534 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
535 SDValue &Addr, SDValue &Align) {
537 // Default to no alignment.
538 Align = CurDAG->getTargetConstant(0, MVT::i32);
542 bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
543 SDValue &Offset, SDValue &Label) {
544 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
545 Offset = N.getOperand(0);
546 SDValue N1 = N.getOperand(1);
547 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
554 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
555 SDValue &Base, SDValue &Offset){
556 // FIXME dl should come from the parent load or store, not the address
557 if (N.getOpcode() != ISD::ADD) {
558 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
559 if (!NC || !NC->isNullValue())
566 Base = N.getOperand(0);
567 Offset = N.getOperand(1);
572 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
573 unsigned Scale, SDValue &Base,
574 SDValue &OffImm, SDValue &Offset) {
576 SDValue TmpBase, TmpOffImm;
577 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
578 return false; // We want to select tLDRspi / tSTRspi instead.
579 if (N.getOpcode() == ARMISD::Wrapper &&
580 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
581 return false; // We want to select tLDRpci instead.
584 if (N.getOpcode() != ISD::ADD) {
585 if (N.getOpcode() == ARMISD::Wrapper &&
586 !(Subtarget->useMovt() &&
587 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
588 Base = N.getOperand(0);
592 Offset = CurDAG->getRegister(0, MVT::i32);
593 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
597 // Thumb does not have [sp, r] address mode.
598 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
599 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
600 if ((LHSR && LHSR->getReg() == ARM::SP) ||
601 (RHSR && RHSR->getReg() == ARM::SP)) {
603 Offset = CurDAG->getRegister(0, MVT::i32);
604 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
608 // If the RHS is + imm5 * scale, fold into addr mode.
609 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
610 int RHSC = (int)RHS->getZExtValue();
611 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
613 if (RHSC >= 0 && RHSC < 32) {
614 Base = N.getOperand(0);
615 Offset = CurDAG->getRegister(0, MVT::i32);
616 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
622 Base = N.getOperand(0);
623 Offset = N.getOperand(1);
624 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
628 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
629 SDValue &Base, SDValue &OffImm,
631 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
634 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
635 SDValue &Base, SDValue &OffImm,
637 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
640 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
641 SDValue &Base, SDValue &OffImm,
643 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
646 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
647 SDValue &Base, SDValue &OffImm) {
648 if (N.getOpcode() == ISD::FrameIndex) {
649 int FI = cast<FrameIndexSDNode>(N)->getIndex();
650 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
651 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
655 if (N.getOpcode() != ISD::ADD)
658 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
659 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
660 (LHSR && LHSR->getReg() == ARM::SP)) {
661 // If the RHS is + imm8 * scale, fold into addr mode.
662 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
663 int RHSC = (int)RHS->getZExtValue();
664 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
666 if (RHSC >= 0 && RHSC < 256) {
667 Base = N.getOperand(0);
668 if (Base.getOpcode() == ISD::FrameIndex) {
669 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
670 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
672 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
682 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
685 if (DisableShifterOp)
688 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
690 // Don't match base register only case. That is matched to a separate
691 // lower complexity pattern with explicit register operand.
692 if (ShOpcVal == ARM_AM::no_shift) return false;
694 BaseReg = N.getOperand(0);
695 unsigned ShImmVal = 0;
696 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
697 ShImmVal = RHS->getZExtValue() & 31;
698 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
705 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
706 SDValue &Base, SDValue &OffImm) {
707 // Match simple R + imm12 operands.
710 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
711 if (N.getOpcode() == ISD::FrameIndex) {
712 // Match frame index...
713 int FI = cast<FrameIndexSDNode>(N)->getIndex();
714 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
715 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
717 } else if (N.getOpcode() == ARMISD::Wrapper &&
718 !(Subtarget->useMovt() &&
719 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
720 Base = N.getOperand(0);
721 if (Base.getOpcode() == ISD::TargetConstantPool)
722 return false; // We want to select t2LDRpci instead.
725 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
729 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
730 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
731 // Let t2LDRi8 handle (R - imm8).
734 int RHSC = (int)RHS->getZExtValue();
735 if (N.getOpcode() == ISD::SUB)
738 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
739 Base = N.getOperand(0);
740 if (Base.getOpcode() == ISD::FrameIndex) {
741 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
742 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
744 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
751 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
755 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
756 SDValue &Base, SDValue &OffImm) {
757 // Match simple R - imm8 operands.
758 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
759 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
760 int RHSC = (int)RHS->getSExtValue();
761 if (N.getOpcode() == ISD::SUB)
764 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
765 Base = N.getOperand(0);
766 if (Base.getOpcode() == ISD::FrameIndex) {
767 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
768 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
770 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
779 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
781 unsigned Opcode = Op->getOpcode();
782 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
783 ? cast<LoadSDNode>(Op)->getAddressingMode()
784 : cast<StoreSDNode>(Op)->getAddressingMode();
785 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
786 int RHSC = (int)RHS->getZExtValue();
787 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
788 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
789 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
790 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
798 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
800 SDValue &OffReg, SDValue &ShImm) {
801 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
802 if (N.getOpcode() != ISD::ADD)
805 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
806 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
807 int RHSC = (int)RHS->getZExtValue();
808 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
810 else if (RHSC < 0 && RHSC >= -255) // 8 bits
814 // Look for (R + R) or (R + (R << [1,2,3])).
816 Base = N.getOperand(0);
817 OffReg = N.getOperand(1);
819 // Swap if it is ((R << c) + R).
820 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
821 if (ShOpcVal != ARM_AM::lsl) {
822 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
823 if (ShOpcVal == ARM_AM::lsl)
824 std::swap(Base, OffReg);
827 if (ShOpcVal == ARM_AM::lsl) {
828 // Check to see if the RHS of the shift is a constant, if not, we can't fold
830 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
831 ShAmt = Sh->getZExtValue();
834 ShOpcVal = ARM_AM::no_shift;
836 OffReg = OffReg.getOperand(0);
838 ShOpcVal = ARM_AM::no_shift;
842 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
847 //===--------------------------------------------------------------------===//
849 /// getAL - Returns a ARMCC::AL immediate node.
850 static inline SDValue getAL(SelectionDAG *CurDAG) {
851 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
854 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
855 LoadSDNode *LD = cast<LoadSDNode>(N);
856 ISD::MemIndexedMode AM = LD->getAddressingMode();
857 if (AM == ISD::UNINDEXED)
860 EVT LoadedVT = LD->getMemoryVT();
861 SDValue Offset, AMOpc;
862 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
865 if (LoadedVT == MVT::i32 &&
866 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
867 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
869 } else if (LoadedVT == MVT::i16 &&
870 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
872 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
873 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
874 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
875 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
876 if (LD->getExtensionType() == ISD::SEXTLOAD) {
877 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
879 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
882 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
884 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
890 SDValue Chain = LD->getChain();
891 SDValue Base = LD->getBasePtr();
892 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
893 CurDAG->getRegister(0, MVT::i32), Chain };
894 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
901 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
902 LoadSDNode *LD = cast<LoadSDNode>(N);
903 ISD::MemIndexedMode AM = LD->getAddressingMode();
904 if (AM == ISD::UNINDEXED)
907 EVT LoadedVT = LD->getMemoryVT();
908 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
910 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
913 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
914 switch (LoadedVT.getSimpleVT().SimpleTy) {
916 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
920 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
922 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
927 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
929 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
938 SDValue Chain = LD->getChain();
939 SDValue Base = LD->getBasePtr();
940 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
941 CurDAG->getRegister(0, MVT::i32), Chain };
942 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
949 /// PairSRegs - Form a D register from a pair of S registers.
951 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
952 DebugLoc dl = V0.getNode()->getDebugLoc();
953 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
954 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
955 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
956 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
959 /// PairDRegs - Form a quad register from a pair of D registers.
961 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
962 DebugLoc dl = V0.getNode()->getDebugLoc();
963 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
964 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
965 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
966 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
969 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
971 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
972 DebugLoc dl = V0.getNode()->getDebugLoc();
973 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
974 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
975 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
976 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
979 /// QuadSRegs - Form 4 consecutive S registers.
981 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
982 SDValue V2, SDValue V3) {
983 DebugLoc dl = V0.getNode()->getDebugLoc();
984 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
985 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
986 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
987 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
988 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
989 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
992 /// QuadDRegs - Form 4 consecutive D registers.
994 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
995 SDValue V2, SDValue V3) {
996 DebugLoc dl = V0.getNode()->getDebugLoc();
997 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
998 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
999 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1000 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1001 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1002 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1005 /// QuadQRegs - Form 4 consecutive Q registers.
1007 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1008 SDValue V2, SDValue V3) {
1009 DebugLoc dl = V0.getNode()->getDebugLoc();
1010 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1011 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1012 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1013 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1014 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1015 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1018 /// OctoDRegs - Form 8 consecutive D registers.
1020 SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1,
1021 SDValue V2, SDValue V3,
1022 SDValue V4, SDValue V5,
1023 SDValue V6, SDValue V7) {
1024 DebugLoc dl = V0.getNode()->getDebugLoc();
1025 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1026 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1027 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1028 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1029 SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32);
1030 SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32);
1031 SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32);
1032 SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32);
1033 const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3,
1034 V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 };
1035 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16);
1038 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1039 /// for a 64-bit subregister of the vector.
1040 static EVT GetNEONSubregVT(EVT VT) {
1041 switch (VT.getSimpleVT().SimpleTy) {
1042 default: llvm_unreachable("unhandled NEON type");
1043 case MVT::v16i8: return MVT::v8i8;
1044 case MVT::v8i16: return MVT::v4i16;
1045 case MVT::v4f32: return MVT::v2f32;
1046 case MVT::v4i32: return MVT::v2i32;
1047 case MVT::v2i64: return MVT::v1i64;
1051 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1052 unsigned *DOpcodes, unsigned *QOpcodes0,
1053 unsigned *QOpcodes1) {
1054 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1055 DebugLoc dl = N->getDebugLoc();
1057 SDValue MemAddr, Align;
1058 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1061 SDValue Chain = N->getOperand(0);
1062 EVT VT = N->getValueType(0);
1063 bool is64BitVector = VT.is64BitVector();
1065 unsigned OpcodeIndex;
1066 switch (VT.getSimpleVT().SimpleTy) {
1067 default: llvm_unreachable("unhandled vld type");
1068 // Double-register operations:
1069 case MVT::v8i8: OpcodeIndex = 0; break;
1070 case MVT::v4i16: OpcodeIndex = 1; break;
1072 case MVT::v2i32: OpcodeIndex = 2; break;
1073 case MVT::v1i64: OpcodeIndex = 3; break;
1074 // Quad-register operations:
1075 case MVT::v16i8: OpcodeIndex = 0; break;
1076 case MVT::v8i16: OpcodeIndex = 1; break;
1078 case MVT::v4i32: OpcodeIndex = 2; break;
1079 case MVT::v2i64: OpcodeIndex = 3;
1080 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1088 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1091 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1094 SDValue Pred = getAL(CurDAG);
1095 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1097 if (is64BitVector) {
1098 unsigned Opc = DOpcodes[OpcodeIndex];
1099 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1100 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1104 SuperReg = SDValue(VLd, 0);
1105 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1106 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1107 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1109 ReplaceUses(SDValue(N, Vec), D);
1111 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1116 // Quad registers are directly supported for VLD1 and VLD2,
1117 // loading pairs of D regs.
1118 unsigned Opc = QOpcodes0[OpcodeIndex];
1119 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1120 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1124 SuperReg = SDValue(VLd, 0);
1125 Chain = SDValue(VLd, 1);
1128 // Otherwise, quad registers are loaded with two separate instructions,
1129 // where one loads the even registers and the other loads the odd registers.
1130 EVT AddrTy = MemAddr.getValueType();
1132 // Load the even subregs.
1133 unsigned Opc = QOpcodes0[OpcodeIndex];
1135 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1136 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1138 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1139 Chain = SDValue(VLdA, 2);
1141 // Load the odd subregs.
1142 Opc = QOpcodes1[OpcodeIndex];
1143 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1144 Pred, Reg0, Chain };
1146 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1147 SuperReg = SDValue(VLdB, 0);
1148 Chain = SDValue(VLdB, 2);
1151 // Extract out the Q registers.
1152 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1153 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1154 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1156 ReplaceUses(SDValue(N, Vec), Q);
1158 ReplaceUses(SDValue(N, NumVecs), Chain);
1162 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1163 unsigned *DOpcodes, unsigned *QOpcodes0,
1164 unsigned *QOpcodes1) {
1165 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1166 DebugLoc dl = N->getDebugLoc();
1168 SDValue MemAddr, Align;
1169 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1172 SDValue Chain = N->getOperand(0);
1173 EVT VT = N->getOperand(3).getValueType();
1174 bool is64BitVector = VT.is64BitVector();
1176 unsigned OpcodeIndex;
1177 switch (VT.getSimpleVT().SimpleTy) {
1178 default: llvm_unreachable("unhandled vst type");
1179 // Double-register operations:
1180 case MVT::v8i8: OpcodeIndex = 0; break;
1181 case MVT::v4i16: OpcodeIndex = 1; break;
1183 case MVT::v2i32: OpcodeIndex = 2; break;
1184 case MVT::v1i64: OpcodeIndex = 3; break;
1185 // Quad-register operations:
1186 case MVT::v16i8: OpcodeIndex = 0; break;
1187 case MVT::v8i16: OpcodeIndex = 1; break;
1189 case MVT::v4i32: OpcodeIndex = 2; break;
1190 case MVT::v2i64: OpcodeIndex = 3;
1191 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1195 SDValue Pred = getAL(CurDAG);
1196 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1198 SmallVector<SDValue, 7> Ops;
1199 Ops.push_back(MemAddr);
1200 Ops.push_back(Align);
1202 if (is64BitVector) {
1204 Ops.push_back(N->getOperand(3));
1207 SDValue V0 = N->getOperand(0+3);
1208 SDValue V1 = N->getOperand(1+3);
1210 // Form a REG_SEQUENCE to force register allocation.
1212 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1214 SDValue V2 = N->getOperand(2+3);
1215 // If it's a vld3, form a quad D-register and leave the last part as
1217 SDValue V3 = (NumVecs == 3)
1218 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1219 : N->getOperand(3+3);
1220 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1222 Ops.push_back(RegSeq);
1224 Ops.push_back(Pred);
1225 Ops.push_back(Reg0); // predicate register
1226 Ops.push_back(Chain);
1227 unsigned Opc = DOpcodes[OpcodeIndex];
1228 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1232 // Quad registers are directly supported for VST1 and VST2.
1233 unsigned Opc = QOpcodes0[OpcodeIndex];
1235 Ops.push_back(N->getOperand(3));
1237 // Form a QQ register.
1238 SDValue Q0 = N->getOperand(3);
1239 SDValue Q1 = N->getOperand(4);
1240 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1242 Ops.push_back(Pred);
1243 Ops.push_back(Reg0); // predicate register
1244 Ops.push_back(Chain);
1245 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1248 // Otherwise, quad registers are stored with two separate instructions,
1249 // where one stores the even registers and the other stores the odd registers.
1251 // Form the QQQQ REG_SEQUENCE.
1252 SDValue V0 = N->getOperand(0+3);
1253 SDValue V1 = N->getOperand(1+3);
1254 SDValue V2 = N->getOperand(2+3);
1255 SDValue V3 = (NumVecs == 3)
1256 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1257 : N->getOperand(3+3);
1258 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1260 // Store the even D registers.
1261 Ops.push_back(Reg0); // post-access address offset
1262 Ops.push_back(RegSeq);
1263 Ops.push_back(Pred);
1264 Ops.push_back(Reg0); // predicate register
1265 Ops.push_back(Chain);
1266 unsigned Opc = QOpcodes0[OpcodeIndex];
1267 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1268 MVT::Other, Ops.data(), 7);
1269 Chain = SDValue(VStA, 1);
1271 // Store the odd D registers.
1272 Ops[0] = SDValue(VStA, 0); // MemAddr
1274 Opc = QOpcodes1[OpcodeIndex];
1275 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1276 MVT::Other, Ops.data(), 7);
1277 Chain = SDValue(VStB, 1);
1278 ReplaceUses(SDValue(N, 0), Chain);
1282 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1283 unsigned NumVecs, unsigned *DOpcodes,
1284 unsigned *QOpcodes0,
1285 unsigned *QOpcodes1) {
1286 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1287 DebugLoc dl = N->getDebugLoc();
1289 SDValue MemAddr, Align;
1290 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1293 SDValue Chain = N->getOperand(0);
1295 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1296 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1297 bool is64BitVector = VT.is64BitVector();
1299 // Quad registers are handled by load/store of subregs. Find the subreg info.
1300 unsigned NumElts = 0;
1303 if (!is64BitVector) {
1304 RegVT = GetNEONSubregVT(VT);
1305 NumElts = RegVT.getVectorNumElements();
1306 Even = Lane < NumElts;
1309 unsigned OpcodeIndex;
1310 switch (VT.getSimpleVT().SimpleTy) {
1311 default: llvm_unreachable("unhandled vld/vst lane type");
1312 // Double-register operations:
1313 case MVT::v8i8: OpcodeIndex = 0; break;
1314 case MVT::v4i16: OpcodeIndex = 1; break;
1316 case MVT::v2i32: OpcodeIndex = 2; break;
1317 // Quad-register operations:
1318 case MVT::v8i16: OpcodeIndex = 0; break;
1320 case MVT::v4i32: OpcodeIndex = 1; break;
1323 SDValue Pred = getAL(CurDAG);
1324 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1326 SmallVector<SDValue, 10> Ops;
1327 Ops.push_back(MemAddr);
1328 Ops.push_back(Align);
1331 if (is64BitVector) {
1332 Opc = DOpcodes[OpcodeIndex];
1334 SDValue V0 = N->getOperand(0+3);
1335 SDValue V1 = N->getOperand(1+3);
1337 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1339 SDValue V2 = N->getOperand(2+3);
1340 SDValue V3 = (NumVecs == 3)
1341 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1342 : N->getOperand(3+3);
1343 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1346 // Now extract the D registers back out.
1347 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
1348 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
1350 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq));
1352 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq));
1354 // Check if this is loading the even or odd subreg of a Q register.
1355 if (Lane < NumElts) {
1356 Opc = QOpcodes0[OpcodeIndex];
1359 Opc = QOpcodes1[OpcodeIndex];
1363 SDValue V0 = N->getOperand(0+3);
1364 SDValue V1 = N->getOperand(1+3);
1366 RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1368 SDValue V2 = N->getOperand(2+3);
1369 SDValue V3 = (NumVecs == 3)
1370 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1371 : N->getOperand(3+3);
1372 RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1375 // Extract the subregs of the input vector.
1376 unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1;
1377 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1378 Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT,
1381 Ops.push_back(getI32Imm(Lane));
1382 Ops.push_back(Pred);
1383 Ops.push_back(Reg0);
1384 Ops.push_back(Chain);
1387 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6);
1389 std::vector<EVT> ResTys(NumVecs, RegVT);
1390 ResTys.push_back(MVT::Other);
1391 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6);
1393 // Form a REG_SEQUENCE to force register allocation.
1395 if (is64BitVector) {
1396 SDValue V0 = SDValue(VLdLn, 0);
1397 SDValue V1 = SDValue(VLdLn, 1);
1399 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1401 SDValue V2 = SDValue(VLdLn, 2);
1402 // If it's a vld3, form a quad D-register but discard the last part.
1403 SDValue V3 = (NumVecs == 3)
1404 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1405 : SDValue(VLdLn, 3);
1406 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1409 // For 128-bit vectors, take the 64-bit results of the load and insert
1410 // them as subregs into the result.
1412 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
1414 V[i] = SDValue(VLdLn, Vec);
1415 V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1418 V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1420 V[i+1] = SDValue(VLdLn, Vec);
1424 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1428 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0);
1430 RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3],
1431 V[4], V[5], V[6], V[7]), 0);
1434 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1435 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1436 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1437 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1438 ReplaceUses(SDValue(N, Vec),
1439 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq));
1440 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs));
1444 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1446 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1447 DebugLoc dl = N->getDebugLoc();
1448 EVT VT = N->getValueType(0);
1449 unsigned FirstTblReg = IsExt ? 2 : 1;
1451 // Form a REG_SEQUENCE to force register allocation.
1453 SDValue V0 = N->getOperand(FirstTblReg + 0);
1454 SDValue V1 = N->getOperand(FirstTblReg + 1);
1456 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1458 SDValue V2 = N->getOperand(FirstTblReg + 2);
1459 // If it's a vtbl3, form a quad D-register and leave the last part as
1461 SDValue V3 = (NumVecs == 3)
1462 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1463 : N->getOperand(FirstTblReg + 3);
1464 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1467 // Now extract the D registers back out.
1468 SmallVector<SDValue, 6> Ops;
1470 Ops.push_back(N->getOperand(1));
1471 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
1472 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
1474 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq));
1476 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq));
1478 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1479 Ops.push_back(getAL(CurDAG)); // predicate
1480 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1481 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1484 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1486 if (!Subtarget->hasV6T2Ops())
1489 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1490 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1493 // For unsigned extracts, check for a shift right and mask
1494 unsigned And_imm = 0;
1495 if (N->getOpcode() == ISD::AND) {
1496 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1498 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1499 if (And_imm & (And_imm + 1))
1502 unsigned Srl_imm = 0;
1503 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1505 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1507 unsigned Width = CountTrailingOnes_32(And_imm);
1508 unsigned LSB = Srl_imm;
1509 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1510 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1511 CurDAG->getTargetConstant(LSB, MVT::i32),
1512 CurDAG->getTargetConstant(Width, MVT::i32),
1513 getAL(CurDAG), Reg0 };
1514 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1520 // Otherwise, we're looking for a shift of a shift
1521 unsigned Shl_imm = 0;
1522 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1523 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1524 unsigned Srl_imm = 0;
1525 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1526 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1527 unsigned Width = 32 - Srl_imm;
1528 int LSB = Srl_imm - Shl_imm;
1531 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1532 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1533 CurDAG->getTargetConstant(LSB, MVT::i32),
1534 CurDAG->getTargetConstant(Width, MVT::i32),
1535 getAL(CurDAG), Reg0 };
1536 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1542 SDNode *ARMDAGToDAGISel::
1543 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1544 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1547 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
1548 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1549 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1552 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1553 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1554 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1555 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1557 llvm_unreachable("Unknown so_reg opcode!");
1561 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1562 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1563 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1564 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1569 SDNode *ARMDAGToDAGISel::
1570 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1571 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1575 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1576 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1577 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1578 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1583 SDNode *ARMDAGToDAGISel::
1584 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1585 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1586 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1590 if (Pred_t2_so_imm(TrueVal.getNode())) {
1591 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1592 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1593 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1594 return CurDAG->SelectNodeTo(N,
1595 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1600 SDNode *ARMDAGToDAGISel::
1601 SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1602 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1603 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1607 if (Pred_so_imm(TrueVal.getNode())) {
1608 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1609 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1610 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1611 return CurDAG->SelectNodeTo(N,
1612 ARM::MOVCCi, MVT::i32, Ops, 5);
1617 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1618 EVT VT = N->getValueType(0);
1619 SDValue FalseVal = N->getOperand(0);
1620 SDValue TrueVal = N->getOperand(1);
1621 SDValue CC = N->getOperand(2);
1622 SDValue CCR = N->getOperand(3);
1623 SDValue InFlag = N->getOperand(4);
1624 assert(CC.getOpcode() == ISD::Constant);
1625 assert(CCR.getOpcode() == ISD::Register);
1626 ARMCC::CondCodes CCVal =
1627 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1629 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1630 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1631 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1632 // Pattern complexity = 18 cost = 1 size = 0
1636 if (Subtarget->isThumb()) {
1637 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1638 CCVal, CCR, InFlag);
1640 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1641 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1645 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1646 CCVal, CCR, InFlag);
1648 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1649 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1654 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1655 // (imm:i32)<<P:Pred_so_imm>>:$true,
1657 // Emits: (MOVCCi:i32 GPR:i32:$false,
1658 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1659 // Pattern complexity = 10 cost = 1 size = 0
1660 if (Subtarget->isThumb()) {
1661 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
1662 CCVal, CCR, InFlag);
1664 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
1665 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1669 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
1670 CCVal, CCR, InFlag);
1672 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
1673 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1679 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1680 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1681 // Pattern complexity = 6 cost = 1 size = 0
1683 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1684 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1685 // Pattern complexity = 6 cost = 11 size = 0
1687 // Also FCPYScc and FCPYDcc.
1688 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1689 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1691 switch (VT.getSimpleVT().SimpleTy) {
1692 default: assert(false && "Illegal conditional move type!");
1695 Opc = Subtarget->isThumb()
1696 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1706 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1709 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1710 // The only time a CONCAT_VECTORS operation can have legal types is when
1711 // two 64-bit vectors are concatenated to a 128-bit vector.
1712 EVT VT = N->getValueType(0);
1713 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1714 llvm_unreachable("unexpected CONCAT_VECTORS");
1715 DebugLoc dl = N->getDebugLoc();
1716 SDValue V0 = N->getOperand(0);
1717 SDValue V1 = N->getOperand(1);
1718 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1719 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1720 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1721 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1724 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1725 DebugLoc dl = N->getDebugLoc();
1727 if (N->isMachineOpcode())
1728 return NULL; // Already selected.
1730 switch (N->getOpcode()) {
1732 case ISD::Constant: {
1733 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1735 if (Subtarget->hasThumb2())
1736 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1737 // be done with MOV + MOVT, at worst.
1740 if (Subtarget->isThumb()) {
1741 UseCP = (Val > 255 && // MOV
1742 ~Val > 255 && // MOV + MVN
1743 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1745 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1746 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1747 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1752 CurDAG->getTargetConstantPool(ConstantInt::get(
1753 Type::getInt32Ty(*CurDAG->getContext()), Val),
1754 TLI.getPointerTy());
1757 if (Subtarget->isThumb1Only()) {
1758 SDValue Pred = getAL(CurDAG);
1759 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1760 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1761 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1766 CurDAG->getRegister(0, MVT::i32),
1767 CurDAG->getTargetConstant(0, MVT::i32),
1769 CurDAG->getRegister(0, MVT::i32),
1770 CurDAG->getEntryNode()
1772 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1775 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1779 // Other cases are autogenerated.
1782 case ISD::FrameIndex: {
1783 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1784 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1785 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1786 if (Subtarget->isThumb1Only()) {
1787 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1788 CurDAG->getTargetConstant(0, MVT::i32));
1790 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1791 ARM::t2ADDri : ARM::ADDri);
1792 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1793 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1794 CurDAG->getRegister(0, MVT::i32) };
1795 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1799 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1803 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1807 if (Subtarget->isThumb1Only())
1809 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1810 unsigned RHSV = C->getZExtValue();
1812 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1813 unsigned ShImm = Log2_32(RHSV-1);
1816 SDValue V = N->getOperand(0);
1817 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1818 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1819 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1820 if (Subtarget->isThumb()) {
1821 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1822 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1824 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1825 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1828 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1829 unsigned ShImm = Log2_32(RHSV+1);
1832 SDValue V = N->getOperand(0);
1833 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1834 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1835 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1836 if (Subtarget->isThumb()) {
1837 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1838 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
1840 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1841 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1847 // Check for unsigned bitfield extract
1848 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1851 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1852 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1853 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1854 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1855 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1856 EVT VT = N->getValueType(0);
1859 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1861 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1864 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1865 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1868 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1869 SDValue N2 = N0.getOperand(1);
1870 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1873 unsigned N1CVal = N1C->getZExtValue();
1874 unsigned N2CVal = N2C->getZExtValue();
1875 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1876 (N1CVal & 0xffffU) == 0xffffU &&
1877 (N2CVal & 0xffffU) == 0x0U) {
1878 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1880 SDValue Ops[] = { N0.getOperand(0), Imm16,
1881 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1882 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1887 case ARMISD::VMOVRRD:
1888 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1889 N->getOperand(0), getAL(CurDAG),
1890 CurDAG->getRegister(0, MVT::i32));
1891 case ISD::UMUL_LOHI: {
1892 if (Subtarget->isThumb1Only())
1894 if (Subtarget->isThumb()) {
1895 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1896 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1897 CurDAG->getRegister(0, MVT::i32) };
1898 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
1900 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1901 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1902 CurDAG->getRegister(0, MVT::i32) };
1903 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1906 case ISD::SMUL_LOHI: {
1907 if (Subtarget->isThumb1Only())
1909 if (Subtarget->isThumb()) {
1910 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1911 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1912 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
1914 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1915 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1916 CurDAG->getRegister(0, MVT::i32) };
1917 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1921 SDNode *ResNode = 0;
1922 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1923 ResNode = SelectT2IndexedLoad(N);
1925 ResNode = SelectARMIndexedLoad(N);
1928 // Other cases are autogenerated.
1931 case ARMISD::BRCOND: {
1932 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1933 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1934 // Pattern complexity = 6 cost = 1 size = 0
1936 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1937 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1938 // Pattern complexity = 6 cost = 1 size = 0
1940 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1941 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1942 // Pattern complexity = 6 cost = 1 size = 0
1944 unsigned Opc = Subtarget->isThumb() ?
1945 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1946 SDValue Chain = N->getOperand(0);
1947 SDValue N1 = N->getOperand(1);
1948 SDValue N2 = N->getOperand(2);
1949 SDValue N3 = N->getOperand(3);
1950 SDValue InFlag = N->getOperand(4);
1951 assert(N1.getOpcode() == ISD::BasicBlock);
1952 assert(N2.getOpcode() == ISD::Constant);
1953 assert(N3.getOpcode() == ISD::Register);
1955 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1956 cast<ConstantSDNode>(N2)->getZExtValue()),
1958 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1959 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1961 Chain = SDValue(ResNode, 0);
1962 if (N->getNumValues() == 2) {
1963 InFlag = SDValue(ResNode, 1);
1964 ReplaceUses(SDValue(N, 1), InFlag);
1966 ReplaceUses(SDValue(N, 0),
1967 SDValue(Chain.getNode(), Chain.getResNo()));
1971 return SelectCMOVOp(N);
1972 case ARMISD::CNEG: {
1973 EVT VT = N->getValueType(0);
1974 SDValue N0 = N->getOperand(0);
1975 SDValue N1 = N->getOperand(1);
1976 SDValue N2 = N->getOperand(2);
1977 SDValue N3 = N->getOperand(3);
1978 SDValue InFlag = N->getOperand(4);
1979 assert(N2.getOpcode() == ISD::Constant);
1980 assert(N3.getOpcode() == ISD::Register);
1982 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1983 cast<ConstantSDNode>(N2)->getZExtValue()),
1985 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1987 switch (VT.getSimpleVT().SimpleTy) {
1988 default: assert(false && "Illegal conditional move type!");
1997 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2000 case ARMISD::VZIP: {
2002 EVT VT = N->getValueType(0);
2003 switch (VT.getSimpleVT().SimpleTy) {
2004 default: return NULL;
2005 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2006 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2008 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2009 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2010 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2012 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2014 SDValue Pred = getAL(CurDAG);
2015 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2016 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2017 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2019 case ARMISD::VUZP: {
2021 EVT VT = N->getValueType(0);
2022 switch (VT.getSimpleVT().SimpleTy) {
2023 default: return NULL;
2024 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2025 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2027 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2028 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2029 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2031 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2033 SDValue Pred = getAL(CurDAG);
2034 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2035 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2036 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2038 case ARMISD::VTRN: {
2040 EVT VT = N->getValueType(0);
2041 switch (VT.getSimpleVT().SimpleTy) {
2042 default: return NULL;
2043 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2044 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2046 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2047 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2048 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2050 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2052 SDValue Pred = getAL(CurDAG);
2053 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2054 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2055 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2057 case ARMISD::BUILD_VECTOR: {
2058 EVT VecVT = N->getValueType(0);
2059 EVT EltVT = VecVT.getVectorElementType();
2060 unsigned NumElts = VecVT.getVectorNumElements();
2061 if (EltVT.getSimpleVT() == MVT::f64) {
2062 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2063 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2065 assert(EltVT.getSimpleVT() == MVT::f32 &&
2066 "unexpected type for BUILD_VECTOR");
2068 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2069 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2070 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2071 N->getOperand(2), N->getOperand(3));
2074 case ISD::INTRINSIC_VOID:
2075 case ISD::INTRINSIC_W_CHAIN: {
2076 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2081 case Intrinsic::arm_neon_vld1: {
2082 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2083 ARM::VLD1d32, ARM::VLD1d64 };
2084 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2085 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2086 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2089 case Intrinsic::arm_neon_vld2: {
2090 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2091 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2092 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2093 ARM::VLD2q32Pseudo };
2094 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2097 case Intrinsic::arm_neon_vld3: {
2098 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2099 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2100 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2101 ARM::VLD3q16Pseudo_UPD,
2102 ARM::VLD3q32Pseudo_UPD };
2103 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2104 ARM::VLD3q16oddPseudo_UPD,
2105 ARM::VLD3q32oddPseudo_UPD };
2106 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2109 case Intrinsic::arm_neon_vld4: {
2110 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2111 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2112 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2113 ARM::VLD4q16Pseudo_UPD,
2114 ARM::VLD4q32Pseudo_UPD };
2115 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2116 ARM::VLD4q16oddPseudo_UPD,
2117 ARM::VLD4q32oddPseudo_UPD };
2118 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2121 case Intrinsic::arm_neon_vld2lane: {
2122 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
2123 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 };
2124 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd };
2125 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
2128 case Intrinsic::arm_neon_vld3lane: {
2129 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
2130 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 };
2131 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd };
2132 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2135 case Intrinsic::arm_neon_vld4lane: {
2136 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
2137 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 };
2138 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd };
2139 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2142 case Intrinsic::arm_neon_vst1: {
2143 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2144 ARM::VST1d32, ARM::VST1d64 };
2145 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2146 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2147 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2150 case Intrinsic::arm_neon_vst2: {
2151 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2152 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2153 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2154 ARM::VST2q32Pseudo };
2155 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2158 case Intrinsic::arm_neon_vst3: {
2159 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2160 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2161 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2162 ARM::VST3q16Pseudo_UPD,
2163 ARM::VST3q32Pseudo_UPD };
2164 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2165 ARM::VST3q16oddPseudo_UPD,
2166 ARM::VST3q32oddPseudo_UPD };
2167 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2170 case Intrinsic::arm_neon_vst4: {
2171 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2172 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2173 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2174 ARM::VST4q16Pseudo_UPD,
2175 ARM::VST4q32Pseudo_UPD };
2176 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2177 ARM::VST4q16oddPseudo_UPD,
2178 ARM::VST4q32oddPseudo_UPD };
2179 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2182 case Intrinsic::arm_neon_vst2lane: {
2183 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
2184 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 };
2185 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd };
2186 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
2189 case Intrinsic::arm_neon_vst3lane: {
2190 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
2191 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 };
2192 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd };
2193 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2196 case Intrinsic::arm_neon_vst4lane: {
2197 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
2198 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 };
2199 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd };
2200 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2206 case ISD::INTRINSIC_WO_CHAIN: {
2207 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2212 case Intrinsic::arm_neon_vtbl2:
2213 return SelectVTBL(N, false, 2, ARM::VTBL2);
2214 case Intrinsic::arm_neon_vtbl3:
2215 return SelectVTBL(N, false, 3, ARM::VTBL3);
2216 case Intrinsic::arm_neon_vtbl4:
2217 return SelectVTBL(N, false, 4, ARM::VTBL4);
2219 case Intrinsic::arm_neon_vtbx2:
2220 return SelectVTBL(N, true, 2, ARM::VTBX2);
2221 case Intrinsic::arm_neon_vtbx3:
2222 return SelectVTBL(N, true, 3, ARM::VTBX3);
2223 case Intrinsic::arm_neon_vtbx4:
2224 return SelectVTBL(N, true, 4, ARM::VTBX4);
2229 case ISD::CONCAT_VECTORS:
2230 return SelectConcatVector(N);
2233 return SelectCode(N);
2236 bool ARMDAGToDAGISel::
2237 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2238 std::vector<SDValue> &OutOps) {
2239 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2240 // Require the address to be in a register. That is safe for all ARM
2241 // variants and it is hard to do anything much smarter without knowing
2242 // how the operand is used.
2243 OutOps.push_back(Op);
2247 /// createARMISelDag - This pass converts a legalized DAG into a
2248 /// ARM-specific DAG, ready for instruction scheduling.
2250 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2251 CodeGenOpt::Level OptLevel) {
2252 return new ARMDAGToDAGISel(TM, OptLevel);