1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
41 /// instructions for SelectionDAG operations.
44 class ARMDAGToDAGISel : public SelectionDAGISel {
45 ARMBaseTargetMachine &TM;
47 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const ARMSubtarget *Subtarget;
52 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
53 CodeGenOpt::Level OptLevel)
54 : SelectionDAGISel(tm, OptLevel), TM(tm),
55 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
58 virtual const char *getPassName() const {
59 return "ARM Instruction Selection";
62 /// getI32Imm - Return a target constant of type i32 with the specified
64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 SDNode *Select(SDNode *N);
70 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
71 SDValue &B, SDValue &C);
72 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
73 SDValue &Offset, SDValue &Opc);
74 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
75 SDValue &Offset, SDValue &Opc);
76 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
77 SDValue &Offset, SDValue &Opc);
78 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
79 SDValue &Offset, SDValue &Opc);
80 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
82 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
84 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align);
86 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDNode *N);
123 SDNode *SelectT2IndexedLoad(SDNode *N);
125 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
126 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
127 /// loads of D registers and even subregs and odd subregs of Q registers.
128 /// For NumVecs <= 2, QOpcodes1 is not used.
129 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
130 unsigned *QOpcodes0, unsigned *QOpcodes1);
132 /// SelectVST - Select NEON store intrinsics. NumVecs should
133 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
134 /// stores of D registers and even subregs and odd subregs of Q registers.
135 /// For NumVecs <= 2, QOpcodes1 is not used.
136 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
137 unsigned *QOpcodes0, unsigned *QOpcodes1);
139 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
140 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
141 /// load/store of D registers and even subregs and odd subregs of Q registers.
142 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
143 unsigned *DOpcodes, unsigned *QOpcodes0,
144 unsigned *QOpcodes1);
146 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
147 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
149 /// SelectCMOVOp - Select CMOV instructions for ARM.
150 SDNode *SelectCMOVOp(SDNode *N);
151 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
152 ARMCC::CondCodes CCVal, SDValue CCR,
154 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
155 ARMCC::CondCodes CCVal, SDValue CCR,
157 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
158 ARMCC::CondCodes CCVal, SDValue CCR,
160 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
161 ARMCC::CondCodes CCVal, SDValue CCR,
164 SDNode *SelectConcatVector(SDNode *N);
166 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
167 /// inline asm expressions.
168 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
170 std::vector<SDValue> &OutOps);
172 // Form pairs of consecutive S, D, or Q registers.
173 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
174 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
175 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
177 // Form sequences of 4 consecutive S, D, or Q registers.
178 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
179 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
180 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
182 // Form sequences of 8 consecutive D registers.
183 SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3,
184 SDValue V4, SDValue V5, SDValue V6, SDValue V7);
188 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
189 /// operand. If so Imm will receive the 32-bit value.
190 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
191 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
192 Imm = cast<ConstantSDNode>(N)->getZExtValue();
198 // isInt32Immediate - This method tests to see if a constant operand.
199 // If so Imm will receive the 32 bit value.
200 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
201 return isInt32Immediate(N.getNode(), Imm);
204 // isOpcWithIntImmediate - This method tests to see if the node is a specific
205 // opcode and that it has a immediate integer right operand.
206 // If so Imm will receive the 32 bit value.
207 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
208 return N->getOpcode() == Opc &&
209 isInt32Immediate(N->getOperand(1).getNode(), Imm);
213 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
218 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
220 // Don't match base register only case. That is matched to a separate
221 // lower complexity pattern with explicit register operand.
222 if (ShOpcVal == ARM_AM::no_shift) return false;
224 BaseReg = N.getOperand(0);
225 unsigned ShImmVal = 0;
226 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
227 ShReg = CurDAG->getRegister(0, MVT::i32);
228 ShImmVal = RHS->getZExtValue() & 31;
230 ShReg = N.getOperand(1);
232 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
237 bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
238 SDValue &Base, SDValue &Offset,
240 if (N.getOpcode() == ISD::MUL) {
241 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
242 // X * [3,5,9] -> X + X * [2,4,8] etc.
243 int RHSC = (int)RHS->getZExtValue();
246 ARM_AM::AddrOpc AddSub = ARM_AM::add;
248 AddSub = ARM_AM::sub;
251 if (isPowerOf2_32(RHSC)) {
252 unsigned ShAmt = Log2_32(RHSC);
253 Base = Offset = N.getOperand(0);
254 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
263 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
265 if (N.getOpcode() == ISD::FrameIndex) {
266 int FI = cast<FrameIndexSDNode>(N)->getIndex();
267 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
268 } else if (N.getOpcode() == ARMISD::Wrapper &&
269 !(Subtarget->useMovt() &&
270 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
271 Base = N.getOperand(0);
273 Offset = CurDAG->getRegister(0, MVT::i32);
274 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
280 // Match simple R +/- imm12 operands.
281 if (N.getOpcode() == ISD::ADD)
282 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
283 int RHSC = (int)RHS->getZExtValue();
284 if ((RHSC >= 0 && RHSC < 0x1000) ||
285 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
286 Base = N.getOperand(0);
287 if (Base.getOpcode() == ISD::FrameIndex) {
288 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
289 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
291 Offset = CurDAG->getRegister(0, MVT::i32);
293 ARM_AM::AddrOpc AddSub = ARM_AM::add;
295 AddSub = ARM_AM::sub;
298 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
305 // Otherwise this is R +/- [possibly shifted] R.
306 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
307 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
310 Base = N.getOperand(0);
311 Offset = N.getOperand(1);
313 if (ShOpcVal != ARM_AM::no_shift) {
314 // Check to see if the RHS of the shift is a constant, if not, we can't fold
316 if (ConstantSDNode *Sh =
317 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
318 ShAmt = Sh->getZExtValue();
319 Offset = N.getOperand(1).getOperand(0);
321 ShOpcVal = ARM_AM::no_shift;
325 // Try matching (R shl C) + (R).
326 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
327 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
328 if (ShOpcVal != ARM_AM::no_shift) {
329 // Check to see if the RHS of the shift is a constant, if not, we can't
331 if (ConstantSDNode *Sh =
332 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
333 ShAmt = Sh->getZExtValue();
334 Offset = N.getOperand(0).getOperand(0);
335 Base = N.getOperand(1);
337 ShOpcVal = ARM_AM::no_shift;
342 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
347 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
348 SDValue &Offset, SDValue &Opc) {
349 unsigned Opcode = Op->getOpcode();
350 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
351 ? cast<LoadSDNode>(Op)->getAddressingMode()
352 : cast<StoreSDNode>(Op)->getAddressingMode();
353 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
354 ? ARM_AM::add : ARM_AM::sub;
355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
356 int Val = (int)C->getZExtValue();
357 if (Val >= 0 && Val < 0x1000) { // 12 bits.
358 Offset = CurDAG->getRegister(0, MVT::i32);
359 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
367 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
369 if (ShOpcVal != ARM_AM::no_shift) {
370 // Check to see if the RHS of the shift is a constant, if not, we can't fold
372 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
373 ShAmt = Sh->getZExtValue();
374 Offset = N.getOperand(0);
376 ShOpcVal = ARM_AM::no_shift;
380 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
386 bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
387 SDValue &Base, SDValue &Offset,
389 if (N.getOpcode() == ISD::SUB) {
390 // X - C is canonicalize to X + -C, no need to handle it here.
391 Base = N.getOperand(0);
392 Offset = N.getOperand(1);
393 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
397 if (N.getOpcode() != ISD::ADD) {
399 if (N.getOpcode() == ISD::FrameIndex) {
400 int FI = cast<FrameIndexSDNode>(N)->getIndex();
401 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
403 Offset = CurDAG->getRegister(0, MVT::i32);
404 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
408 // If the RHS is +/- imm8, fold into addr mode.
409 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
410 int RHSC = (int)RHS->getZExtValue();
411 if ((RHSC >= 0 && RHSC < 256) ||
412 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
413 Base = N.getOperand(0);
414 if (Base.getOpcode() == ISD::FrameIndex) {
415 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
416 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
418 Offset = CurDAG->getRegister(0, MVT::i32);
420 ARM_AM::AddrOpc AddSub = ARM_AM::add;
422 AddSub = ARM_AM::sub;
425 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
430 Base = N.getOperand(0);
431 Offset = N.getOperand(1);
432 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
436 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
437 SDValue &Offset, SDValue &Opc) {
438 unsigned Opcode = Op->getOpcode();
439 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
440 ? cast<LoadSDNode>(Op)->getAddressingMode()
441 : cast<StoreSDNode>(Op)->getAddressingMode();
442 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
443 ? ARM_AM::add : ARM_AM::sub;
444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
445 int Val = (int)C->getZExtValue();
446 if (Val >= 0 && Val < 256) {
447 Offset = CurDAG->getRegister(0, MVT::i32);
448 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
454 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
458 bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
459 SDValue &Addr, SDValue &Mode) {
461 Mode = CurDAG->getTargetConstant(0, MVT::i32);
465 bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
466 SDValue &Base, SDValue &Offset) {
467 if (N.getOpcode() != ISD::ADD) {
469 if (N.getOpcode() == ISD::FrameIndex) {
470 int FI = cast<FrameIndexSDNode>(N)->getIndex();
471 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
472 } else if (N.getOpcode() == ARMISD::Wrapper &&
473 !(Subtarget->useMovt() &&
474 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
475 Base = N.getOperand(0);
477 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
482 // If the RHS is +/- imm8, fold into addr mode.
483 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
484 int RHSC = (int)RHS->getZExtValue();
485 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
487 if ((RHSC >= 0 && RHSC < 256) ||
488 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
489 Base = N.getOperand(0);
490 if (Base.getOpcode() == ISD::FrameIndex) {
491 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
492 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
495 ARM_AM::AddrOpc AddSub = ARM_AM::add;
497 AddSub = ARM_AM::sub;
500 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
508 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
513 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
514 SDValue &Addr, SDValue &Align) {
516 // Default to no alignment.
517 Align = CurDAG->getTargetConstant(0, MVT::i32);
521 bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
522 SDValue &Offset, SDValue &Label) {
523 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
524 Offset = N.getOperand(0);
525 SDValue N1 = N.getOperand(1);
526 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
533 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
534 SDValue &Base, SDValue &Offset){
535 // FIXME dl should come from the parent load or store, not the address
536 if (N.getOpcode() != ISD::ADD) {
537 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
538 if (!NC || !NC->isNullValue())
545 Base = N.getOperand(0);
546 Offset = N.getOperand(1);
551 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
552 unsigned Scale, SDValue &Base,
553 SDValue &OffImm, SDValue &Offset) {
555 SDValue TmpBase, TmpOffImm;
556 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
557 return false; // We want to select tLDRspi / tSTRspi instead.
558 if (N.getOpcode() == ARMISD::Wrapper &&
559 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
560 return false; // We want to select tLDRpci instead.
563 if (N.getOpcode() != ISD::ADD) {
564 if (N.getOpcode() == ARMISD::Wrapper &&
565 !(Subtarget->useMovt() &&
566 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
567 Base = N.getOperand(0);
571 Offset = CurDAG->getRegister(0, MVT::i32);
572 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
576 // Thumb does not have [sp, r] address mode.
577 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
578 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
579 if ((LHSR && LHSR->getReg() == ARM::SP) ||
580 (RHSR && RHSR->getReg() == ARM::SP)) {
582 Offset = CurDAG->getRegister(0, MVT::i32);
583 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
587 // If the RHS is + imm5 * scale, fold into addr mode.
588 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
589 int RHSC = (int)RHS->getZExtValue();
590 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
592 if (RHSC >= 0 && RHSC < 32) {
593 Base = N.getOperand(0);
594 Offset = CurDAG->getRegister(0, MVT::i32);
595 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
601 Base = N.getOperand(0);
602 Offset = N.getOperand(1);
603 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
607 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
608 SDValue &Base, SDValue &OffImm,
610 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
613 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
614 SDValue &Base, SDValue &OffImm,
616 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
619 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
620 SDValue &Base, SDValue &OffImm,
622 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
625 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
626 SDValue &Base, SDValue &OffImm) {
627 if (N.getOpcode() == ISD::FrameIndex) {
628 int FI = cast<FrameIndexSDNode>(N)->getIndex();
629 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
630 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
634 if (N.getOpcode() != ISD::ADD)
637 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
638 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
639 (LHSR && LHSR->getReg() == ARM::SP)) {
640 // If the RHS is + imm8 * scale, fold into addr mode.
641 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
642 int RHSC = (int)RHS->getZExtValue();
643 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
645 if (RHSC >= 0 && RHSC < 256) {
646 Base = N.getOperand(0);
647 if (Base.getOpcode() == ISD::FrameIndex) {
648 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
649 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
651 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
661 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
664 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
666 // Don't match base register only case. That is matched to a separate
667 // lower complexity pattern with explicit register operand.
668 if (ShOpcVal == ARM_AM::no_shift) return false;
670 BaseReg = N.getOperand(0);
671 unsigned ShImmVal = 0;
672 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
673 ShImmVal = RHS->getZExtValue() & 31;
674 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
681 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
682 SDValue &Base, SDValue &OffImm) {
683 // Match simple R + imm12 operands.
686 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
687 if (N.getOpcode() == ISD::FrameIndex) {
688 // Match frame index...
689 int FI = cast<FrameIndexSDNode>(N)->getIndex();
690 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
691 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
693 } else if (N.getOpcode() == ARMISD::Wrapper &&
694 !(Subtarget->useMovt() &&
695 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
696 Base = N.getOperand(0);
697 if (Base.getOpcode() == ISD::TargetConstantPool)
698 return false; // We want to select t2LDRpci instead.
701 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
705 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
706 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
707 // Let t2LDRi8 handle (R - imm8).
710 int RHSC = (int)RHS->getZExtValue();
711 if (N.getOpcode() == ISD::SUB)
714 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
715 Base = N.getOperand(0);
716 if (Base.getOpcode() == ISD::FrameIndex) {
717 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
718 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
720 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
727 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
731 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
732 SDValue &Base, SDValue &OffImm) {
733 // Match simple R - imm8 operands.
734 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
735 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
736 int RHSC = (int)RHS->getSExtValue();
737 if (N.getOpcode() == ISD::SUB)
740 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
741 Base = N.getOperand(0);
742 if (Base.getOpcode() == ISD::FrameIndex) {
743 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
744 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
746 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
755 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
757 unsigned Opcode = Op->getOpcode();
758 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
759 ? cast<LoadSDNode>(Op)->getAddressingMode()
760 : cast<StoreSDNode>(Op)->getAddressingMode();
761 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
762 int RHSC = (int)RHS->getZExtValue();
763 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
764 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
765 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
766 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
774 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N,
775 SDValue &Base, SDValue &OffImm) {
776 if (N.getOpcode() == ISD::ADD) {
777 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
778 int RHSC = (int)RHS->getZExtValue();
780 if (((RHSC & 0x3) == 0) &&
781 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) {
782 Base = N.getOperand(0);
783 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
787 } else if (N.getOpcode() == ISD::SUB) {
788 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
789 int RHSC = (int)RHS->getZExtValue();
791 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) {
792 Base = N.getOperand(0);
793 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
802 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
804 SDValue &OffReg, SDValue &ShImm) {
805 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
806 if (N.getOpcode() != ISD::ADD)
809 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
810 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
811 int RHSC = (int)RHS->getZExtValue();
812 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
814 else if (RHSC < 0 && RHSC >= -255) // 8 bits
818 // Look for (R + R) or (R + (R << [1,2,3])).
820 Base = N.getOperand(0);
821 OffReg = N.getOperand(1);
823 // Swap if it is ((R << c) + R).
824 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
825 if (ShOpcVal != ARM_AM::lsl) {
826 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
827 if (ShOpcVal == ARM_AM::lsl)
828 std::swap(Base, OffReg);
831 if (ShOpcVal == ARM_AM::lsl) {
832 // Check to see if the RHS of the shift is a constant, if not, we can't fold
834 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
835 ShAmt = Sh->getZExtValue();
838 ShOpcVal = ARM_AM::no_shift;
840 OffReg = OffReg.getOperand(0);
842 ShOpcVal = ARM_AM::no_shift;
846 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
851 //===--------------------------------------------------------------------===//
853 /// getAL - Returns a ARMCC::AL immediate node.
854 static inline SDValue getAL(SelectionDAG *CurDAG) {
855 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
858 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
859 LoadSDNode *LD = cast<LoadSDNode>(N);
860 ISD::MemIndexedMode AM = LD->getAddressingMode();
861 if (AM == ISD::UNINDEXED)
864 EVT LoadedVT = LD->getMemoryVT();
865 SDValue Offset, AMOpc;
866 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
869 if (LoadedVT == MVT::i32 &&
870 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
871 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
873 } else if (LoadedVT == MVT::i16 &&
874 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
876 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
877 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
878 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
879 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
880 if (LD->getExtensionType() == ISD::SEXTLOAD) {
881 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
883 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
886 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
888 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
894 SDValue Chain = LD->getChain();
895 SDValue Base = LD->getBasePtr();
896 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
897 CurDAG->getRegister(0, MVT::i32), Chain };
898 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
905 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
906 LoadSDNode *LD = cast<LoadSDNode>(N);
907 ISD::MemIndexedMode AM = LD->getAddressingMode();
908 if (AM == ISD::UNINDEXED)
911 EVT LoadedVT = LD->getMemoryVT();
912 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
914 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
917 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
918 switch (LoadedVT.getSimpleVT().SimpleTy) {
920 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
924 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
926 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
931 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
933 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
942 SDValue Chain = LD->getChain();
943 SDValue Base = LD->getBasePtr();
944 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
945 CurDAG->getRegister(0, MVT::i32), Chain };
946 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
953 /// PairSRegs - Form a D register from a pair of S registers.
955 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
956 DebugLoc dl = V0.getNode()->getDebugLoc();
957 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
958 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
959 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
960 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
963 /// PairDRegs - Form a quad register from a pair of D registers.
965 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
966 DebugLoc dl = V0.getNode()->getDebugLoc();
967 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
968 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
969 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
970 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
973 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
975 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
976 DebugLoc dl = V0.getNode()->getDebugLoc();
977 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
978 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
979 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
980 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
983 /// QuadSRegs - Form 4 consecutive S registers.
985 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
986 SDValue V2, SDValue V3) {
987 DebugLoc dl = V0.getNode()->getDebugLoc();
988 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
989 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
990 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
991 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
992 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
993 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
996 /// QuadDRegs - Form 4 consecutive D registers.
998 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
999 SDValue V2, SDValue V3) {
1000 DebugLoc dl = V0.getNode()->getDebugLoc();
1001 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1002 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1003 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1004 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1005 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1006 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1009 /// QuadQRegs - Form 4 consecutive Q registers.
1011 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1012 SDValue V2, SDValue V3) {
1013 DebugLoc dl = V0.getNode()->getDebugLoc();
1014 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1015 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1016 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1017 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1018 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1019 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1022 /// OctoDRegs - Form 8 consecutive D registers.
1024 SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1,
1025 SDValue V2, SDValue V3,
1026 SDValue V4, SDValue V5,
1027 SDValue V6, SDValue V7) {
1028 DebugLoc dl = V0.getNode()->getDebugLoc();
1029 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1030 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1031 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1032 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1033 SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32);
1034 SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32);
1035 SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32);
1036 SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32);
1037 const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3,
1038 V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 };
1039 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16);
1042 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1043 /// for a 64-bit subregister of the vector.
1044 static EVT GetNEONSubregVT(EVT VT) {
1045 switch (VT.getSimpleVT().SimpleTy) {
1046 default: llvm_unreachable("unhandled NEON type");
1047 case MVT::v16i8: return MVT::v8i8;
1048 case MVT::v8i16: return MVT::v4i16;
1049 case MVT::v4f32: return MVT::v2f32;
1050 case MVT::v4i32: return MVT::v2i32;
1051 case MVT::v2i64: return MVT::v1i64;
1055 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1056 unsigned *DOpcodes, unsigned *QOpcodes0,
1057 unsigned *QOpcodes1) {
1058 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1059 DebugLoc dl = N->getDebugLoc();
1061 SDValue MemAddr, Align;
1062 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1065 SDValue Chain = N->getOperand(0);
1066 EVT VT = N->getValueType(0);
1067 bool is64BitVector = VT.is64BitVector();
1069 unsigned OpcodeIndex;
1070 switch (VT.getSimpleVT().SimpleTy) {
1071 default: llvm_unreachable("unhandled vld type");
1072 // Double-register operations:
1073 case MVT::v8i8: OpcodeIndex = 0; break;
1074 case MVT::v4i16: OpcodeIndex = 1; break;
1076 case MVT::v2i32: OpcodeIndex = 2; break;
1077 case MVT::v1i64: OpcodeIndex = 3; break;
1078 // Quad-register operations:
1079 case MVT::v16i8: OpcodeIndex = 0; break;
1080 case MVT::v8i16: OpcodeIndex = 1; break;
1082 case MVT::v4i32: OpcodeIndex = 2; break;
1083 case MVT::v2i64: OpcodeIndex = 3;
1084 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1088 SDValue Pred = getAL(CurDAG);
1089 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1090 if (is64BitVector) {
1091 unsigned Opc = DOpcodes[OpcodeIndex];
1092 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1093 std::vector<EVT> ResTys(NumVecs, VT);
1094 ResTys.push_back(MVT::Other);
1095 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1100 SDValue V0 = SDValue(VLd, 0);
1101 SDValue V1 = SDValue(VLd, 1);
1103 // Form a REG_SEQUENCE to force register allocation.
1105 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1107 SDValue V2 = SDValue(VLd, 2);
1108 // If it's a vld3, form a quad D-register but discard the last part.
1109 SDValue V3 = (NumVecs == 3)
1110 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1112 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1115 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1116 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1117 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1119 ReplaceUses(SDValue(N, Vec), D);
1121 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs));
1125 EVT RegVT = GetNEONSubregVT(VT);
1127 // Quad registers are directly supported for VLD1 and VLD2,
1128 // loading pairs of D regs.
1129 unsigned Opc = QOpcodes0[OpcodeIndex];
1130 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1131 std::vector<EVT> ResTys(2 * NumVecs, RegVT);
1132 ResTys.push_back(MVT::Other);
1133 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1134 Chain = SDValue(VLd, 2 * NumVecs);
1136 // Combine the even and odd subregs to produce the result.
1138 SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
1139 ReplaceUses(SDValue(N, 0), SDValue(Q, 0));
1141 SDValue QQ = SDValue(QuadDRegs(MVT::v4i64,
1142 SDValue(VLd, 0), SDValue(VLd, 1),
1143 SDValue(VLd, 2), SDValue(VLd, 3)), 0);
1144 SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ);
1145 SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ);
1146 ReplaceUses(SDValue(N, 0), Q0);
1147 ReplaceUses(SDValue(N, 1), Q1);
1150 // Otherwise, quad registers are loaded with two separate instructions,
1151 // where one loads the even registers and the other loads the odd registers.
1153 std::vector<EVT> ResTys(NumVecs, RegVT);
1154 ResTys.push_back(MemAddr.getValueType());
1155 ResTys.push_back(MVT::Other);
1157 // Load the even subregs.
1158 unsigned Opc = QOpcodes0[OpcodeIndex];
1159 const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain };
1160 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6);
1161 Chain = SDValue(VLdA, NumVecs+1);
1163 // Load the odd subregs.
1164 Opc = QOpcodes1[OpcodeIndex];
1165 const SDValue OpsB[] = { SDValue(VLdA, NumVecs),
1166 Align, Reg0, Pred, Reg0, Chain };
1167 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6);
1168 Chain = SDValue(VLdB, NumVecs+1);
1170 SDValue V0 = SDValue(VLdA, 0);
1171 SDValue V1 = SDValue(VLdB, 0);
1172 SDValue V2 = SDValue(VLdA, 1);
1173 SDValue V3 = SDValue(VLdB, 1);
1174 SDValue V4 = SDValue(VLdA, 2);
1175 SDValue V5 = SDValue(VLdB, 2);
1176 SDValue V6 = (NumVecs == 3)
1177 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
1179 SDValue V7 = (NumVecs == 3)
1180 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
1182 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3,
1183 V4, V5, V6, V7), 0);
1185 // Extract out the 3 / 4 Q registers.
1186 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1187 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1188 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1190 ReplaceUses(SDValue(N, Vec), Q);
1193 ReplaceUses(SDValue(N, NumVecs), Chain);
1197 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1198 unsigned *DOpcodes, unsigned *QOpcodes0,
1199 unsigned *QOpcodes1) {
1200 assert(NumVecs >=1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1201 DebugLoc dl = N->getDebugLoc();
1203 SDValue MemAddr, Align;
1204 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1207 SDValue Chain = N->getOperand(0);
1208 EVT VT = N->getOperand(3).getValueType();
1209 bool is64BitVector = VT.is64BitVector();
1211 unsigned OpcodeIndex;
1212 switch (VT.getSimpleVT().SimpleTy) {
1213 default: llvm_unreachable("unhandled vst type");
1214 // Double-register operations:
1215 case MVT::v8i8: OpcodeIndex = 0; break;
1216 case MVT::v4i16: OpcodeIndex = 1; break;
1218 case MVT::v2i32: OpcodeIndex = 2; break;
1219 case MVT::v1i64: OpcodeIndex = 3; break;
1220 // Quad-register operations:
1221 case MVT::v16i8: OpcodeIndex = 0; break;
1222 case MVT::v8i16: OpcodeIndex = 1; break;
1224 case MVT::v4i32: OpcodeIndex = 2; break;
1225 case MVT::v2i64: OpcodeIndex = 3;
1226 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1230 SDValue Pred = getAL(CurDAG);
1231 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1233 SmallVector<SDValue, 10> Ops;
1234 Ops.push_back(MemAddr);
1235 Ops.push_back(Align);
1237 if (is64BitVector) {
1240 SDValue V0 = N->getOperand(0+3);
1241 SDValue V1 = N->getOperand(1+3);
1243 // Form a REG_SEQUENCE to force register allocation.
1245 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1247 SDValue V2 = N->getOperand(2+3);
1248 // If it's a vld3, form a quad D-register and leave the last part as
1250 SDValue V3 = (NumVecs == 3)
1251 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1252 : N->getOperand(3+3);
1253 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1256 // Now extract the D registers back out.
1257 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
1259 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT,
1262 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,
1265 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
1268 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1269 Ops.push_back(N->getOperand(Vec+3));
1271 Ops.push_back(Pred);
1272 Ops.push_back(Reg0); // predicate register
1273 Ops.push_back(Chain);
1274 unsigned Opc = DOpcodes[OpcodeIndex];
1275 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1278 EVT RegVT = GetNEONSubregVT(VT);
1280 // Quad registers are directly supported for VST1 and VST2,
1281 // storing pairs of D regs.
1282 unsigned Opc = QOpcodes0[OpcodeIndex];
1284 // First extract the pair of Q registers.
1285 SDValue Q0 = N->getOperand(3);
1286 SDValue Q1 = N->getOperand(4);
1288 // Form a QQ register.
1289 SDValue QQ = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1291 // Now extract the D registers back out.
1292 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
1294 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
1296 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, RegVT,
1298 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, RegVT,
1300 Ops.push_back(Pred);
1301 Ops.push_back(Reg0); // predicate register
1302 Ops.push_back(Chain);
1303 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 5 + 4);
1305 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1306 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
1307 N->getOperand(Vec+3)));
1308 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
1309 N->getOperand(Vec+3)));
1311 Ops.push_back(Pred);
1312 Ops.push_back(Reg0); // predicate register
1313 Ops.push_back(Chain);
1314 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
1319 // Otherwise, quad registers are stored with two separate instructions,
1320 // where one stores the even registers and the other stores the odd registers.
1322 // Form the QQQQ REG_SEQUENCE.
1324 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
1325 V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
1326 N->getOperand(Vec+3));
1327 V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
1328 N->getOperand(Vec+3));
1331 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1334 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3],
1335 V[4], V[5], V[6], V[7]), 0);
1337 // Store the even D registers.
1338 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1339 Ops.push_back(Reg0); // post-access address offset
1340 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1341 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl,
1343 Ops.push_back(Pred);
1344 Ops.push_back(Reg0); // predicate register
1345 Ops.push_back(Chain);
1346 unsigned Opc = QOpcodes0[OpcodeIndex];
1347 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1348 MVT::Other, Ops.data(), NumVecs+6);
1349 Chain = SDValue(VStA, 1);
1351 // Store the odd D registers.
1352 Ops[0] = SDValue(VStA, 0); // MemAddr
1353 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1354 Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl,
1356 Ops[NumVecs+5] = Chain;
1357 Opc = QOpcodes1[OpcodeIndex];
1358 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1359 MVT::Other, Ops.data(), NumVecs+6);
1360 Chain = SDValue(VStB, 1);
1361 ReplaceUses(SDValue(N, 0), Chain);
1365 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1366 unsigned NumVecs, unsigned *DOpcodes,
1367 unsigned *QOpcodes0,
1368 unsigned *QOpcodes1) {
1369 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1370 DebugLoc dl = N->getDebugLoc();
1372 SDValue MemAddr, Align;
1373 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1376 SDValue Chain = N->getOperand(0);
1378 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1379 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1380 bool is64BitVector = VT.is64BitVector();
1382 // Quad registers are handled by load/store of subregs. Find the subreg info.
1383 unsigned NumElts = 0;
1386 if (!is64BitVector) {
1387 RegVT = GetNEONSubregVT(VT);
1388 NumElts = RegVT.getVectorNumElements();
1389 Even = Lane < NumElts;
1392 unsigned OpcodeIndex;
1393 switch (VT.getSimpleVT().SimpleTy) {
1394 default: llvm_unreachable("unhandled vld/vst lane type");
1395 // Double-register operations:
1396 case MVT::v8i8: OpcodeIndex = 0; break;
1397 case MVT::v4i16: OpcodeIndex = 1; break;
1399 case MVT::v2i32: OpcodeIndex = 2; break;
1400 // Quad-register operations:
1401 case MVT::v8i16: OpcodeIndex = 0; break;
1403 case MVT::v4i32: OpcodeIndex = 1; break;
1406 SDValue Pred = getAL(CurDAG);
1407 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1409 SmallVector<SDValue, 10> Ops;
1410 Ops.push_back(MemAddr);
1411 Ops.push_back(Align);
1414 if (is64BitVector) {
1415 Opc = DOpcodes[OpcodeIndex];
1417 SDValue V0 = N->getOperand(0+3);
1418 SDValue V1 = N->getOperand(1+3);
1420 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1422 SDValue V2 = N->getOperand(2+3);
1423 SDValue V3 = (NumVecs == 3)
1424 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1425 : N->getOperand(3+3);
1426 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1429 // Now extract the D registers back out.
1430 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
1431 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
1433 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq));
1435 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq));
1437 // Check if this is loading the even or odd subreg of a Q register.
1438 if (Lane < NumElts) {
1439 Opc = QOpcodes0[OpcodeIndex];
1442 Opc = QOpcodes1[OpcodeIndex];
1446 SDValue V0 = N->getOperand(0+3);
1447 SDValue V1 = N->getOperand(1+3);
1449 RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1451 SDValue V2 = N->getOperand(2+3);
1452 SDValue V3 = (NumVecs == 3)
1453 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1454 : N->getOperand(3+3);
1455 RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1458 // Extract the subregs of the input vector.
1459 unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1;
1460 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1461 Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT,
1464 Ops.push_back(getI32Imm(Lane));
1465 Ops.push_back(Pred);
1466 Ops.push_back(Reg0);
1467 Ops.push_back(Chain);
1470 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6);
1472 std::vector<EVT> ResTys(NumVecs, RegVT);
1473 ResTys.push_back(MVT::Other);
1474 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6);
1476 // Form a REG_SEQUENCE to force register allocation.
1478 if (is64BitVector) {
1479 SDValue V0 = SDValue(VLdLn, 0);
1480 SDValue V1 = SDValue(VLdLn, 1);
1482 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1484 SDValue V2 = SDValue(VLdLn, 2);
1485 // If it's a vld3, form a quad D-register but discard the last part.
1486 SDValue V3 = (NumVecs == 3)
1487 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1488 : SDValue(VLdLn, 3);
1489 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1492 // For 128-bit vectors, take the 64-bit results of the load and insert
1493 // them as subregs into the result.
1495 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
1497 V[i] = SDValue(VLdLn, Vec);
1498 V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1501 V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1503 V[i+1] = SDValue(VLdLn, Vec);
1507 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1511 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0);
1513 RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3],
1514 V[4], V[5], V[6], V[7]), 0);
1517 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1518 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1519 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1520 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1521 ReplaceUses(SDValue(N, Vec),
1522 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq));
1523 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs));
1527 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1529 if (!Subtarget->hasV6T2Ops())
1532 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1533 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1536 // For unsigned extracts, check for a shift right and mask
1537 unsigned And_imm = 0;
1538 if (N->getOpcode() == ISD::AND) {
1539 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1541 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1542 if (And_imm & (And_imm + 1))
1545 unsigned Srl_imm = 0;
1546 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1548 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1550 unsigned Width = CountTrailingOnes_32(And_imm);
1551 unsigned LSB = Srl_imm;
1552 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1553 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1554 CurDAG->getTargetConstant(LSB, MVT::i32),
1555 CurDAG->getTargetConstant(Width, MVT::i32),
1556 getAL(CurDAG), Reg0 };
1557 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1563 // Otherwise, we're looking for a shift of a shift
1564 unsigned Shl_imm = 0;
1565 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1566 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1567 unsigned Srl_imm = 0;
1568 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1569 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1570 unsigned Width = 32 - Srl_imm;
1571 int LSB = Srl_imm - Shl_imm;
1574 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1575 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1576 CurDAG->getTargetConstant(LSB, MVT::i32),
1577 CurDAG->getTargetConstant(Width, MVT::i32),
1578 getAL(CurDAG), Reg0 };
1579 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1585 SDNode *ARMDAGToDAGISel::
1586 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1587 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1590 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
1591 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1592 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1595 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1596 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1597 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1598 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1600 llvm_unreachable("Unknown so_reg opcode!");
1604 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1605 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1606 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1607 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1612 SDNode *ARMDAGToDAGISel::
1613 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1614 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1618 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1619 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1620 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1621 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1626 SDNode *ARMDAGToDAGISel::
1627 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1628 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1629 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1633 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1634 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1635 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1636 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1637 return CurDAG->SelectNodeTo(N,
1638 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1643 SDNode *ARMDAGToDAGISel::
1644 SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1645 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1646 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1650 if (Predicate_so_imm(TrueVal.getNode())) {
1651 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1652 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1653 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1654 return CurDAG->SelectNodeTo(N,
1655 ARM::MOVCCi, MVT::i32, Ops, 5);
1660 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1661 EVT VT = N->getValueType(0);
1662 SDValue FalseVal = N->getOperand(0);
1663 SDValue TrueVal = N->getOperand(1);
1664 SDValue CC = N->getOperand(2);
1665 SDValue CCR = N->getOperand(3);
1666 SDValue InFlag = N->getOperand(4);
1667 assert(CC.getOpcode() == ISD::Constant);
1668 assert(CCR.getOpcode() == ISD::Register);
1669 ARMCC::CondCodes CCVal =
1670 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1672 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1673 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1674 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1675 // Pattern complexity = 18 cost = 1 size = 0
1679 if (Subtarget->isThumb()) {
1680 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1681 CCVal, CCR, InFlag);
1683 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1684 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1688 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1689 CCVal, CCR, InFlag);
1691 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1692 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1697 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1698 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1700 // Emits: (MOVCCi:i32 GPR:i32:$false,
1701 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1702 // Pattern complexity = 10 cost = 1 size = 0
1703 if (Subtarget->isThumb()) {
1704 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
1705 CCVal, CCR, InFlag);
1707 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
1708 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1712 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
1713 CCVal, CCR, InFlag);
1715 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
1716 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1722 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1723 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1724 // Pattern complexity = 6 cost = 1 size = 0
1726 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1727 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1728 // Pattern complexity = 6 cost = 11 size = 0
1730 // Also FCPYScc and FCPYDcc.
1731 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1732 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1734 switch (VT.getSimpleVT().SimpleTy) {
1735 default: assert(false && "Illegal conditional move type!");
1738 Opc = Subtarget->isThumb()
1739 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1749 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1752 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1753 // The only time a CONCAT_VECTORS operation can have legal types is when
1754 // two 64-bit vectors are concatenated to a 128-bit vector.
1755 EVT VT = N->getValueType(0);
1756 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1757 llvm_unreachable("unexpected CONCAT_VECTORS");
1758 DebugLoc dl = N->getDebugLoc();
1759 SDValue V0 = N->getOperand(0);
1760 SDValue V1 = N->getOperand(1);
1761 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1762 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1763 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1764 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1767 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1768 DebugLoc dl = N->getDebugLoc();
1770 if (N->isMachineOpcode())
1771 return NULL; // Already selected.
1773 switch (N->getOpcode()) {
1775 case ISD::Constant: {
1776 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1778 if (Subtarget->hasThumb2())
1779 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1780 // be done with MOV + MOVT, at worst.
1783 if (Subtarget->isThumb()) {
1784 UseCP = (Val > 255 && // MOV
1785 ~Val > 255 && // MOV + MVN
1786 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1788 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1789 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1790 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1795 CurDAG->getTargetConstantPool(ConstantInt::get(
1796 Type::getInt32Ty(*CurDAG->getContext()), Val),
1797 TLI.getPointerTy());
1800 if (Subtarget->isThumb1Only()) {
1801 SDValue Pred = getAL(CurDAG);
1802 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1803 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1804 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1809 CurDAG->getRegister(0, MVT::i32),
1810 CurDAG->getTargetConstant(0, MVT::i32),
1812 CurDAG->getRegister(0, MVT::i32),
1813 CurDAG->getEntryNode()
1815 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1818 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1822 // Other cases are autogenerated.
1825 case ISD::FrameIndex: {
1826 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1827 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1828 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1829 if (Subtarget->isThumb1Only()) {
1830 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1831 CurDAG->getTargetConstant(0, MVT::i32));
1833 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1834 ARM::t2ADDri : ARM::ADDri);
1835 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1836 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1837 CurDAG->getRegister(0, MVT::i32) };
1838 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1842 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1846 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1850 if (Subtarget->isThumb1Only())
1852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1853 unsigned RHSV = C->getZExtValue();
1855 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1856 unsigned ShImm = Log2_32(RHSV-1);
1859 SDValue V = N->getOperand(0);
1860 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1861 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1862 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1863 if (Subtarget->isThumb()) {
1864 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1865 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1867 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1868 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1871 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1872 unsigned ShImm = Log2_32(RHSV+1);
1875 SDValue V = N->getOperand(0);
1876 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1877 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1878 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1879 if (Subtarget->isThumb()) {
1880 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1881 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
1883 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1884 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1890 // Check for unsigned bitfield extract
1891 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1894 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1895 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1896 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1897 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1898 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1899 EVT VT = N->getValueType(0);
1902 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1904 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1907 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1908 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1911 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1912 SDValue N2 = N0.getOperand(1);
1913 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1916 unsigned N1CVal = N1C->getZExtValue();
1917 unsigned N2CVal = N2C->getZExtValue();
1918 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1919 (N1CVal & 0xffffU) == 0xffffU &&
1920 (N2CVal & 0xffffU) == 0x0U) {
1921 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1923 SDValue Ops[] = { N0.getOperand(0), Imm16,
1924 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1925 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1930 case ARMISD::VMOVRRD:
1931 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1932 N->getOperand(0), getAL(CurDAG),
1933 CurDAG->getRegister(0, MVT::i32));
1934 case ISD::UMUL_LOHI: {
1935 if (Subtarget->isThumb1Only())
1937 if (Subtarget->isThumb()) {
1938 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1939 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1940 CurDAG->getRegister(0, MVT::i32) };
1941 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
1943 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1944 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1945 CurDAG->getRegister(0, MVT::i32) };
1946 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1949 case ISD::SMUL_LOHI: {
1950 if (Subtarget->isThumb1Only())
1952 if (Subtarget->isThumb()) {
1953 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1954 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1955 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
1957 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1958 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1959 CurDAG->getRegister(0, MVT::i32) };
1960 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1964 SDNode *ResNode = 0;
1965 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1966 ResNode = SelectT2IndexedLoad(N);
1968 ResNode = SelectARMIndexedLoad(N);
1972 // VLDMQ must be custom-selected for "v2f64 load" to set the AM5Opc value.
1973 if (Subtarget->hasVFP2() &&
1974 N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) {
1975 SDValue Chain = N->getOperand(0);
1977 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
1978 SDValue Pred = getAL(CurDAG);
1979 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1980 SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
1981 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1982 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
1983 SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl,
1984 MVT::v2f64, MVT::Other, Ops, 5);
1985 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1988 // Other cases are autogenerated.
1992 // VSTMQ must be custom-selected for "v2f64 store" to set the AM5Opc value.
1993 if (Subtarget->hasVFP2() &&
1994 N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) {
1995 SDValue Chain = N->getOperand(0);
1997 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
1998 SDValue Pred = getAL(CurDAG);
1999 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2000 SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
2001 AM5Opc, Pred, PredReg, Chain };
2002 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2003 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
2004 SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
2005 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
2008 // Other cases are autogenerated.
2011 case ARMISD::BRCOND: {
2012 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2013 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2014 // Pattern complexity = 6 cost = 1 size = 0
2016 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2017 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2018 // Pattern complexity = 6 cost = 1 size = 0
2020 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2021 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2022 // Pattern complexity = 6 cost = 1 size = 0
2024 unsigned Opc = Subtarget->isThumb() ?
2025 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2026 SDValue Chain = N->getOperand(0);
2027 SDValue N1 = N->getOperand(1);
2028 SDValue N2 = N->getOperand(2);
2029 SDValue N3 = N->getOperand(3);
2030 SDValue InFlag = N->getOperand(4);
2031 assert(N1.getOpcode() == ISD::BasicBlock);
2032 assert(N2.getOpcode() == ISD::Constant);
2033 assert(N3.getOpcode() == ISD::Register);
2035 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2036 cast<ConstantSDNode>(N2)->getZExtValue()),
2038 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2039 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2041 Chain = SDValue(ResNode, 0);
2042 if (N->getNumValues() == 2) {
2043 InFlag = SDValue(ResNode, 1);
2044 ReplaceUses(SDValue(N, 1), InFlag);
2046 ReplaceUses(SDValue(N, 0),
2047 SDValue(Chain.getNode(), Chain.getResNo()));
2051 return SelectCMOVOp(N);
2052 case ARMISD::CNEG: {
2053 EVT VT = N->getValueType(0);
2054 SDValue N0 = N->getOperand(0);
2055 SDValue N1 = N->getOperand(1);
2056 SDValue N2 = N->getOperand(2);
2057 SDValue N3 = N->getOperand(3);
2058 SDValue InFlag = N->getOperand(4);
2059 assert(N2.getOpcode() == ISD::Constant);
2060 assert(N3.getOpcode() == ISD::Register);
2062 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2063 cast<ConstantSDNode>(N2)->getZExtValue()),
2065 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2067 switch (VT.getSimpleVT().SimpleTy) {
2068 default: assert(false && "Illegal conditional move type!");
2077 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2080 case ARMISD::VZIP: {
2082 EVT VT = N->getValueType(0);
2083 switch (VT.getSimpleVT().SimpleTy) {
2084 default: return NULL;
2085 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2086 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2088 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2089 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2090 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2092 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2094 SDValue Pred = getAL(CurDAG);
2095 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2096 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2097 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2099 case ARMISD::VUZP: {
2101 EVT VT = N->getValueType(0);
2102 switch (VT.getSimpleVT().SimpleTy) {
2103 default: return NULL;
2104 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2105 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2107 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2108 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2109 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2111 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2113 SDValue Pred = getAL(CurDAG);
2114 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2115 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2116 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2118 case ARMISD::VTRN: {
2120 EVT VT = N->getValueType(0);
2121 switch (VT.getSimpleVT().SimpleTy) {
2122 default: return NULL;
2123 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2124 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2126 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2127 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2128 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2130 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2132 SDValue Pred = getAL(CurDAG);
2133 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2134 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2135 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2137 case ARMISD::BUILD_VECTOR: {
2138 EVT VecVT = N->getValueType(0);
2139 EVT EltVT = VecVT.getVectorElementType();
2140 unsigned NumElts = VecVT.getVectorNumElements();
2141 if (EltVT.getSimpleVT() == MVT::f64) {
2142 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2143 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2145 assert(EltVT.getSimpleVT() == MVT::f32 &&
2146 "unexpected type for BUILD_VECTOR");
2148 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2149 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2150 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2151 N->getOperand(2), N->getOperand(3));
2154 case ISD::INTRINSIC_VOID:
2155 case ISD::INTRINSIC_W_CHAIN: {
2156 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2161 case Intrinsic::arm_neon_vld1: {
2162 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2163 ARM::VLD1d32, ARM::VLD1d64 };
2164 unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
2165 ARM::VLD1q32, ARM::VLD1q64 };
2166 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2169 case Intrinsic::arm_neon_vld2: {
2170 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
2171 ARM::VLD2d32, ARM::VLD1q64 };
2172 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
2173 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2176 case Intrinsic::arm_neon_vld3: {
2177 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
2178 ARM::VLD3d32, ARM::VLD1d64T };
2179 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
2182 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
2183 ARM::VLD3q16odd_UPD,
2184 ARM::VLD3q32odd_UPD };
2185 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2188 case Intrinsic::arm_neon_vld4: {
2189 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
2190 ARM::VLD4d32, ARM::VLD1d64Q };
2191 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
2194 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
2195 ARM::VLD4q16odd_UPD,
2196 ARM::VLD4q32odd_UPD };
2197 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2200 case Intrinsic::arm_neon_vld2lane: {
2201 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
2202 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 };
2203 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd };
2204 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
2207 case Intrinsic::arm_neon_vld3lane: {
2208 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
2209 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 };
2210 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd };
2211 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2214 case Intrinsic::arm_neon_vld4lane: {
2215 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
2216 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 };
2217 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd };
2218 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2221 case Intrinsic::arm_neon_vst1: {
2222 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2223 ARM::VST1d32, ARM::VST1d64 };
2224 unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
2225 ARM::VST1q32, ARM::VST1q64 };
2226 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2229 case Intrinsic::arm_neon_vst2: {
2230 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
2231 ARM::VST2d32, ARM::VST1q64 };
2232 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
2233 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2236 case Intrinsic::arm_neon_vst3: {
2237 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
2238 ARM::VST3d32, ARM::VST1d64T };
2239 unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
2242 unsigned QOpcodes1[] = { ARM::VST3q8odd_UPD,
2243 ARM::VST3q16odd_UPD,
2244 ARM::VST3q32odd_UPD };
2245 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2248 case Intrinsic::arm_neon_vst4: {
2249 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
2250 ARM::VST4d32, ARM::VST1d64Q };
2251 unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
2254 unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD,
2255 ARM::VST4q16odd_UPD,
2256 ARM::VST4q32odd_UPD };
2257 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2260 case Intrinsic::arm_neon_vst2lane: {
2261 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
2262 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 };
2263 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd };
2264 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
2267 case Intrinsic::arm_neon_vst3lane: {
2268 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
2269 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 };
2270 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd };
2271 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2274 case Intrinsic::arm_neon_vst4lane: {
2275 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
2276 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 };
2277 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd };
2278 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2284 case ISD::CONCAT_VECTORS:
2285 return SelectConcatVector(N);
2288 return SelectCode(N);
2291 bool ARMDAGToDAGISel::
2292 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2293 std::vector<SDValue> &OutOps) {
2294 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2295 // Require the address to be in a register. That is safe for all ARM
2296 // variants and it is hard to do anything much smarter without knowing
2297 // how the operand is used.
2298 OutOps.push_back(Op);
2302 /// createARMISelDag - This pass converts a legalized DAG into a
2303 /// ARM-specific DAG, ready for instruction scheduling.
2305 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2306 CodeGenOpt::Level OptLevel) {
2307 return new ARMDAGToDAGISel(TM, OptLevel);