1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMTargetMachine.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "arm-isel"
42 DisableShifterOp("disable-shifter-op", cl::Hidden,
43 cl::desc("Disable isel of shifter-op"),
47 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
48 cl::desc("Check fp vmla / vmls hazard at isel time"),
51 //===--------------------------------------------------------------------===//
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
53 /// instructions for SelectionDAG operations.
58 AM2_BASE, // Simple AM2 (+-imm12)
59 AM2_SHOP // Shifter-op AM2
62 class ARMDAGToDAGISel : public SelectionDAGISel {
63 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
64 /// make the right decision when generating code for different targets.
65 const ARMSubtarget *Subtarget;
68 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
69 : SelectionDAGISel(tm, OptLevel) {}
71 bool runOnMachineFunction(MachineFunction &MF) override {
72 // Reset the subtarget each time through.
73 Subtarget = &MF.getTarget().getSubtarget<ARMSubtarget>();
74 SelectionDAGISel::runOnMachineFunction(MF);
78 const char *getPassName() const override {
79 return "ARM Instruction Selection";
82 void PreprocessISelDAG() override;
84 /// getI32Imm - Return a target constant of type i32 with the specified
86 inline SDValue getI32Imm(unsigned Imm) {
87 return CurDAG->getTargetConstant(Imm, MVT::i32);
90 SDNode *Select(SDNode *N) override;
93 bool hasNoVMLxHazardUse(SDNode *N) const;
94 bool isShifterOpProfitable(const SDValue &Shift,
95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
96 bool SelectRegShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, SDValue &C,
98 bool CheckProfitability = true);
99 bool SelectImmShifterOperand(SDValue N, SDValue &A,
100 SDValue &B, bool CheckProfitability = true);
101 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
102 SDValue &B, SDValue &C) {
103 // Don't apply the profitability check
104 return SelectRegShifterOperand(N, A, B, C, false);
106 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
108 // Don't apply the profitability check
109 return SelectImmShifterOperand(N, A, B, false);
112 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
113 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
115 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
116 SDValue &Offset, SDValue &Opc);
117 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
119 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
124 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
129 SelectAddrMode2Worker(N, Base, Offset, Opc);
130 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
131 // This always matches one way or another.
135 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
136 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
137 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
138 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
142 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
143 SDValue &Offset, SDValue &Opc);
144 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
145 SDValue &Offset, SDValue &Opc);
146 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
147 SDValue &Offset, SDValue &Opc);
148 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
149 bool SelectAddrMode3(SDValue N, SDValue &Base,
150 SDValue &Offset, SDValue &Opc);
151 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
152 SDValue &Offset, SDValue &Opc);
153 bool SelectAddrMode5(SDValue N, SDValue &Base,
155 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
156 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
158 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
160 // Thumb Addressing Modes:
161 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
162 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
164 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
165 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
166 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
167 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
169 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
171 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
173 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
175 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
177 // Thumb 2 Addressing Modes:
178 bool SelectT2ShifterOperandReg(SDValue N,
179 SDValue &BaseReg, SDValue &Opc);
180 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
181 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
183 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
185 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
186 SDValue &OffReg, SDValue &ShImm);
187 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
189 inline bool is_so_imm(unsigned Imm) const {
190 return ARM_AM::getSOImmVal(Imm) != -1;
193 inline bool is_so_imm_not(unsigned Imm) const {
194 return ARM_AM::getSOImmVal(~Imm) != -1;
197 inline bool is_t2_so_imm(unsigned Imm) const {
198 return ARM_AM::getT2SOImmVal(Imm) != -1;
201 inline bool is_t2_so_imm_not(unsigned Imm) const {
202 return ARM_AM::getT2SOImmVal(~Imm) != -1;
205 // Include the pieces autogenerated from the target description.
206 #include "ARMGenDAGISel.inc"
209 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
211 SDNode *SelectARMIndexedLoad(SDNode *N);
212 SDNode *SelectT2IndexedLoad(SDNode *N);
214 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
215 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
216 /// loads of D registers and even subregs and odd subregs of Q registers.
217 /// For NumVecs <= 2, QOpcodes1 is not used.
218 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
219 const uint16_t *DOpcodes,
220 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
222 /// SelectVST - Select NEON store intrinsics. NumVecs should
223 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
224 /// stores of D registers and even subregs and odd subregs of Q registers.
225 /// For NumVecs <= 2, QOpcodes1 is not used.
226 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
227 const uint16_t *DOpcodes,
228 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
230 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
231 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
232 /// load/store of D registers and Q registers.
233 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
234 bool isUpdating, unsigned NumVecs,
235 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
237 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
238 /// should be 2, 3 or 4. The opcode array specifies the instructions used
239 /// for loading D registers. (Q registers are not supported.)
240 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
241 const uint16_t *Opcodes);
243 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
244 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
245 /// generated to force the table registers to be consecutive.
246 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
248 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
249 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
251 // Select special operations if node forms integer ABS pattern
252 SDNode *SelectABSOp(SDNode *N);
254 SDNode *SelectInlineAsm(SDNode *N);
256 SDNode *SelectConcatVector(SDNode *N);
258 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
259 /// inline asm expressions.
260 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
261 std::vector<SDValue> &OutOps) override;
263 // Form pairs of consecutive R, S, D, or Q registers.
264 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
265 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
266 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
267 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
269 // Form sequences of 4 consecutive S, D, or Q registers.
270 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
271 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
274 // Get the alignment operand for a NEON VLD or VST instruction.
275 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
279 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
280 /// operand. If so Imm will receive the 32-bit value.
281 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
282 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
283 Imm = cast<ConstantSDNode>(N)->getZExtValue();
289 // isInt32Immediate - This method tests to see if a constant operand.
290 // If so Imm will receive the 32 bit value.
291 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
292 return isInt32Immediate(N.getNode(), Imm);
295 // isOpcWithIntImmediate - This method tests to see if the node is a specific
296 // opcode and that it has a immediate integer right operand.
297 // If so Imm will receive the 32 bit value.
298 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
299 return N->getOpcode() == Opc &&
300 isInt32Immediate(N->getOperand(1).getNode(), Imm);
303 /// \brief Check whether a particular node is a constant value representable as
304 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
306 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
307 static bool isScaledConstantInRange(SDValue Node, int Scale,
308 int RangeMin, int RangeMax,
309 int &ScaledConstant) {
310 assert(Scale > 0 && "Invalid scale!");
312 // Check that this is a constant.
313 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
317 ScaledConstant = (int) C->getZExtValue();
318 if ((ScaledConstant % Scale) != 0)
321 ScaledConstant /= Scale;
322 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
325 void ARMDAGToDAGISel::PreprocessISelDAG() {
326 if (!Subtarget->hasV6T2Ops())
329 bool isThumb2 = Subtarget->isThumb();
330 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
331 E = CurDAG->allnodes_end(); I != E; ) {
332 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
334 if (N->getOpcode() != ISD::ADD)
337 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
338 // leading zeros, followed by consecutive set bits, followed by 1 or 2
339 // trailing zeros, e.g. 1020.
340 // Transform the expression to
341 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
342 // of trailing zeros of c2. The left shift would be folded as an shifter
343 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
346 SDValue N0 = N->getOperand(0);
347 SDValue N1 = N->getOperand(1);
348 unsigned And_imm = 0;
349 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
350 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
356 // Check if the AND mask is an immediate of the form: 000.....1111111100
357 unsigned TZ = countTrailingZeros(And_imm);
358 if (TZ != 1 && TZ != 2)
359 // Be conservative here. Shifter operands aren't always free. e.g. On
360 // Swift, left shifter operand of 1 / 2 for free but others are not.
362 // ubfx r3, r1, #16, #8
363 // ldr.w r3, [r0, r3, lsl #2]
366 // and.w r2, r9, r1, lsr #14
370 if (And_imm & (And_imm + 1))
373 // Look for (and (srl X, c1), c2).
374 SDValue Srl = N1.getOperand(0);
375 unsigned Srl_imm = 0;
376 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
380 // Make sure first operand is not a shifter operand which would prevent
381 // folding of the left shift.
386 if (SelectT2ShifterOperandReg(N0, CPTmp0, CPTmp1))
389 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
390 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
394 // Now make the transformation.
395 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
397 CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
398 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
399 Srl, CurDAG->getConstant(And_imm, MVT::i32));
400 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
401 N1, CurDAG->getConstant(TZ, MVT::i32));
402 CurDAG->UpdateNodeOperands(N, N0, N1);
406 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
407 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
408 /// least on current ARM implementations) which should be avoidded.
409 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
410 if (OptLevel == CodeGenOpt::None)
413 if (!CheckVMLxHazard)
416 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
417 !Subtarget->isCortexA9() && !Subtarget->isSwift())
423 SDNode *Use = *N->use_begin();
424 if (Use->getOpcode() == ISD::CopyToReg)
426 if (Use->isMachineOpcode()) {
427 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
428 CurDAG->getSubtarget().getInstrInfo());
430 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
433 unsigned Opcode = MCID.getOpcode();
434 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
436 // vmlx feeding into another vmlx. We actually want to unfold
437 // the use later in the MLxExpansion pass. e.g.
439 // vmla (stall 8 cycles)
444 // This adds up to about 18 - 19 cycles.
447 // vmul (stall 4 cycles)
448 // vadd adds up to about 14 cycles.
449 return TII->isFpMLxInstruction(Opcode);
455 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
456 ARM_AM::ShiftOpc ShOpcVal,
458 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
460 if (Shift.hasOneUse())
463 return ShOpcVal == ARM_AM::lsl &&
464 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
467 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
470 bool CheckProfitability) {
471 if (DisableShifterOp)
474 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
476 // Don't match base register only case. That is matched to a separate
477 // lower complexity pattern with explicit register operand.
478 if (ShOpcVal == ARM_AM::no_shift) return false;
480 BaseReg = N.getOperand(0);
481 unsigned ShImmVal = 0;
482 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
483 if (!RHS) return false;
484 ShImmVal = RHS->getZExtValue() & 31;
485 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
490 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
494 bool CheckProfitability) {
495 if (DisableShifterOp)
498 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
500 // Don't match base register only case. That is matched to a separate
501 // lower complexity pattern with explicit register operand.
502 if (ShOpcVal == ARM_AM::no_shift) return false;
504 BaseReg = N.getOperand(0);
505 unsigned ShImmVal = 0;
506 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
507 if (RHS) return false;
509 ShReg = N.getOperand(1);
510 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
512 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
518 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
521 // Match simple R + imm12 operands.
524 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
525 !CurDAG->isBaseWithConstantOffset(N)) {
526 if (N.getOpcode() == ISD::FrameIndex) {
527 // Match frame index.
528 int FI = cast<FrameIndexSDNode>(N)->getIndex();
529 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
530 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
534 if (N.getOpcode() == ARMISD::Wrapper &&
535 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
536 Base = N.getOperand(0);
539 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
543 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
544 int RHSC = (int)RHS->getSExtValue();
545 if (N.getOpcode() == ISD::SUB)
548 if (RHSC > -0x1000 && RHSC < 0x1000) { // 12 bits
549 Base = N.getOperand(0);
550 if (Base.getOpcode() == ISD::FrameIndex) {
551 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
552 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
554 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
561 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
567 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
569 if (N.getOpcode() == ISD::MUL &&
570 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
571 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
572 // X * [3,5,9] -> X + X * [2,4,8] etc.
573 int RHSC = (int)RHS->getZExtValue();
576 ARM_AM::AddrOpc AddSub = ARM_AM::add;
578 AddSub = ARM_AM::sub;
581 if (isPowerOf2_32(RHSC)) {
582 unsigned ShAmt = Log2_32(RHSC);
583 Base = Offset = N.getOperand(0);
584 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
593 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
594 // ISD::OR that is equivalent to an ISD::ADD.
595 !CurDAG->isBaseWithConstantOffset(N))
598 // Leave simple R +/- imm12 operands for LDRi12
599 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
601 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
602 -0x1000+1, 0x1000, RHSC)) // 12 bits.
606 // Otherwise this is R +/- [possibly shifted] R.
607 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
608 ARM_AM::ShiftOpc ShOpcVal =
609 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
612 Base = N.getOperand(0);
613 Offset = N.getOperand(1);
615 if (ShOpcVal != ARM_AM::no_shift) {
616 // Check to see if the RHS of the shift is a constant, if not, we can't fold
618 if (ConstantSDNode *Sh =
619 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
620 ShAmt = Sh->getZExtValue();
621 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
622 Offset = N.getOperand(1).getOperand(0);
625 ShOpcVal = ARM_AM::no_shift;
628 ShOpcVal = ARM_AM::no_shift;
632 // Try matching (R shl C) + (R).
633 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
634 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
635 N.getOperand(0).hasOneUse())) {
636 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
637 if (ShOpcVal != ARM_AM::no_shift) {
638 // Check to see if the RHS of the shift is a constant, if not, we can't
640 if (ConstantSDNode *Sh =
641 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
642 ShAmt = Sh->getZExtValue();
643 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
644 Offset = N.getOperand(0).getOperand(0);
645 Base = N.getOperand(1);
648 ShOpcVal = ARM_AM::no_shift;
651 ShOpcVal = ARM_AM::no_shift;
656 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
664 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
668 if (N.getOpcode() == ISD::MUL &&
669 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
670 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
671 // X * [3,5,9] -> X + X * [2,4,8] etc.
672 int RHSC = (int)RHS->getZExtValue();
675 ARM_AM::AddrOpc AddSub = ARM_AM::add;
677 AddSub = ARM_AM::sub;
680 if (isPowerOf2_32(RHSC)) {
681 unsigned ShAmt = Log2_32(RHSC);
682 Base = Offset = N.getOperand(0);
683 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
692 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
693 // ISD::OR that is equivalent to an ADD.
694 !CurDAG->isBaseWithConstantOffset(N)) {
696 if (N.getOpcode() == ISD::FrameIndex) {
697 int FI = cast<FrameIndexSDNode>(N)->getIndex();
698 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
699 } else if (N.getOpcode() == ARMISD::Wrapper &&
700 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
701 Base = N.getOperand(0);
703 Offset = CurDAG->getRegister(0, MVT::i32);
704 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
710 // Match simple R +/- imm12 operands.
711 if (N.getOpcode() != ISD::SUB) {
713 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
714 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
715 Base = N.getOperand(0);
716 if (Base.getOpcode() == ISD::FrameIndex) {
717 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
718 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
720 Offset = CurDAG->getRegister(0, MVT::i32);
722 ARM_AM::AddrOpc AddSub = ARM_AM::add;
724 AddSub = ARM_AM::sub;
727 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
734 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
735 // Compute R +/- (R << N) and reuse it.
737 Offset = CurDAG->getRegister(0, MVT::i32);
738 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
744 // Otherwise this is R +/- [possibly shifted] R.
745 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
746 ARM_AM::ShiftOpc ShOpcVal =
747 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
750 Base = N.getOperand(0);
751 Offset = N.getOperand(1);
753 if (ShOpcVal != ARM_AM::no_shift) {
754 // Check to see if the RHS of the shift is a constant, if not, we can't fold
756 if (ConstantSDNode *Sh =
757 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
758 ShAmt = Sh->getZExtValue();
759 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
760 Offset = N.getOperand(1).getOperand(0);
763 ShOpcVal = ARM_AM::no_shift;
766 ShOpcVal = ARM_AM::no_shift;
770 // Try matching (R shl C) + (R).
771 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
772 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
773 N.getOperand(0).hasOneUse())) {
774 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
775 if (ShOpcVal != ARM_AM::no_shift) {
776 // Check to see if the RHS of the shift is a constant, if not, we can't
778 if (ConstantSDNode *Sh =
779 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
780 ShAmt = Sh->getZExtValue();
781 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
782 Offset = N.getOperand(0).getOperand(0);
783 Base = N.getOperand(1);
786 ShOpcVal = ARM_AM::no_shift;
789 ShOpcVal = ARM_AM::no_shift;
794 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
799 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
800 SDValue &Offset, SDValue &Opc) {
801 unsigned Opcode = Op->getOpcode();
802 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
803 ? cast<LoadSDNode>(Op)->getAddressingMode()
804 : cast<StoreSDNode>(Op)->getAddressingMode();
805 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
806 ? ARM_AM::add : ARM_AM::sub;
808 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
812 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
814 if (ShOpcVal != ARM_AM::no_shift) {
815 // Check to see if the RHS of the shift is a constant, if not, we can't fold
817 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
818 ShAmt = Sh->getZExtValue();
819 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
820 Offset = N.getOperand(0);
823 ShOpcVal = ARM_AM::no_shift;
826 ShOpcVal = ARM_AM::no_shift;
830 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
835 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
836 SDValue &Offset, SDValue &Opc) {
837 unsigned Opcode = Op->getOpcode();
838 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
839 ? cast<LoadSDNode>(Op)->getAddressingMode()
840 : cast<StoreSDNode>(Op)->getAddressingMode();
841 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
842 ? ARM_AM::add : ARM_AM::sub;
844 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
845 if (AddSub == ARM_AM::sub) Val *= -1;
846 Offset = CurDAG->getRegister(0, MVT::i32);
847 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
855 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
856 SDValue &Offset, SDValue &Opc) {
857 unsigned Opcode = Op->getOpcode();
858 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
859 ? cast<LoadSDNode>(Op)->getAddressingMode()
860 : cast<StoreSDNode>(Op)->getAddressingMode();
861 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
862 ? ARM_AM::add : ARM_AM::sub;
864 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
865 Offset = CurDAG->getRegister(0, MVT::i32);
866 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
875 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
880 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
881 SDValue &Base, SDValue &Offset,
883 if (N.getOpcode() == ISD::SUB) {
884 // X - C is canonicalize to X + -C, no need to handle it here.
885 Base = N.getOperand(0);
886 Offset = N.getOperand(1);
887 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
891 if (!CurDAG->isBaseWithConstantOffset(N)) {
893 if (N.getOpcode() == ISD::FrameIndex) {
894 int FI = cast<FrameIndexSDNode>(N)->getIndex();
895 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
897 Offset = CurDAG->getRegister(0, MVT::i32);
898 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
902 // If the RHS is +/- imm8, fold into addr mode.
904 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
905 -256 + 1, 256, RHSC)) { // 8 bits.
906 Base = N.getOperand(0);
907 if (Base.getOpcode() == ISD::FrameIndex) {
908 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
909 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
911 Offset = CurDAG->getRegister(0, MVT::i32);
913 ARM_AM::AddrOpc AddSub = ARM_AM::add;
915 AddSub = ARM_AM::sub;
918 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
922 Base = N.getOperand(0);
923 Offset = N.getOperand(1);
924 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
928 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
929 SDValue &Offset, SDValue &Opc) {
930 unsigned Opcode = Op->getOpcode();
931 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
932 ? cast<LoadSDNode>(Op)->getAddressingMode()
933 : cast<StoreSDNode>(Op)->getAddressingMode();
934 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
935 ? ARM_AM::add : ARM_AM::sub;
937 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
938 Offset = CurDAG->getRegister(0, MVT::i32);
939 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
944 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
948 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
949 SDValue &Base, SDValue &Offset) {
950 if (!CurDAG->isBaseWithConstantOffset(N)) {
952 if (N.getOpcode() == ISD::FrameIndex) {
953 int FI = cast<FrameIndexSDNode>(N)->getIndex();
954 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
955 } else if (N.getOpcode() == ARMISD::Wrapper &&
956 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
957 Base = N.getOperand(0);
959 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
964 // If the RHS is +/- imm8, fold into addr mode.
966 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
967 -256 + 1, 256, RHSC)) {
968 Base = N.getOperand(0);
969 if (Base.getOpcode() == ISD::FrameIndex) {
970 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
971 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
974 ARM_AM::AddrOpc AddSub = ARM_AM::add;
976 AddSub = ARM_AM::sub;
979 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
985 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
990 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
994 unsigned Alignment = 0;
995 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
996 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
997 // The maximum alignment is equal to the memory size being referenced.
998 unsigned LSNAlign = LSN->getAlignment();
999 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
1000 if (LSNAlign >= MemSize && MemSize > 1)
1001 Alignment = MemSize;
1003 // All other uses of addrmode6 are for intrinsics. For now just record
1004 // the raw alignment value; it will be refined later based on the legal
1005 // alignment operands for the intrinsic.
1006 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
1009 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1013 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1015 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1016 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1017 if (AM != ISD::POST_INC)
1020 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1021 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1022 Offset = CurDAG->getRegister(0, MVT::i32);
1027 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1028 SDValue &Offset, SDValue &Label) {
1029 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1030 Offset = N.getOperand(0);
1031 SDValue N1 = N.getOperand(1);
1032 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1041 //===----------------------------------------------------------------------===//
1042 // Thumb Addressing Modes
1043 //===----------------------------------------------------------------------===//
1045 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1046 SDValue &Base, SDValue &Offset){
1047 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1048 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1049 if (!NC || !NC->isNullValue())
1056 Base = N.getOperand(0);
1057 Offset = N.getOperand(1);
1062 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
1063 SDValue &Offset, unsigned Scale) {
1065 SDValue TmpBase, TmpOffImm;
1066 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1067 return false; // We want to select tLDRspi / tSTRspi instead.
1069 if (N.getOpcode() == ARMISD::Wrapper &&
1070 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1071 return false; // We want to select tLDRpci instead.
1074 if (!CurDAG->isBaseWithConstantOffset(N))
1077 // Thumb does not have [sp, r] address mode.
1078 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1079 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1080 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1081 (RHSR && RHSR->getReg() == ARM::SP))
1084 // FIXME: Why do we explicitly check for a match here and then return false?
1085 // Presumably to allow something else to match, but shouldn't this be
1088 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1091 Base = N.getOperand(0);
1092 Offset = N.getOperand(1);
1097 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1100 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1104 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1107 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1111 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1114 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1118 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1119 SDValue &Base, SDValue &OffImm) {
1121 SDValue TmpBase, TmpOffImm;
1122 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1123 return false; // We want to select tLDRspi / tSTRspi instead.
1125 if (N.getOpcode() == ARMISD::Wrapper &&
1126 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1127 return false; // We want to select tLDRpci instead.
1130 if (!CurDAG->isBaseWithConstantOffset(N)) {
1131 if (N.getOpcode() == ARMISD::Wrapper &&
1132 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1133 Base = N.getOperand(0);
1138 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1142 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1143 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1144 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1145 (RHSR && RHSR->getReg() == ARM::SP)) {
1146 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1147 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1148 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1149 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1151 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1152 if (LHSC != 0 || RHSC != 0) return false;
1155 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1159 // If the RHS is + imm5 * scale, fold into addr mode.
1161 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1162 Base = N.getOperand(0);
1163 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1167 Base = N.getOperand(0);
1168 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1173 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1175 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1179 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1181 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1185 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1187 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1190 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1191 SDValue &Base, SDValue &OffImm) {
1192 if (N.getOpcode() == ISD::FrameIndex) {
1193 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1194 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1195 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1199 if (!CurDAG->isBaseWithConstantOffset(N))
1202 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1203 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1204 (LHSR && LHSR->getReg() == ARM::SP)) {
1205 // If the RHS is + imm8 * scale, fold into addr mode.
1207 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1208 Base = N.getOperand(0);
1209 if (Base.getOpcode() == ISD::FrameIndex) {
1210 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1211 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1213 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1222 //===----------------------------------------------------------------------===//
1223 // Thumb 2 Addressing Modes
1224 //===----------------------------------------------------------------------===//
1227 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1229 if (DisableShifterOp)
1232 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1234 // Don't match base register only case. That is matched to a separate
1235 // lower complexity pattern with explicit register operand.
1236 if (ShOpcVal == ARM_AM::no_shift) return false;
1238 BaseReg = N.getOperand(0);
1239 unsigned ShImmVal = 0;
1240 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1241 ShImmVal = RHS->getZExtValue() & 31;
1242 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1249 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1250 SDValue &Base, SDValue &OffImm) {
1251 // Match simple R + imm12 operands.
1254 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1255 !CurDAG->isBaseWithConstantOffset(N)) {
1256 if (N.getOpcode() == ISD::FrameIndex) {
1257 // Match frame index.
1258 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1259 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1260 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1264 if (N.getOpcode() == ARMISD::Wrapper &&
1265 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1266 Base = N.getOperand(0);
1267 if (Base.getOpcode() == ISD::TargetConstantPool)
1268 return false; // We want to select t2LDRpci instead.
1271 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1275 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1276 if (SelectT2AddrModeImm8(N, Base, OffImm))
1277 // Let t2LDRi8 handle (R - imm8).
1280 int RHSC = (int)RHS->getZExtValue();
1281 if (N.getOpcode() == ISD::SUB)
1284 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1285 Base = N.getOperand(0);
1286 if (Base.getOpcode() == ISD::FrameIndex) {
1287 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1288 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1290 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1297 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1301 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1302 SDValue &Base, SDValue &OffImm) {
1303 // Match simple R - imm8 operands.
1304 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1305 !CurDAG->isBaseWithConstantOffset(N))
1308 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1309 int RHSC = (int)RHS->getSExtValue();
1310 if (N.getOpcode() == ISD::SUB)
1313 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1314 Base = N.getOperand(0);
1315 if (Base.getOpcode() == ISD::FrameIndex) {
1316 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1317 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1319 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1327 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1329 unsigned Opcode = Op->getOpcode();
1330 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1331 ? cast<LoadSDNode>(Op)->getAddressingMode()
1332 : cast<StoreSDNode>(Op)->getAddressingMode();
1334 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1335 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1336 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1337 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1344 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1346 SDValue &OffReg, SDValue &ShImm) {
1347 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1348 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1351 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1352 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1353 int RHSC = (int)RHS->getZExtValue();
1354 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1356 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1360 // Look for (R + R) or (R + (R << [1,2,3])).
1362 Base = N.getOperand(0);
1363 OffReg = N.getOperand(1);
1365 // Swap if it is ((R << c) + R).
1366 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1367 if (ShOpcVal != ARM_AM::lsl) {
1368 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1369 if (ShOpcVal == ARM_AM::lsl)
1370 std::swap(Base, OffReg);
1373 if (ShOpcVal == ARM_AM::lsl) {
1374 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1376 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1377 ShAmt = Sh->getZExtValue();
1378 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1379 OffReg = OffReg.getOperand(0);
1382 ShOpcVal = ARM_AM::no_shift;
1385 ShOpcVal = ARM_AM::no_shift;
1389 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1394 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1396 // This *must* succeed since it's used for the irreplaceable ldrex and strex
1399 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1401 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1404 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1408 uint32_t RHSC = (int)RHS->getZExtValue();
1409 if (RHSC > 1020 || RHSC % 4 != 0)
1412 Base = N.getOperand(0);
1413 if (Base.getOpcode() == ISD::FrameIndex) {
1414 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1415 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1418 OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
1422 //===--------------------------------------------------------------------===//
1424 /// getAL - Returns a ARMCC::AL immediate node.
1425 static inline SDValue getAL(SelectionDAG *CurDAG) {
1426 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1429 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1430 LoadSDNode *LD = cast<LoadSDNode>(N);
1431 ISD::MemIndexedMode AM = LD->getAddressingMode();
1432 if (AM == ISD::UNINDEXED)
1435 EVT LoadedVT = LD->getMemoryVT();
1436 SDValue Offset, AMOpc;
1437 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1438 unsigned Opcode = 0;
1440 if (LoadedVT == MVT::i32 && isPre &&
1441 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1442 Opcode = ARM::LDR_PRE_IMM;
1444 } else if (LoadedVT == MVT::i32 && !isPre &&
1445 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1446 Opcode = ARM::LDR_POST_IMM;
1448 } else if (LoadedVT == MVT::i32 &&
1449 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1450 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1453 } else if (LoadedVT == MVT::i16 &&
1454 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1456 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1457 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1458 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1459 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1460 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1461 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1463 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1467 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1469 Opcode = ARM::LDRB_PRE_IMM;
1470 } else if (!isPre &&
1471 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1473 Opcode = ARM::LDRB_POST_IMM;
1474 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1476 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1482 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1483 SDValue Chain = LD->getChain();
1484 SDValue Base = LD->getBasePtr();
1485 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1486 CurDAG->getRegister(0, MVT::i32), Chain };
1487 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1488 MVT::i32, MVT::Other, Ops);
1490 SDValue Chain = LD->getChain();
1491 SDValue Base = LD->getBasePtr();
1492 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1493 CurDAG->getRegister(0, MVT::i32), Chain };
1494 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1495 MVT::i32, MVT::Other, Ops);
1502 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1503 LoadSDNode *LD = cast<LoadSDNode>(N);
1504 ISD::MemIndexedMode AM = LD->getAddressingMode();
1505 if (AM == ISD::UNINDEXED)
1508 EVT LoadedVT = LD->getMemoryVT();
1509 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1511 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1512 unsigned Opcode = 0;
1514 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1515 switch (LoadedVT.getSimpleVT().SimpleTy) {
1517 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1521 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1523 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1528 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1530 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1539 SDValue Chain = LD->getChain();
1540 SDValue Base = LD->getBasePtr();
1541 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1542 CurDAG->getRegister(0, MVT::i32), Chain };
1543 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1550 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1551 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1552 SDLoc dl(V0.getNode());
1554 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1555 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1556 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1557 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1558 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1561 /// \brief Form a D register from a pair of S registers.
1562 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1563 SDLoc dl(V0.getNode());
1565 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1566 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1567 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1568 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1569 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1572 /// \brief Form a quad register from a pair of D registers.
1573 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1574 SDLoc dl(V0.getNode());
1575 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1576 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1577 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1578 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1579 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1582 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1583 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1584 SDLoc dl(V0.getNode());
1585 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1586 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1587 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1588 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1589 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1592 /// \brief Form 4 consecutive S registers.
1593 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1594 SDValue V2, SDValue V3) {
1595 SDLoc dl(V0.getNode());
1597 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1598 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1599 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1600 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1601 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1602 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1603 V2, SubReg2, V3, SubReg3 };
1604 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1607 /// \brief Form 4 consecutive D registers.
1608 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1609 SDValue V2, SDValue V3) {
1610 SDLoc dl(V0.getNode());
1611 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1612 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1613 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1614 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1615 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1616 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1617 V2, SubReg2, V3, SubReg3 };
1618 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1621 /// \brief Form 4 consecutive Q registers.
1622 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1623 SDValue V2, SDValue V3) {
1624 SDLoc dl(V0.getNode());
1625 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1626 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1627 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1628 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1629 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1630 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1631 V2, SubReg2, V3, SubReg3 };
1632 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1635 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1636 /// of a NEON VLD or VST instruction. The supported values depend on the
1637 /// number of registers being loaded.
1638 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1639 bool is64BitVector) {
1640 unsigned NumRegs = NumVecs;
1641 if (!is64BitVector && NumVecs < 3)
1644 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1645 if (Alignment >= 32 && NumRegs == 4)
1647 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1649 else if (Alignment >= 8)
1654 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1657 static bool isVLDfixed(unsigned Opc)
1660 default: return false;
1661 case ARM::VLD1d8wb_fixed : return true;
1662 case ARM::VLD1d16wb_fixed : return true;
1663 case ARM::VLD1d64Qwb_fixed : return true;
1664 case ARM::VLD1d32wb_fixed : return true;
1665 case ARM::VLD1d64wb_fixed : return true;
1666 case ARM::VLD1d64TPseudoWB_fixed : return true;
1667 case ARM::VLD1d64QPseudoWB_fixed : return true;
1668 case ARM::VLD1q8wb_fixed : return true;
1669 case ARM::VLD1q16wb_fixed : return true;
1670 case ARM::VLD1q32wb_fixed : return true;
1671 case ARM::VLD1q64wb_fixed : return true;
1672 case ARM::VLD2d8wb_fixed : return true;
1673 case ARM::VLD2d16wb_fixed : return true;
1674 case ARM::VLD2d32wb_fixed : return true;
1675 case ARM::VLD2q8PseudoWB_fixed : return true;
1676 case ARM::VLD2q16PseudoWB_fixed : return true;
1677 case ARM::VLD2q32PseudoWB_fixed : return true;
1678 case ARM::VLD2DUPd8wb_fixed : return true;
1679 case ARM::VLD2DUPd16wb_fixed : return true;
1680 case ARM::VLD2DUPd32wb_fixed : return true;
1684 static bool isVSTfixed(unsigned Opc)
1687 default: return false;
1688 case ARM::VST1d8wb_fixed : return true;
1689 case ARM::VST1d16wb_fixed : return true;
1690 case ARM::VST1d32wb_fixed : return true;
1691 case ARM::VST1d64wb_fixed : return true;
1692 case ARM::VST1q8wb_fixed : return true;
1693 case ARM::VST1q16wb_fixed : return true;
1694 case ARM::VST1q32wb_fixed : return true;
1695 case ARM::VST1q64wb_fixed : return true;
1696 case ARM::VST1d64TPseudoWB_fixed : return true;
1697 case ARM::VST1d64QPseudoWB_fixed : return true;
1698 case ARM::VST2d8wb_fixed : return true;
1699 case ARM::VST2d16wb_fixed : return true;
1700 case ARM::VST2d32wb_fixed : return true;
1701 case ARM::VST2q8PseudoWB_fixed : return true;
1702 case ARM::VST2q16PseudoWB_fixed : return true;
1703 case ARM::VST2q32PseudoWB_fixed : return true;
1707 // Get the register stride update opcode of a VLD/VST instruction that
1708 // is otherwise equivalent to the given fixed stride updating instruction.
1709 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1710 assert((isVLDfixed(Opc) || isVSTfixed(Opc))
1711 && "Incorrect fixed stride updating instruction.");
1714 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1715 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1716 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1717 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1718 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1719 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1720 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1721 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1722 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1723 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1724 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1725 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1727 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1728 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1729 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1730 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1731 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1732 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1733 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1734 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1735 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1736 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1738 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1739 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1740 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1741 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1742 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1743 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1745 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1746 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1747 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1748 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1749 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1750 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1752 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1753 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1754 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1756 return Opc; // If not one we handle, return it unchanged.
1759 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1760 const uint16_t *DOpcodes,
1761 const uint16_t *QOpcodes0,
1762 const uint16_t *QOpcodes1) {
1763 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1766 SDValue MemAddr, Align;
1767 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1768 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1771 SDValue Chain = N->getOperand(0);
1772 EVT VT = N->getValueType(0);
1773 bool is64BitVector = VT.is64BitVector();
1774 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1776 unsigned OpcodeIndex;
1777 switch (VT.getSimpleVT().SimpleTy) {
1778 default: llvm_unreachable("unhandled vld type");
1779 // Double-register operations:
1780 case MVT::v8i8: OpcodeIndex = 0; break;
1781 case MVT::v4i16: OpcodeIndex = 1; break;
1783 case MVT::v2i32: OpcodeIndex = 2; break;
1784 case MVT::v1i64: OpcodeIndex = 3; break;
1785 // Quad-register operations:
1786 case MVT::v16i8: OpcodeIndex = 0; break;
1787 case MVT::v8i16: OpcodeIndex = 1; break;
1789 case MVT::v4i32: OpcodeIndex = 2; break;
1790 case MVT::v2i64: OpcodeIndex = 3;
1791 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1799 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1802 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1804 std::vector<EVT> ResTys;
1805 ResTys.push_back(ResTy);
1807 ResTys.push_back(MVT::i32);
1808 ResTys.push_back(MVT::Other);
1810 SDValue Pred = getAL(CurDAG);
1811 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1813 SmallVector<SDValue, 7> Ops;
1815 // Double registers and VLD1/VLD2 quad registers are directly supported.
1816 if (is64BitVector || NumVecs <= 2) {
1817 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1818 QOpcodes0[OpcodeIndex]);
1819 Ops.push_back(MemAddr);
1820 Ops.push_back(Align);
1822 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1823 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1824 // case entirely when the rest are updated to that form, too.
1825 if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
1826 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1827 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1828 // check for that explicitly too. Horribly hacky, but temporary.
1829 if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
1830 !isa<ConstantSDNode>(Inc.getNode()))
1831 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1833 Ops.push_back(Pred);
1834 Ops.push_back(Reg0);
1835 Ops.push_back(Chain);
1836 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1839 // Otherwise, quad registers are loaded with two separate instructions,
1840 // where one loads the even registers and the other loads the odd registers.
1841 EVT AddrTy = MemAddr.getValueType();
1843 // Load the even subregs. This is always an updating load, so that it
1844 // provides the address to the second load for the odd subregs.
1846 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1847 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1848 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1849 ResTy, AddrTy, MVT::Other, OpsA);
1850 Chain = SDValue(VLdA, 2);
1852 // Load the odd subregs.
1853 Ops.push_back(SDValue(VLdA, 1));
1854 Ops.push_back(Align);
1856 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1857 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1858 "only constant post-increment update allowed for VLD3/4");
1860 Ops.push_back(Reg0);
1862 Ops.push_back(SDValue(VLdA, 0));
1863 Ops.push_back(Pred);
1864 Ops.push_back(Reg0);
1865 Ops.push_back(Chain);
1866 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1869 // Transfer memoperands.
1870 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1871 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1872 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1877 // Extract out the subregisters.
1878 SDValue SuperReg = SDValue(VLd, 0);
1879 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1880 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1881 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1882 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1883 ReplaceUses(SDValue(N, Vec),
1884 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1885 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1887 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1891 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1892 const uint16_t *DOpcodes,
1893 const uint16_t *QOpcodes0,
1894 const uint16_t *QOpcodes1) {
1895 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1898 SDValue MemAddr, Align;
1899 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1900 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1901 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1904 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1905 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1907 SDValue Chain = N->getOperand(0);
1908 EVT VT = N->getOperand(Vec0Idx).getValueType();
1909 bool is64BitVector = VT.is64BitVector();
1910 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1912 unsigned OpcodeIndex;
1913 switch (VT.getSimpleVT().SimpleTy) {
1914 default: llvm_unreachable("unhandled vst type");
1915 // Double-register operations:
1916 case MVT::v8i8: OpcodeIndex = 0; break;
1917 case MVT::v4i16: OpcodeIndex = 1; break;
1919 case MVT::v2i32: OpcodeIndex = 2; break;
1920 case MVT::v1i64: OpcodeIndex = 3; break;
1921 // Quad-register operations:
1922 case MVT::v16i8: OpcodeIndex = 0; break;
1923 case MVT::v8i16: OpcodeIndex = 1; break;
1925 case MVT::v4i32: OpcodeIndex = 2; break;
1926 case MVT::v2i64: OpcodeIndex = 3;
1927 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1931 std::vector<EVT> ResTys;
1933 ResTys.push_back(MVT::i32);
1934 ResTys.push_back(MVT::Other);
1936 SDValue Pred = getAL(CurDAG);
1937 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1938 SmallVector<SDValue, 7> Ops;
1940 // Double registers and VST1/VST2 quad registers are directly supported.
1941 if (is64BitVector || NumVecs <= 2) {
1944 SrcReg = N->getOperand(Vec0Idx);
1945 } else if (is64BitVector) {
1946 // Form a REG_SEQUENCE to force register allocation.
1947 SDValue V0 = N->getOperand(Vec0Idx + 0);
1948 SDValue V1 = N->getOperand(Vec0Idx + 1);
1950 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1952 SDValue V2 = N->getOperand(Vec0Idx + 2);
1953 // If it's a vst3, form a quad D-register and leave the last part as
1955 SDValue V3 = (NumVecs == 3)
1956 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1957 : N->getOperand(Vec0Idx + 3);
1958 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1961 // Form a QQ register.
1962 SDValue Q0 = N->getOperand(Vec0Idx);
1963 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1964 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1967 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1968 QOpcodes0[OpcodeIndex]);
1969 Ops.push_back(MemAddr);
1970 Ops.push_back(Align);
1972 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1973 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1974 // case entirely when the rest are updated to that form, too.
1975 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1976 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1977 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1978 // check for that explicitly too. Horribly hacky, but temporary.
1979 if (!isa<ConstantSDNode>(Inc.getNode()))
1981 else if (NumVecs > 2 && !isVSTfixed(Opc))
1982 Ops.push_back(Reg0);
1984 Ops.push_back(SrcReg);
1985 Ops.push_back(Pred);
1986 Ops.push_back(Reg0);
1987 Ops.push_back(Chain);
1988 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1990 // Transfer memoperands.
1991 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1996 // Otherwise, quad registers are stored with two separate instructions,
1997 // where one stores the even registers and the other stores the odd registers.
1999 // Form the QQQQ REG_SEQUENCE.
2000 SDValue V0 = N->getOperand(Vec0Idx + 0);
2001 SDValue V1 = N->getOperand(Vec0Idx + 1);
2002 SDValue V2 = N->getOperand(Vec0Idx + 2);
2003 SDValue V3 = (NumVecs == 3)
2004 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2005 : N->getOperand(Vec0Idx + 3);
2006 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2008 // Store the even D registers. This is always an updating store, so that it
2009 // provides the address to the second store for the odd subregs.
2010 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2011 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
2012 MemAddr.getValueType(),
2014 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
2015 Chain = SDValue(VStA, 1);
2017 // Store the odd D registers.
2018 Ops.push_back(SDValue(VStA, 0));
2019 Ops.push_back(Align);
2021 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2022 assert(isa<ConstantSDNode>(Inc.getNode()) &&
2023 "only constant post-increment update allowed for VST3/4");
2025 Ops.push_back(Reg0);
2027 Ops.push_back(RegSeq);
2028 Ops.push_back(Pred);
2029 Ops.push_back(Reg0);
2030 Ops.push_back(Chain);
2031 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
2033 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
2037 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
2038 bool isUpdating, unsigned NumVecs,
2039 const uint16_t *DOpcodes,
2040 const uint16_t *QOpcodes) {
2041 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2044 SDValue MemAddr, Align;
2045 unsigned AddrOpIdx = isUpdating ? 1 : 2;
2046 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2047 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2050 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2051 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2053 SDValue Chain = N->getOperand(0);
2055 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2056 EVT VT = N->getOperand(Vec0Idx).getValueType();
2057 bool is64BitVector = VT.is64BitVector();
2059 unsigned Alignment = 0;
2061 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2062 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2063 if (Alignment > NumBytes)
2064 Alignment = NumBytes;
2065 if (Alignment < 8 && Alignment < NumBytes)
2067 // Alignment must be a power of two; make sure of that.
2068 Alignment = (Alignment & -Alignment);
2072 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2074 unsigned OpcodeIndex;
2075 switch (VT.getSimpleVT().SimpleTy) {
2076 default: llvm_unreachable("unhandled vld/vst lane type");
2077 // Double-register operations:
2078 case MVT::v8i8: OpcodeIndex = 0; break;
2079 case MVT::v4i16: OpcodeIndex = 1; break;
2081 case MVT::v2i32: OpcodeIndex = 2; break;
2082 // Quad-register operations:
2083 case MVT::v8i16: OpcodeIndex = 0; break;
2085 case MVT::v4i32: OpcodeIndex = 1; break;
2088 std::vector<EVT> ResTys;
2090 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2093 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2094 MVT::i64, ResTyElts));
2097 ResTys.push_back(MVT::i32);
2098 ResTys.push_back(MVT::Other);
2100 SDValue Pred = getAL(CurDAG);
2101 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2103 SmallVector<SDValue, 8> Ops;
2104 Ops.push_back(MemAddr);
2105 Ops.push_back(Align);
2107 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2108 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2112 SDValue V0 = N->getOperand(Vec0Idx + 0);
2113 SDValue V1 = N->getOperand(Vec0Idx + 1);
2116 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2118 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2120 SDValue V2 = N->getOperand(Vec0Idx + 2);
2121 SDValue V3 = (NumVecs == 3)
2122 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2123 : N->getOperand(Vec0Idx + 3);
2125 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2127 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2129 Ops.push_back(SuperReg);
2130 Ops.push_back(getI32Imm(Lane));
2131 Ops.push_back(Pred);
2132 Ops.push_back(Reg0);
2133 Ops.push_back(Chain);
2135 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2136 QOpcodes[OpcodeIndex]);
2137 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2138 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2142 // Extract the subregisters.
2143 SuperReg = SDValue(VLdLn, 0);
2144 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2145 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2146 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2147 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2148 ReplaceUses(SDValue(N, Vec),
2149 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2150 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2152 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2156 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2158 const uint16_t *Opcodes) {
2159 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2162 SDValue MemAddr, Align;
2163 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2166 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2167 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2169 SDValue Chain = N->getOperand(0);
2170 EVT VT = N->getValueType(0);
2172 unsigned Alignment = 0;
2174 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2175 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2176 if (Alignment > NumBytes)
2177 Alignment = NumBytes;
2178 if (Alignment < 8 && Alignment < NumBytes)
2180 // Alignment must be a power of two; make sure of that.
2181 Alignment = (Alignment & -Alignment);
2185 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2187 unsigned OpcodeIndex;
2188 switch (VT.getSimpleVT().SimpleTy) {
2189 default: llvm_unreachable("unhandled vld-dup type");
2190 case MVT::v8i8: OpcodeIndex = 0; break;
2191 case MVT::v4i16: OpcodeIndex = 1; break;
2193 case MVT::v2i32: OpcodeIndex = 2; break;
2196 SDValue Pred = getAL(CurDAG);
2197 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2199 unsigned Opc = Opcodes[OpcodeIndex];
2200 SmallVector<SDValue, 6> Ops;
2201 Ops.push_back(MemAddr);
2202 Ops.push_back(Align);
2204 // fixed-stride update instructions don't have an explicit writeback
2205 // operand. It's implicit in the opcode itself.
2206 SDValue Inc = N->getOperand(2);
2207 if (!isa<ConstantSDNode>(Inc.getNode()))
2209 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2210 else if (NumVecs > 2)
2211 Ops.push_back(Reg0);
2213 Ops.push_back(Pred);
2214 Ops.push_back(Reg0);
2215 Ops.push_back(Chain);
2217 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2218 std::vector<EVT> ResTys;
2219 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2221 ResTys.push_back(MVT::i32);
2222 ResTys.push_back(MVT::Other);
2223 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2224 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2225 SuperReg = SDValue(VLdDup, 0);
2227 // Extract the subregisters.
2228 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2229 unsigned SubIdx = ARM::dsub_0;
2230 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2231 ReplaceUses(SDValue(N, Vec),
2232 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2233 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2235 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2239 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2241 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2243 EVT VT = N->getValueType(0);
2244 unsigned FirstTblReg = IsExt ? 2 : 1;
2246 // Form a REG_SEQUENCE to force register allocation.
2248 SDValue V0 = N->getOperand(FirstTblReg + 0);
2249 SDValue V1 = N->getOperand(FirstTblReg + 1);
2251 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2253 SDValue V2 = N->getOperand(FirstTblReg + 2);
2254 // If it's a vtbl3, form a quad D-register and leave the last part as
2256 SDValue V3 = (NumVecs == 3)
2257 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2258 : N->getOperand(FirstTblReg + 3);
2259 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2262 SmallVector<SDValue, 6> Ops;
2264 Ops.push_back(N->getOperand(1));
2265 Ops.push_back(RegSeq);
2266 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2267 Ops.push_back(getAL(CurDAG)); // predicate
2268 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2269 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2272 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2274 if (!Subtarget->hasV6T2Ops())
2277 unsigned Opc = isSigned
2278 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2279 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2281 // For unsigned extracts, check for a shift right and mask
2282 unsigned And_imm = 0;
2283 if (N->getOpcode() == ISD::AND) {
2284 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2286 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2287 if (And_imm & (And_imm + 1))
2290 unsigned Srl_imm = 0;
2291 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2293 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2295 // Note: The width operand is encoded as width-1.
2296 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2297 unsigned LSB = Srl_imm;
2299 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2301 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2302 // It's cheaper to use a right shift to extract the top bits.
2303 if (Subtarget->isThumb()) {
2304 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2305 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2306 CurDAG->getTargetConstant(LSB, MVT::i32),
2307 getAL(CurDAG), Reg0, Reg0 };
2308 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2311 // ARM models shift instructions as MOVsi with shifter operand.
2312 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2314 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
2316 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2317 getAL(CurDAG), Reg0, Reg0 };
2318 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
2321 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2322 CurDAG->getTargetConstant(LSB, MVT::i32),
2323 CurDAG->getTargetConstant(Width, MVT::i32),
2324 getAL(CurDAG), Reg0 };
2325 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2331 // Otherwise, we're looking for a shift of a shift
2332 unsigned Shl_imm = 0;
2333 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2334 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2335 unsigned Srl_imm = 0;
2336 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2337 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2338 // Note: The width operand is encoded as width-1.
2339 unsigned Width = 32 - Srl_imm - 1;
2340 int LSB = Srl_imm - Shl_imm;
2343 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2344 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2345 CurDAG->getTargetConstant(LSB, MVT::i32),
2346 CurDAG->getTargetConstant(Width, MVT::i32),
2347 getAL(CurDAG), Reg0 };
2348 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2352 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2353 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
2355 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
2356 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
2359 if (LSB + Width > 32)
2362 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2363 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2364 CurDAG->getTargetConstant(LSB, MVT::i32),
2365 CurDAG->getTargetConstant(Width - 1, MVT::i32),
2366 getAL(CurDAG), Reg0 };
2367 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2373 /// Target-specific DAG combining for ISD::XOR.
2374 /// Target-independent combining lowers SELECT_CC nodes of the form
2375 /// select_cc setg[ge] X, 0, X, -X
2376 /// select_cc setgt X, -1, X, -X
2377 /// select_cc setl[te] X, 0, -X, X
2378 /// select_cc setlt X, 1, -X, X
2379 /// which represent Integer ABS into:
2380 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2381 /// ARM instruction selection detects the latter and matches it to
2382 /// ARM::ABS or ARM::t2ABS machine node.
2383 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2384 SDValue XORSrc0 = N->getOperand(0);
2385 SDValue XORSrc1 = N->getOperand(1);
2386 EVT VT = N->getValueType(0);
2388 if (Subtarget->isThumb1Only())
2391 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2394 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2395 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2396 SDValue SRASrc0 = XORSrc1.getOperand(0);
2397 SDValue SRASrc1 = XORSrc1.getOperand(1);
2398 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2399 EVT XType = SRASrc0.getValueType();
2400 unsigned Size = XType.getSizeInBits() - 1;
2402 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2403 XType.isInteger() && SRAConstant != nullptr &&
2404 Size == SRAConstant->getZExtValue()) {
2405 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2406 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2412 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2413 // The only time a CONCAT_VECTORS operation can have legal types is when
2414 // two 64-bit vectors are concatenated to a 128-bit vector.
2415 EVT VT = N->getValueType(0);
2416 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2417 llvm_unreachable("unexpected CONCAT_VECTORS");
2418 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2421 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2424 if (N->isMachineOpcode()) {
2426 return nullptr; // Already selected.
2429 switch (N->getOpcode()) {
2431 case ISD::INLINEASM: {
2432 SDNode *ResNode = SelectInlineAsm(N);
2438 // Select special operations if XOR node forms integer ABS pattern
2439 SDNode *ResNode = SelectABSOp(N);
2442 // Other cases are autogenerated.
2445 case ISD::Constant: {
2446 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2448 if (Subtarget->useMovt(*MF))
2449 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2450 // be done with MOV + MOVT, at worst.
2453 if (Subtarget->isThumb()) {
2454 UseCP = (Val > 255 && // MOV
2455 ~Val > 255 && // MOV + MVN
2456 !ARM_AM::isThumbImmShiftedVal(Val) && // MOV + LSL
2457 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2459 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2460 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2461 !ARM_AM::isSOImmTwoPartVal(Val) && // two instrs.
2462 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2466 SDValue CPIdx = CurDAG->getTargetConstantPool(
2467 ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
2468 TLI->getPointerTy());
2471 if (Subtarget->isThumb()) {
2472 SDValue Pred = getAL(CurDAG);
2473 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2474 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2475 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2480 CurDAG->getTargetConstant(0, MVT::i32),
2482 CurDAG->getRegister(0, MVT::i32),
2483 CurDAG->getEntryNode()
2485 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2488 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2492 // Other cases are autogenerated.
2495 case ISD::FrameIndex: {
2496 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2497 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2498 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
2499 if (Subtarget->isThumb1Only()) {
2500 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2501 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2502 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops);
2504 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2505 ARM::t2ADDri : ARM::ADDri);
2506 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2507 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2508 CurDAG->getRegister(0, MVT::i32) };
2509 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2513 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2516 case ISD::SIGN_EXTEND_INREG:
2518 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2522 if (Subtarget->isThumb1Only())
2524 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2525 unsigned RHSV = C->getZExtValue();
2527 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2528 unsigned ShImm = Log2_32(RHSV-1);
2531 SDValue V = N->getOperand(0);
2532 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2533 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2534 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2535 if (Subtarget->isThumb()) {
2536 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2537 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
2539 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2540 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
2543 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2544 unsigned ShImm = Log2_32(RHSV+1);
2547 SDValue V = N->getOperand(0);
2548 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2549 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2550 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2551 if (Subtarget->isThumb()) {
2552 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2553 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
2555 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2556 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
2562 // Check for unsigned bitfield extract
2563 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2566 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2567 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2568 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2569 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2570 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2571 EVT VT = N->getValueType(0);
2574 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2576 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2579 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2580 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2583 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2584 SDValue N2 = N0.getOperand(1);
2585 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2588 unsigned N1CVal = N1C->getZExtValue();
2589 unsigned N2CVal = N2C->getZExtValue();
2590 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2591 (N1CVal & 0xffffU) == 0xffffU &&
2592 (N2CVal & 0xffffU) == 0x0U) {
2593 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2595 SDValue Ops[] = { N0.getOperand(0), Imm16,
2596 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2597 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2602 case ARMISD::VMOVRRD:
2603 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2604 N->getOperand(0), getAL(CurDAG),
2605 CurDAG->getRegister(0, MVT::i32));
2606 case ISD::UMUL_LOHI: {
2607 if (Subtarget->isThumb1Only())
2609 if (Subtarget->isThumb()) {
2610 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2611 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2612 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2614 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2615 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2616 CurDAG->getRegister(0, MVT::i32) };
2617 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2618 ARM::UMULL : ARM::UMULLv5,
2619 dl, MVT::i32, MVT::i32, Ops);
2622 case ISD::SMUL_LOHI: {
2623 if (Subtarget->isThumb1Only())
2625 if (Subtarget->isThumb()) {
2626 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2627 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2628 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2630 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2631 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2632 CurDAG->getRegister(0, MVT::i32) };
2633 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2634 ARM::SMULL : ARM::SMULLv5,
2635 dl, MVT::i32, MVT::i32, Ops);
2638 case ARMISD::UMLAL:{
2639 if (Subtarget->isThumb()) {
2640 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2641 N->getOperand(3), getAL(CurDAG),
2642 CurDAG->getRegister(0, MVT::i32)};
2643 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2645 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2646 N->getOperand(3), getAL(CurDAG),
2647 CurDAG->getRegister(0, MVT::i32),
2648 CurDAG->getRegister(0, MVT::i32) };
2649 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2650 ARM::UMLAL : ARM::UMLALv5,
2651 dl, MVT::i32, MVT::i32, Ops);
2654 case ARMISD::SMLAL:{
2655 if (Subtarget->isThumb()) {
2656 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2657 N->getOperand(3), getAL(CurDAG),
2658 CurDAG->getRegister(0, MVT::i32)};
2659 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2661 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2662 N->getOperand(3), getAL(CurDAG),
2663 CurDAG->getRegister(0, MVT::i32),
2664 CurDAG->getRegister(0, MVT::i32) };
2665 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2666 ARM::SMLAL : ARM::SMLALv5,
2667 dl, MVT::i32, MVT::i32, Ops);
2671 SDNode *ResNode = nullptr;
2672 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2673 ResNode = SelectT2IndexedLoad(N);
2675 ResNode = SelectARMIndexedLoad(N);
2678 // Other cases are autogenerated.
2681 case ARMISD::BRCOND: {
2682 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2683 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2684 // Pattern complexity = 6 cost = 1 size = 0
2686 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2687 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2688 // Pattern complexity = 6 cost = 1 size = 0
2690 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2691 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2692 // Pattern complexity = 6 cost = 1 size = 0
2694 unsigned Opc = Subtarget->isThumb() ?
2695 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2696 SDValue Chain = N->getOperand(0);
2697 SDValue N1 = N->getOperand(1);
2698 SDValue N2 = N->getOperand(2);
2699 SDValue N3 = N->getOperand(3);
2700 SDValue InFlag = N->getOperand(4);
2701 assert(N1.getOpcode() == ISD::BasicBlock);
2702 assert(N2.getOpcode() == ISD::Constant);
2703 assert(N3.getOpcode() == ISD::Register);
2705 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2706 cast<ConstantSDNode>(N2)->getZExtValue()),
2708 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2709 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2711 Chain = SDValue(ResNode, 0);
2712 if (N->getNumValues() == 2) {
2713 InFlag = SDValue(ResNode, 1);
2714 ReplaceUses(SDValue(N, 1), InFlag);
2716 ReplaceUses(SDValue(N, 0),
2717 SDValue(Chain.getNode(), Chain.getResNo()));
2720 case ARMISD::VZIP: {
2722 EVT VT = N->getValueType(0);
2723 switch (VT.getSimpleVT().SimpleTy) {
2724 default: return nullptr;
2725 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2726 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2728 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2729 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2730 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2731 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2733 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2735 SDValue Pred = getAL(CurDAG);
2736 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2737 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2738 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2740 case ARMISD::VUZP: {
2742 EVT VT = N->getValueType(0);
2743 switch (VT.getSimpleVT().SimpleTy) {
2744 default: return nullptr;
2745 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2746 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2748 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2749 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2750 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2751 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2753 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2755 SDValue Pred = getAL(CurDAG);
2756 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2757 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2758 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2760 case ARMISD::VTRN: {
2762 EVT VT = N->getValueType(0);
2763 switch (VT.getSimpleVT().SimpleTy) {
2764 default: return nullptr;
2765 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2766 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2768 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2769 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2770 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2772 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2774 SDValue Pred = getAL(CurDAG);
2775 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2776 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2777 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2779 case ARMISD::BUILD_VECTOR: {
2780 EVT VecVT = N->getValueType(0);
2781 EVT EltVT = VecVT.getVectorElementType();
2782 unsigned NumElts = VecVT.getVectorNumElements();
2783 if (EltVT == MVT::f64) {
2784 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2785 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2787 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2789 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2790 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2791 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2792 N->getOperand(2), N->getOperand(3));
2795 case ARMISD::VLD2DUP: {
2796 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2798 return SelectVLDDup(N, false, 2, Opcodes);
2801 case ARMISD::VLD3DUP: {
2802 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2803 ARM::VLD3DUPd16Pseudo,
2804 ARM::VLD3DUPd32Pseudo };
2805 return SelectVLDDup(N, false, 3, Opcodes);
2808 case ARMISD::VLD4DUP: {
2809 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2810 ARM::VLD4DUPd16Pseudo,
2811 ARM::VLD4DUPd32Pseudo };
2812 return SelectVLDDup(N, false, 4, Opcodes);
2815 case ARMISD::VLD2DUP_UPD: {
2816 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2817 ARM::VLD2DUPd16wb_fixed,
2818 ARM::VLD2DUPd32wb_fixed };
2819 return SelectVLDDup(N, true, 2, Opcodes);
2822 case ARMISD::VLD3DUP_UPD: {
2823 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2824 ARM::VLD3DUPd16Pseudo_UPD,
2825 ARM::VLD3DUPd32Pseudo_UPD };
2826 return SelectVLDDup(N, true, 3, Opcodes);
2829 case ARMISD::VLD4DUP_UPD: {
2830 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2831 ARM::VLD4DUPd16Pseudo_UPD,
2832 ARM::VLD4DUPd32Pseudo_UPD };
2833 return SelectVLDDup(N, true, 4, Opcodes);
2836 case ARMISD::VLD1_UPD: {
2837 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2838 ARM::VLD1d16wb_fixed,
2839 ARM::VLD1d32wb_fixed,
2840 ARM::VLD1d64wb_fixed };
2841 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2842 ARM::VLD1q16wb_fixed,
2843 ARM::VLD1q32wb_fixed,
2844 ARM::VLD1q64wb_fixed };
2845 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
2848 case ARMISD::VLD2_UPD: {
2849 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2850 ARM::VLD2d16wb_fixed,
2851 ARM::VLD2d32wb_fixed,
2852 ARM::VLD1q64wb_fixed};
2853 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2854 ARM::VLD2q16PseudoWB_fixed,
2855 ARM::VLD2q32PseudoWB_fixed };
2856 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
2859 case ARMISD::VLD3_UPD: {
2860 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2861 ARM::VLD3d16Pseudo_UPD,
2862 ARM::VLD3d32Pseudo_UPD,
2863 ARM::VLD1d64TPseudoWB_fixed};
2864 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2865 ARM::VLD3q16Pseudo_UPD,
2866 ARM::VLD3q32Pseudo_UPD };
2867 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2868 ARM::VLD3q16oddPseudo_UPD,
2869 ARM::VLD3q32oddPseudo_UPD };
2870 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2873 case ARMISD::VLD4_UPD: {
2874 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2875 ARM::VLD4d16Pseudo_UPD,
2876 ARM::VLD4d32Pseudo_UPD,
2877 ARM::VLD1d64QPseudoWB_fixed};
2878 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2879 ARM::VLD4q16Pseudo_UPD,
2880 ARM::VLD4q32Pseudo_UPD };
2881 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2882 ARM::VLD4q16oddPseudo_UPD,
2883 ARM::VLD4q32oddPseudo_UPD };
2884 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2887 case ARMISD::VLD2LN_UPD: {
2888 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2889 ARM::VLD2LNd16Pseudo_UPD,
2890 ARM::VLD2LNd32Pseudo_UPD };
2891 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2892 ARM::VLD2LNq32Pseudo_UPD };
2893 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2896 case ARMISD::VLD3LN_UPD: {
2897 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2898 ARM::VLD3LNd16Pseudo_UPD,
2899 ARM::VLD3LNd32Pseudo_UPD };
2900 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2901 ARM::VLD3LNq32Pseudo_UPD };
2902 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2905 case ARMISD::VLD4LN_UPD: {
2906 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2907 ARM::VLD4LNd16Pseudo_UPD,
2908 ARM::VLD4LNd32Pseudo_UPD };
2909 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2910 ARM::VLD4LNq32Pseudo_UPD };
2911 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2914 case ARMISD::VST1_UPD: {
2915 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2916 ARM::VST1d16wb_fixed,
2917 ARM::VST1d32wb_fixed,
2918 ARM::VST1d64wb_fixed };
2919 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2920 ARM::VST1q16wb_fixed,
2921 ARM::VST1q32wb_fixed,
2922 ARM::VST1q64wb_fixed };
2923 return SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
2926 case ARMISD::VST2_UPD: {
2927 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2928 ARM::VST2d16wb_fixed,
2929 ARM::VST2d32wb_fixed,
2930 ARM::VST1q64wb_fixed};
2931 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2932 ARM::VST2q16PseudoWB_fixed,
2933 ARM::VST2q32PseudoWB_fixed };
2934 return SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
2937 case ARMISD::VST3_UPD: {
2938 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2939 ARM::VST3d16Pseudo_UPD,
2940 ARM::VST3d32Pseudo_UPD,
2941 ARM::VST1d64TPseudoWB_fixed};
2942 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2943 ARM::VST3q16Pseudo_UPD,
2944 ARM::VST3q32Pseudo_UPD };
2945 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2946 ARM::VST3q16oddPseudo_UPD,
2947 ARM::VST3q32oddPseudo_UPD };
2948 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2951 case ARMISD::VST4_UPD: {
2952 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2953 ARM::VST4d16Pseudo_UPD,
2954 ARM::VST4d32Pseudo_UPD,
2955 ARM::VST1d64QPseudoWB_fixed};
2956 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2957 ARM::VST4q16Pseudo_UPD,
2958 ARM::VST4q32Pseudo_UPD };
2959 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2960 ARM::VST4q16oddPseudo_UPD,
2961 ARM::VST4q32oddPseudo_UPD };
2962 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2965 case ARMISD::VST2LN_UPD: {
2966 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2967 ARM::VST2LNd16Pseudo_UPD,
2968 ARM::VST2LNd32Pseudo_UPD };
2969 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2970 ARM::VST2LNq32Pseudo_UPD };
2971 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2974 case ARMISD::VST3LN_UPD: {
2975 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2976 ARM::VST3LNd16Pseudo_UPD,
2977 ARM::VST3LNd32Pseudo_UPD };
2978 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2979 ARM::VST3LNq32Pseudo_UPD };
2980 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2983 case ARMISD::VST4LN_UPD: {
2984 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
2985 ARM::VST4LNd16Pseudo_UPD,
2986 ARM::VST4LNd32Pseudo_UPD };
2987 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2988 ARM::VST4LNq32Pseudo_UPD };
2989 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2992 case ISD::INTRINSIC_VOID:
2993 case ISD::INTRINSIC_W_CHAIN: {
2994 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2999 case Intrinsic::arm_ldaexd:
3000 case Intrinsic::arm_ldrexd: {
3002 SDValue Chain = N->getOperand(0);
3003 SDValue MemAddr = N->getOperand(2);
3004 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3006 bool IsAcquire = IntNo == Intrinsic::arm_ldaexd;
3007 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
3008 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
3010 // arm_ldrexd returns a i64 value in {i32, i32}
3011 std::vector<EVT> ResTys;
3013 ResTys.push_back(MVT::i32);
3014 ResTys.push_back(MVT::i32);
3016 ResTys.push_back(MVT::Untyped);
3017 ResTys.push_back(MVT::Other);
3019 // Place arguments in the right order.
3020 SmallVector<SDValue, 7> Ops;
3021 Ops.push_back(MemAddr);
3022 Ops.push_back(getAL(CurDAG));
3023 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3024 Ops.push_back(Chain);
3025 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3026 // Transfer memoperands.
3027 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3028 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3029 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3032 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3033 if (!SDValue(N, 0).use_empty()) {
3036 Result = SDValue(Ld, 0);
3038 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3039 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3040 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3041 Result = SDValue(ResNode,0);
3043 ReplaceUses(SDValue(N, 0), Result);
3045 if (!SDValue(N, 1).use_empty()) {
3048 Result = SDValue(Ld, 1);
3050 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3051 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3052 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3053 Result = SDValue(ResNode,0);
3055 ReplaceUses(SDValue(N, 1), Result);
3057 ReplaceUses(SDValue(N, 2), OutChain);
3060 case Intrinsic::arm_stlexd:
3061 case Intrinsic::arm_strexd: {
3063 SDValue Chain = N->getOperand(0);
3064 SDValue Val0 = N->getOperand(2);
3065 SDValue Val1 = N->getOperand(3);
3066 SDValue MemAddr = N->getOperand(4);
3068 // Store exclusive double return a i32 value which is the return status
3069 // of the issued store.
3070 EVT ResTys[] = { MVT::i32, MVT::Other };
3072 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3073 // Place arguments in the right order.
3074 SmallVector<SDValue, 7> Ops;
3076 Ops.push_back(Val0);
3077 Ops.push_back(Val1);
3079 // arm_strexd uses GPRPair.
3080 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3081 Ops.push_back(MemAddr);
3082 Ops.push_back(getAL(CurDAG));
3083 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3084 Ops.push_back(Chain);
3086 bool IsRelease = IntNo == Intrinsic::arm_stlexd;
3087 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
3088 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
3090 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3091 // Transfer memoperands.
3092 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3093 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3094 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3099 case Intrinsic::arm_neon_vld1: {
3100 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3101 ARM::VLD1d32, ARM::VLD1d64 };
3102 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3103 ARM::VLD1q32, ARM::VLD1q64};
3104 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
3107 case Intrinsic::arm_neon_vld2: {
3108 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3109 ARM::VLD2d32, ARM::VLD1q64 };
3110 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3111 ARM::VLD2q32Pseudo };
3112 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3115 case Intrinsic::arm_neon_vld3: {
3116 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3119 ARM::VLD1d64TPseudo };
3120 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3121 ARM::VLD3q16Pseudo_UPD,
3122 ARM::VLD3q32Pseudo_UPD };
3123 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3124 ARM::VLD3q16oddPseudo,
3125 ARM::VLD3q32oddPseudo };
3126 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3129 case Intrinsic::arm_neon_vld4: {
3130 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3133 ARM::VLD1d64QPseudo };
3134 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3135 ARM::VLD4q16Pseudo_UPD,
3136 ARM::VLD4q32Pseudo_UPD };
3137 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3138 ARM::VLD4q16oddPseudo,
3139 ARM::VLD4q32oddPseudo };
3140 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3143 case Intrinsic::arm_neon_vld2lane: {
3144 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3145 ARM::VLD2LNd16Pseudo,
3146 ARM::VLD2LNd32Pseudo };
3147 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3148 ARM::VLD2LNq32Pseudo };
3149 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3152 case Intrinsic::arm_neon_vld3lane: {
3153 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3154 ARM::VLD3LNd16Pseudo,
3155 ARM::VLD3LNd32Pseudo };
3156 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3157 ARM::VLD3LNq32Pseudo };
3158 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3161 case Intrinsic::arm_neon_vld4lane: {
3162 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3163 ARM::VLD4LNd16Pseudo,
3164 ARM::VLD4LNd32Pseudo };
3165 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3166 ARM::VLD4LNq32Pseudo };
3167 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3170 case Intrinsic::arm_neon_vst1: {
3171 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3172 ARM::VST1d32, ARM::VST1d64 };
3173 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3174 ARM::VST1q32, ARM::VST1q64 };
3175 return SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
3178 case Intrinsic::arm_neon_vst2: {
3179 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3180 ARM::VST2d32, ARM::VST1q64 };
3181 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3182 ARM::VST2q32Pseudo };
3183 return SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
3186 case Intrinsic::arm_neon_vst3: {
3187 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3190 ARM::VST1d64TPseudo };
3191 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3192 ARM::VST3q16Pseudo_UPD,
3193 ARM::VST3q32Pseudo_UPD };
3194 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3195 ARM::VST3q16oddPseudo,
3196 ARM::VST3q32oddPseudo };
3197 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3200 case Intrinsic::arm_neon_vst4: {
3201 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3204 ARM::VST1d64QPseudo };
3205 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3206 ARM::VST4q16Pseudo_UPD,
3207 ARM::VST4q32Pseudo_UPD };
3208 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3209 ARM::VST4q16oddPseudo,
3210 ARM::VST4q32oddPseudo };
3211 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3214 case Intrinsic::arm_neon_vst2lane: {
3215 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3216 ARM::VST2LNd16Pseudo,
3217 ARM::VST2LNd32Pseudo };
3218 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3219 ARM::VST2LNq32Pseudo };
3220 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3223 case Intrinsic::arm_neon_vst3lane: {
3224 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3225 ARM::VST3LNd16Pseudo,
3226 ARM::VST3LNd32Pseudo };
3227 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3228 ARM::VST3LNq32Pseudo };
3229 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3232 case Intrinsic::arm_neon_vst4lane: {
3233 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3234 ARM::VST4LNd16Pseudo,
3235 ARM::VST4LNd32Pseudo };
3236 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3237 ARM::VST4LNq32Pseudo };
3238 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3244 case ISD::INTRINSIC_WO_CHAIN: {
3245 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3250 case Intrinsic::arm_neon_vtbl2:
3251 return SelectVTBL(N, false, 2, ARM::VTBL2);
3252 case Intrinsic::arm_neon_vtbl3:
3253 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3254 case Intrinsic::arm_neon_vtbl4:
3255 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3257 case Intrinsic::arm_neon_vtbx2:
3258 return SelectVTBL(N, true, 2, ARM::VTBX2);
3259 case Intrinsic::arm_neon_vtbx3:
3260 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3261 case Intrinsic::arm_neon_vtbx4:
3262 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3267 case ARMISD::VTBL1: {
3269 EVT VT = N->getValueType(0);
3270 SmallVector<SDValue, 6> Ops;
3272 Ops.push_back(N->getOperand(0));
3273 Ops.push_back(N->getOperand(1));
3274 Ops.push_back(getAL(CurDAG)); // Predicate
3275 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3276 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3278 case ARMISD::VTBL2: {
3280 EVT VT = N->getValueType(0);
3282 // Form a REG_SEQUENCE to force register allocation.
3283 SDValue V0 = N->getOperand(0);
3284 SDValue V1 = N->getOperand(1);
3285 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3287 SmallVector<SDValue, 6> Ops;
3288 Ops.push_back(RegSeq);
3289 Ops.push_back(N->getOperand(2));
3290 Ops.push_back(getAL(CurDAG)); // Predicate
3291 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3292 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3295 case ISD::CONCAT_VECTORS:
3296 return SelectConcatVector(N);
3299 return SelectCode(N);
3302 SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3303 std::vector<SDValue> AsmNodeOperands;
3304 unsigned Flag, Kind;
3305 bool Changed = false;
3306 unsigned NumOps = N->getNumOperands();
3308 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3309 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3310 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3311 // respectively. Since there is no constraint to explicitly specify a
3312 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3313 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3314 // them into a GPRPair.
3317 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
3318 : SDValue(nullptr,0);
3320 SmallVector<bool, 8> OpChanged;
3321 // Glue node will be appended late.
3322 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3323 SDValue op = N->getOperand(i);
3324 AsmNodeOperands.push_back(op);
3326 if (i < InlineAsm::Op_FirstOperand)
3329 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3330 Flag = C->getZExtValue();
3331 Kind = InlineAsm::getKind(Flag);
3336 // Immediate operands to inline asm in the SelectionDAG are modeled with
3337 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3338 // the second is a constant with the value of the immediate. If we get here
3339 // and we have a Kind_Imm, skip the next operand, and continue.
3340 if (Kind == InlineAsm::Kind_Imm) {
3341 SDValue op = N->getOperand(++i);
3342 AsmNodeOperands.push_back(op);
3346 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3348 OpChanged.push_back(false);
3350 unsigned DefIdx = 0;
3351 bool IsTiedToChangedOp = false;
3352 // If it's a use that is tied with a previous def, it has no
3353 // reg class constraint.
3354 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3355 IsTiedToChangedOp = OpChanged[DefIdx];
3357 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3358 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3362 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3363 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3367 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3368 SDValue V0 = N->getOperand(i+1);
3369 SDValue V1 = N->getOperand(i+2);
3370 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3371 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3373 MachineRegisterInfo &MRI = MF->getRegInfo();
3375 if (Kind == InlineAsm::Kind_RegDef ||
3376 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3377 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3378 // the original GPRs.
3380 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3381 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3382 SDValue Chain = SDValue(N,0);
3384 SDNode *GU = N->getGluedUser();
3385 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3388 // Extract values from a GPRPair reg and copy to the original GPR reg.
3389 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3391 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3393 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3394 RegCopy.getValue(1));
3395 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3397 // Update the original glue user.
3398 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3399 Ops.push_back(T1.getValue(1));
3400 CurDAG->UpdateNodeOperands(GU, Ops);
3404 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3405 // GPRPair and then pass the GPRPair to the inline asm.
3406 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3408 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3409 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3411 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3413 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3415 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3416 // i32 VRs of inline asm with it.
3417 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3418 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3419 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3421 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3422 Glue = Chain.getValue(1);
3427 if(PairedReg.getNode()) {
3428 OpChanged[OpChanged.size() -1 ] = true;
3429 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3430 if (IsTiedToChangedOp)
3431 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3433 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3434 // Replace the current flag.
3435 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3437 // Add the new register node and skip the original two GPRs.
3438 AsmNodeOperands.push_back(PairedReg);
3439 // Skip the next two GPRs.
3445 AsmNodeOperands.push_back(Glue);
3449 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3450 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
3452 return New.getNode();
3456 bool ARMDAGToDAGISel::
3457 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3458 std::vector<SDValue> &OutOps) {
3459 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3460 // Require the address to be in a register. That is safe for all ARM
3461 // variants and it is hard to do anything much smarter without knowing
3462 // how the operand is used.
3463 OutOps.push_back(Op);
3467 /// createARMISelDag - This pass converts a legalized DAG into a
3468 /// ARM-specific DAG, ready for instruction scheduling.
3470 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3471 CodeGenOpt::Level OptLevel) {
3472 return new ARMDAGToDAGISel(TM, OptLevel);